1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /* Driver for BayHub Technology LV2 PCI to SD bridge */
4
5 #include <console/console.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pciexp.h>
9 #include <device/pci_ops.h>
10 #include <device/pci_ids.h>
11 #include "chip.h"
12 #include "lv2.h"
13
14 /*
15 * This chip has an errata where PCIe config space registers 0x234, 0x248, and
16 * 0x24C only support DWORD access, therefore reprogram these in the `finalize`
17 * callback.
18 */
lv2_enable_ltr(struct device * dev)19 static void lv2_enable_ltr(struct device *dev)
20 {
21 u16 max_snoop, max_nosnoop;
22 if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop))
23 return;
24
25 const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID, 0);
26 if (!ltr_cap)
27 return;
28
29 pci_write_config32(dev, ltr_cap + PCI_LTR_MAX_SNOOP, (max_snoop << 16) | max_nosnoop);
30 printk(BIOS_INFO, "%s: Re-programmed LTR max latencies using chip-specific quirk\n",
31 dev_path(dev));
32 }
33
lv2_enable(struct device * dev)34 static void lv2_enable(struct device *dev)
35 {
36 struct drivers_generic_bayhub_lv2_config *config = dev->chip_info;
37 pci_dev_init(dev);
38
39 if (!config || !config->enable_power_saving)
40 return;
41 /*
42 * This procedure for enabling power-saving mode is from the
43 * BayHub BIOS Implementation Guideline document.
44 */
45 pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF);
46 pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE);
47 pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER);
48 pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
49 pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
50 pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
51 pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
52 LV2_L1_SUBSTATE_OPTIMISE);
53 pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
54 pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
55 LV2_DRIVER_STRENGTH);
56 pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
57 LV2_RESET_DMA_DISABLE);
58 pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
59 printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n");
60 }
61
62 static struct device_operations lv2_ops = {
63 .read_resources = pci_dev_read_resources,
64 .set_resources = pci_dev_set_resources,
65 .enable_resources = pci_dev_enable_resources,
66 .ops_pci = &pci_dev_ops_pci,
67 .enable = lv2_enable,
68 .final = lv2_enable_ltr,
69 };
70
71 static const unsigned short pci_device_ids[] = {
72 PCI_DID_O2_LV2,
73 0
74 };
75
76 static const struct pci_driver bayhub_lv2 __pci_driver = {
77 .ops = &lv2_ops,
78 .vendor = PCI_VID_O2,
79 .devices = pci_device_ids,
80 };
81
82 struct chip_operations drivers_generic_bayhub_lv2_ops = {
83 .name = "BayHub Technology LV2 PCIe to SD bridge",
84 };
85