1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 /* Version */ 8 #define RTL_VERSION 9 10 /* instruction pipeline depth */ 11 #define ISP_BRANCHDELAY 5 12 13 /* bus */ 14 #define ISP_BUS_WIDTH 32 15 #define ISP_BUS_ADDR_WIDTH 32 16 #define ISP_BUS_BURST_SIZE 1 17 18 /* data-path */ 19 #define ISP_SCALAR_WIDTH 32 20 #define ISP_SLICE_NELEMS 4 21 #define ISP_VEC_NELEMS 64 22 #define ISP_VEC_ELEMBITS 14 23 #define ISP_VEC_ELEM8BITS 16 24 #define ISP_CLONE_DATAPATH_IS_16 1 25 26 /* memories */ 27 #define ISP_DMEM_DEPTH 4096 28 #define ISP_DMEM_BSEL_DOWNSAMPLE 8 29 #define ISP_VMEM_DEPTH 3072 30 #define ISP_VMEM_BSEL_DOWNSAMPLE 8 31 #define ISP_VMEM_ELEMBITS 14 32 #define ISP_VMEM_ELEM_PRECISION 14 33 #define ISP_PMEM_DEPTH 2048 34 #define ISP_PMEM_WIDTH 640 35 #define ISP_VAMEM_ADDRESS_BITS 12 36 #define ISP_VAMEM_ELEMBITS 12 37 #define ISP_VAMEM_DEPTH 2048 38 #define ISP_VAMEM_ALIGNMENT 2 39 #define ISP_VA_ADDRESS_WIDTH 896 40 #define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS 41 #define ISP_HIST_ADDRESS_BITS 12 42 #define ISP_HIST_ALIGNMENT 4 43 #define ISP_HIST_COMP_IN_PREC 12 44 #define ISP_HIST_DEPTH 1024 45 #define ISP_HIST_WIDTH 24 46 #define ISP_HIST_COMPONENTS 4 47 48 /* program counter */ 49 #define ISP_PC_WIDTH 13 50 51 /* Template switches */ 52 #define ISP_SHIELD_INPUT_DMEM 0 53 #define ISP_SHIELD_OUTPUT_DMEM 1 54 #define ISP_SHIELD_INPUT_VMEM 0 55 #define ISP_SHIELD_OUTPUT_VMEM 0 56 #define ISP_SHIELD_INPUT_PMEM 1 57 #define ISP_SHIELD_OUTPUT_PMEM 1 58 #define ISP_SHIELD_INPUT_HIST 1 59 #define ISP_SHIELD_OUTPUT_HIST 1 60 /* When LUT is select the shielding is always on */ 61 #define ISP_SHIELD_INPUT_VAMEM 1 62 #define ISP_SHIELD_OUTPUT_VAMEM 1 63 64 #define ISP_HAS_IRQ 1 65 #define ISP_HAS_SOFT_RESET 1 66 #define ISP_HAS_VEC_DIV 0 67 #define ISP_HAS_VFU_W_2O 1 68 #define ISP_HAS_DEINT3 1 69 #define ISP_HAS_LUT 1 70 #define ISP_HAS_HIST 1 71 #define ISP_HAS_VALSU 1 72 #define ISP_HAS_3rdVALSU 1 73 #define ISP_VRF1_HAS_2P 1 74 75 #define ISP_SRU_GUARDING 1 76 #define ISP_VLSU_GUARDING 1 77 78 #define ISP_VRF_RAM 1 79 #define ISP_SRF_RAM 1 80 81 #define ISP_SPLIT_VMUL_VADD_IS 0 82 #define ISP_RFSPLIT_FPGA 0 83 84 /* RSN or Bus pipelining */ 85 #define ISP_RSN_PIPE 1 86 #define ISP_VSF_BUS_PIPE 0 87 88 /* extra slave port to vmem */ 89 #define ISP_IF_VMEM 0 90 #define ISP_GDC_VMEM 0 91 92 /* Streaming ports */ 93 #define ISP_IF 1 94 #define ISP_IF_B 1 95 #define ISP_GDC 1 96 #define ISP_SCL 1 97 #define ISP_GPFIFO 1 98 #define ISP_SP 1 99 100 /* Removing Issue Slot(s) */ 101 #define ISP_HAS_NOT_SIMD_IS2 0 102 #define ISP_HAS_NOT_SIMD_IS3 0 103 #define ISP_HAS_NOT_SIMD_IS4 0 104 #define ISP_HAS_NOT_SIMD_IS4_VADD 0 105 #define ISP_HAS_NOT_SIMD_IS5 0 106 #define ISP_HAS_NOT_SIMD_IS6 0 107 #define ISP_HAS_NOT_SIMD_IS7 0 108 #define ISP_HAS_NOT_SIMD_IS8 0 109 110 /* ICache */ 111 #define ISP_ICACHE 1 112 #define ISP_ICACHE_ONLY 0 113 #define ISP_ICACHE_PREFETCH 1 114 #define ISP_ICACHE_INDEX_BITS 8 115 #define ISP_ICACHE_SET_BITS 5 116 #define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 117 118 /* Experimental Flags */ 119 #define ISP_EXP_1 0 120 #define ISP_EXP_2 0 121 #define ISP_EXP_3 0 122 #define ISP_EXP_4 0 123 #define ISP_EXP_5 0 124 #define ISP_EXP_6 0 125 126 /* Derived values */ 127 #define ISP_LOG2_PMEM_WIDTH 10 128 #define ISP_VEC_WIDTH 896 129 #define ISP_SLICE_WIDTH 56 130 #define ISP_VMEM_WIDTH 896 131 #define ISP_VMEM_ALIGN 128 132 #define ISP_SIMDLSU 1 133 #define ISP_LSU_IMM_BITS 12 134 135 /* convenient shortcuts for software*/ 136 #define ISP_NWAY ISP_VEC_NELEMS 137 #define NBITS ISP_VEC_ELEMBITS 138 139 #define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b)) 140 141 #define ISP_VEC_ALIGN ISP_VMEM_ALIGN 142 143 /* register file sizes */ 144 #define ISP_RF0_SIZE 64 145 #define ISP_RF1_SIZE 16 146 #define ISP_RF2_SIZE 64 147 #define ISP_RF3_SIZE 4 148 #define ISP_RF4_SIZE 64 149 #define ISP_RF5_SIZE 16 150 #define ISP_RF6_SIZE 16 151 #define ISP_RF7_SIZE 16 152 #define ISP_RF8_SIZE 16 153 #define ISP_RF9_SIZE 16 154 #define ISP_RF10_SIZE 16 155 #define ISP_RF11_SIZE 16 156 157 #define ISP_SRF1_SIZE 4 158 #define ISP_SRF2_SIZE 64 159 #define ISP_SRF3_SIZE 64 160 #define ISP_SRF4_SIZE 32 161 #define ISP_SRF5_SIZE 64 162 #define ISP_FRF0_SIZE 16 163 #define ISP_FRF1_SIZE 4 164 #define ISP_FRF2_SIZE 16 165 #define ISP_FRF3_SIZE 4 166 #define ISP_FRF4_SIZE 4 167 #define ISP_FRF5_SIZE 8 168 #define ISP_FRF6_SIZE 4 169 /* register file read latency */ 170 #define ISP_VRF1_READ_LAT 1 171 #define ISP_VRF2_READ_LAT 1 172 #define ISP_VRF3_READ_LAT 1 173 #define ISP_VRF4_READ_LAT 1 174 #define ISP_VRF5_READ_LAT 1 175 #define ISP_VRF6_READ_LAT 1 176 #define ISP_VRF7_READ_LAT 1 177 #define ISP_VRF8_READ_LAT 1 178 #define ISP_SRF1_READ_LAT 1 179 #define ISP_SRF2_READ_LAT 1 180 #define ISP_SRF3_READ_LAT 1 181 #define ISP_SRF4_READ_LAT 1 182 #define ISP_SRF5_READ_LAT 1 183 #define ISP_SRF5_READ_LAT 1 184 /* immediate sizes */ 185 #define ISP_IS1_IMM_BITS 14 186 #define ISP_IS2_IMM_BITS 13 187 #define ISP_IS3_IMM_BITS 14 188 #define ISP_IS4_IMM_BITS 14 189 #define ISP_IS5_IMM_BITS 9 190 #define ISP_IS6_IMM_BITS 16 191 #define ISP_IS7_IMM_BITS 9 192 #define ISP_IS8_IMM_BITS 16 193 #define ISP_IS9_IMM_BITS 11 194 /* fifo depths */ 195 #define ISP_IF_FIFO_DEPTH 0 196 #define ISP_IF_B_FIFO_DEPTH 0 197 #define ISP_DMA_FIFO_DEPTH 0 198 #define ISP_OF_FIFO_DEPTH 0 199 #define ISP_GDC_FIFO_DEPTH 0 200 #define ISP_SCL_FIFO_DEPTH 0 201 #define ISP_GPFIFO_FIFO_DEPTH 0 202 #define ISP_SP_FIFO_DEPTH 0 203