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23 ======================= end_copyright_notice ==================================*/
24 //!
25 //! \file codechal_hw_xe_hpm.cpp
26 //! \brief Implements HW interface layer for dg2 used on all OSs.
27 //! \details Implements HW interface layer for dg2 to be used on on all operating systems/DDIs, across CODECHAL components.
28 //! This module must not contain any OS dependent code.
29 //!
30
31 #include "codechal_hw_xe_hpm.h"
32 #include "codechal_hw_g12_X.h"
33 #include "mhw_render_g12_X.h"
34 #include "mhw_vdbox_hcp_hwcmd_xe_hpm.h" // temporary include for calculating size of various hardware commands
35 #include "mhw_vdbox_vdenc_g12_X.h"
36 #include "mhw_vdbox_hcp_g12_X.h"
37 #include "media_interfaces_xehp_sdv.h"// temporary include for getting avp interface
38 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
39 #include "Xe_Hpm_Film_Grain.h"
40 #endif
41
PrepareCmdSize(CODECHAL_FUNCTION codecFunction)42 void CodechalHwInterfaceXe_Hpm::PrepareCmdSize(CODECHAL_FUNCTION codecFunction)
43 {
44 m_bltState = MOS_New(BltStateXe_Xpm, m_osInterface);
45 if(m_bltState != nullptr)
46 {
47 m_bltState->Initialize();
48 }
49 else
50 {
51 MHW_ASSERTMESSAGE("Invalid(nullptr) BltStateXe_Xpm!");
52 }
53
54 InitCacheabilityControlSettings(codecFunction);
55
56 m_isVdencSuperSliceEnabled = true;
57
58 m_ssEuTable = m_defaultSsEuLutG12;
59
60 // Set platform dependent parameters
61 m_sizeOfCmdBatchBufferEnd = mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
62 m_sizeOfCmdMediaReset = mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 8;
63 m_vdencBrcImgStateBufferSize = 80
64 + mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize
65 + 92
66 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
67
68 m_vdencBatchBuffer1stGroupSize = mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_PIPE_MODE_SELECT_CMD::byteSize
69 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 2
70 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
71
72 m_vdencBatchBuffer2ndGroupSize = 132
73 + mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_PIC_STATE_CMD::byteSize
74 + 248
75 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
76
77 m_vdencReadBatchBufferSize =
78 m_vdenc2ndLevelBatchBufferSize = m_vdencBatchBuffer1stGroupSize
79 + m_vdencBatchBuffer2ndGroupSize
80 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES
81 * (2 * mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_WEIGHTOFFSET_STATE_CMD::byteSize
82 + mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_SLICE_STATE_CMD::byteSize
83 + 3 * mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_PAK_INSERT_OBJECT_CMD::byteSize
84 + 28
85 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize
86 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
87
88 m_HucStitchCmdBatchBufferSize = 7 * 4
89 + 14 * 4
90 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
91
92 // HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
93 m_vdencBatchBufferPerSliceConstSize = mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_SLICE_STATE_CMD::byteSize
94 + mhw::vdbox::hcp::xe_xpm_base::xe_hpm::Cmd::HCP_PAK_INSERT_OBJECT_CMD::byteSize // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
95 + 28
96 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
97
98 // Set to size of the BRC update command buffer, since it is larger than BRC Init/ PAK integration commands
99 m_hucCommandBufferSize = mhw_vdbox_huc_g12_X::HUC_IMEM_STATE_CMD::byteSize
100 + mhw_vdbox_huc_g12_X::HUC_PIPE_MODE_SELECT_CMD::byteSize
101 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 3
102 + mhw_vdbox_huc_g12_X::HUC_DMEM_STATE_CMD::byteSize
103 + mhw_vdbox_huc_g12_X::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize
104 + mhw_vdbox_huc_g12_X::HUC_STREAM_OBJECT_CMD::byteSize
105 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize
106 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize
107 + mhw_vdbox_huc_g12_X::HUC_START_CMD::byteSize
108 + mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize
109 + mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize
110 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 2
111 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 2
112 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
113
114 m_maxKernelLoadCmdSize =
115 mhw_mi_g12_X::PIPE_CONTROL_CMD::byteSize +
116 mhw_render_g12_X::PIPELINE_SELECT_CMD::byteSize +
117 mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize +
118 mhw_render_g12_X::STATE_BASE_ADDRESS_CMD::byteSize +
119 mhw_render_g12_X::MEDIA_VFE_STATE_CMD::byteSize +
120 mhw_render_g12_X::MEDIA_CURBE_LOAD_CMD::byteSize +
121 mhw_render_g12_X::MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD::byteSize +
122 mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize +
123 mhw_render_g12_X::MEDIA_OBJECT_WALKER_CMD::byteSize +
124 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize;
125
126 m_sizeOfCmdMediaObject = mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize;
127 m_sizeOfCmdMediaStateFlush = mhw_mi_g12_X::MEDIA_STATE_FLUSH_CMD::byteSize;
128 }
129
CodechalHwInterfaceXe_Hpm(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces,bool disableScalability)130 CodechalHwInterfaceXe_Hpm::CodechalHwInterfaceXe_Hpm(
131 PMOS_INTERFACE osInterface,
132 CODECHAL_FUNCTION codecFunction,
133 MhwInterfaces *mhwInterfaces,
134 bool disableScalability)
135 : CodechalHwInterfaceG12(osInterface, codecFunction, mhwInterfaces, disableScalability)
136 {
137 CODECHAL_HW_FUNCTION_ENTER;
138 m_avpInterface = static_cast<MhwInterfacesXehp_Sdv*>(mhwInterfaces)->m_avpInterface;
139 PrepareCmdSize(codecFunction);
140 }
141
GetVdencPictureSecondLevelCommandsSize(uint32_t mode,uint32_t * commandsSize)142 MOS_STATUS CodechalHwInterfaceXe_Hpm::GetVdencPictureSecondLevelCommandsSize(
143 uint32_t mode,
144 uint32_t *commandsSize)
145 {
146 CODECHAL_HW_FUNCTION_ENTER;
147
148 uint32_t commands = 0;
149
150 MHW_MI_CHK_NULL(m_hcpInterface);
151 MHW_MI_CHK_NULL(m_vdencInterface);
152
153 uint32_t standard = CodecHal_GetStandardFromMode(mode);
154
155 if (standard == CODECHAL_VP9)
156 {
157 commands += m_hcpInterface->GetHcpVp9PicStateCommandSize();
158 commands += m_hcpInterface->GetHcpVp9SegmentStateCommandSize() * 8;
159 commands += 132;
160 commands += 248;
161 commands += m_sizeOfCmdBatchBufferEnd;
162 commands += 24; // padding for alignment on 64
163 }
164 else
165 {
166 MHW_ASSERTMESSAGE("Unsupported encode mode.");
167 return MOS_STATUS_UNKNOWN;
168 }
169
170 *commandsSize = commands;
171
172 return MOS_STATUS_SUCCESS;
173 }
174
GetFilmGrainKernelInfo(uint8_t * & kernelBase,uint32_t & kernelSize)175 MOS_STATUS CodechalHwInterfaceXe_Hpm::GetFilmGrainKernelInfo(
176 uint8_t*& kernelBase,
177 uint32_t& kernelSize)
178 {
179 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
180
181 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
182 kernelBase = (uint8_t*)XE_HPM_FILM_GRAIN;
183 kernelSize = XE_HPM_FILM_GRAIN_SIZE;
184 #else
185 kernelBase = nullptr;
186 kernelSize = 0;
187 #endif
188
189 return eStatus;
190 }
191
UsesRenderEngine(CODECHAL_FUNCTION codecFunction,uint32_t standard)192 bool CodechalHwInterfaceXe_Hpm::UsesRenderEngine(CODECHAL_FUNCTION codecFunction, uint32_t standard)
193 {
194 if (codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK && standard == CODECHAL_AV1)
195 return false;
196 else
197 return CodechalHwInterface::UsesRenderEngine(codecFunction, standard);
198 }
199
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])200 MOS_STATUS CodechalHwInterfaceXe_Hpm::SetCacheabilitySettings(
201 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
202 {
203 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
204
205 CODECHAL_HW_FUNCTION_ENTER;
206
207 if (m_mfxInterface)
208 {
209 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->SetCacheabilitySettings(cacheabilitySettings));
210 }
211 if (GetHcpInterfaceNext())
212 {
213 CODECHAL_HW_CHK_STATUS_RETURN(GetHcpInterfaceNext()->SetCacheabilitySettings(cacheabilitySettings));
214 }
215 if (m_hcpInterface)
216 {
217 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->SetCacheabilitySettings(cacheabilitySettings));
218 }
219 if (GetVdencInterfaceNext())
220 {
221 CODECHAL_HW_CHK_STATUS_RETURN(GetVdencInterfaceNext()->SetCacheabilitySettings(cacheabilitySettings));
222 }
223 else if (m_vdencInterface)
224 {
225 CODECHAL_HW_CHK_STATUS_RETURN(m_vdencInterface->SetCacheabilitySettings(cacheabilitySettings));
226 }
227 if (GetAvpInterfaceNext())
228 {
229 CODECHAL_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->SetCacheabilitySettings(cacheabilitySettings));
230 }
231 else if (m_avpInterface)
232 {
233 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->SetCacheabilitySettings(cacheabilitySettings));
234 }
235 if (GetHucInterfaceNext())
236 {
237 CODECHAL_HW_CHK_STATUS_RETURN(GetHucInterfaceNext()->SetCacheabilitySettings(cacheabilitySettings));
238 }
239 else if (m_hucInterface)
240 {
241 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->SetCacheabilitySettings(cacheabilitySettings));
242 }
243
244 return eStatus;
245 }
246
GetAvpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)247 MOS_STATUS CodechalHwInterfaceXe_Hpm::GetAvpStateCommandSize(
248 uint32_t mode,
249 uint32_t *commandsSize,
250 uint32_t *patchListSize,
251 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
252 {
253 CODECHAL_HW_FUNCTION_ENTER;
254
255 //calculate AVP related commands size
256 uint32_t avpCommandsSize = 0;
257 uint32_t avpPatchListSize = 0;
258 uint32_t cpCmdsize = 0;
259 uint32_t cpPatchListSize = 0;
260
261
262 if (GetAvpInterfaceNext())
263 {
264 CODECHAL_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->GetAvpStateCmdSize(
265 (uint32_t *)&avpCommandsSize,
266 (uint32_t *)&avpPatchListSize,
267 params));
268 }
269 else if (m_avpInterface)
270 {
271 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->GetAvpStateCommandSize(
272 (uint32_t *)&avpCommandsSize,
273 (uint32_t *)&avpPatchListSize,
274 params));
275 }
276
277 if (m_cpInterface)
278 {
279 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
280 }
281
282 //Calc final command size
283 *commandsSize = avpCommandsSize + cpCmdsize;
284 *patchListSize = avpPatchListSize + cpPatchListSize;
285
286 return MOS_STATUS_SUCCESS;
287 }
288
289
GetAvpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)290 MOS_STATUS CodechalHwInterfaceXe_Hpm::GetAvpPrimitiveCommandSize(
291 uint32_t mode,
292 uint32_t *commandsSize,
293 uint32_t *patchListSize)
294 {
295 CODECHAL_HW_FUNCTION_ENTER;
296
297 //calculate AVP related commands size
298 uint32_t avpCommandsSize = 0;
299 uint32_t avpPatchListSize = 0;
300 uint32_t cpCmdsize = 0;
301 uint32_t cpPatchListSize = 0;
302
303
304 if (GetAvpInterfaceNext())
305 {
306 MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams;
307 CODECHAL_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->GetAvpPrimitiveCmdSize(
308 (uint32_t*)&avpCommandsSize,
309 (uint32_t*)&avpPatchListSize,
310 &stateCmdSizeParams));
311 }
312 else if (m_avpInterface)
313 {
314 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->GetAvpPrimitiveCommandSize(
315 (uint32_t*)&avpCommandsSize,
316 (uint32_t*)&avpPatchListSize));
317 }
318
319 if (m_cpInterface)
320 {
321 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
322 }
323
324 //Calc final command size
325 *commandsSize = avpCommandsSize + cpCmdsize;
326 *patchListSize = avpPatchListSize + cpPatchListSize;
327
328 return MOS_STATUS_SUCCESS;
329 }
330
CreateMediaCopy(PMOS_INTERFACE mosInterface)331 MediaCopyBaseState* CodechalHwInterfaceXe_Hpm::CreateMediaCopy(PMOS_INTERFACE mosInterface)
332 {
333 VP_FUNC_CALL();
334
335 MediaCopyBaseState* mediaCopy = nullptr;
336 PMOS_CONTEXT mos_context = nullptr;
337
338 if (mosInterface && mosInterface->pfnGetMosContext)
339 {
340 mosInterface->pfnGetMosContext(mosInterface, &mos_context);
341 }
342 mediaCopy = static_cast<MediaCopyBaseState*>(McpyDevice::CreateFactory(mos_context));
343
344 return mediaCopy;
345 }