1 /*
2 * Copyright (c) 2011-2024, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_hw.cpp
24 //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across CODECHAL components.
25 //!
26 #include "codechal_hw.h"
27 #include "codechal_setting.h"
28 #include "mos_os_cp_interface_specific.h"
29
CodechalHwInterface(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces,bool disableScalability)30 CodechalHwInterface::CodechalHwInterface(
31 PMOS_INTERFACE osInterface,
32 CODECHAL_FUNCTION codecFunction,
33 MhwInterfaces *mhwInterfaces,
34 bool disableScalability)
35 {
36 CODECHAL_HW_FUNCTION_ENTER;
37
38 // Basic intialization
39 m_osInterface = osInterface;
40
41 MOS_ZeroMemory(&m_platform, sizeof(PLATFORM));
42 m_osInterface->pfnGetPlatform(m_osInterface, &m_platform);
43
44 m_skuTable = m_osInterface->pfnGetSkuTable(m_osInterface);
45 m_waTable = m_osInterface->pfnGetWaTable(m_osInterface);
46
47 CODECHAL_HW_ASSERT(m_skuTable);
48 CODECHAL_HW_ASSERT(m_waTable);
49
50 // Init sub-interfaces
51 m_cpInterface = mhwInterfaces->m_cpInterface;
52 m_mfxInterface = mhwInterfaces->m_mfxInterface;
53 m_hcpInterface = mhwInterfaces->m_hcpInterface;
54 m_hucInterface = mhwInterfaces->m_hucInterface;
55 m_vdencInterface = mhwInterfaces->m_vdencInterface;
56 m_veboxInterface = mhwInterfaces->m_veboxInterface;
57 m_sfcInterface = mhwInterfaces->m_sfcInterface;
58 m_miInterface = mhwInterfaces->m_miInterface;
59 m_renderInterface = mhwInterfaces->m_renderInterface;
60 // Prevent double free
61 mhwInterfaces->m_cpInterface = nullptr;
62 mhwInterfaces->m_mfxInterface = nullptr;
63 mhwInterfaces->m_hcpInterface = nullptr;
64 mhwInterfaces->m_hucInterface = nullptr;
65 mhwInterfaces->m_vdencInterface = nullptr;
66 mhwInterfaces->m_veboxInterface = nullptr;
67 mhwInterfaces->m_sfcInterface = nullptr;
68 mhwInterfaces->m_miInterface = nullptr;
69 mhwInterfaces->m_renderInterface = nullptr;
70
71 m_stateHeapSettings = MHW_STATE_HEAP_SETTINGS();
72 m_disableScalability = disableScalability;
73
74 MOS_ZeroMemory(&m_hucDmemDummy, sizeof(m_hucDmemDummy));
75 MOS_ZeroMemory(&m_dummyStreamIn, sizeof(m_dummyStreamIn));
76 MOS_ZeroMemory(&m_dummyStreamOut, sizeof(m_dummyStreamOut));
77 MOS_ZeroMemory(&m_conditionalBbEndDummy, sizeof(m_conditionalBbEndDummy));
78 }
79
Create(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces,bool disableScalability)80 CodechalHwInterface *CodechalHwInterface::Create(
81 PMOS_INTERFACE osInterface,
82 CODECHAL_FUNCTION codecFunction,
83 MhwInterfaces *mhwInterfaces,
84 bool disableScalability)
85 {
86 return MOS_New(CodechalHwInterface,
87 osInterface, codecFunction, mhwInterfaces, disableScalability);
88 }
89
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])90 MOS_STATUS CodechalHwInterface::SetCacheabilitySettings(
91 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
92 {
93 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
94
95 CODECHAL_HW_FUNCTION_ENTER;
96
97 if (m_mfxInterface)
98 {
99 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->SetCacheabilitySettings(cacheabilitySettings));
100 }
101 if (m_hcpInterface)
102 {
103 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->SetCacheabilitySettings(cacheabilitySettings));
104 }
105 if (m_vdencInterface)
106 {
107 CODECHAL_HW_CHK_STATUS_RETURN(m_vdencInterface->SetCacheabilitySettings(cacheabilitySettings));
108 }
109 if (m_hucInterface)
110 {
111 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->SetCacheabilitySettings(cacheabilitySettings));
112 }
113 return eStatus;
114 }
115
SetRowstoreCachingOffsets(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)116 MOS_STATUS CodechalHwInterface::SetRowstoreCachingOffsets(
117 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)
118 {
119 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
120
121 CODECHAL_HW_FUNCTION_ENTER;
122
123 if (m_vdencInterface)
124 {
125 CODECHAL_HW_CHK_STATUS_RETURN(m_vdencInterface->GetRowstoreCachingAddrs(rowstoreParams));
126 }
127 if (m_mfxInterface)
128 {
129 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->GetRowstoreCachingAddrs(rowstoreParams));
130 }
131 if (m_hcpInterface)
132 {
133 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->GetRowstoreCachingAddrs(rowstoreParams));
134 }
135
136 return eStatus;
137 }
138
InitCacheabilityControlSettings(CODECHAL_FUNCTION codecFunction)139 MOS_STATUS CodechalHwInterface::InitCacheabilityControlSettings(
140 CODECHAL_FUNCTION codecFunction)
141 {
142 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
143
144 CODECHAL_HW_FUNCTION_ENTER;
145
146 CODECHAL_HW_CHK_NULL_RETURN(m_osInterface);
147
148 for (uint32_t i = MOS_CODEC_RESOURCE_USAGE_BEGIN_CODEC + 1; i < MOS_CODEC_RESOURCE_USAGE_END_CODEC; i++)
149 {
150 CODECHAL_HW_CHK_STATUS_RETURN(CachePolicyGetMemoryObject(
151 (MOS_HW_RESOURCE_DEF)i));
152 }
153
154 SetCacheabilitySettings(m_cacheabilitySettings);
155
156 // This code needs to be removed
157 PMHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings = &m_cacheabilitySettings[0];
158 bool l3CachingEnabled = !m_osInterface->bSimIsActive;
159
160 if (m_checkTargetCache)
161 {
162 l3CachingEnabled =
163 ((cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_CURR_ENCODE].Gen8.TargetCache == 0x3) ||
164 (cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Gen8.TargetCache == 0x3) ||
165 (cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Gen8.TargetCache == 0x3) ||
166 (cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_HME_DOWNSAMPLED_ENCODE].Gen8.TargetCache == 0x3));
167 }
168
169 if (m_checkBankCount)
170 {
171 CODECHAL_HW_CHK_NULL_RETURN(m_osInterface);
172 auto gtSysInfo = m_osInterface->pfnGetGtSystemInfo(m_osInterface);
173 CODECHAL_HW_CHK_NULL_RETURN(gtSysInfo);
174
175 l3CachingEnabled = (gtSysInfo->L3BankCount != 0 || gtSysInfo->L3CacheSizeInKb != 0);
176 }
177
178 if (l3CachingEnabled)
179 {
180 InitL3CacheSettings();
181 }
182
183 return eStatus;
184 }
185
InitL3CacheSettings()186 MOS_STATUS CodechalHwInterface::InitL3CacheSettings()
187 {
188
189 // Get default L3 cache settings
190 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->EnableL3Caching(nullptr));
191
192 #if (_DEBUG || _RELEASE_INTERNAL)
193 // Override default L3 cache settings
194 auto l3CacheConfig =
195 m_renderInterface->GetL3CacheConfig();
196 MHW_RENDER_ENGINE_L3_CACHE_SETTINGS l3Overrides;
197 CODECHAL_HW_CHK_STATUS_RETURN(InitL3ControlUserFeatureSettings(
198 l3CacheConfig,
199 &l3Overrides));
200 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->EnableL3Caching(
201 &l3Overrides));
202 #endif // (_DEBUG || _RELEASE_INTERNAL)
203
204 return MOS_STATUS_SUCCESS;
205 }
206
CachePolicyGetMemoryObject(MOS_HW_RESOURCE_DEF mosUsage)207 MOS_STATUS CodechalHwInterface::CachePolicyGetMemoryObject(
208 MOS_HW_RESOURCE_DEF mosUsage)
209 {
210 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
211
212 m_cacheabilitySettings[mosUsage].Value =
213 (m_osInterface->pfnCachePolicyGetMemoryObject(
214 mosUsage,
215 m_osInterface->pfnGetGmmClientContext(m_osInterface))).DwordValue;
216
217 m_cacheabilitySettings[mosUsage].Value = ComposeSurfaceCacheabilityControl(
218 mosUsage,
219 codechalUncacheableWa);
220
221 return eStatus;
222 }
223
GetMfxStateCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool shortFormat)224 MOS_STATUS CodechalHwInterface::GetMfxStateCommandsDataSize(
225 uint32_t mode,
226 uint32_t *commandsSize,
227 uint32_t *patchListSize,
228 bool shortFormat)
229 {
230 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
231
232 CODECHAL_HW_FUNCTION_ENTER;
233
234 uint32_t cpCmdsize = 0;
235 uint32_t cpPatchListSize = 0;
236
237 if (m_mfxInterface)
238 {
239 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->GetMfxStateCommandsDataSize(
240 mode, (uint32_t*)commandsSize, (uint32_t*)patchListSize, shortFormat ? true : false));
241
242 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
243 }
244 *commandsSize += (uint32_t)cpCmdsize;
245 *patchListSize += (uint32_t)cpPatchListSize;
246
247 return eStatus;
248 }
249
GetMfxPrimitiveCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)250 MOS_STATUS CodechalHwInterface::GetMfxPrimitiveCommandsDataSize(
251 uint32_t mode,
252 uint32_t *commandsSize,
253 uint32_t *patchListSize,
254 bool modeSpecific)
255 {
256 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
257
258 CODECHAL_HW_FUNCTION_ENTER;
259
260 uint32_t cpCmdsize = 0;
261 uint32_t cpPatchListSize = 0;
262
263 if (m_mfxInterface)
264 {
265 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->GetMfxPrimitiveCommandsDataSize(
266 mode, (uint32_t*)commandsSize, (uint32_t*)patchListSize, modeSpecific ? true : false));
267
268 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
269 }
270
271 *commandsSize += (uint32_t)cpCmdsize;
272 *patchListSize += (uint32_t)cpPatchListSize;
273
274 return eStatus;
275 }
276
GetHxxStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)277 MOS_STATUS CodechalHwInterface::GetHxxStateCommandSize(
278 uint32_t mode,
279 uint32_t *commandsSize,
280 uint32_t *patchListSize,
281 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
282 {
283 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
284
285 CODECHAL_HW_FUNCTION_ENTER;
286
287 uint32_t standard = CodecHal_GetStandardFromMode(mode);
288
289 uint32_t hcpCommandsSize = 0;
290 uint32_t hcpPatchListSize = 0;
291 uint32_t cpCmdsize = 0;
292 uint32_t cpPatchListSize = 0;
293
294 if (m_hcpInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
295 {
296 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->GetHcpStateCommandSize(
297 mode, (uint32_t*)&hcpCommandsSize, (uint32_t*)&hcpPatchListSize, params));
298
299 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
300 }
301
302 uint32_t hucCommandsSize = 0;
303 uint32_t hucPatchListSize = 0;
304
305 if (m_hucInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_CENC || standard == CODECHAL_VP9 || standard == CODECHAL_AVC))
306 {
307 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->GetHucStateCommandSize(
308 mode, (uint32_t*)&hucCommandsSize, (uint32_t*)&hucPatchListSize, params));
309 }
310
311 *commandsSize = hcpCommandsSize + hucCommandsSize + (uint32_t)cpCmdsize;
312 *patchListSize = hcpPatchListSize + hucPatchListSize + (uint32_t)cpPatchListSize;
313
314 return eStatus;
315 }
316
GetHxxPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)317 MOS_STATUS CodechalHwInterface::GetHxxPrimitiveCommandSize(
318 uint32_t mode,
319 uint32_t *commandsSize,
320 uint32_t *patchListSize,
321 bool modeSpecific)
322 {
323 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
324
325 CODECHAL_HW_FUNCTION_ENTER;
326
327 uint32_t standard = CodecHal_GetStandardFromMode(mode);
328
329 uint32_t hcpCommandsSize = 0;
330 uint32_t hcpPatchListSize = 0;
331 uint32_t cpCmdsize = 0;
332 uint32_t cpPatchListSize = 0;
333
334 if (m_hcpInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
335 {
336 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->GetHcpPrimitiveCommandSize(
337 mode, (uint32_t*)&hcpCommandsSize, (uint32_t*)&hcpPatchListSize, modeSpecific ? true : false));
338
339 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
340 }
341
342 uint32_t hucCommandsSize = 0;
343 uint32_t hucPatchListSize = 0;
344
345 if (m_hucInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_CENC || standard == CODECHAL_VP9))
346 {
347 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->GetHucPrimitiveCommandSize(
348 mode, (uint32_t*)&hucCommandsSize, (uint32_t*)&hucPatchListSize));
349 }
350
351 *commandsSize = hcpCommandsSize + hucCommandsSize + (uint32_t)cpCmdsize;
352 *patchListSize = hcpPatchListSize + hucPatchListSize + (uint32_t)cpPatchListSize;
353
354 return eStatus;
355 }
356
GetHcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)357 MOS_STATUS CodechalHwInterface::GetHcpStateCommandSize(
358 uint32_t mode,
359 uint32_t * commandsSize,
360 uint32_t * patchListSize,
361 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
362 {
363 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
364
365 CODECHAL_HW_FUNCTION_ENTER;
366
367 uint32_t standard = CodecHal_GetStandardFromMode(mode);
368
369 uint32_t hcpCommandsSize = 0;
370 uint32_t hcpPatchListSize = 0;
371 uint32_t cpCmdsize = 0;
372 uint32_t cpPatchListSize = 0;
373
374 if (m_hcpInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
375 {
376 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->GetHcpStateCommandSize(
377 mode, &hcpCommandsSize, &hcpPatchListSize, params));
378
379 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
380 }
381
382 *commandsSize = hcpCommandsSize + cpCmdsize;
383 *patchListSize = hcpPatchListSize + cpPatchListSize;
384
385 return eStatus;
386 }
387
GetHcpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)388 MOS_STATUS CodechalHwInterface::GetHcpPrimitiveCommandSize(
389 uint32_t mode,
390 uint32_t *commandsSize,
391 uint32_t *patchListSize,
392 bool modeSpecific)
393 {
394 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
395
396 CODECHAL_HW_FUNCTION_ENTER;
397
398 uint32_t standard = CodecHal_GetStandardFromMode(mode);
399
400 uint32_t hcpCommandsSize = 0;
401 uint32_t hcpPatchListSize = 0;
402 uint32_t cpCmdsize = 0;
403 uint32_t cpPatchListSize = 0;
404
405 if (m_hcpInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
406 {
407 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->GetHcpPrimitiveCommandSize(
408 mode, &hcpCommandsSize, &hcpPatchListSize, modeSpecific ? true : false));
409
410 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
411 }
412
413 *commandsSize = hcpCommandsSize + cpCmdsize;
414 *patchListSize = hcpPatchListSize + cpPatchListSize;
415
416 return eStatus;
417 }
418
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)419 MOS_STATUS CodechalHwInterface::GetHucStateCommandSize(
420 uint32_t mode,
421 uint32_t * commandsSize,
422 uint32_t * patchListSize,
423 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
424 {
425 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
426
427 CODECHAL_HW_FUNCTION_ENTER;
428
429 uint32_t standard = CodecHal_GetStandardFromMode(mode);
430 uint32_t hucCommandsSize = 0;
431 uint32_t hucPatchListSize = 0;
432 uint32_t cpCmdsize = 0;
433 uint32_t cpPatchListSize = 0;
434
435 if (m_hucInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_CENC || standard == CODECHAL_VP9
436 || standard == CODECHAL_AVC || standard == CODECHAL_MPEG2 || standard == CODECHAL_VC1 || standard == CODECHAL_JPEG))
437 {
438 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->GetHucStateCommandSize(
439 mode, &hucCommandsSize, &hucPatchListSize, params));
440
441 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
442 }
443
444 *commandsSize = hucCommandsSize + cpCmdsize;
445 *patchListSize = hucPatchListSize + cpPatchListSize;
446
447 return eStatus;
448 }
449
GetHucPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)450 MOS_STATUS CodechalHwInterface::GetHucPrimitiveCommandSize(
451 uint32_t mode,
452 uint32_t *commandsSize,
453 uint32_t *patchListSize)
454 {
455 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
456
457 CODECHAL_HW_FUNCTION_ENTER;
458
459 uint32_t standard = CodecHal_GetStandardFromMode(mode);
460 uint32_t hucCommandsSize = 0;
461 uint32_t hucPatchListSize = 0;
462 uint32_t cpCmdsize = 0;
463 uint32_t cpPatchListSize = 0;
464
465 if (m_hucInterface && (standard == CODECHAL_HEVC || standard == CODECHAL_CENC || standard == CODECHAL_VP9))
466 {
467 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->GetHucPrimitiveCommandSize(
468 mode, &hucCommandsSize, &hucPatchListSize));
469 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
470 }
471
472 *commandsSize = hucCommandsSize + cpCmdsize;
473 *patchListSize = hucPatchListSize + cpPatchListSize;
474
475 return eStatus;
476 }
477
GetVdencStateCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)478 MOS_STATUS CodechalHwInterface::GetVdencStateCommandsDataSize(
479 uint32_t mode,
480 uint32_t *commandsSize,
481 uint32_t *patchListSize)
482 {
483 CODECHAL_HW_FUNCTION_ENTER;
484
485 MHW_MI_CHK_NULL(m_miInterface);
486 MHW_MI_CHK_NULL(m_hcpInterface);
487 MHW_MI_CHK_NULL(m_vdencInterface);
488
489 uint32_t commands = 0;
490 uint32_t patchList = 0;
491
492 uint32_t standard = CodecHal_GetStandardFromMode(mode);
493
494 MHW_MI_CHK_STATUS(m_vdencInterface->GetVdencStateCommandsDataSize(
495 mode,
496 0,
497 &commands,
498 &patchList));
499
500 commands += m_sizeOfCmdMediaReset;
501
502 if (standard == CODECHAL_AVC)
503 {
504 commands += m_miInterface->GetMiFlushDwCmdSize();
505 commands += m_miInterface->GetMiBatchBufferStartCmdSize();
506 commands += m_sizeOfCmdBatchBufferEnd;
507 }
508 else if (standard == CODECHAL_HEVC)
509 {
510 commands += m_miInterface->GetMiFlushDwCmdSize();
511 commands += m_miInterface->GetMiBatchBufferStartCmdSize();
512 commands += m_hcpInterface->GetHcpHevcVp9RdoqStateCommandSize();
513 commands += m_sizeOfCmdBatchBufferEnd;
514 }
515 else if (standard == CODECHAL_VP9)
516 {
517 commands += m_miInterface->GetMiFlushDwCmdSize();
518 commands += m_miInterface->GetMiBatchBufferStartCmdSize();
519 }
520 else if (standard == CODECHAL_AV1)
521 {
522 commands += m_miInterface->GetMiFlushDwCmdSize();
523 commands += m_miInterface->GetMiBatchBufferStartCmdSize();
524 commands += m_sizeOfCmdBatchBufferEnd;
525 }
526 else
527 {
528 MHW_ASSERTMESSAGE("Unsupported encode mode.");
529 return MOS_STATUS_UNKNOWN;
530 }
531
532 *commandsSize = commands;
533 *patchListSize = patchList;
534
535 return MOS_STATUS_SUCCESS;
536 }
537
GetVdencPrimitiveCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)538 MOS_STATUS CodechalHwInterface::GetVdencPrimitiveCommandsDataSize(
539 uint32_t mode,
540 uint32_t *commandsSize,
541 uint32_t *patchListSize)
542 {
543 CODECHAL_HW_FUNCTION_ENTER;
544
545 MHW_MI_CHK_NULL(m_miInterface);
546 MHW_MI_CHK_NULL(m_hcpInterface);
547 MHW_MI_CHK_NULL(m_vdencInterface);
548
549 uint32_t commands = 0;
550 uint32_t patchList = 0;
551
552 MHW_MI_CHK_STATUS(m_vdencInterface->GetVdencPrimitiveCommandsDataSize(
553 mode,
554 &commands,
555 &patchList));
556
557 *commandsSize = commands;
558 *patchListSize = patchList;
559
560 return MOS_STATUS_SUCCESS;
561 }
562
GetVdencPictureSecondLevelCommandsSize(uint32_t mode,uint32_t * commandsSize)563 MOS_STATUS CodechalHwInterface::GetVdencPictureSecondLevelCommandsSize(
564 uint32_t mode,
565 uint32_t *commandsSize)
566 {
567 CODECHAL_HW_FUNCTION_ENTER;
568
569 uint32_t commands = 0;
570
571 MHW_MI_CHK_NULL(m_hcpInterface);
572 MHW_MI_CHK_NULL(m_vdencInterface);
573
574 uint32_t standard = CodecHal_GetStandardFromMode(mode);
575
576 if (standard == CODECHAL_VP9)
577 {
578 commands += m_hcpInterface->GetHcpVp9PicStateCommandSize();
579 commands += m_hcpInterface->GetHcpVp9SegmentStateCommandSize() * 8;
580 commands += 128;
581 commands += 220;
582 commands += m_sizeOfCmdBatchBufferEnd;
583 }
584 else
585 {
586 MHW_ASSERTMESSAGE("Unsupported encode mode.");
587 return MOS_STATUS_UNKNOWN;
588 }
589
590 *commandsSize = commands;
591
592 return MOS_STATUS_SUCCESS;
593 }
594
GetStreamoutCommandSize(uint32_t * commandsSize,uint32_t * patchListSize)595 MOS_STATUS CodechalHwInterface::GetStreamoutCommandSize(
596 uint32_t *commandsSize,
597 uint32_t *patchListSize)
598 {
599 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
600
601 CODECHAL_HW_FUNCTION_ENTER;
602
603 MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams;
604
605 stateCmdSizeParams.bShortFormat = false;
606 stateCmdSizeParams.bHucDummyStream = MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable);
607 CODECHAL_HW_CHK_STATUS_RETURN(GetHxxStateCommandSize(
608 CODECHAL_DECODE_MODE_CENC, // For cenc phase
609 commandsSize,
610 patchListSize,
611 &stateCmdSizeParams));
612
613 return eStatus;
614 }
615
Initialize(CodechalSetting * settings)616 MOS_STATUS CodechalHwInterface::Initialize(
617 CodechalSetting *settings)
618 {
619 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
620 MediaUserSettingSharedPtr userSettingPtr = nullptr;
621 uint32_t value = 0;
622
623 CODECHAL_HW_FUNCTION_ENTER;
624
625 if (UsesRenderEngine(settings->codecFunction, settings->standard) ||
626 CodecHalIsEnableFieldScaling(settings->codecFunction, settings->standard, settings->downsamplingHinted))
627 {
628 CODECHAL_HW_CHK_NULL_RETURN(m_renderInterface);
629
630 m_stateHeapSettings.m_ishBehavior = HeapManager::Behavior::clientControlled;
631 m_stateHeapSettings.m_dshBehavior = HeapManager::Behavior::destructiveExtend;
632 // As a performance optimization keep the DSH locked always,
633 // the ISH is only accessed at device creation and thus does not need to be locked
634 m_stateHeapSettings.m_keepDshLocked = true;
635 m_stateHeapSettings.dwDshIncrement = 2 * MOS_PAGE_SIZE;
636
637 if (m_stateHeapSettings.dwIshSize > 0 &&
638 m_stateHeapSettings.dwDshSize > 0 &&
639 m_stateHeapSettings.dwNumSyncTags > 0)
640 {
641 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->AllocateHeaps(
642 m_stateHeapSettings));
643 }
644 }
645
646 #if (_DEBUG || _RELEASE_INTERNAL)
647 userSettingPtr = m_osInterface->pfnGetUserSettingInstance(m_osInterface);
648 ReadUserSettingForDebug(
649 userSettingPtr,
650 value,
651 __MEDIA_USER_FEATURE_VALUE_SSEU_SETTING_OVERRIDE,
652 MediaUserSetting::Group::Device);
653
654 if (value != 0xDEADC0DE)
655 {
656 m_numRequestedEuSlicesOverride = value & 0xFF; // Bits 0-7
657 m_numRequestedSubSlicesOverride = (value >> 8) & 0xFF; // Bits 8-15
658 m_numRequestedEusOverride = (value >> 16) & 0xFFFF; // Bits 16-31
659 m_numRequestedOverride = true;
660 }
661 #endif
662
663 m_enableCodecMmc = !MEDIA_IS_WA(GetWaTable(), WaDisableCodecMmc);
664
665 return eStatus;
666 }
667
GetMediaObjectBufferSize(uint32_t numMbs,uint32_t inlineDataSize)668 uint32_t CodechalHwInterface::GetMediaObjectBufferSize(
669 uint32_t numMbs,
670 uint32_t inlineDataSize)
671 {
672 uint32_t maxSize = 0;
673
674 maxSize +=
675 (m_sizeOfCmdMediaObject + inlineDataSize) * numMbs +
676 m_sizeOfCmdMediaStateFlush +
677 m_sizeOfCmdBatchBufferEnd +
678 128; // extra padding needed for scaling
679
680 return maxSize;
681 }
682
AddVdencBrcImgBuffer(PMOS_RESOURCE vdencBrcImgBuffer,PMHW_VDBOX_AVC_IMG_PARAMS params)683 MOS_STATUS CodechalHwInterface::AddVdencBrcImgBuffer(
684 PMOS_RESOURCE vdencBrcImgBuffer,
685 PMHW_VDBOX_AVC_IMG_PARAMS params)
686 {
687 CODECHAL_HW_FUNCTION_ENTER;
688
689 MHW_MI_CHK_NULL(m_osInterface);
690 MHW_MI_CHK_NULL(m_mfxInterface);
691 MHW_MI_CHK_NULL(m_vdencInterface);
692
693 uint8_t *data = nullptr;
694 MOS_LOCK_PARAMS lockFlags;
695
696 uint32_t mfxAvcImgStateSize = m_mfxInterface->GetAvcImgStateSize();
697 uint32_t vdencAvcCostStateSize = m_vdencInterface->GetVdencAvcCostStateSize();
698 uint32_t vdencCmd3Size = m_vdencInterface->GetVdencCmd3Size();
699 uint32_t vdencAvcImgStateSize = m_vdencInterface->GetVdencAvcImgStateSize();
700
701 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
702 lockFlags.WriteOnly = 1;
703
704 data = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, vdencBrcImgBuffer, &lockFlags);
705 MHW_MI_CHK_NULL(data);
706
707 MOS_COMMAND_BUFFER constructedCmdBuf;
708
709 MOS_ZeroMemory(&constructedCmdBuf, sizeof(MOS_COMMAND_BUFFER));
710 constructedCmdBuf.pCmdBase = (uint32_t *)data;
711 constructedCmdBuf.iRemaining = mfxAvcImgStateSize + vdencAvcCostStateSize + vdencCmd3Size + vdencAvcImgStateSize;
712
713 // Set MFX_IMAGE_STATE command
714 constructedCmdBuf.pCmdPtr = (uint32_t *)data;
715 constructedCmdBuf.iOffset = 0;
716 MHW_MI_CHK_STATUS(m_mfxInterface->AddMfxAvcImgCmd(&constructedCmdBuf, nullptr, params));
717
718 // Set VDENC_COST_STATE command
719 constructedCmdBuf.pCmdPtr = (uint32_t *)(data + mfxAvcImgStateSize);
720 constructedCmdBuf.iOffset = mfxAvcImgStateSize;
721 MHW_MI_CHK_STATUS(m_vdencInterface->AddVdencAvcCostStateCmd(&constructedCmdBuf, nullptr, params));
722
723 // Set VDENC_CMD3 command
724 constructedCmdBuf.pCmdPtr = (uint32_t *)(data + mfxAvcImgStateSize + vdencAvcCostStateSize);
725 constructedCmdBuf.iOffset = mfxAvcImgStateSize + vdencAvcCostStateSize;
726 MHW_MI_CHK_STATUS(m_vdencInterface->AddVdencCmd3Cmd(&constructedCmdBuf, nullptr, params));
727
728 // Set VDENC_IMAGE_STATE command
729 constructedCmdBuf.pCmdPtr = (uint32_t *)(data + mfxAvcImgStateSize + vdencAvcCostStateSize + vdencCmd3Size);
730 constructedCmdBuf.iOffset = mfxAvcImgStateSize + vdencAvcCostStateSize + vdencCmd3Size;
731 MHW_MI_CHK_STATUS(m_vdencInterface->AddVdencImgStateCmd(&constructedCmdBuf, nullptr, params));
732
733 // Add batch buffer end insertion flag
734 m_miInterface->AddBatchBufferEndInsertionFlag(constructedCmdBuf);
735
736 if (data)
737 {
738 m_osInterface->pfnUnlockResource(
739 m_osInterface,
740 vdencBrcImgBuffer);
741 }
742
743 return MOS_STATUS_SUCCESS;
744 }
745
AddVdencSfdImgBuffer(PMOS_RESOURCE vdencSfdImgBuffer,PMHW_VDBOX_AVC_IMG_PARAMS params)746 MOS_STATUS CodechalHwInterface::AddVdencSfdImgBuffer(
747 PMOS_RESOURCE vdencSfdImgBuffer,
748 PMHW_VDBOX_AVC_IMG_PARAMS params)
749 {
750 CODECHAL_HW_FUNCTION_ENTER;
751
752 MHW_MI_CHK_NULL(m_osInterface);
753 MHW_MI_CHK_NULL(m_vdencInterface);
754
755 uint8_t *data = nullptr;
756 MOS_LOCK_PARAMS lockFlags;
757
758 uint32_t vdencAvcImgStateSize = m_vdencInterface->GetVdencAvcImgStateSize();
759
760 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
761 lockFlags.WriteOnly = 1;
762
763 data = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, vdencSfdImgBuffer, &lockFlags);
764 MHW_MI_CHK_NULL(data);
765
766 MOS_COMMAND_BUFFER constructedCmdBuf;
767
768 MOS_ZeroMemory(&constructedCmdBuf, sizeof(MOS_COMMAND_BUFFER));
769 constructedCmdBuf.pCmdBase = (uint32_t *)data;
770 constructedCmdBuf.pCmdPtr = (uint32_t *)data;
771 constructedCmdBuf.iOffset = 0;
772 constructedCmdBuf.iRemaining = vdencAvcImgStateSize + m_sizeOfCmdBatchBufferEnd;
773
774 MHW_MI_CHK_STATUS(m_vdencInterface->AddVdencImgStateCmd(&constructedCmdBuf, nullptr, params));
775
776 // Add batch buffer end insertion flag
777 constructedCmdBuf.pCmdPtr = (uint32_t *)(data + vdencAvcImgStateSize);
778 constructedCmdBuf.iOffset = vdencAvcImgStateSize;
779 constructedCmdBuf.iRemaining = m_sizeOfCmdBatchBufferEnd;
780 m_miInterface->AddBatchBufferEndInsertionFlag(constructedCmdBuf);
781
782 if (data)
783 {
784 m_osInterface->pfnUnlockResource(
785 m_osInterface,
786 vdencSfdImgBuffer);
787 }
788
789 return MOS_STATUS_SUCCESS;
790 }
791
GetKernelLoadCommandSize(uint32_t maxNumSurfaces)792 uint32_t CodechalHwInterface::GetKernelLoadCommandSize(
793 uint32_t maxNumSurfaces)
794 {
795 CODECHAL_HW_FUNCTION_ENTER;
796
797 MOS_UNUSED(maxNumSurfaces);
798
799 return m_maxKernelLoadCmdSize;
800 }
801
ResizeCommandBufferAndPatchList(uint32_t requestedCommandBufferSize,uint32_t requestedPatchListSize)802 MOS_STATUS CodechalHwInterface::ResizeCommandBufferAndPatchList(
803 uint32_t requestedCommandBufferSize,
804 uint32_t requestedPatchListSize)
805 {
806 CODECHAL_HW_FUNCTION_ENTER;
807
808 if (m_osInterface->bUsesCmdBufHeaderInResize)
809 {
810 return ResizeCommandBufferAndPatchListCmd(requestedCommandBufferSize, requestedPatchListSize);
811 }
812 else
813 {
814 return ResizeCommandBufferAndPatchListOs(requestedCommandBufferSize, requestedPatchListSize);
815 }
816 }
817
ResizeCommandBufferAndPatchListCmd(uint32_t requestedCommandBufferSize,uint32_t requestedPatchListSize)818 MOS_STATUS CodechalHwInterface::ResizeCommandBufferAndPatchListCmd(
819 uint32_t requestedCommandBufferSize,
820 uint32_t requestedPatchListSize)
821 {
822 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
823
824 CODECHAL_HW_FUNCTION_ENTER;
825
826 CODECHAL_HW_CHK_NULL_RETURN(m_miInterface);
827
828 MOS_COMMAND_BUFFER cmdBuffer;
829
830 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
831 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiNoop(&cmdBuffer, nullptr));
832 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
833 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnResizeCommandBufferAndPatchList(m_osInterface, requestedCommandBufferSize, requestedPatchListSize, 0));
834
835 return eStatus;
836 }
837
ResizeCommandBufferAndPatchListOs(uint32_t requestedCommandBufferSize,uint32_t requestedPatchListSize)838 MOS_STATUS CodechalHwInterface::ResizeCommandBufferAndPatchListOs(
839 uint32_t requestedCommandBufferSize,
840 uint32_t requestedPatchListSize)
841 {
842 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
843
844 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnResizeCommandBufferAndPatchList(m_osInterface, requestedCommandBufferSize, requestedPatchListSize, 0));
845
846 return eStatus;
847 }
848
WriteSyncTagToResource(PMOS_COMMAND_BUFFER cmdBuffer,PMOS_SYNC_PARAMS syncParams)849 MOS_STATUS CodechalHwInterface::WriteSyncTagToResource(
850 PMOS_COMMAND_BUFFER cmdBuffer,
851 PMOS_SYNC_PARAMS syncParams)
852 {
853 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
854
855 CODECHAL_HW_FUNCTION_ENTER;
856
857 CODECHAL_HW_CHK_NULL_RETURN(m_miInterface);
858 MOS_UNUSED(syncParams);
859
860 MHW_MI_STORE_DATA_PARAMS params;
861 PMOS_RESOURCE globalGpuContextSyncTagBuffer = nullptr;
862 uint32_t offset = 0;
863 uint32_t value = 0;
864
865 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnGetGpuStatusBufferResource(
866 m_osInterface,
867 globalGpuContextSyncTagBuffer));
868 CODECHAL_HW_CHK_NULL_RETURN(globalGpuContextSyncTagBuffer);
869
870 offset = m_osInterface->pfnGetGpuStatusTagOffset(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
871 value = m_osInterface->pfnGetGpuStatusTag(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
872
873 params.pOsResource = globalGpuContextSyncTagBuffer;
874 params.dwResourceOffset = offset;
875 params.dwValue = value;
876
877 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, ¶ms));
878
879 // Increment GPU Context Tag for next use
880 m_osInterface->pfnIncrementGpuStatusTag(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
881
882 return eStatus;
883 }
884
ComposeSurfaceCacheabilityControl(uint32_t cacheabiltySettingIdx,uint32_t cacheabilityTypeRequested)885 uint32_t CodechalHwInterface::ComposeSurfaceCacheabilityControl(
886 uint32_t cacheabiltySettingIdx,
887 uint32_t cacheabilityTypeRequested)
888 {
889 CODECHAL_HW_FUNCTION_ENTER;
890
891 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheSetting = m_cacheabilitySettings[cacheabiltySettingIdx];
892
893 if (m_noSeparateL3LlcCacheabilitySettings)
894 {
895 if (cacheabilityTypeRequested == codechalUncacheableWa)
896 {
897 if (cacheSetting.Gen8.TargetCache == CODECHAL_MO_TARGET_CACHE_ELLC)
898 {
899 //Check if the SKU doesn't have EDRAM
900 if (!MEDIA_IS_SKU(m_skuTable, FtrEDram))
901 {
902 // No eDRAM, set the caching to uncache
903 cacheSetting.Gen8.CacheControl = 1;
904 }
905 }
906 }
907 // No separate LLC and L3 cacheability settings in the memory control object, so just return the value
908 return (uint32_t)cacheSetting.Value;
909 }
910
911 return (uint32_t)m_cacheabilitySettings[cacheabiltySettingIdx].Value;
912 }
913
AddHucDummyStreamOut(PMOS_COMMAND_BUFFER cmdBuffer)914 MOS_STATUS CodechalHwInterface::AddHucDummyStreamOut(
915 PMOS_COMMAND_BUFFER cmdBuffer)
916 {
917 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
918
919 if (!MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable))
920 {
921 return eStatus;
922 }
923
924 CODECHAL_HW_FUNCTION_ENTER;
925
926 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
927 CODECHAL_HW_CHK_NULL_RETURN(m_miInterface);
928
929 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
930 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams;
931 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS indObjParams;
932 MHW_VDBOX_HUC_STREAM_OBJ_PARAMS streamObjParams;
933
934 if (Mos_ResourceIsNull(&m_dummyStreamOut))
935 {
936 MOS_LOCK_PARAMS lockFlags;
937 uint8_t* data;
938 MOS_ALLOC_GFXRES_PARAMS allocParamsForBufferLinear;
939
940 MOS_ZeroMemory(&allocParamsForBufferLinear, sizeof(MOS_ALLOC_GFXRES_PARAMS));
941 allocParamsForBufferLinear.Type = MOS_GFXRES_BUFFER;
942 allocParamsForBufferLinear.TileType = MOS_TILE_LINEAR;
943 allocParamsForBufferLinear.Format = Format_Buffer;
944
945 m_dmemBufSize = MHW_CACHELINE_SIZE;
946
947 allocParamsForBufferLinear.dwBytes = m_dmemBufSize;
948 allocParamsForBufferLinear.pBufName = "HucDmemBufferDummy";
949 CODECHAL_HW_CHK_STATUS_RETURN((MOS_STATUS)m_osInterface->pfnAllocateResource(
950 m_osInterface,
951 &allocParamsForBufferLinear,
952 &m_hucDmemDummy));
953 // set lock flag to WRITE_ONLY
954 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
955 lockFlags.WriteOnly = 1;
956 data =
957 (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, &m_hucDmemDummy, &lockFlags);
958 CODECHAL_HW_CHK_NULL_RETURN(data);
959 MOS_ZeroMemory(data, m_dmemBufSize);
960 *data = 8;
961 m_osInterface->pfnUnlockResource(m_osInterface, &m_hucDmemDummy);
962
963 allocParamsForBufferLinear.dwBytes = CODECHAL_CACHELINE_SIZE;
964
965 allocParamsForBufferLinear.pBufName = "HucDummyStreamInBuffer";
966 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnAllocateResource(
967 m_osInterface,
968 &allocParamsForBufferLinear,
969 &m_dummyStreamIn));
970 allocParamsForBufferLinear.pBufName = "HucDummyStreamOutBuffer";
971 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnAllocateResource(
972 m_osInterface,
973 &allocParamsForBufferLinear,
974 &m_dummyStreamOut));
975 }
976
977 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
978 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
979
980 // pipe mode select
981 pipeModeSelectParams.dwMediaSoftResetCounterValue = 2400;
982
983 // pass bit-stream buffer by Ind Obj Addr command. Set size to 1 for dummy stream
984 MOS_ZeroMemory(&indObjParams, sizeof(indObjParams));
985 indObjParams.presDataBuffer = &m_dummyStreamIn;
986 indObjParams.dwDataSize = 1;
987 indObjParams.presStreamOutObjectBuffer = &m_dummyStreamOut;
988 indObjParams.dwStreamOutObjectSize = 1;
989
990 // set stream object with stream out enabled
991 MOS_ZeroMemory(&streamObjParams, sizeof(streamObjParams));
992 streamObjParams.dwIndStreamInLength = 1;
993 streamObjParams.dwIndStreamInStartAddrOffset = 0;
994 streamObjParams.bHucProcessing = true;
995 streamObjParams.dwIndStreamOutStartAddrOffset = 0;
996 streamObjParams.bStreamOutEnable = 1;
997
998 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
999
1000 MHW_VDBOX_HUC_IMEM_STATE_PARAMS imemParams;
1001 MHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams;
1002 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams;
1003
1004 MOS_ZeroMemory(&imemParams, sizeof(imemParams));
1005 imemParams.dwKernelDescriptor = VDBOX_HUC_VDENC_BRC_INIT_KERNEL_DESCRIPTOR;
1006
1007 // set HuC DMEM param
1008 MOS_ZeroMemory(&dmemParams, sizeof(dmemParams));
1009 dmemParams.presHucDataSource = &m_hucDmemDummy;
1010 dmemParams.dwDataLength = m_dmemBufSize;
1011 dmemParams.dwDmemOffset = HUC_DMEM_OFFSET_RTOS_GEMS;
1012
1013 MOS_ZeroMemory(&virtualAddrParams, sizeof(virtualAddrParams));
1014 virtualAddrParams.regionParams[0].presRegion = &m_dummyStreamOut;
1015
1016 streamObjParams.bHucProcessing = true;
1017 streamObjParams.bStreamInEnable = 1;
1018
1019 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucImemStateCmd(cmdBuffer, &imemParams));
1020 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucPipeModeSelectCmd(cmdBuffer, &pipeModeSelectParams));
1021 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucDmemStateCmd(cmdBuffer, &dmemParams));
1022 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucVirtualAddrStateCmd(cmdBuffer, &virtualAddrParams));
1023 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucIndObjBaseAddrStateCmd(cmdBuffer, &indObjParams));
1024 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucStreamObjectCmd(cmdBuffer, &streamObjParams));
1025 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucStartCmd(cmdBuffer, true));
1026
1027 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
1028
1029 return eStatus;
1030
1031 }
1032
PerformHucStreamOut(CodechalHucStreamoutParams * hucStreamOutParams,PMOS_COMMAND_BUFFER cmdBuffer)1033 MOS_STATUS CodechalHwInterface::PerformHucStreamOut(
1034 CodechalHucStreamoutParams *hucStreamOutParams,
1035 PMOS_COMMAND_BUFFER cmdBuffer)
1036 {
1037 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1038
1039 CODECHAL_HW_FUNCTION_ENTER;
1040 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1041
1042 if (MEDIA_IS_SKU(m_skuTable, FtrEnableMediaKernels) && MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable))
1043 {
1044 CODECHAL_HW_CHK_STATUS_RETURN(AddHucDummyStreamOut(cmdBuffer));
1045 }
1046
1047 // pipe mode select
1048 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams;
1049 pipeModeSelectParams.Mode = hucStreamOutParams->mode;
1050 pipeModeSelectParams.dwMediaSoftResetCounterValue = 2400;
1051 pipeModeSelectParams.bStreamObjectUsed = true;
1052 pipeModeSelectParams.bStreamOutEnabled = true;
1053 if (hucStreamOutParams->segmentInfo == nullptr && m_osInterface->osCpInterface->IsCpEnabled())
1054 {
1055 // Disable protection control setting in huc drm
1056 pipeModeSelectParams.disableProtectionSetting = true;
1057 }
1058
1059 // Enlarge the stream in/out data size to avoid upper bound hit assert in HuC
1060 hucStreamOutParams->dataSize += hucStreamOutParams->inputRelativeOffset;
1061 hucStreamOutParams->streamOutObjectSize += hucStreamOutParams->outputRelativeOffset;
1062
1063 // pass bit-stream buffer by Ind Obj Addr command
1064 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS indObjParams;
1065 MOS_ZeroMemory(&indObjParams, sizeof(indObjParams));
1066 indObjParams.presDataBuffer = hucStreamOutParams->dataBuffer;
1067 indObjParams.dwDataSize = MOS_ALIGN_CEIL(hucStreamOutParams->dataSize, MHW_PAGE_SIZE);
1068 indObjParams.dwDataOffset = hucStreamOutParams->dataOffset;
1069 indObjParams.presStreamOutObjectBuffer = hucStreamOutParams->streamOutObjectBuffer;
1070 indObjParams.dwStreamOutObjectSize = MOS_ALIGN_CEIL(hucStreamOutParams->streamOutObjectSize, MHW_PAGE_SIZE);
1071 indObjParams.dwStreamOutObjectOffset = hucStreamOutParams->streamOutObjectOffset;
1072
1073 // set stream object with stream out enabled
1074 MHW_VDBOX_HUC_STREAM_OBJ_PARAMS streamObjParams;
1075 MOS_ZeroMemory(&streamObjParams, sizeof(streamObjParams));
1076 streamObjParams.dwIndStreamInLength = hucStreamOutParams->indStreamInLength;
1077 streamObjParams.dwIndStreamInStartAddrOffset = hucStreamOutParams->inputRelativeOffset;
1078 streamObjParams.dwIndStreamOutStartAddrOffset = hucStreamOutParams->outputRelativeOffset;
1079 streamObjParams.bHucProcessing = true;
1080 streamObjParams.bStreamInEnable = true;
1081 streamObjParams.bStreamOutEnable = true;
1082
1083 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucPipeModeSelectCmd(cmdBuffer, &pipeModeSelectParams));
1084 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucIndObjBaseAddrStateCmd(cmdBuffer, &indObjParams));
1085 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->AddHucStreamObjectCmd(cmdBuffer, &streamObjParams));
1086
1087 // This flag is always false if huc fw is not loaded.
1088 if (MEDIA_IS_SKU(m_skuTable, FtrEnableMediaKernels) &&
1089 MEDIA_IS_WA(m_waTable, WaHucStreamoutOnlyDisable))
1090 {
1091 CODECHAL_HW_CHK_STATUS_RETURN(AddHucDummyStreamOut(cmdBuffer));
1092 }
1093
1094 return eStatus;
1095 }
1096
UpdateSSEuForCmdBuffer(PMOS_COMMAND_BUFFER cmdBuffer,bool singleTaskPhaseSupported,bool lastTaskInPhase)1097 MOS_STATUS CodechalHwInterface::UpdateSSEuForCmdBuffer(
1098 PMOS_COMMAND_BUFFER cmdBuffer,
1099 bool singleTaskPhaseSupported,
1100 bool lastTaskInPhase)
1101 {
1102 CODECHAL_HW_FUNCTION_ENTER;
1103
1104 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1105
1106 if (singleTaskPhaseSupported && lastTaskInPhase)
1107 {
1108 PMOS_COMMAND_BUFFER_ATTRIBUTES attributes = &cmdBuffer->Attributes; // Base of the command buffer is where the command buffer header would be
1109
1110 // Update the SSEU realted values in the comand buffer header header with the final values in the HwInterface structure
1111 attributes->dwNumRequestedEUSlices = m_numRequestedEuSlices;
1112 attributes->dwNumRequestedSubSlices = m_numRequestedSubSlices;
1113 attributes->dwNumRequestedEUs = m_numRequestedEus;
1114 CODECHAL_HW_VERBOSEMESSAGE("CB Attributes Updated: S/SS/EU: %d/%d/%d.", m_numRequestedEuSlices, m_numRequestedSubSlices, m_numRequestedEus);
1115 }
1116
1117 // Clear the SSEU setting in HwInterface always for non-singletaskphase mode and after updating command buffer header for singletaskphase mode
1118 if ((!singleTaskPhaseSupported) || (singleTaskPhaseSupported && lastTaskInPhase))
1119 {
1120 m_numRequestedSubSlices = 0;
1121 m_numRequestedEus = 0;
1122 }
1123
1124 return MOS_STATUS_SUCCESS;
1125 }
1126
GetDefaultSSEuSetting(CODECHAL_MEDIA_STATE_TYPE mediaStateType,bool setRequestedSlices,bool setRequestedSubSlices,bool setRequestedEus)1127 MOS_STATUS CodechalHwInterface::GetDefaultSSEuSetting(
1128 CODECHAL_MEDIA_STATE_TYPE mediaStateType,
1129 bool setRequestedSlices,
1130 bool setRequestedSubSlices,
1131 bool setRequestedEus)
1132 {
1133 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1134
1135 CODECHAL_HW_FUNCTION_ENTER;
1136
1137 MOS_UNUSED(setRequestedSlices);
1138
1139 if (m_ssEuTable == nullptr) // SSEUTable may be nullptr if not initialized(for newer platforms) or not supported(on HSW). Its not an error, just return success.
1140 {
1141 return eStatus;
1142 }
1143
1144 if (mediaStateType >= m_numMediaStates)
1145 {
1146 return MOS_STATUS_INVALID_PARAMETER;
1147 }
1148
1149 #if (_DEBUG || _RELEASE_INTERNAL)
1150 if (m_numRequestedOverride)
1151 {
1152 m_numRequestedEuSlices = m_numRequestedEuSlicesOverride;
1153 m_numRequestedSubSlices = m_numRequestedSubSlicesOverride;
1154 m_numRequestedEus = m_numRequestedEusOverride;
1155 return eStatus;
1156 }
1157 #endif
1158
1159 CODECHAL_SSEU_SETTING const *ssEutable = m_ssEuTable + mediaStateType;
1160
1161 if (m_numRequestedEuSlices != CODECHAL_SLICE_SHUTDOWN_DEFAULT) // Num Slices will be set based on table only if it is not set to default (HALO)
1162 {
1163 if (m_numRequestedEuSlices < ssEutable->ui8NumSlices)
1164 {
1165 m_numRequestedEuSlices = ssEutable->ui8NumSlices;
1166 }
1167 }
1168 if (!setRequestedSubSlices) // If num Sub-Slices is already programmed, then don't change it
1169 {
1170 if (m_numRequestedSubSlices < ssEutable->ui8NumSubSlices)
1171 {
1172 m_numRequestedSubSlices = ssEutable->ui8NumSubSlices;
1173 }
1174 }
1175 if (!setRequestedEus) // If num EUs is already programmed, then don't change it
1176 {
1177 if (m_numRequestedEus < ssEutable->ui8NumEUs)
1178 {
1179 m_numRequestedEus = ssEutable->ui8NumEUs;
1180 }
1181 }
1182
1183 return eStatus;
1184 }
1185
CopyDataSourceWithDrv(CodechalDataCopyParams * dataCopyParams)1186 MOS_STATUS CodechalHwInterface::CopyDataSourceWithDrv(
1187 CodechalDataCopyParams *dataCopyParams)
1188 {
1189 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1190
1191 CODECHAL_HW_FUNCTION_ENTER;
1192 CODECHAL_HW_CHK_NULL_RETURN(dataCopyParams);
1193 CODECHAL_HW_CHK_NULL_RETURN(dataCopyParams->srcResource);
1194 CODECHAL_HW_CHK_NULL_RETURN(dataCopyParams->dstResource)
1195
1196 uint8_t* src = nullptr;
1197 uint8_t* dst = nullptr;
1198 MOS_LOCK_PARAMS lockFlags;
1199
1200 // initiate lock flags
1201 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
1202 lockFlags.ReadOnly = 1;
1203
1204 src = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, dataCopyParams->srcResource, &lockFlags);
1205 if (nullptr != src)
1206 {
1207 src += dataCopyParams->srcOffset;
1208
1209 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
1210 lockFlags.WriteOnly = 1;
1211
1212 dst = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, dataCopyParams->dstResource, &lockFlags);
1213 if (nullptr != dst)
1214 {
1215 dst += dataCopyParams->dstOffset;
1216 eStatus = MOS_SecureMemcpy(dst, dataCopyParams->dstSize, src, dataCopyParams->srcSize);
1217 if (eStatus != MOS_STATUS_SUCCESS)
1218 {
1219 CODECHAL_HW_ASSERTMESSAGE("Failed to copy memory.");
1220 return eStatus;
1221 }
1222
1223 m_osInterface->pfnUnlockResource(m_osInterface, dataCopyParams->dstResource);
1224 }
1225
1226 m_osInterface->pfnUnlockResource(m_osInterface, dataCopyParams->srcResource);
1227 }
1228
1229 return eStatus;
1230 }
1231
1232 #if (_DEBUG || _RELEASE_INTERNAL)
InitL3ControlUserFeatureSettings(MHW_RENDER_ENGINE_L3_CACHE_CONFIG * l3CacheConfig,MHW_RENDER_ENGINE_L3_CACHE_SETTINGS * l3Overrides)1233 MOS_STATUS CodechalHwInterface::InitL3ControlUserFeatureSettings(
1234 MHW_RENDER_ENGINE_L3_CACHE_CONFIG *l3CacheConfig,
1235 MHW_RENDER_ENGINE_L3_CACHE_SETTINGS *l3Overrides)
1236 {
1237 CODECHAL_HW_FUNCTION_ENTER;
1238
1239 CODECHAL_HW_CHK_NULL_RETURN(l3CacheConfig);
1240 CODECHAL_HW_CHK_NULL_RETURN(l3Overrides);
1241
1242 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
1243 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1244 userFeatureData.u32Data = l3CacheConfig->dwL3CacheCntlReg_Setting;
1245 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
1246 MOS_UserFeature_ReadValue_ID(
1247 nullptr,
1248 __MEDIA_USER_FEATURE_VALUE_ENCODE_L3_CACHE_CNTLREG_OVERRIDE_ID,
1249 &userFeatureData,
1250 m_osInterface->pOsContext);
1251 l3Overrides->dwCntlReg = (uint32_t)userFeatureData.i32Data;
1252
1253 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1254 userFeatureData.u32Data = l3CacheConfig->dwL3CacheCntlReg2_Setting;
1255 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
1256 MOS_UserFeature_ReadValue_ID(
1257 nullptr,
1258 __MEDIA_USER_FEATURE_VALUE_ENCODE_L3_CACHE_CNTLREG2_OVERRIDE_ID,
1259 &userFeatureData,
1260 m_osInterface->pOsContext);
1261 l3Overrides->dwCntlReg2 = (uint32_t)userFeatureData.i32Data;
1262
1263 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1264 userFeatureData.u32Data = l3CacheConfig->dwL3CacheCntlReg3_Setting;
1265 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
1266 MOS_UserFeature_ReadValue_ID(
1267 nullptr,
1268 __MEDIA_USER_FEATURE_VALUE_ENCODE_L3_CACHE_CNTLREG3_OVERRIDE_ID,
1269 &userFeatureData,
1270 m_osInterface->pOsContext);
1271 l3Overrides->dwCntlReg3 = (uint32_t)userFeatureData.i32Data;
1272
1273 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1274 userFeatureData.u32Data = l3CacheConfig->dwL3CacheSqcReg1_Setting;
1275 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
1276 MOS_UserFeature_ReadValue_ID(
1277 nullptr,
1278 __MEDIA_USER_FEATURE_VALUE_ENCODE_L3_CACHE_SQCREG1_OVERRIDE_ID,
1279 &userFeatureData,
1280 m_osInterface->pOsContext);
1281 l3Overrides->dwSqcReg1 = (uint32_t)userFeatureData.i32Data;
1282
1283 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1284 userFeatureData.u32Data = l3CacheConfig->dwL3CacheSqcReg4_Setting;
1285 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
1286 MOS_UserFeature_ReadValue_ID(
1287 nullptr,
1288 __MEDIA_USER_FEATURE_VALUE_ENCODE_L3_CACHE_SQCREG4_OVERRIDE_ID,
1289 &userFeatureData,
1290 m_osInterface->pOsContext);
1291 l3Overrides->dwSqcReg4 = (uint32_t)userFeatureData.i32Data;
1292
1293 if (l3CacheConfig->bL3LRA1Reset)
1294 {
1295 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1296 userFeatureData.u32Data = l3CacheConfig->dwL3LRA1Reg_Setting;
1297 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
1298 MOS_UserFeature_ReadValue_ID(
1299 nullptr,
1300 __MEDIA_USER_FEATURE_VALUE_ENCODE_L3_LRA_1_REG1_OVERRIDE_ID,
1301 &userFeatureData,
1302 m_osInterface->pOsContext);
1303 l3Overrides->dwLra1Reg = (uint32_t)userFeatureData.i32Data;
1304 }
1305
1306 return MOS_STATUS_SUCCESS;
1307 }
1308 #endif // _DEBUG || _RELEASE_INTERNAL
1309
SendHwSemaphoreWaitCmd(PMOS_RESOURCE semaMem,uint32_t semaData,MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION opCode,PMOS_COMMAND_BUFFER cmdBuffer,uint32_t semaMemOffset)1310 MOS_STATUS CodechalHwInterface::SendHwSemaphoreWaitCmd(
1311 PMOS_RESOURCE semaMem,
1312 uint32_t semaData,
1313 MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION opCode,
1314 PMOS_COMMAND_BUFFER cmdBuffer,
1315 uint32_t semaMemOffset)
1316 {
1317 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1318
1319 CODECHAL_HW_FUNCTION_ENTER;
1320
1321 MHW_MI_SEMAPHORE_WAIT_PARAMS miSemaphoreWaitParams;
1322 MOS_ZeroMemory((&miSemaphoreWaitParams), sizeof(miSemaphoreWaitParams));
1323 miSemaphoreWaitParams.presSemaphoreMem = semaMem;
1324 miSemaphoreWaitParams.bPollingWaitMode = true;
1325 miSemaphoreWaitParams.dwSemaphoreData = semaData;
1326 miSemaphoreWaitParams.CompareOperation = opCode;
1327 miSemaphoreWaitParams.dwResourceOffset = semaMemOffset;
1328 eStatus = m_miInterface->AddMiSemaphoreWaitCmd(cmdBuffer, &miSemaphoreWaitParams);
1329
1330 return eStatus;
1331 }
1332
SendMiAtomicDwordCmd(PMOS_RESOURCE resource,uint32_t immData,MHW_COMMON_MI_ATOMIC_OPCODE opCode,PMOS_COMMAND_BUFFER cmdBuffer)1333 MOS_STATUS CodechalHwInterface::SendMiAtomicDwordCmd(
1334 PMOS_RESOURCE resource,
1335 uint32_t immData,
1336 MHW_COMMON_MI_ATOMIC_OPCODE opCode,
1337 PMOS_COMMAND_BUFFER cmdBuffer)
1338 {
1339 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1340
1341 CODECHAL_HW_FUNCTION_ENTER;
1342
1343 CODECHAL_HW_CHK_NULL_RETURN(m_miInterface);
1344
1345 MHW_MI_ATOMIC_PARAMS atomicParams;
1346 MOS_ZeroMemory((&atomicParams), sizeof(atomicParams));
1347 atomicParams.pOsResource = resource;
1348 atomicParams.dwDataSize = sizeof(uint32_t);
1349 atomicParams.Operation = opCode;
1350 atomicParams.bInlineData = true;
1351 atomicParams.dwOperand1Data[0] = immData;
1352 eStatus = m_miInterface->AddMiAtomicCmd(cmdBuffer, &atomicParams);
1353
1354 return eStatus;
1355 }
1356
SendCondBbEndCmd(PMOS_RESOURCE resource,uint32_t offset,uint32_t compData,bool disableCompMask,PMOS_COMMAND_BUFFER cmdBuffer)1357 MOS_STATUS CodechalHwInterface::SendCondBbEndCmd(
1358 PMOS_RESOURCE resource,
1359 uint32_t offset,
1360 uint32_t compData,
1361 bool disableCompMask,
1362 PMOS_COMMAND_BUFFER cmdBuffer)
1363 {
1364 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1365
1366 CODECHAL_HW_FUNCTION_ENTER;
1367
1368 if (!Mos_ResourceIsNull(&m_conditionalBbEndDummy))
1369 {
1370 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
1371 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
1372 flushDwParams.postSyncOperation = 1;
1373 flushDwParams.pOsResource = &m_conditionalBbEndDummy;
1374 flushDwParams.dwDataDW1 = 0;
1375 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
1376 }
1377
1378 MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS conditionalBatchBufferEndParams;
1379 MOS_ZeroMemory(&conditionalBatchBufferEndParams, sizeof(conditionalBatchBufferEndParams));
1380 conditionalBatchBufferEndParams.presSemaphoreBuffer = resource;
1381 conditionalBatchBufferEndParams.dwOffset = offset;
1382 conditionalBatchBufferEndParams.dwValue = compData;
1383 conditionalBatchBufferEndParams.bDisableCompareMask = disableCompMask;
1384 eStatus = m_miInterface->AddMiConditionalBatchBufferEndCmd(cmdBuffer, &conditionalBatchBufferEndParams);
1385
1386 return eStatus;
1387 }
1388
MhwInitISH(PMHW_STATE_HEAP_INTERFACE stateHeapInterface,PMHW_KERNEL_STATE kernelState)1389 MOS_STATUS CodechalHwInterface::MhwInitISH(
1390 PMHW_STATE_HEAP_INTERFACE stateHeapInterface,
1391 PMHW_KERNEL_STATE kernelState)
1392 {
1393 CODECHAL_HW_FUNCTION_ENTER;
1394
1395 CODECHAL_HW_CHK_NULL_RETURN(stateHeapInterface);
1396 CODECHAL_HW_CHK_NULL_RETURN(kernelState);
1397
1398 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1399 CODECHAL_HW_CHK_STATUS_RETURN(stateHeapInterface->pfnAssignSpaceInStateHeap(
1400 stateHeapInterface,
1401 MHW_ISH_TYPE,
1402 kernelState,
1403 kernelState->KernelParams.iSize,
1404 true,
1405 false));
1406
1407 CODECHAL_HW_CHK_STATUS_RETURN(kernelState->m_ishRegion.AddData(
1408 kernelState->KernelParams.pBinary,
1409 0,
1410 kernelState->KernelParams.iSize));
1411
1412 return MOS_STATUS_SUCCESS;
1413 }
1414
AssignDshAndSshSpace(PMHW_STATE_HEAP_INTERFACE stateHeapInterface,PMHW_KERNEL_STATE kernelState,bool noDshSpaceRequested,uint32_t forcedDshSize,bool noSshSpaceRequested,uint32_t currCmdBufId)1415 MOS_STATUS CodechalHwInterface::AssignDshAndSshSpace(
1416 PMHW_STATE_HEAP_INTERFACE stateHeapInterface,
1417 PMHW_KERNEL_STATE kernelState,
1418 bool noDshSpaceRequested,
1419 uint32_t forcedDshSize,
1420 bool noSshSpaceRequested,
1421 uint32_t currCmdBufId)
1422 {
1423 CODECHAL_HW_FUNCTION_ENTER;
1424
1425 CODECHAL_HW_CHK_NULL_RETURN(stateHeapInterface);
1426 CODECHAL_HW_CHK_NULL_RETURN(kernelState);
1427
1428 kernelState->m_currTrackerId = currCmdBufId;
1429
1430 if (!noDshSpaceRequested)
1431 {
1432 uint32_t dshSize = 0;
1433 if (forcedDshSize != 0)
1434 {
1435 dshSize = forcedDshSize;
1436 }
1437 else
1438 {
1439 dshSize = stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData()+
1440 MOS_ALIGN_CEIL(kernelState->KernelParams.iCurbeLength,
1441 stateHeapInterface->pStateHeapInterface->GetCurbeAlignment());
1442 }
1443
1444 CODECHAL_HW_CHK_STATUS_RETURN(stateHeapInterface->pfnAssignSpaceInStateHeap(
1445 stateHeapInterface,
1446 MHW_DSH_TYPE,
1447 kernelState,
1448 dshSize,
1449 false,
1450 true));
1451 }
1452
1453 if (!noSshSpaceRequested)
1454 {
1455 CODECHAL_HW_CHK_STATUS_RETURN(stateHeapInterface->pfnAssignSpaceInStateHeap(
1456 stateHeapInterface,
1457 MHW_SSH_TYPE,
1458 kernelState,
1459 kernelState->dwSshSize,
1460 false,
1461 false));
1462 }
1463
1464 return MOS_STATUS_SUCCESS;
1465 }
1466
SelectVdboxAndGetMmioRegister(MHW_VDBOX_NODE_IND index,PMOS_COMMAND_BUFFER pCmdBuffer)1467 MmioRegistersMfx * CodechalHwInterface::SelectVdboxAndGetMmioRegister(
1468 MHW_VDBOX_NODE_IND index,
1469 PMOS_COMMAND_BUFFER pCmdBuffer)
1470 {
1471 if (m_getVdboxNodeByUMD)
1472 {
1473 pCmdBuffer->iVdboxNodeIndex = m_osInterface->pfnGetVdboxNodeId(m_osInterface, pCmdBuffer);
1474 switch (pCmdBuffer->iVdboxNodeIndex)
1475 {
1476 case MOS_VDBOX_NODE_1:
1477 index = MHW_VDBOX_NODE_1;
1478 break;
1479 case MOS_VDBOX_NODE_2:
1480 index = MHW_VDBOX_NODE_2;
1481 break;
1482 case MOS_VDBOX_NODE_INVALID:
1483 // That's a legal case meaning that we were not assigned with per-bb index because
1484 // balancing algorithm can't work (forcedly diabled or miss kernel support).
1485 // If that's the case we just proceed with the further static context assignment.
1486 break;
1487 default:
1488 // That's the case when MHW and MOS enumerations mismatch. We again proceed with the
1489 // best effort (static context assignment, but provide debug note).
1490 MHW_ASSERTMESSAGE("MOS and MHW VDBOX enumerations mismatch! Adjust HW description!");
1491 break;
1492 }
1493 }
1494
1495 return m_mfxInterface->GetMmioRegisters(index);
1496 }
1497
SendMiStoreDataImm(PMOS_RESOURCE resource,uint32_t immData,PMOS_COMMAND_BUFFER cmdBuffer)1498 MOS_STATUS CodechalHwInterface::SendMiStoreDataImm(
1499 PMOS_RESOURCE resource,
1500 uint32_t immData,
1501 PMOS_COMMAND_BUFFER cmdBuffer)
1502 {
1503 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1504
1505 CODECHAL_HW_FUNCTION_ENTER;
1506
1507 CODECHAL_HW_CHK_NULL_RETURN(resource);
1508 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1509
1510 MHW_MI_STORE_DATA_PARAMS storeDataParams;
1511 MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams));
1512 storeDataParams.pOsResource = resource;
1513 storeDataParams.dwResourceOffset = 0;
1514 storeDataParams.dwValue = immData;
1515
1516 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(
1517 cmdBuffer,
1518 &storeDataParams));
1519
1520 return eStatus;
1521 }
1522
ReadMfcStatus(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)1523 MOS_STATUS CodechalHwInterface::ReadMfcStatus(
1524 MHW_VDBOX_NODE_IND vdboxIndex,
1525 const EncodeStatusReadParams ¶ms,
1526 PMOS_COMMAND_BUFFER cmdBuffer)
1527 {
1528 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1529
1530 CODECHAL_HW_FUNCTION_ENTER;
1531
1532 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1533
1534 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
1535 MmioRegistersMfx* mmioRegisters = SelectVdboxAndGetMmioRegister(vdboxIndex, cmdBuffer);
1536
1537 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
1538 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
1539 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
1540
1541 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
1542 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1543
1544 miStoreRegMemParams.presStoreBuffer = params.resBitstreamByteCountPerFrame;
1545 miStoreRegMemParams.dwOffset = params.bitstreamByteCountPerFrameOffset;
1546 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset;
1547 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1548
1549 miStoreRegMemParams.presStoreBuffer = params.resBitstreamSyntaxElementOnlyBitCount;
1550 miStoreRegMemParams.dwOffset = params.bitstreamSyntaxElementOnlyBitCountOffset;
1551 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamSeBitcountFrameRegOffset;
1552 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1553
1554 miStoreRegMemParams.presStoreBuffer = params.resQpStatusCount;
1555 miStoreRegMemParams.dwOffset = params.qpStatusCountOffset;
1556 miStoreRegMemParams.dwRegister = mmioRegisters->mfcQPStatusCountOffset;
1557 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1558
1559 if (mmioRegisters->mfcAvcNumSlicesRegOffset > 0)
1560 {
1561 //read MFC_AVC_NUM_SLICES register to status report
1562 miStoreRegMemParams.presStoreBuffer = params.resNumSlices;
1563 miStoreRegMemParams.dwOffset = params.numSlicesOffset;
1564 miStoreRegMemParams.dwRegister = mmioRegisters->mfcAvcNumSlicesRegOffset;
1565 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1566 }
1567
1568 if (params.vdencBrcEnabled)
1569 {
1570 // Store PAK FrameSize MMIO to DMEM for HuC next BRC pass of current frame and first pass of next frame.
1571 for (int i = 0; i < 2; i++)
1572 {
1573 if (params.resVdencBrcUpdateDmemBufferPtr[i])
1574 {
1575 miStoreRegMemParams.presStoreBuffer = params.resVdencBrcUpdateDmemBufferPtr[i];
1576 miStoreRegMemParams.dwOffset = 5 * sizeof(uint32_t);
1577 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset;
1578 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1579
1580 if (params.vdencBrcNumOfSliceOffset)
1581 {
1582 miStoreRegMemParams.presStoreBuffer = params.resVdencBrcUpdateDmemBufferPtr[i];
1583 miStoreRegMemParams.dwOffset = params.vdencBrcNumOfSliceOffset;
1584 miStoreRegMemParams.dwRegister = mmioRegisters->mfcAvcNumSlicesRegOffset;
1585 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1586 }
1587 }
1588 }
1589 }
1590
1591 CODECHAL_HW_CHK_STATUS_RETURN(ReadImageStatus(vdboxIndex, params, cmdBuffer));
1592
1593 return eStatus;
1594 }
1595
ReadImageStatus(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)1596 MOS_STATUS CodechalHwInterface::ReadImageStatus(
1597 MHW_VDBOX_NODE_IND vdboxIndex,
1598 const EncodeStatusReadParams ¶ms,
1599 PMOS_COMMAND_BUFFER cmdBuffer)
1600 {
1601 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1602
1603 CODECHAL_HW_FUNCTION_ENTER;
1604
1605 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1606
1607 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
1608 MmioRegistersMfx* mmioRegisters = SelectVdboxAndGetMmioRegister(vdboxIndex, cmdBuffer);
1609
1610 MOS_RESOURCE *osResource;
1611 uint32_t offset;
1612
1613 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
1614 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1615
1616 miStoreRegMemParams.presStoreBuffer = params.resImageStatusMask;
1617 miStoreRegMemParams.dwOffset = params.imageStatusMaskOffset;
1618 miStoreRegMemParams.dwRegister = mmioRegisters->mfcImageStatusMaskRegOffset;
1619 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1620
1621 miStoreRegMemParams.presStoreBuffer = params.resImageStatusCtrl;
1622 miStoreRegMemParams.dwOffset = params.imageStatusCtrlOffset;
1623 miStoreRegMemParams.dwRegister = mmioRegisters->mfcImageStatusCtrlRegOffset;
1624 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1625
1626 // VDEnc dynamic slice overflow semaphore, DW0 is SW programmed mask(MFX_IMAGE_MASK does not support), DW1 is MFX_IMAGE_STATUS_CONTROL
1627 if (params.vdencBrcEnabled)
1628 {
1629 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams;
1630
1631 // Added for VDEnc slice overflow bit in MFC_IMAGE_STATUS_CONTROL
1632 // The bit is connected on the non-AVC encoder side of MMIO register.
1633 // Need a dummy MFX_PIPE_MODE_SELECT to decoder and read this register.
1634 if (params.waReadVDEncOverflowStatus)
1635 {
1636 MOS_ZeroMemory(&pipeModeSelectParams, sizeof(pipeModeSelectParams));
1637 pipeModeSelectParams.Mode = CODECHAL_DECODE_MODE_AVCVLD;
1638 m_mfxInterface->SetDecodeInUse(true);
1639 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->AddMfxPipeModeSelectCmd(cmdBuffer, &pipeModeSelectParams));
1640 }
1641
1642 // Store MFC_IMAGE_STATUS_CONTROL MMIO to DMEM for HuC next BRC pass of current frame and first pass of next frame.
1643 for (int i = 0; i < 2; i++)
1644 {
1645 if (params.resVdencBrcUpdateDmemBufferPtr[i])
1646 {
1647 miStoreRegMemParams.presStoreBuffer = params.resVdencBrcUpdateDmemBufferPtr[i];
1648 miStoreRegMemParams.dwOffset = 7 * sizeof(uint32_t); // offset of SliceSizeViolation in HUC_BRC_UPDATE_DMEM
1649 miStoreRegMemParams.dwRegister = mmioRegisters->mfcImageStatusCtrlRegOffset;
1650 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1651 }
1652 }
1653
1654 // Restore MFX_PIPE_MODE_SELECT to encode mode
1655 if (params.waReadVDEncOverflowStatus)
1656 {
1657 MOS_ZeroMemory(&pipeModeSelectParams, sizeof(pipeModeSelectParams));
1658 pipeModeSelectParams.Mode = params.mode;
1659 pipeModeSelectParams.bVdencEnabled = true;
1660 m_mfxInterface->SetDecodeInUse(false);
1661 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->AddMfxPipeModeSelectCmd(cmdBuffer, &pipeModeSelectParams));
1662 }
1663 }
1664
1665 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
1666 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
1667 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
1668
1669 return eStatus;
1670 }
1671
ReadBrcPakStatistics(MHW_VDBOX_NODE_IND vdboxIndex,const BrcPakStatsReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)1672 MOS_STATUS CodechalHwInterface::ReadBrcPakStatistics(
1673 MHW_VDBOX_NODE_IND vdboxIndex,
1674 const BrcPakStatsReadParams ¶ms,
1675 PMOS_COMMAND_BUFFER cmdBuffer)
1676 {
1677 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1678
1679 CODECHAL_HW_FUNCTION_ENTER;
1680
1681 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1682 CODECHAL_HW_CHK_NULL_RETURN(params.presBrcPakStatisticBuffer);
1683
1684 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
1685 MmioRegistersMfx* mmioRegisters = SelectVdboxAndGetMmioRegister(vdboxIndex, cmdBuffer);
1686
1687 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
1688 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1689
1690 miStoreRegMemParams.presStoreBuffer = params.presBrcPakStatisticBuffer;
1691 miStoreRegMemParams.dwOffset = 0;
1692 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset;
1693 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1694
1695 miStoreRegMemParams.presStoreBuffer = params.presBrcPakStatisticBuffer;
1696 miStoreRegMemParams.dwOffset = sizeof(uint32_t);
1697 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountSliceRegOffset;
1698 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1699
1700 MHW_MI_STORE_DATA_PARAMS storeDataParams;
1701 storeDataParams.pOsResource = params.presBrcPakStatisticBuffer;
1702 storeDataParams.dwResourceOffset = sizeof(uint32_t) * 2;
1703 storeDataParams.dwValue = params.ucPass + 1;
1704 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
1705
1706 storeDataParams.pOsResource = params.presStatusBuffer;
1707 storeDataParams.dwResourceOffset = params.dwStatusBufNumPassesOffset;
1708 storeDataParams.dwValue = params.ucPass + 1;
1709 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
1710
1711 miStoreRegMemParams.presStoreBuffer = params.presBrcPakStatisticBuffer;
1712 miStoreRegMemParams.dwOffset = sizeof(uint32_t) * (4 + params.ucPass);
1713 miStoreRegMemParams.dwRegister = mmioRegisters->mfcImageStatusCtrlRegOffset;
1714 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1715
1716 return eStatus;
1717 }
1718
ReadHcpStatus(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)1719 MOS_STATUS CodechalHwInterface::ReadHcpStatus(
1720 MHW_VDBOX_NODE_IND vdboxIndex,
1721 const EncodeStatusReadParams ¶ms,
1722 PMOS_COMMAND_BUFFER cmdBuffer)
1723 {
1724 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1725
1726 CODECHAL_HW_FUNCTION_ENTER;
1727
1728 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1729
1730 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
1731
1732 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
1733 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
1734 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
1735
1736 auto mmioRegisters = m_hcpInterface->GetMmioRegisters(vdboxIndex);
1737
1738 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
1739 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1740 miStoreRegMemParams.presStoreBuffer = params.resBitstreamByteCountPerFrame;
1741 miStoreRegMemParams.dwOffset = params.bitstreamByteCountPerFrameOffset;
1742 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncBitstreamBytecountFrameRegOffset;
1743 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1744
1745 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1746 miStoreRegMemParams.presStoreBuffer = params.resBitstreamSyntaxElementOnlyBitCount;
1747 miStoreRegMemParams.dwOffset = params.bitstreamSyntaxElementOnlyBitCountOffset;
1748 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncBitstreamSeBitcountFrameRegOffset;
1749 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1750
1751 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1752 miStoreRegMemParams.presStoreBuffer = params.resQpStatusCount;
1753 miStoreRegMemParams.dwOffset = params.qpStatusCountOffset;
1754 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncQpStatusCountRegOffset;
1755 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1756
1757 return eStatus;
1758 }
1759
ReadImageStatusForHcp(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)1760 MOS_STATUS CodechalHwInterface::ReadImageStatusForHcp(
1761 MHW_VDBOX_NODE_IND vdboxIndex,
1762 const EncodeStatusReadParams ¶ms,
1763 PMOS_COMMAND_BUFFER cmdBuffer)
1764 {
1765 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1766
1767 CODECHAL_HW_FUNCTION_ENTER;
1768
1769 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1770
1771 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
1772
1773 auto mmioRegisters = m_hcpInterface->GetMmioRegisters(vdboxIndex);
1774
1775 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
1776 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1777 miStoreRegMemParams.presStoreBuffer = params.resImageStatusMask;
1778 miStoreRegMemParams.dwOffset = params.imageStatusMaskOffset;
1779 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncImageStatusMaskRegOffset;
1780 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1781
1782 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1783 miStoreRegMemParams.presStoreBuffer = params.resImageStatusCtrl;
1784 miStoreRegMemParams.dwOffset = params.imageStatusCtrlOffset;
1785 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncImageStatusCtrlRegOffset;
1786 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1787
1788 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
1789 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
1790 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
1791
1792 return eStatus;
1793 }
1794
ReadBrcPakStatisticsForHcp(MHW_VDBOX_NODE_IND vdboxIndex,const BrcPakStatsReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)1795 MOS_STATUS CodechalHwInterface::ReadBrcPakStatisticsForHcp(
1796 MHW_VDBOX_NODE_IND vdboxIndex,
1797 const BrcPakStatsReadParams ¶ms,
1798 PMOS_COMMAND_BUFFER cmdBuffer)
1799 {
1800 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1801
1802 CODECHAL_HW_FUNCTION_ENTER;
1803
1804 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
1805 CODECHAL_HW_CHK_NULL_RETURN(params.presBrcPakStatisticBuffer);
1806
1807 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
1808
1809 auto mmioRegisters = m_hcpInterface->GetMmioRegisters(vdboxIndex);
1810
1811 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
1812 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1813 miStoreRegMemParams.presStoreBuffer = params.presBrcPakStatisticBuffer;
1814 miStoreRegMemParams.dwOffset = params.bitstreamBytecountFrameOffset;
1815 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncBitstreamBytecountFrameRegOffset;
1816 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1817
1818 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1819 miStoreRegMemParams.presStoreBuffer = params.presBrcPakStatisticBuffer;
1820 miStoreRegMemParams.dwOffset = params.bitstreamBytecountFrameNoHeaderOffset;
1821 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncBitstreamBytecountFrameNoHeaderRegOffset;
1822 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1823
1824 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
1825 miStoreRegMemParams.presStoreBuffer = params.presBrcPakStatisticBuffer;
1826 miStoreRegMemParams.dwOffset = params.imageStatusCtrlOffset;
1827 miStoreRegMemParams.dwRegister = mmioRegisters->hcpEncImageStatusCtrlRegOffset;
1828 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
1829
1830 MHW_MI_STORE_DATA_PARAMS storeDataParams;
1831 storeDataParams.pOsResource = params.presStatusBuffer;
1832 storeDataParams.dwResourceOffset = params.dwStatusBufNumPassesOffset;
1833 storeDataParams.dwValue = params.ucPass;
1834 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
1835
1836 return eStatus;
1837 }
1838
SetStatusTagByPipeCtrl(PMOS_RESOURCE osResource,uint32_t offset,uint32_t tag,bool needFlushCache,PMOS_COMMAND_BUFFER cmdBuffer)1839 MOS_STATUS CodechalHwInterface::SetStatusTagByPipeCtrl(
1840 PMOS_RESOURCE osResource,
1841 uint32_t offset,
1842 uint32_t tag,
1843 bool needFlushCache,
1844 PMOS_COMMAND_BUFFER cmdBuffer)
1845 {
1846 MOS_STATUS result = MOS_STATUS_SUCCESS;
1847
1848 MHW_PIPE_CONTROL_PARAMS pipeControlParams;
1849 MOS_ZeroMemory(&pipeControlParams, sizeof(pipeControlParams));
1850
1851 if (!needFlushCache)
1852 {
1853 pipeControlParams.presDest = osResource;
1854 pipeControlParams.dwPostSyncOp = MHW_FLUSH_WRITE_IMMEDIATE_DATA;
1855 pipeControlParams.dwResourceOffset = offset;
1856 pipeControlParams.dwDataDW1 = tag;
1857 result = m_miInterface->AddPipeControl(
1858 cmdBuffer,
1859 nullptr,
1860 &pipeControlParams);
1861
1862 return result;
1863 }
1864
1865 pipeControlParams.dwFlushMode = MHW_FLUSH_WRITE_CACHE;
1866 pipeControlParams.bGenericMediaStateClear = true;
1867 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddPipeControl(cmdBuffer, nullptr, &pipeControlParams));
1868
1869 if (MEDIA_IS_WA(m_waTable, WaSendDummyVFEafterPipelineSelect))
1870 {
1871 MHW_VFE_PARAMS vfeStateParams;
1872
1873 MOS_ZeroMemory(&vfeStateParams, sizeof(vfeStateParams));
1874 vfeStateParams.dwNumberofURBEntries = 1;
1875 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->AddMediaVfeCmd(cmdBuffer, &vfeStateParams));
1876 }
1877
1878 MHW_MI_STORE_DATA_PARAMS storeDataParams;
1879 MOS_ZeroMemory(&storeDataParams, sizeof(MHW_MI_STORE_DATA_PARAMS));
1880 storeDataParams.pOsResource = osResource;
1881 storeDataParams.dwResourceOffset = offset;
1882 storeDataParams.dwValue = tag;
1883 result = m_miInterface->AddMiStoreDataImmCmd(
1884 cmdBuffer,
1885 &storeDataParams);
1886
1887 return result;
1888 }
1889
SetStatusTagByMiCommand(PMOS_RESOURCE osResource,uint32_t offset,uint32_t tag,PMOS_COMMAND_BUFFER cmdBuffer)1890 MOS_STATUS CodechalHwInterface::SetStatusTagByMiCommand(
1891 PMOS_RESOURCE osResource,
1892 uint32_t offset,
1893 uint32_t tag,
1894 PMOS_COMMAND_BUFFER cmdBuffer)
1895 {
1896 MOS_STATUS result = MOS_STATUS_SUCCESS;
1897
1898 MHW_MI_STORE_DATA_PARAMS storeDataParams;
1899 MOS_ZeroMemory(&storeDataParams, sizeof(MHW_MI_STORE_DATA_PARAMS));
1900 storeDataParams.pOsResource = osResource;
1901 storeDataParams.dwResourceOffset = offset;
1902 storeDataParams.dwValue = tag;
1903
1904 result = m_miInterface->AddMiStoreDataImmCmd(
1905 cmdBuffer,
1906 &storeDataParams);
1907
1908 return result;
1909 }
1910
UsesRenderEngine(CODECHAL_FUNCTION codecFunction,uint32_t standard)1911 bool CodechalHwInterface::UsesRenderEngine(CODECHAL_FUNCTION codecFunction, uint32_t standard)
1912 {
1913 if(codecFunction == CODECHAL_FUNCTION_ENC ||
1914 (codecFunction == CODECHAL_FUNCTION_ENC_PAK) ||
1915 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK ||
1916 ((codecFunction == CODECHAL_FUNCTION_DECODE) && (standard == CODECHAL_VC1)) ||
1917 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK ||
1918 codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC ||
1919 codecFunction == CODECHAL_FUNCTION_FEI_ENC ||
1920 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK)
1921 {
1922 return true;
1923 }
1924
1925 return false;
1926 }
1927
GetFilmGrainKernelInfo(uint8_t * & kernelBase,uint32_t & kernelSize)1928 MOS_STATUS CodechalHwInterface::GetFilmGrainKernelInfo(
1929 uint8_t*& kernelBase,
1930 uint32_t& kernelSize)
1931 {
1932 kernelBase = nullptr;
1933 kernelSize = 0;
1934
1935 return MOS_STATUS_SUCCESS;
1936 }
1937