1 /*
2 * Copyright (c) 2014-2018, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_hw_g11_X.cpp
24 //! \brief This modules implements HW interface layer for CNL+ to be used on on all operating systems/DDIs, across CODECHAL components.
25 //!
26 #include "codechal_hw_g11_X.h"
27 #include "mhw_render_g11_X.h"
28 #include "mhw_vdbox_mfx_hwcmd_g11_X.h"
29 #include "mhw_vdbox_hcp_hwcmd_g11_X.h"
30 #include "mhw_vdbox_huc_hwcmd_g11_X.h"
31 #include "mhw_vdbox_vdenc_hwcmd_g11_X.h" // temporary include for calculating size of various hardware commands
32 #include "mhw_mi_hwcmd_g11_X.h"
33 #include "mhw_vdbox_hcp_g11_X.h"
34
35 // Currently initialized with dummy values, just as an example. Will be updated later.
36 const CODECHAL_SSEU_SETTING CodechalHwInterfaceG11::m_defaultSsEuLutG11[CODECHAL_NUM_MEDIA_STATES] =
37 {
38 // Slice Sub-Slice EU Rsvd(freq)
39 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_OLP
40 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_NORMAL
41 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_PERFORMANCE
42 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_QUALITY
43 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_DIST
44 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_SCALING
45 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_SCALING
46 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_SCALING
47 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_ME
48 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_ME
49 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_ME
50 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_INIT_RESET
51 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_UPDATE
52 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_BLOCK_COPY
53 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P1
54 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P2
55 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_CHROMA
56 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_LUMA
57 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MPU_FHB
58 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_TPU_FHB
59 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PA_COPY
60 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PL2_COPY
61 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_ADV
62 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_SCALING
63 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_PU_MODE_DECISION
64 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_SAD
65 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_MODE_DECISION
66 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU
67 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU_FMODE
68 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_B_INTRA_CHECK
69 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_MBENC
70 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_RESET_VLINE_STRIDE
71 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_PAK
72 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE
73 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN
74 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_32x32
75 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_16x16
76 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_P
77 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_TX
78 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_RECON
79 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_RECON
80 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK
81 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK
82 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK
83 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_MC_PRED
84 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON
85 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON
86 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON
87 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON
88 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PREPROC
89 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_WP
90 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_I_MBENC
91 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_CSC_DS_COPY
92 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_4X_SCALING
93 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_LCU64_B_MBENC
94 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MB_BRC_UPDATE
95 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_STATIC_FRAME_DETECTION
96 { 1, 0, 8, 0 } // CODECHAL_MEDIA_STATE_SW_SCOREBOARD_INIT
97 };
98
CodechalHwInterfaceG11(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces)99 CodechalHwInterfaceG11::CodechalHwInterfaceG11(
100 PMOS_INTERFACE osInterface,
101 CODECHAL_FUNCTION codecFunction,
102 MhwInterfaces *mhwInterfaces)
103 : CodechalHwInterface(osInterface, codecFunction, mhwInterfaces)
104 {
105 CODECHAL_HW_FUNCTION_ENTER;
106
107 m_checkBankCount = true;
108 InitCacheabilityControlSettings(codecFunction);
109
110 m_isVdencSuperSliceEnabled = true;
111
112 m_ssEuTable = m_defaultSsEuLutG11;
113
114 // Set platform dependent parameters
115 m_sizeOfCmdBatchBufferEnd = mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
116 m_sizeOfCmdMediaReset = mhw_mi_g11_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 8;
117 m_vdencBrcImgStateBufferSize = mhw_vdbox_vdenc_g11_X::VDENC_IMG_STATE_CMD::byteSize
118 + mhw_vdbox_mfx_g11_X::MFX_AVC_IMG_STATE_CMD::byteSize
119 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
120 m_vdencBatchBuffer1stGroupSize = mhw_vdbox_hcp_g11_X::HCP_PIPE_MODE_SELECT_CMD::byteSize
121 + mhw_mi_g11_X::MFX_WAIT_CMD::byteSize * 2
122 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
123 m_vdencBatchBuffer2ndGroupSize = 120
124 + mhw_vdbox_hcp_g11_X::HCP_PIC_STATE_CMD::byteSize
125 + 148
126 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
127 m_vdencReadBatchBufferSize =
128 m_vdencBatchBuffer1stGroupSize
129 + m_vdencBatchBuffer2ndGroupSize;
130 m_vdencGroup3BatchBufferSize =
131 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES
132 * (2 * mhw_vdbox_hcp_g11_X::HCP_WEIGHTOFFSET_STATE_CMD::byteSize
133 + mhw_vdbox_hcp_g11_X::HCP_SLICE_STATE_CMD::byteSize
134 + (HEVC_MAX_NAL_UNIT_TYPE + 2) * mhw_vdbox_hcp_g11_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize
135 + mhw_vdbox_vdenc_g11_X::VDENC_WEIGHTSOFFSETS_STATE_CMD::byteSize
136 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize
137 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
138
139 m_vdenc2ndLevelBatchBufferSize = m_vdencReadBatchBufferSize + m_vdencGroup3BatchBufferSize;
140
141 m_HucStitchCmdBatchBufferSize = 7 * 4
142 + 14 * 4
143 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
144 m_vdencCopyBatchBufferSize =
145 7 * 4 + 14 * 4 +
146 mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
147 // mhw_vdbox_hcp_g11_X::HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
148 m_vdencBatchBufferPerSliceConstSize = mhw_vdbox_hcp_g11_X::HCP_SLICE_STATE_CMD::byteSize
149 + mhw_vdbox_hcp_g11_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
150 + mhw_vdbox_vdenc_g11_X::VDENC_WEIGHTSOFFSETS_STATE_CMD::byteSize
151 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
152 // Set to size of the BRC update command buffer, since it is larger than BRC Init/ PAK integration commands
153 m_hucCommandBufferSize = mhw_vdbox_huc_g11_X::HUC_IMEM_STATE_CMD::byteSize
154 + mhw_vdbox_huc_g11_X::HUC_PIPE_MODE_SELECT_CMD::byteSize
155 + mhw_mi_g11_X::MFX_WAIT_CMD::byteSize * 3
156 + mhw_vdbox_huc_g11_X::HUC_DMEM_STATE_CMD::byteSize
157 + mhw_vdbox_huc_g11_X::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize
158 + mhw_vdbox_huc_g11_X::HUC_STREAM_OBJECT_CMD::byteSize
159 + mhw_mi_g11_X::MI_STORE_DATA_IMM_CMD::byteSize
160 + mhw_mi_g11_X::MI_STORE_REGISTER_MEM_CMD::byteSize
161 + mhw_vdbox_huc_g11_X::HUC_START_CMD::byteSize
162 + mhw_vdbox_vdenc_g11_X::VD_PIPELINE_FLUSH_CMD::byteSize
163 + mhw_mi_g11_X::MI_FLUSH_DW_CMD::byteSize
164 + mhw_mi_g11_X::MI_STORE_DATA_IMM_CMD::byteSize * 2
165 + mhw_mi_g11_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 2
166 + mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD::byteSize;
167
168 m_maxKernelLoadCmdSize =
169 mhw_mi_g11_X::PIPE_CONTROL_CMD::byteSize +
170 mhw_render_g11_X::PIPELINE_SELECT_CMD::byteSize +
171 mhw_render_g11_X::MEDIA_OBJECT_CMD::byteSize +
172 mhw_render_g11_X::STATE_BASE_ADDRESS_CMD::byteSize +
173 mhw_render_g11_X::MEDIA_VFE_STATE_CMD::byteSize +
174 mhw_render_g11_X::MEDIA_CURBE_LOAD_CMD::byteSize +
175 mhw_render_g11_X::MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD::byteSize +
176 mhw_mi_g11_X::MI_BATCH_BUFFER_START_CMD::byteSize +
177 mhw_render_g11_X::MEDIA_OBJECT_WALKER_CMD::byteSize +
178 mhw_mi_g11_X::MI_STORE_DATA_IMM_CMD::byteSize;
179
180 m_sizeOfCmdMediaObject = mhw_render_g11_X::MEDIA_OBJECT_CMD::byteSize;
181 m_sizeOfCmdMediaStateFlush = mhw_mi_g11_X::MEDIA_STATE_FLUSH_CMD::byteSize;
182
183 // HW WA for COND BBE on GEN11
184 if (Mos_ResourceIsNull(&m_conditionalBbEndDummy))
185 {
186 MOS_LOCK_PARAMS lockFlags;
187 uint8_t* data;
188 MOS_ALLOC_GFXRES_PARAMS allocParams;
189
190 MOS_ZeroMemory(&allocParams, sizeof(MOS_ALLOC_GFXRES_PARAMS));
191 allocParams.Type = MOS_GFXRES_BUFFER;
192 allocParams.TileType = MOS_TILE_LINEAR;
193 allocParams.Format = Format_Buffer;
194 allocParams.dwBytes = MHW_CACHELINE_SIZE;
195 allocParams.pBufName = "DummyBufferForWA";
196 if (MOS_STATUS_SUCCESS != m_osInterface->pfnAllocateResource(
197 m_osInterface,
198 &allocParams,
199 &m_conditionalBbEndDummy))
200 {
201 return;
202 }
203
204 // set lock flag to WRITE_ONLY
205 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
206 lockFlags.WriteOnly = 1;
207 data = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, &m_conditionalBbEndDummy, &lockFlags);
208 CODECHAL_HW_ASSERT(data);
209 MOS_ZeroMemory(data, allocParams.dwBytes);
210 m_osInterface->pfnUnlockResource(m_osInterface, &m_conditionalBbEndDummy);
211 }
212 }
213
InitL3CacheSettings()214 MOS_STATUS CodechalHwInterfaceG11::InitL3CacheSettings()
215 {
216 // Get default L3 cache settings
217 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->EnableL3Caching(nullptr));
218
219 #if (_DEBUG || _RELEASE_INTERNAL)
220 // Override default L3 cache settings
221 auto l3CacheConfig =
222 m_renderInterface->GetL3CacheConfig();
223 MHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G11 l3Overrides;
224 l3Overrides.dwTcCntlReg =
225 static_cast<MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G11*>(l3CacheConfig)->dwL3CacheTcCntlReg_Setting;
226 CODECHAL_HW_CHK_STATUS_RETURN(InitL3ControlUserFeatureSettings(
227 l3CacheConfig,
228 &l3Overrides));
229 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->EnableL3Caching(
230 &l3Overrides));
231 #endif // (_DEBUG || _RELEASE_INTERNAL)
232
233 return MOS_STATUS_SUCCESS;
234 }
235
GetStreamoutCommandSize(uint32_t * commandsSize,uint32_t * patchListSize)236 MOS_STATUS CodechalHwInterfaceG11::GetStreamoutCommandSize(
237 uint32_t *commandsSize,
238 uint32_t *patchListSize)
239 {
240 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
241
242 CODECHAL_HW_FUNCTION_ENTER;
243
244 MHW_VDBOX_STATE_CMDSIZE_PARAMS_G11 stateCmdSizeParams;
245
246 stateCmdSizeParams.bShortFormat = false;
247 stateCmdSizeParams.bHucDummyStream = MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable);
248 CODECHAL_HW_CHK_STATUS_RETURN(GetHxxStateCommandSize(
249 CODECHAL_DECODE_MODE_CENC, // For cenc phase
250 commandsSize,
251 patchListSize,
252 &stateCmdSizeParams));
253
254 return eStatus;
255 }
256