1 /*
2 * Copyright (c) 2017-2020, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_vdenc_avc_g12.cpp
24 //! \brief This file implements the C++ class/interface for Gen12 platform's AVC
25 //! VDEnc encoding to be used CODECHAL components.
26 //!
27
28 #include "codechal_vdenc_avc_g12.h"
29 #include "codechal_mmc_encode_avc_g12.h"
30 #include "codechal_kernel_header_g12.h"
31 #include "codechal_kernel_hme_g12.h"
32 #include "mhw_mi_g12_X.h"
33 #include "mhw_vdbox_vdenc_g12_X.h"
34 #include "mhw_vdbox_g12_X.h"
35 #include "mhw_render_g12_X.h"
36 #include "codeckrnheader.h"
37 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
38 #include "igcodeckrn_g12.h"
39 #endif
40 #if USE_CODECHAL_DEBUG_TOOL
41 #include "codechal_debug_encode_par_g12.h"
42 #include "mhw_vdbox_mfx_hwcmd_g12_X.h"
43 #include "mhw_vdbox_vdenc_hwcmd_g12_X.h"
44 #include <iomanip>
45 #endif
46 #include "hal_oca_interface.h"
47
48 #define CODEC_AVC_MIN_BLOCK_HEIGHT 16
49
50 enum SfdBindingTableOffset
51 {
52 sfdVdencInputImageState = 0,
53 sfdMvDataSurface = 1,
54 sfdInterDistortionSurface = 2,
55 sfdOutputDataSurface = 3,
56 sfdVdencOutputImageState = 4,
57 sfdNumSurfaces = 5
58 };
59
60 // clang-format off
61 // CURBE for Static Frame Detection kernel
62 class CodechalVdencAvcStateG12::SfdCurbe
63 {
64 public:
65
66 union
67 {
68 struct
69 {
70 uint32_t m_vdencModeDisable : MOS_BITFIELD_BIT(0);
71 uint32_t m_brcModeEnable : MOS_BITFIELD_BIT(1);
72 uint32_t m_sliceType : MOS_BITFIELD_RANGE(2, 3);
73 uint32_t : MOS_BITFIELD_BIT(4);
74 uint32_t m_streamInType : MOS_BITFIELD_RANGE(5, 8);
75 uint32_t m_enableAdaptiveMvStreamIn : MOS_BITFIELD_BIT(9);
76 uint32_t : MOS_BITFIELD_BIT(10);
77 uint32_t m_enableIntraCostScalingForStaticFrame : MOS_BITFIELD_BIT(11);
78 uint32_t m_reserved : MOS_BITFIELD_RANGE(12, 31);
79 };
80 struct
81 {
82 uint32_t m_value;
83 };
84 } m_dw0;
85
86 union
87 {
88 struct
89 {
90 uint32_t m_qpValue : MOS_BITFIELD_RANGE(0, 7);
91 uint32_t m_numOfRefs : MOS_BITFIELD_RANGE(8, 15);
92 uint32_t m_hmeStreamInRefCost : MOS_BITFIELD_RANGE(16, 23);
93 uint32_t m_reserved : MOS_BITFIELD_RANGE(24, 31);
94 };
95 struct
96 {
97 uint32_t m_value;
98 };
99 } m_dw1;
100
101 union
102 {
103 struct
104 {
105 uint32_t m_frameWidthInMBs : MOS_BITFIELD_RANGE(0, 15); // round-up to 4-MB aligned
106 uint32_t m_frameHeightInMBs : MOS_BITFIELD_RANGE(16, 31); // round-up to 4-MB aligned
107 };
108 struct
109 {
110 uint32_t m_value;
111 };
112 } m_dw2;
113
114 union
115 {
116 struct
117 {
118 uint32_t m_largeMvThresh;
119 };
120 struct
121 {
122 uint32_t m_value;
123 };
124 } m_dw3;
125
126 union
127 {
128 struct
129 {
130 uint32_t m_totalLargeMvThreshold;
131 };
132 struct
133 {
134 uint32_t m_value;
135 };
136 } m_dw4;
137
138 union
139 {
140 struct
141 {
142 uint32_t m_zMVThreshold;
143 };
144 struct
145 {
146 uint32_t m_value;
147 };
148 } m_dw5;
149
150 union
151 {
152 struct
153 {
154 uint32_t m_totalZMVThreshold;
155 };
156 struct
157 {
158 uint32_t m_value;
159 };
160 } m_dw6;
161
162 union
163 {
164 struct
165 {
166 uint32_t m_minDistThreshold;
167 };
168 struct
169 {
170 uint32_t m_value;
171 };
172 } m_dw7;
173
174 uint8_t m_costTable[52];
175
176 union
177 {
178 struct
179 {
180 uint32_t m_actualWidthInMB : MOS_BITFIELD_RANGE(0, 15);
181 uint32_t m_actualHeightInMB : MOS_BITFIELD_RANGE(16, 31);
182 };
183 struct
184 {
185 uint32_t m_value;
186 };
187 } m_dw21;
188
189 union
190 {
191 struct
192 {
193 uint32_t m_reserved;
194 };
195 struct
196 {
197 uint32_t m_value;
198 };
199 } m_dw22;
200
201 union
202 {
203 struct
204 {
205 uint32_t m_reserved;
206 };
207 struct
208 {
209 uint32_t m_value;
210 };
211 } m_dw23;
212
213 union
214 {
215 struct
216 {
217 uint32_t m_vdencInputImagStateIndex; // used in VDEnc CQP mode
218 };
219 struct
220 {
221 uint32_t m_value;
222 };
223 } m_dw24;
224
225 union
226 {
227 struct
228 {
229 uint32_t m_reserved;
230 };
231 struct
232 {
233 uint32_t m_value;
234 };
235 } m_dw25;
236
237 union
238 {
239 struct
240 {
241 uint32_t m_mvDataSurfaceIndex; // contains HME MV Data generated by HME kernel
242 };
243 struct
244 {
245 uint32_t m_value;
246 };
247 } m_dw26;
248
249 union
250 {
251 struct
252 {
253 uint32_t m_interDistortionSurfaceIndex; // contains HME Inter Distortion generated by HME kernel
254 };
255 struct
256 {
257 uint32_t m_value;
258 };
259 } m_dw27;
260
261 union
262 {
263 struct
264 {
265 uint32_t m_outputDataSurfaceIndex;
266 };
267 struct
268 {
269 uint32_t m_value;
270 };
271 } m_dw28;
272
273 union
274 {
275 ;
276 struct
277 {
278 uint32_t m_vdencOutputImagStateIndex;
279 };
280 struct
281 {
282 uint32_t m_value;
283 };
284 } m_dw29;
285
SfdCurbe()286 SfdCurbe()
287 {
288 m_dw0.m_value = 0;
289 m_dw1.m_value = 0;
290 m_dw2.m_value = 0;
291 m_dw3.m_value = 0;
292 m_dw4.m_value = 0;
293 m_dw5.m_value = 0;
294 m_dw6.m_value = 0;
295 m_dw7.m_value = 0;
296 m_dw21.m_value = 0;
297 m_dw22.m_value = 0;
298 m_dw23.m_value = 0;
299 m_dw24.m_value = 0;
300 m_dw25.m_value = 0;
301 m_dw26.m_value = 0;
302 m_dw27.m_value = 0;
303 m_dw28.m_value = 0;
304 m_dw29.m_value = 0;
305
306 for (uint8_t i = 0; i < 52; i++)
307 m_costTable[i] = 0;
308 }
309 };
310 // clang-format on
311
312 struct CodechalVdencAvcStateG12::BrcInitDmem
313 {
314 uint8_t BRCFunc_U8; // 0: Init; 2: Reset
315 uint8_t OpenSourceEnable_U8; // 0: disable opensource, 1: enable opensource
316 uint8_t RVSD[2];
317 uint16_t INIT_BRCFlag_U16; // ICQ or CQP with slice size control: 0x00 CBR: 0x10; VBR: 0x20; VCM: 0x40; LOWDELAY: 0x80.
318 uint16_t Reserved;
319 uint16_t INIT_FrameWidth_U16; // Luma width in bytes
320 uint16_t INIT_FrameHeight_U16; // Luma height in bytes
321 uint32_t INIT_TargetBitrate_U32; // target bitrate, set by application
322 uint32_t INIT_MinRate_U32; // 0
323 uint32_t INIT_MaxRate_U32; // Maximum bit rate in bits per second (bps).
324 uint32_t INIT_BufSize_U32; // buffer size
325 uint32_t INIT_InitBufFull_U32; // initial buffer fullness
326 uint32_t INIT_ProfileLevelMaxFrame_U32; // user defined. refer to AVC BRC for conformance check and correction
327 uint32_t INIT_FrameRateM_U32; // FrameRateM is the number of frames in FrameRateD
328 uint32_t INIT_FrameRateD_U32; // If driver gets this FrameRateD from VUI, it is the num_units_in_tick field (32 bits unsigned integer).
329 uint16_t INIT_GopP_U16; // number of P frames in a GOP
330 uint16_t INIT_GopB_U16; // number of B frames in a GOP
331 uint16_t INIT_MinQP_U16; // 10
332 uint16_t INIT_MaxQP_U16; // 51
333 int8_t INIT_DevThreshPB0_S8[8]; // lowdelay ? (-45, -33, -23, -15, -8, 0, 15, 25) : (-46, -38, -30, -23, 23, 30, 40, 46)
334 int8_t INIT_DevThreshVBR0_S8[8]; // lowdelay ? (-45, -35, -25, -15, -8, 0, 20, 40) : (-46, -40, -32, -23, 56, 64, 83, 93)
335 int8_t INIT_DevThreshI0_S8[8]; // lowdelay ? (-40, -30, -17, -10, -5, 0, 10, 20) : (-43, -36, -25, -18, 18, 28, 38, 46)
336 uint8_t INIT_InitQPIP; // Initial QP for I and P
337
338 uint8_t INIT_NotUseRhoDm_U8; // Reserved
339 uint8_t INIT_InitQPB; // Initial QP for B
340 uint8_t INIT_MbQpCtrl_U8; // Enable MB level QP control (global)
341 uint8_t INIT_SliceSizeCtrlEn_U8; // Enable slice size control
342 int8_t INIT_IntraQPDelta_I8[3]; // set to zero for all by default
343 int8_t INIT_SkipQPDelta_I8; // Reserved
344 int8_t INIT_DistQPDelta_I8[4]; // lowdelay ? (-5, -2, 2, 5) : (0, 0, 0, 0)
345 uint8_t INIT_OscillationQpDelta_U8; // BRCFLAG_ISVCM ? 16 : 0
346 uint8_t INIT_HRDConformanceCheckDisable_U8; // BRCFLAG_ISAVBR ? 1 : 0
347 uint8_t INIT_SkipFrameEnableFlag;
348 uint8_t INIT_TopQPDeltaThrForAdapt2Pass_U8; // =1. QP Delta threshold for second pass.
349 uint8_t INIT_TopFrmSzThrForAdapt2Pass_U8; // lowdelay ? 10 : 50. Top frame size threshold for second pass
350 uint8_t INIT_BotFrmSzThrForAdapt2Pass_U8; // lowdelay ? 10 : 200. Bottom frame size threshold for second pass
351 uint8_t INIT_QPSelectForFirstPass_U8; // lowdelay ? 0 : 1. =0 to use previous frame final QP; or =1 to use (targetQP + previousQP) / 2.
352 uint8_t INIT_MBHeaderCompensation_U8; // Reserved
353 uint8_t INIT_OverShootCarryFlag_U8; // set to zero by default
354 uint8_t INIT_OverShootSkipFramePct_U8; // set to zero by default
355 uint8_t INIT_EstRateThreshP0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
356 uint8_t INIT_EstRateThreshB0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
357 uint8_t INIT_EstRateThreshI0_U8[7]; // 4, 8, 12, 16, 20, 24, 28
358 uint8_t INIT_FracQPEnable_U8; // ExtendedRhoDomainEn from par file
359 uint8_t INIT_ScenarioInfo_U8; // 0: UNKNOWN, 1: DISPLAYREMOTING, 2: VIDEOCONFERENCE, 3: ARCHIVE, 4: LIVESTREAMING.
360 uint8_t INIT_StaticRegionStreamIn_U8; // should be programmed from par file
361 uint8_t INIT_DeltaQP_Adaptation_U8; // =1, should be programmed from par file
362 uint8_t INIT_MaxCRFQualityFactor_U8; // =52, should be programmed from par file
363 uint8_t INIT_CRFQualityFactor_U8; // =25, should be programmed from par file
364 uint8_t INIT_BotQPDeltaThrForAdapt2Pass_U8; // =1. QP Delta threshold for second pass.
365 uint8_t INIT_SlidingWindowSize_U8; // =30, the window size (in frames) used to compute bit rate
366 uint8_t INIT_SlidingWidowRCEnable_U8; // =0, sliding window based rate control (SWRC) disabled, 1: enabled
367 uint8_t INIT_SlidingWindowMaxRateRatio_U8; // =120, ratio between the max rate within the window and average target bitrate
368 uint8_t INIT_LowDelayGoldenFrameBoost_U8; // only for lowdelay mode, 0 (default): no boost for I and scene change frames, 1: boost
369 uint8_t INIT_AdaptiveCostEnable_U8; // 0: disabled, 1: enabled
370 uint8_t INIT_AdaptiveHMEExtensionEnable_U8; // 0: disabled, 1: enabled
371 uint8_t INIT_ICQReEncode_U8; // 0: disabled, 1: enabled
372 uint8_t INIT_LookaheadDepth_U8; // Lookahead depth in unit of frames [0, 127]
373 uint8_t INIT_SinglePassOnly; // 0: disabled, 1: enabled
374 uint8_t INIT_New_DeltaQP_Adaptation_U8; // = 1 to enable new delta QP adaption
375 uint8_t RSVD2[55]; // must be zero
376 };
377
378 struct CodechalVdencAvcStateG12::BrcUpdateDmem
379 {
380 uint8_t BRCFunc_U8; // =1 for Update, other values are reserved for future use
381 uint8_t RSVD[3];
382 uint32_t UPD_TARGETSIZE_U32; // refer to AVC BRC for calculation
383 uint32_t UPD_FRAMENUM_U32; // frame number
384 uint32_t UPD_PeakTxBitsPerFrame_U32; // current global target bits - previous global target bits (global target bits += input bits per frame)
385 uint32_t UPD_FrameBudget_U32; // target time counter
386 uint32_t FrameByteCount; // PAK output via MMIO
387 uint32_t TimingBudgetOverflow; // PAK output via MMIO
388 uint32_t ImgStatusCtrl; // PAK output via MMIO
389 uint32_t IPCMNonConformant; // PAK output via MMIO
390
391 uint16_t UPD_startGAdjFrame_U16[4]; // 10, 50, 100, 150
392 uint16_t UPD_MBBudget_U16[52]; // MB bugdet for QP 0 � 51.
393 uint16_t UPD_SLCSZ_TARGETSLCSZ_U16; // target slice size
394 uint16_t UPD_SLCSZ_UPD_THRDELTAI_U16[42]; // slice size threshold delta for I frame
395 uint16_t UPD_SLCSZ_UPD_THRDELTAP_U16[42]; // slice size threshold delta for P frame
396 uint16_t UPD_NumOfFramesSkipped_U16; // Recording how many frames have been skipped.
397 uint16_t UPD_SkipFrameSize_U16; // Recording the skip frame size for one frame. =NumMBs * 1, assuming one bit per mb for skip frame.
398 uint16_t UPD_StaticRegionPct_U16; // One entry, recording the percentage of static region
399 uint8_t UPD_gRateRatioThreshold_U8[7]; // 80,95,99,101,105,125,160
400 uint8_t UPD_CurrFrameType_U8; // I frame: 2; P frame: 0; B frame: 1.
401 uint8_t UPD_startGAdjMult_U8[5]; // 1, 1, 3, 2, 1
402 uint8_t UPD_startGAdjDiv_U8[5]; // 40, 5, 5, 3, 1
403 uint8_t UPD_gRateRatioThresholdQP_U8[8]; // 253,254,255,0,1,1,2,3
404 uint8_t UPD_PAKPassNum_U8; // current pak pass number
405 uint8_t UPD_MaxNumPass_U8; // 2
406 uint8_t UPD_SceneChgWidth_U8[2]; // set both to MIN((NumP + 1) / 5, 6)
407 uint8_t UPD_SceneChgDetectEn_U8; // Enable scene change detection
408 uint8_t UPD_SceneChgPrevIntraPctThreshold_U8; // =96. scene change previous intra percentage threshold
409 uint8_t UPD_SceneChgCurIntraPctThreshold_U8; // =192. scene change current intra percentage threshold
410 uint8_t UPD_IPAverageCoeff_U8; // lowdelay ? 0 : 128
411 uint8_t UPD_MinQpAdjustment_U8; // Minimum QP increase step
412 uint8_t UPD_TimingBudgetCheck_U8; // Flag indicating if kernel will check timing budget.
413 int8_t reserved_I8[4]; // must be zero
414 uint8_t UPD_CQP_QpValue_U8; // Application specified target QP in BRC_ICQ mode
415 uint8_t UPD_CQP_FracQp_U8; // Application specified fine position in BRC_ICQ mode
416 uint8_t UPD_HMEDetectionEnable_U8; // 0: default, 1: HuC BRC kernel requires information from HME detection kernel output
417 uint8_t UPD_HMECostEnable_U8; // 0: default, 1: driver provides HME cost table
418 uint8_t UPD_DisablePFrame8x8Transform_U8; // 0: enable, 1: disable
419 uint8_t RSVD3; // must be zero
420 uint8_t UPD_ROISource_U8; // =0: disable, 1: ROIMap from HME Static Region or from App dirty rectangle, 2: ROIMap from App
421 uint8_t RSVD4; // must be zero
422 uint16_t UPD_TargetSliceSize_U16; // default: 1498, max target slice size from app DDI
423 uint16_t UPD_MaxNumSliceAllowed_U16; // computed by driver based on level idc
424 uint16_t UPD_SLBB_Size_U16; // second level batch buffer (SLBB) size in bytes, the input buffer will contain two SLBBs A and B, A followed by B, A and B have the same structure.
425 uint16_t UPD_SLBB_B_Offset_U16; // offset in bytes from the beginning of the input buffer, it points to the start of SLBB B, set by driver for skip frame support
426 uint16_t UPD_AvcImgStateOffset_U16; // offset in bytes from the beginning of SLBB A
427 uint16_t reserved_u16;
428 uint32_t NumOfSlice; // PAK output via MMIO
429
430 /* HME distortion based QP adjustment */
431 uint16_t AveHmeDist_U16; // default: 0, in HME detection kernel output
432 uint8_t HmeDistAvailable_U8; // 0: disabled, 1: enabled
433 uint8_t DisableDMA; // default =0, use DMA data transfer; =1, use regular region read/write
434 uint16_t AdditionalFrameSize_U16; // for slice size control improvement
435 uint8_t AddNALHeaderSizeInternally_U8;
436 uint8_t UPD_RoiQpViaForceQp_U8; // HuC does not update StreamIn Buffer, 1: HuC updates StreamIn Buffer
437 uint32_t CABACZeroInsertionSize_U32; // PAK output via MMIO
438 uint32_t MiniFramePaddingSize_U32; // PAK output via MMIO
439 uint16_t UPD_WidthInMB_U16; // width in MB
440 uint16_t UPD_HeightInMB_U16; // height in MB
441 int8_t UPD_ROIQpDelta_I8[8]; // Application specified ROI QP Adjustment for Zone0, Zone1, Zone2 and Zone3, Zone4, Zone5, Zone6 and Zone7.
442
443 //HME--Offset values need to be a multiple of 4 in order to be aligned to the 4x4 HME block for downscaled 4X HME precision and HME--Offset range is [-128,127]
444 int8_t HME0XOffset_I8; // default = 32, Frame level X offset from the co-located (0, 0) location for HME0.
445 int8_t HME0YOffset_I8; // default = 24, Frame level Y offset from the co-located (0, 0) location for HME0.
446 int8_t HME1XOffset_I8; // default = -32, Frame level X offset from the co-located (0, 0) location for HME1.
447 int8_t HME1YOffset_I8; // default = -24, Frame level Y offset from the co-located (0, 0) location for HME1.
448 uint8_t MOTION_ADAPTIVE_G4;
449 uint8_t EnableLookAhead;
450 uint8_t UPD_LA_Data_Offset_U8;
451 uint8_t UPD_CQMEnabled_U8; // 0 indicates CQM is disabled for current frame; otherwise CQM is enabled.
452 uint32_t UPD_LA_TargetSize_U32; // target frame size in lookahead BRC (if EnableLookAhead == 1) or TCBRC mode. If zero, lookahead BRC or TCBRC is disabled.
453 uint32_t UPD_LA_TargetFulness_U32; // target VBV buffer fulness in lookahead BRC mode (if EnableLookAhead == 1).
454 uint8_t UPD_Delta_U8; // delta QP of pyramid
455 uint8_t UPD_ROM_CURRENT_U8; // ROM average of current frame
456 uint8_t UPD_ROM_ZERO_U8; // ROM zero percentage (255 is 100%)
457 uint8_t UPD_TCBRC_SCENARIO_U8;
458 uint8_t UPD_EnableFineGrainLA;
459 int8_t UPD_DeltaQpDcOffset;
460 uint16_t UPD_NumSlicesForRounding;
461 uint32_t UPD_UserMaxFramePB; // In Bytes
462 uint8_t RSVD2[4];
463 };
464
465 // clang-format off
466 const uint32_t CodechalVdencAvcStateG12::m_mvCostSkipBiasQPel[3][8] =
467 {
468 // for normal case
469 { 0, 6, 6, 9, 10, 13, 14, 16 },
470 // for QP = 47,48,49
471 { 0, 6, 6, 6, 6, 7, 8, 8 },
472 // for QP = 50,51
473 { 0, 6, 6, 6, 6, 7, 7, 7 }
474 };
475
476 const uint32_t CodechalVdencAvcStateG12::m_hmeCostDisplayRemote[8][CODEC_AVC_NUM_QP] =
477 {
478 //mv=0
479 {
480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
484 },
485 //mv<=16
486 {
487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
491 },
492 //mv<=32
493 {
494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[0 ~12]
495 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[13 ~25]
496 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[26 ~38]
497 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 //QP=[39 ~51]
498 },
499 //mv<=64
500 {
501 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
502 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[13 ~25]
503 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[26 ~38]
504 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 //QP=[39 ~51]
505 },
506 //mv<=128
507 {
508 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
509 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
510 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
511 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 //QP=[39 ~51]
512 },
513 //mv<=256
514 {
515 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
516 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
517 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
518 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 //QP=[39 ~51]
519 },
520 //mv<=512
521 {
522 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
523 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
524 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
525 20, 20, 20, 20, 20, 30, 30, 30, 30, 30, 30, 30, 30 //QP=[39 ~51]
526 },
527 //mv<=1024
528 {
529 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
530 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
531 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
532 20, 20, 20, 30, 40, 50, 50, 50, 50, 50, 50, 50, 50 //QP=[39 ~51]
533 }
534 };
535
536 const uint32_t CodechalVdencAvcStateG12::m_hmeCost[8][CODEC_AVC_NUM_QP] =
537 {
538 //mv=0
539 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
543 },
544 //mv<=16
545 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[13 ~25]
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[26 ~38]
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 //QP=[39 ~51]
549 },
550 //mv<=32
551 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[0 ~12]
552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[13 ~25]
553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, //QP=[26 ~38]
554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 //QP=[39 ~51]
555 },
556 //mv<=64
557 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
558 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[13 ~25]
559 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[26 ~38]
560 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 //QP=[39 ~51]
561 },
562 //mv<=128
563 { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
564 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
565 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
566 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 //QP=[39 ~51]
567 },
568 //mv<=256
569 { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[0 ~12]
570 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[13 ~25]
571 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, //QP=[26 ~38]
572 10, 10, 10, 10, 20, 30, 40, 50, 50, 50, 50, 50, 50 //QP=[39 ~51]
573 },
574 //mv<=512
575 { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
576 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
577 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
578 20, 20, 20, 40, 60, 80, 100, 100, 100, 100, 100, 100, 100 //QP=[39 ~51]
579 },
580 //mv<=1024
581 { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[0 ~12]
582 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[13 ~25]
583 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, //QP=[26 ~38]
584 20, 20, 30, 50, 100, 200, 200, 200, 200, 200, 200, 200, 200 //QP=[39 ~51]
585 }
586 };
587
588 const int8_t CodechalVdencAvcStateG12::m_brcInitDistQpDeltaI8[4] =
589 {
590 0, 0, 0, 0
591 };
592
593 const int8_t CodechalVdencAvcStateG12::m_brcInitDistQpDeltaI8LowDelay[4] =
594 {
595 -5, -2, 2, 5
596 };
597 // clang-format on
598
CodechalVdencAvcStateG12(CodechalHwInterface * hwInterface,CodechalDebugInterface * debugInterface,PCODECHAL_STANDARD_INFO standardInfo)599 CodechalVdencAvcStateG12::CodechalVdencAvcStateG12(
600 CodechalHwInterface * hwInterface,
601 CodechalDebugInterface *debugInterface,
602 PCODECHAL_STANDARD_INFO standardInfo) : CodechalVdencAvcState(hwInterface, debugInterface, standardInfo), m_sinlgePipeVeState(nullptr)
603 {
604 CODECHAL_ENCODE_FUNCTION_ENTER;
605
606 CODECHAL_ENCODE_CHK_NULL_NO_STATUS_RETURN(m_osInterface);
607
608 // Virtual Engine is enabled in default.
609 Mos_SetVirtualEngineSupported(m_osInterface, true);
610
611 m_osInterface->pfnVirtualEngineSupported(m_osInterface, false, true);
612
613 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
614 m_kernelBase = (uint8_t*)IGCODECKRN_G12;
615 #endif
616 m_kuidCommon = IDR_CODEC_HME_DS_SCOREBOARD_KERNEL;
617 AddIshSize(m_kuidCommon, m_kernelBase);
618
619 m_cmKernelEnable = true;
620 m_mbStatsSupported = true;
621
622 pfnGetKernelHeaderAndSize = nullptr;
623
624 m_vdencBrcInitDmemBufferSize = sizeof(BrcInitDmem);
625 m_vdencBrcUpdateDmemBufferSize = sizeof(BrcUpdateDmem);
626 m_vdencBrcNumOfSliceOffset = (m_waTable && MEDIA_IS_WA(m_waTable, Wa_22010554215)) ? 0 : CODECHAL_OFFSETOF(BrcUpdateDmem, NumOfSlice);
627
628 // One Gen12, avc vdenc ref index need to be one on one mapping
629 m_oneOnOneMapping = true;
630
631 m_vdboxOneDefaultUsed = true;
632 m_nonNativeBrcRoiSupported = true;
633 m_brcAdaptiveRegionBoostSupported = true;
634
635 m_hmeSupported = true;
636 m_16xMeSupported = true;
637 m_32xMeSupported = true;
638
639 CODECHAL_DEBUG_TOOL(
640 CODECHAL_ENCODE_CHK_NULL_NO_STATUS_RETURN(m_encodeParState = MOS_New(CodechalDebugEncodeParG12, this));
641 CreateAvcPar();
642 )
643 }
644
~CodechalVdencAvcStateG12()645 CodechalVdencAvcStateG12::~CodechalVdencAvcStateG12()
646 {
647 CODECHAL_ENCODE_FUNCTION_ENTER;
648
649 if (m_sinlgePipeVeState)
650 {
651 MOS_FreeMemAndSetNull(m_sinlgePipeVeState);
652 }
653 MOS_SafeFreeMemory(m_pMBQPShadowBuffer);
654
655 if (!m_swBrcMode && m_singleTaskPhaseSupported)
656 {
657 m_osInterface->pfnFreeResource(m_osInterface, &m_resPakOutputViaMmioBuffer);
658 }
659
660 CODECHAL_DEBUG_TOOL(
661 DestroyAvcPar();
662 MOS_Delete(m_encodeParState);
663 )
664 }
665
InitializeDataMember()666 void CodechalVdencAvcStateG12::InitializeDataMember()
667 {
668 CODECHAL_ENCODE_FUNCTION_ENTER;
669 CodechalVdencAvcState::InitializeDataMember();
670 if (!m_swBrcMode && m_singleTaskPhaseSupported)
671 {
672 MOS_ZeroMemory(&m_resPakOutputViaMmioBuffer, sizeof(MOS_RESOURCE));
673 }
674 }
675
InitializeState()676 MOS_STATUS CodechalVdencAvcStateG12::InitializeState()
677 {
678 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
679
680 CODECHAL_ENCODE_FUNCTION_ENTER;
681
682 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencAvcState::InitializeState());
683
684 m_sliceSizeStreamoutSupported = MEDIA_IS_WA(m_waTable, Wa_22010554215) ? false : true;
685 m_useHwScoreboard = false;
686 m_useCommonKernel = true;
687
688 if (MOS_VE_SUPPORTED(m_osInterface))
689 {
690 m_sinlgePipeVeState = (PCODECHAL_ENCODE_SINGLEPIPE_VIRTUALENGINE_STATE)MOS_AllocAndZeroMemory(sizeof(CODECHAL_ENCODE_SINGLEPIPE_VIRTUALENGINE_STATE));
691 CODECHAL_ENCODE_CHK_NULL_RETURN(m_sinlgePipeVeState);
692 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalEncodeSinglePipeVE_InitInterface(m_hwInterface, m_sinlgePipeVeState));
693 }
694
695 return eStatus;
696 }
697
AllocateResources()698 MOS_STATUS CodechalVdencAvcStateG12::AllocateResources()
699 {
700 CODECHAL_ENCODE_FUNCTION_ENTER;
701
702 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencAvcState::AllocateResources());
703
704 if (!m_swBrcMode && m_singleTaskPhaseSupported)
705 {
706 // Initiate allocation parameters and lock flags
707 MOS_ALLOC_GFXRES_PARAMS allocParamsForBufferLinear;
708 MOS_ZeroMemory(&allocParamsForBufferLinear, sizeof(MOS_ALLOC_GFXRES_PARAMS));
709 allocParamsForBufferLinear.Type = MOS_GFXRES_BUFFER;
710 allocParamsForBufferLinear.TileType = MOS_TILE_LINEAR;
711 allocParamsForBufferLinear.Format = Format_Buffer;
712
713 MOS_LOCK_PARAMS lockFlagsWriteOnly;
714 MOS_ZeroMemory(&lockFlagsWriteOnly, sizeof(MOS_LOCK_PARAMS));
715 lockFlagsWriteOnly.WriteOnly = 1;
716
717 // PAK statistics buffer
718 allocParamsForBufferLinear.dwBytes = CODECHAL_PAGE_SIZE;
719 allocParamsForBufferLinear.pBufName = "VDENC PAK Statistics MMIO Registers Output Buffer";
720
721 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
722 m_osInterface,
723 &allocParamsForBufferLinear,
724 &m_resPakOutputViaMmioBuffer),
725 "%s: Failed to allocate '%s'\n",
726 __FUNCTION__,
727 allocParamsForBufferLinear.pBufName);
728
729 uint8_t* data = (uint8_t*)m_osInterface->pfnLockResource(
730 m_osInterface,
731 &(m_resPakOutputViaMmioBuffer),
732 &lockFlagsWriteOnly);
733
734 if (data == nullptr)
735 {
736 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to Lock '%s'", allocParamsForBufferLinear.pBufName);
737 return MOS_STATUS_UNKNOWN;
738 }
739
740 MOS_ZeroMemory(data, allocParamsForBufferLinear.dwBytes);
741 m_osInterface->pfnUnlockResource(m_osInterface, &m_resPakOutputViaMmioBuffer);
742 }
743
744 return MOS_STATUS_SUCCESS;
745 }
746
SetSequenceStructs()747 MOS_STATUS CodechalVdencAvcStateG12::SetSequenceStructs()
748 {
749 CODECHAL_ENCODE_FUNCTION_ENTER;
750
751 m_forcedTCBRC = false;
752 // For g12+ tcbrc is used instead of LowDelayBRC,
753 // also needs TargetFrameSize in PPS.
754 if (m_avcSeqParam->FrameSizeTolerance == EFRAMESIZETOL_EXTREMELY_LOW && !m_avcSeqParam->LookaheadDepth)
755 {
756 CODECHAL_ENCODE_NORMALMESSAGE("LDBRC switched to TCBRC\n");
757 m_forcedTCBRC = true;
758 m_avcSeqParam->FrameSizeTolerance = EFRAMESIZETOL_NORMAL;
759 m_avcSeqParam->MBBRC = mbBrcDisabled; // no need with ARB
760 }
761
762 return CodechalVdencAvcState::SetSequenceStructs();
763 }
764
SetPictureStructs()765 MOS_STATUS CodechalVdencAvcStateG12::SetPictureStructs()
766 {
767 CODECHAL_ENCODE_FUNCTION_ENTER;
768
769 // TCBRC forced from LowDelayBRC also needs TargetFrameSize
770 if (m_forcedTCBRC)
771 {
772 if (m_avcPicParam->NumDirtyROI || m_avcPicParam->NumROI)
773 {
774 CODECHAL_ENCODE_ASSERTMESSAGE("ROI/DirtyROI disabled for TCBRC\n");
775 m_avcPicParam->NumDirtyROI = m_avcPicParam->NumROI = 0;
776 }
777 if (m_avcSeqParam->FramesPer100Sec == 0)
778 {
779 return MOS_STATUS_INVALID_PARAMETER;
780 }
781 m_avcPicParam->TargetFrameSize = uint32_t(m_avcSeqParam->TargetBitRate * (100. / 8) / m_avcSeqParam->FramesPer100Sec);
782 }
783
784 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencAvcState::SetPictureStructs());
785
786 if (m_encodeParams.bMbQpDataEnabled)
787 {
788 if (m_avcPicParam->NumDirtyROI || m_avcPicParam->NumROI)
789 {
790 CODECHAL_ENCODE_ASSERTMESSAGE("MBQP feature is not compatible with ROI/DirtyROI\n");
791 return MOS_STATUS_INVALID_PARAMETER;
792 }
793
794 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetupMBQPStreamIn(
795 &(m_resVdencStreamInBuffer[m_currRecycledBufIdx])));
796 }
797
798 return MOS_STATUS_SUCCESS;
799 }
800
ExecutePictureLevel()801 MOS_STATUS CodechalVdencAvcStateG12::ExecutePictureLevel()
802 {
803 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
804
805 CODECHAL_ENCODE_FUNCTION_ENTER;
806
807 #if MHW_HWCMDPARSER_ENABLED
808 char frameType = '\0';
809 switch (m_avcPicParam->CodingType)
810 {
811 case I_TYPE:
812 frameType = 'I';
813 break;
814 case P_TYPE:
815 frameType = 'P';
816 break;
817 case B_TYPE:
818 frameType = m_avcPicParam->RefPicFlag ? 'B' : 'b';
819 break;
820 }
821
822 auto instance = mhw::HwcmdParser::GetInstance();
823 if (instance)
824 {
825 instance->Update(frameType, nullptr);
826 }
827 #endif
828
829 MHW_BATCH_BUFFER batchBuffer;
830 MOS_ZeroMemory(&batchBuffer, sizeof(batchBuffer));
831 batchBuffer.dwOffset = m_currPass * BRC_IMG_STATE_SIZE_PER_PASS;
832 batchBuffer.bSecondLevel = true;
833
834 CODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS encodePictureLevelParams;
835 MOS_ZeroMemory(&encodePictureLevelParams, sizeof(encodePictureLevelParams));
836 encodePictureLevelParams.psPreDeblockSurface = &m_reconSurface;
837 encodePictureLevelParams.psPostDeblockSurface = &m_reconSurface;
838 encodePictureLevelParams.bBrcEnabled = false;
839 encodePictureLevelParams.pImgStateBatchBuffer = &batchBuffer;
840
841 bool suppressReconPic =
842 ((!m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef) && m_suppressReconPicSupported);
843 encodePictureLevelParams.bDeblockerStreamOutEnable = 0;
844 encodePictureLevelParams.bPreDeblockOutEnable = !m_deblockingEnabled && !suppressReconPic;
845 encodePictureLevelParams.bPostDeblockOutEnable = m_deblockingEnabled && !suppressReconPic;
846 encodePictureLevelParams.bPerMBStreamOutEnable = m_perMBStreamOutEnable;
847 if (!m_staticFrameDetectionInUse)
848 {
849 CODECHAL_ENCODE_CHK_STATUS_RETURN(LoadCosts(m_avcPicParam->CodingType,
850 m_avcPicParam->QpY + m_avcSliceParams->slice_qp_delta));
851
852 m_vdencHmeMvCostTbl = m_vdEncHmeMvCost;
853 m_vdencModeCostTbl = m_vdEncModeCost;
854 m_vdencMvCostTbl = m_vdEncMvCost;
855 }
856
857 // VDEnc HuC BRC
858 if (m_vdencBrcEnabled)
859 {
860 PerfTagSetting perfTag;
861 perfTag.Value = 0;
862 perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK;
863 perfTag.CallType = CODECHAL_ENCODE_PERFTAG_CALL_BRC_INIT_RESET;
864 perfTag.PictureCodingType = m_pictureCodingType;
865 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
866
867 SetBufferToStorePakStatistics();
868
869 // Invoke BRC init/reset FW
870 if (m_brcInit || m_brcReset)
871 {
872 CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcInitReset());
873 }
874
875 perfTag.CallType = m_currPass == 0 ? CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE : CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_SECOND_PASS;
876 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
877
878 // Invoke BRC update FW
879 CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcUpdate());
880 m_brcInit = m_brcReset = false;
881 }
882
883 PerfTagSetting perfTag;
884 perfTag.Value = 0;
885 perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK;
886 perfTag.CallType = m_currPass == 0 ? CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE : CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE_SECOND_PASS;
887 perfTag.PictureCodingType = m_pictureCodingType;
888 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
889
890 MOS_COMMAND_BUFFER cmdBuffer;
891 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
892
893 // PAK cmd buffer header insertion for 1) non STF 2) STF (except VDEnc BRC case inserted in HuC cmd buffer)
894 if (!m_singleTaskPhaseSupported || (m_firstTaskInPhase && (!m_vdencBrcEnabled)))
895 {
896 bool requestFrameTracking = false;
897
898 m_hwInterface->m_numRequestedEuSlices = ((m_frameHeight * m_frameWidth) >= m_ssdResolutionThreshold &&
899 m_targetUsage <= m_ssdTargetUsageThreshold)
900 ? m_sliceShutdownRequestState
901 : m_sliceShutdownDefaultState;
902
903 MHW_MI_MMIOREGISTERS mmioRegister;
904 bool validMmio = m_mfxInterface->ConvertToMiRegister(m_vdboxIndex, mmioRegister);
905
906 // Send command buffer header at the beginning (OS dependent)
907 // frame tracking tag is only added in the last command buffer header
908 requestFrameTracking = m_singleTaskPhaseSupported ? m_firstTaskInPhase : m_lastTaskInPhase;
909 CODECHAL_ENCODE_CHK_STATUS_RETURN(SendPrologWithFrameTracking(&cmdBuffer, requestFrameTracking, validMmio ? &mmioRegister : nullptr));
910
911 m_hwInterface->m_numRequestedEuSlices = CODECHAL_SLICE_SHUTDOWN_DEFAULT;
912 }
913
914 // Set TBL distribution to VMC = 240 for VDEnc performance
915 if (MEDIA_IS_WA(m_waTable, WaTlbAllocationForAvcVdenc) &&
916 (!m_singleTaskPhaseSupported || !m_currPass))
917 {
918 TLBAllocationParams tlbAllocationParams;
919 tlbAllocationParams.presTlbMmioBuffer = &m_vdencTlbMmioBuffer;
920 tlbAllocationParams.dwMmioMfxLra0Override = m_mmioMfxLra0Override;
921 tlbAllocationParams.dwMmioMfxLra1Override = m_mmioMfxLra1Override;
922 tlbAllocationParams.dwMmioMfxLra2Override = m_mmioMfxLra2Override;
923 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetTLBAllocation(&cmdBuffer, &tlbAllocationParams));
924 }
925
926 MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS miConditionalBatchBufferEndParams;
927 if (m_vdencBrcEnabled && !m_swBrcMode)
928 {
929 // Insert conditional batch buffer end for HuC valid IMEM loaded check
930 MOS_ZeroMemory(&miConditionalBatchBufferEndParams, sizeof(MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS));
931 miConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_resHucStatus2Buffer;
932
933 CODECHAL_ENCODE_CHK_STATUS_RETURN(
934 m_miInterface->AddMiConditionalBatchBufferEndCmd(
935 &cmdBuffer,
936 &miConditionalBatchBufferEndParams));
937 }
938
939 if (m_currPass)
940 {
941 if (m_inlineEncodeStatusUpdate && m_vdencBrcEnabled)
942 {
943 // inc dwStoreData conditionaly
944 UpdateEncodeStatus(&cmdBuffer, false);
945 }
946
947 // Insert conditional batch buffer end
948 MOS_ZeroMemory(&miConditionalBatchBufferEndParams, sizeof(MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS));
949
950 if (!m_vdencBrcEnabled)
951 {
952 miConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_encodeStatusBuf.resStatusBuffer;
953 miConditionalBatchBufferEndParams.dwOffset =
954 (m_encodeStatusBuf.wCurrIndex * m_encodeStatusBuf.dwReportSize) +
955 m_encodeStatusBuf.dwImageStatusMaskOffset + (sizeof(uint32_t) * 2);
956 }
957 else
958 {
959 // VDENC uses HuC BRC FW generated semaphore for conditional 2nd pass
960 miConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_resPakMmioBuffer;
961 }
962 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiConditionalBatchBufferEndCmd(
963 &cmdBuffer,
964 &miConditionalBatchBufferEndParams));
965 }
966
967 if (!m_currPass && m_osInterface->bTagResourceSync)
968 {
969 // This is a short term solution to solve the sync tag issue: the sync tag write for PAK is inserted at the end of 2nd pass PAK BB
970 // which may be skipped in multi-pass PAK enabled case. The idea here is to insert the previous frame's tag at the beginning
971 // of the BB and keep the current frame's tag at the end of the BB. There will be a delay for tag update but it should be fine
972 // as long as Dec/VP/Enc won't depend on this PAK so soon.
973 PMOS_RESOURCE globalGpuContextSyncTagBuffer = nullptr;
974 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnGetGpuStatusBufferResource(
975 m_osInterface,
976 globalGpuContextSyncTagBuffer));
977 CODECHAL_ENCODE_CHK_NULL_RETURN(globalGpuContextSyncTagBuffer);
978
979 uint32_t value = m_osInterface->pfnGetGpuStatusTag(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
980 MHW_MI_STORE_DATA_PARAMS params;
981 params.pOsResource = globalGpuContextSyncTagBuffer;
982 params.dwResourceOffset = m_osInterface->pfnGetGpuStatusTagOffset(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
983 params.dwValue = (value > 0) ? (value - 1) : 0;
984 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(&cmdBuffer, ¶ms));
985 }
986
987 CODECHAL_ENCODE_CHK_STATUS_RETURN(StartStatusReport(&cmdBuffer, CODECHAL_NUM_MEDIA_STATES));
988
989 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencControlStateCmd(&cmdBuffer));
990
991 // set MFX_SURFACE_STATE values
992 // Ref surface
993 MHW_VDBOX_SURFACE_PARAMS reconSurfaceParams;
994 MOS_ZeroMemory(&reconSurfaceParams, sizeof(reconSurfaceParams));
995 reconSurfaceParams.Mode = m_mode;
996 reconSurfaceParams.ucSurfaceStateId = CODECHAL_MFX_REF_SURFACE_ID;
997 reconSurfaceParams.psSurface = &m_reconSurface;
998 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(&m_reconSurface, "ReconSurface"));
999
1000 // Src surface
1001 MHW_VDBOX_SURFACE_PARAMS surfaceParams;
1002 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
1003 surfaceParams.Mode = m_mode;
1004 surfaceParams.ucSurfaceStateId = CODECHAL_MFX_SRC_SURFACE_ID;
1005 surfaceParams.psSurface = m_rawSurfaceToPak;
1006 surfaceParams.dwActualHeight = m_avcSeqParam->FrameHeight;
1007 surfaceParams.dwActualWidth = m_avcSeqParam->FrameWidth;
1008 surfaceParams.bDisplayFormatSwizzle = m_avcPicParam->bDisplayFormatSwizzle;
1009 surfaceParams.bColorSpaceSelection = (m_avcSeqParam->InputColorSpace == ECOLORSPACE_P709) ? 1 : 0;
1010 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(m_rawSurfaceToPak, "RawSurfaceToPak"));
1011
1012 MHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams;
1013 pipeBufAddrParams.pRawSurfParam = &surfaceParams;
1014 pipeBufAddrParams.pDecodedReconParam = &reconSurfaceParams;
1015 SetMfxPipeBufAddrStateParams(encodePictureLevelParams, pipeBufAddrParams);
1016 CODECHAL_ENCODE_CHK_NULL_RETURN(m_mmcState);
1017 m_mmcState->SetPipeBufAddr(&pipeBufAddrParams, &cmdBuffer);
1018
1019 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams = m_vdencInterface->CreateMhwVdboxPipeModeSelectParams();
1020 CODECHAL_ENCODE_CHK_NULL_RETURN(pipeModeSelectParams);
1021
1022 //add fill_pad_with_value
1023 if (MEDIA_IS_WA(m_waTable, Wa_AvcUnalignedHeight))
1024 {
1025 if (m_avcSeqParam->frame_cropping_flag)
1026 {
1027 m_frame_crop_bottom_offset = m_avcSeqParam->frame_crop_bottom_offset;
1028 m_frame_mbs_only_flag = m_avcSeqParam->frame_mbs_only_flag;
1029 uint32_t crop_unit_y = 2 * (2 - m_frame_mbs_only_flag);
1030 uint32_t real_height = m_oriFrameHeight - (m_frame_crop_bottom_offset * crop_unit_y);
1031 uint32_t aligned_height = MOS_ALIGN_CEIL(real_height, CODEC_AVC_MIN_BLOCK_HEIGHT);
1032 fill_pad_with_value(m_rawSurfaceToPak, real_height, aligned_height);
1033 }
1034 }
1035
1036 auto release_func = [&]()
1037 {
1038 m_vdencInterface->ReleaseMhwVdboxPipeModeSelectParams(pipeModeSelectParams);
1039 pipeModeSelectParams = nullptr;
1040 };
1041
1042 SetMfxPipeModeSelectParams(encodePictureLevelParams, *pipeModeSelectParams);
1043 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxPipeModeSelectCmd(&cmdBuffer, pipeModeSelectParams), release_func);
1044
1045 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxSurfaceCmd(&cmdBuffer, &reconSurfaceParams), release_func);
1046
1047 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxSurfaceCmd(&cmdBuffer, &surfaceParams), release_func);
1048
1049 // 4xDS surface
1050 MHW_VDBOX_SURFACE_PARAMS dsSurfaceParams;
1051 MOS_ZeroMemory(&dsSurfaceParams, sizeof(dsSurfaceParams));
1052 dsSurfaceParams.Mode = m_mode;
1053 dsSurfaceParams.ucSurfaceStateId = CODECHAL_MFX_DSRECON_SURFACE_ID;
1054 dsSurfaceParams.psSurface = m_trackedBuf->Get4xDsReconSurface(CODEC_CURR_TRACKED_BUFFER);
1055 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(dsSurfaceParams.psSurface, "4xDsReconSurface"));
1056 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxSurfaceCmd(&cmdBuffer, &dsSurfaceParams), release_func);
1057 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxPipeBufAddrCmd(&cmdBuffer, &pipeBufAddrParams), release_func);
1058
1059 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS indObjBaseAddrParams;
1060 SetMfxIndObjBaseAddrStateParams(indObjBaseAddrParams);
1061 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxIndObjBaseAddrCmd(&cmdBuffer, &indObjBaseAddrParams), release_func);
1062
1063 MHW_VDBOX_BSP_BUF_BASE_ADDR_PARAMS bspBufBaseAddrParams;
1064 SetMfxBspBufBaseAddrStateParams(bspBufBaseAddrParams);
1065 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxBspBufBaseAddrCmd(&cmdBuffer, &bspBufBaseAddrParams), release_func);
1066
1067 if (m_avcPicParam->StatusReportEnable.fields.FrameStats)
1068 {
1069 pipeModeSelectParams->bFrameStatisticsStreamOutEnable = true;
1070 }
1071 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_vdencInterface->AddVdencPipeModeSelectCmd(&cmdBuffer, pipeModeSelectParams), release_func);
1072 m_vdencInterface->ReleaseMhwVdboxPipeModeSelectParams(pipeModeSelectParams);
1073
1074 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencSrcSurfaceStateCmd(&cmdBuffer, &surfaceParams));
1075
1076 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencRefSurfaceStateCmd(&cmdBuffer, &reconSurfaceParams));
1077
1078 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencDsRefSurfaceStateCmd(&cmdBuffer, &dsSurfaceParams, 1));
1079
1080 // PerfMode is enabled only on BXT, KBL+, replace all 4x Ds refs with the 1st L0 ref
1081 if (m_vdencInterface->IsPerfModeSupported() && m_perfModeEnabled[m_avcSeqParam->TargetUsage] &&
1082 pipeBufAddrParams.dwNumRefIdxL0ActiveMinus1 == 0)
1083 {
1084 pipeBufAddrParams.dwNumRefIdxL0ActiveMinus1 = 1;
1085 pipeBufAddrParams.presVdencReferences[1] = nullptr;
1086 pipeBufAddrParams.presVdenc4xDsSurface[1] = pipeBufAddrParams.presVdenc4xDsSurface[0];
1087 }
1088
1089 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencPipeBufAddrCmd(&cmdBuffer, &pipeBufAddrParams));
1090
1091 MHW_VDBOX_VDENC_CQPT_STATE_PARAMS vdencCQPTStateParams;
1092 SetVdencCqptStateParams(vdencCQPTStateParams);
1093 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencConstQPStateCmd(&cmdBuffer, &vdencCQPTStateParams));
1094
1095 if (encodePictureLevelParams.bBrcEnabled && m_avcSeqParam->RateControlMethod != RATECONTROL_ICQ)
1096 {
1097 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferStartCmd(
1098 &cmdBuffer,
1099 encodePictureLevelParams.pImgStateBatchBuffer));
1100 }
1101 else
1102 {
1103 //Set MFX_AVC_IMG_STATE command
1104 PMHW_VDBOX_AVC_IMG_PARAMS imageStateParams = CreateMhwVdboxAvcImgParams();
1105 CODECHAL_ENCODE_CHK_NULL_RETURN(imageStateParams);
1106 SetMfxAvcImgStateParams(*imageStateParams);
1107
1108 PMHW_BATCH_BUFFER secondLevelBatchBufferUsed = nullptr;
1109
1110 // VDENC CQP case
1111 if (!m_vdencBrcEnabled)
1112 {
1113 // VDENC case uses multiple buffers for concurrency between SFD and VDENC
1114 secondLevelBatchBufferUsed = &(m_batchBufferForVdencImgStat[m_currRecycledBufIdx]);
1115
1116 if (!m_staticFrameDetectionInUse)
1117 {
1118 // CQP case, driver programs the 2nd Level BB
1119 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_LockBb(m_osInterface, secondLevelBatchBufferUsed));
1120
1121 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxAvcImgCmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
1122
1123 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencAvcCostStateCmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
1124
1125 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencCmd3Cmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
1126
1127 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencImgStateCmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
1128
1129 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(nullptr, secondLevelBatchBufferUsed));
1130
1131 #if MHW_HWCMDPARSER_ENABLED
1132 auto instance = mhw::HwcmdParser::GetInstance();
1133 if (instance)
1134 {
1135 instance->ParseCmdBuf(IGFX_UNKNOWN, (uint32_t *)(secondLevelBatchBufferUsed->pData),
1136 secondLevelBatchBufferUsed->iCurrent / sizeof(uint32_t));
1137 }
1138 #endif
1139
1140 CODECHAL_DEBUG_TOOL(
1141 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulatePakParam(
1142 nullptr,
1143 secondLevelBatchBufferUsed));
1144
1145 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateEncParam(
1146 0,
1147 nullptr));
1148
1149 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpEncodeImgStats(nullptr));)
1150
1151 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_UnlockBb(m_osInterface, secondLevelBatchBufferUsed, true));
1152 }
1153 else
1154 {
1155 // SFD enabled, SFD kernel updates VDENC IMG STATE
1156 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxAvcImgCmd(&cmdBuffer, nullptr, imageStateParams));
1157 //#if (_DEBUG || _RELEASE_INTERNAL)
1158 //secondLevelBatchBufferUsed->iLastCurrent = CODECHAL_ENCODE_VDENC_IMG_STATE_CMD_SIZE + CODECHAL_ENCODE_MI_BATCH_BUFFER_END_CMD_SIZE;
1159 //#endif
1160 CODECHAL_DEBUG_TOOL(
1161 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulatePakParam(
1162 &cmdBuffer,
1163 nullptr));
1164 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpEncodeImgStats(&cmdBuffer));)
1165 }
1166 }
1167 else
1168 {
1169 // current location to add cmds in 2nd level batch buffer
1170 m_batchBufferForVdencImgStat[0].iCurrent = 0;
1171 // reset starting location (offset) executing 2nd level batch buffer for each frame & each pass
1172 m_batchBufferForVdencImgStat[0].dwOffset = 0;
1173 secondLevelBatchBufferUsed = &(m_batchBufferForVdencImgStat[0]);
1174 }
1175 MOS_Delete(imageStateParams);
1176
1177 HalOcaInterface::OnSubLevelBBStart(cmdBuffer, (MOS_CONTEXT_HANDLE)m_osInterface->pOsContext, &secondLevelBatchBufferUsed->OsResource, 0, true, 0);
1178
1179 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferStartCmd(&cmdBuffer, secondLevelBatchBufferUsed));
1180
1181 CODECHAL_DEBUG_TOOL(
1182 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->Dump2ndLvlBatch(
1183 secondLevelBatchBufferUsed,
1184 CODECHAL_MEDIA_STATE_ENC_NORMAL,
1185 nullptr));)
1186 }
1187
1188 MHW_VDBOX_QM_PARAMS qmParams;
1189 MHW_VDBOX_QM_PARAMS fqmParams;
1190 SetMfxQmStateParams(qmParams, fqmParams);
1191 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxQmCmd(&cmdBuffer, &qmParams));
1192 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxFqmCmd(&cmdBuffer, &fqmParams));
1193
1194 if (m_pictureCodingType == B_TYPE)
1195 {
1196 // Add AVC Direct Mode command
1197 MHW_VDBOX_AVC_DIRECTMODE_PARAMS directmodeParams;
1198 MOS_ZeroMemory(&directmodeParams, sizeof(directmodeParams));
1199 directmodeParams.CurrPic = m_avcPicParam->CurrReconstructedPic;
1200 directmodeParams.isEncode = true;
1201 directmodeParams.uiUsedForReferenceFlags = 0xFFFFFFFF;
1202 directmodeParams.pAvcPicIdx = &(m_picIdx[0]);
1203 directmodeParams.avcRefList = (void**)m_refList;
1204 directmodeParams.bPicIdRemappingInUse = false;
1205 directmodeParams.bDisableDmvBuffers = true;
1206 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxAvcDirectmodeCmd(&cmdBuffer, &directmodeParams));
1207 }
1208
1209 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
1210
1211 return eStatus;
1212 }
1213
SetAndPopulateVEHintParams(PMOS_COMMAND_BUFFER cmdBuffer)1214 MOS_STATUS CodechalVdencAvcStateG12::SetAndPopulateVEHintParams(
1215 PMOS_COMMAND_BUFFER cmdBuffer)
1216 {
1217 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1218
1219 CODECHAL_ENCODE_FUNCTION_ENTER;
1220
1221 if (!MOS_VE_SUPPORTED(m_osInterface))
1222 {
1223 return eStatus;
1224 }
1225
1226 if (!MOS_VE_CTXBASEDSCHEDULING_SUPPORTED(m_osInterface))
1227 {
1228 MOS_VIRTUALENGINE_SET_PARAMS vesetParams;
1229 MOS_ZeroMemory(&vesetParams, sizeof(vesetParams));
1230 vesetParams.bNeedSyncWithPrevious = true;
1231 vesetParams.bSFCInUse = false;
1232 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalEncodeSinglePipeVE_SetHintParams(m_sinlgePipeVeState, &vesetParams));
1233 }
1234 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalEncodeSinglePipeVE_PopulateHintParams(m_sinlgePipeVeState, cmdBuffer, true));
1235
1236 return eStatus;
1237 }
1238
SetupMBQPStreamIn(PMOS_RESOURCE vdencStreamIn)1239 MOS_STATUS CodechalVdencAvcStateG12::SetupMBQPStreamIn(
1240 PMOS_RESOURCE vdencStreamIn)
1241 {
1242 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1243
1244 CODECHAL_ENCODE_FUNCTION_ENTER;
1245
1246 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencStreamIn);
1247
1248 m_vdencStreamInEnabled = true;
1249
1250 MOS_LOCK_PARAMS lockFlags;
1251 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
1252 lockFlags.WriteOnly = true;
1253
1254 auto pData = (CODECHAL_VDENC_STREAMIN_STATE*)m_osInterface->pfnLockResource(
1255 m_osInterface,
1256 vdencStreamIn,
1257 &lockFlags);
1258 CODECHAL_ENCODE_CHK_NULL_RETURN(pData);
1259
1260 MOS_ZeroMemory(pData, m_picHeightInMb * m_picWidthInMb * CODECHAL_CACHELINE_SIZE);
1261
1262 MOS_LOCK_PARAMS lockFlagsReadOnly;
1263 MOS_ZeroMemory(&lockFlagsReadOnly, sizeof(MOS_LOCK_PARAMS));
1264 lockFlagsReadOnly.ReadOnly = true;
1265
1266 auto pMBQPBuffer = (uint8_t*)m_osInterface->pfnLockResource(
1267 m_osInterface,
1268 &(m_encodeParams.psMbQpDataSurface->OsResource),
1269 &lockFlagsReadOnly);
1270 CODECHAL_ENCODE_CHK_NULL_RETURN(pMBQPBuffer);
1271
1272 uint32_t uiSize = (uint32_t)m_encodeParams.psMbQpDataSurface->OsResource.pGmmResInfo->GetSizeSurface();
1273 uint32_t uiAlign = 64;
1274 if (uiSize + uiAlign > m_uiMBQPShadowBufferSize)
1275 {
1276 m_uiMBQPShadowBufferSize = uiSize + uiAlign;
1277 m_pMBQPShadowBuffer = (uint8_t*)MOS_ReallocMemory(m_pMBQPShadowBuffer, m_uiMBQPShadowBufferSize);
1278 }
1279 CODECHAL_ENCODE_CHK_NULL_RETURN(m_pMBQPShadowBuffer);
1280
1281 auto pMBQPShadowBufferBase = (uint8_t*)((((uint64_t)(m_pMBQPShadowBuffer) + uiAlign - 1) / uiAlign) * uiAlign);
1282 MOS_SecureMemcpy(pMBQPShadowBufferBase, uiSize, pMBQPBuffer, uiSize);
1283
1284 CopyMBQPDataToStreamIn(pData, pMBQPShadowBufferBase);
1285
1286 m_osInterface->pfnUnlockResource(
1287 m_osInterface,
1288 vdencStreamIn);
1289 m_osInterface->pfnUnlockResource(
1290 m_osInterface,
1291 &m_encodeParams.psMbQpDataSurface->OsResource);
1292
1293 return eStatus;
1294 }
1295
SetGpuCtxCreatOption()1296 MOS_STATUS CodechalVdencAvcStateG12::SetGpuCtxCreatOption()
1297 {
1298 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1299
1300 CODECHAL_ENCODE_FUNCTION_ENTER;
1301
1302 if (!MOS_VE_CTXBASEDSCHEDULING_SUPPORTED(m_osInterface))
1303 {
1304 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncoderState::SetGpuCtxCreatOption());
1305 }
1306 else
1307 {
1308 m_gpuCtxCreatOpt = MOS_New(MOS_GPUCTX_CREATOPTIONS_ENHANCED);
1309 CODECHAL_ENCODE_CHK_NULL_RETURN(m_gpuCtxCreatOpt);
1310
1311 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalEncodeSinglePipeVE_ConstructParmsForGpuCtxCreation(
1312 m_sinlgePipeVeState,
1313 (PMOS_GPUCTX_CREATOPTIONS_ENHANCED)m_gpuCtxCreatOpt));
1314 }
1315
1316 return eStatus;
1317 }
1318
UserFeatureKeyReport()1319 MOS_STATUS CodechalVdencAvcStateG12::UserFeatureKeyReport()
1320 {
1321 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1322
1323 CODECHAL_ENCODE_FUNCTION_ENTER;
1324
1325 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencAvcState::UserFeatureKeyReport());
1326
1327 #if (_DEBUG || _RELEASE_INTERNAL)
1328
1329 // VE2.0 Reporting
1330 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_ENABLE_ENCODE_VE_CTXSCHEDULING_ID, MOS_VE_CTXBASEDSCHEDULING_SUPPORTED(m_osInterface), m_osInterface->pOsContext);
1331
1332 #endif // _DEBUG || _RELEASE_INTERNAL
1333 return eStatus;
1334 }
1335
SetBufferToStorePakStatistics()1336 void CodechalVdencAvcStateG12::SetBufferToStorePakStatistics()
1337 {
1338 CODECHAL_ENCODE_FUNCTION_ENTER;
1339
1340 if (!m_swBrcMode && m_singleTaskPhaseSupported)
1341 {
1342 // Store PAK statistics after encode Frame_N into separate internal buffer to get rid of
1343 // dependency with the DMEM buffer for Frame_N+1
1344 //
1345 // This data will be copied into DMEM for Frame_N+1 at the start of CMD buffer for Frame_N+1
1346 // using MI_COPY_MEM_MEM cmd
1347 m_resVdencBrcUpdateDmemBufferPtr[0] = &m_resPakOutputViaMmioBuffer;
1348 m_resVdencBrcUpdateDmemBufferPtr[1] = nullptr;
1349 }
1350 else
1351 {
1352 CodechalVdencAvcState::SetBufferToStorePakStatistics();
1353 }
1354 }
1355
AddMiStoreForHWOutputToHucDmem(PMOS_COMMAND_BUFFER cmdBuffer)1356 MOS_STATUS CodechalVdencAvcStateG12::AddMiStoreForHWOutputToHucDmem(PMOS_COMMAND_BUFFER cmdBuffer)
1357 {
1358 CODECHAL_ENCODE_FUNCTION_ENTER;
1359
1360 if (!m_swBrcMode && m_singleTaskPhaseSupported)
1361 {
1362 // Copy PAK statistics data from internal buffer to DMEM
1363 MHW_MI_COPY_MEM_MEM_PARAMS copyMemMemParams = {};
1364 copyMemMemParams.presSrc = &m_resPakOutputViaMmioBuffer;
1365 copyMemMemParams.presDst = &(m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass]);
1366
1367 copyMemMemParams.dwSrcOffset = copyMemMemParams.dwDstOffset = CODECHAL_OFFSETOF(BrcUpdateDmem, FrameByteCount);
1368 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiCopyMemMemCmd(
1369 cmdBuffer,
1370 ©MemMemParams));
1371
1372 copyMemMemParams.dwSrcOffset = copyMemMemParams.dwDstOffset = CODECHAL_OFFSETOF(BrcUpdateDmem, ImgStatusCtrl);
1373 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiCopyMemMemCmd(
1374 cmdBuffer,
1375 ©MemMemParams));
1376
1377 copyMemMemParams.dwSrcOffset = copyMemMemParams.dwDstOffset = m_vdencBrcNumOfSliceOffset;
1378 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiCopyMemMemCmd(
1379 cmdBuffer,
1380 ©MemMemParams));
1381 }
1382
1383 return MOS_STATUS_SUCCESS;
1384 }
1385
SubmitCommandBuffer(PMOS_COMMAND_BUFFER cmdBuffer,bool bNullRendering)1386 MOS_STATUS CodechalVdencAvcStateG12::SubmitCommandBuffer(
1387 PMOS_COMMAND_BUFFER cmdBuffer,
1388 bool bNullRendering)
1389 {
1390 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1391
1392 CODECHAL_ENCODE_FUNCTION_ENTER;
1393
1394 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
1395
1396 HalOcaInterface::On1stLevelBBEnd(*cmdBuffer, *m_osInterface);
1397 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetAndPopulateVEHintParams(cmdBuffer));
1398 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnSubmitCommandBuffer(m_osInterface, cmdBuffer, bNullRendering));
1399 return eStatus;
1400 }
1401
InitKernelStateSFD()1402 MOS_STATUS CodechalVdencAvcStateG12::InitKernelStateSFD()
1403 {
1404 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1405
1406 CODECHAL_ENCODE_FUNCTION_ENTER;
1407
1408 auto renderEngineInterface = m_hwInterface->GetRenderInterface();
1409 auto stateHeapInterface = m_renderEngineInterface->m_stateHeapInterface;
1410 CODECHAL_ENCODE_CHK_NULL_RETURN(stateHeapInterface);
1411
1412 uint8_t* kernelBinary;
1413 uint32_t kernelSize;
1414
1415 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuidCommon, &kernelBinary, &kernelSize);
1416 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
1417
1418 CODECHAL_KERNEL_HEADER currKrnHeader;
1419 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetCommonKernelHeaderAndSizeG12(
1420 kernelBinary,
1421 ENC_SFD,
1422 0,
1423 (void*)&currKrnHeader,
1424 &kernelSize));
1425
1426 auto kernelStatePtr = m_sfdKernelState;
1427 kernelStatePtr->KernelParams.iBTCount = sfdNumSurfaces;
1428 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
1429 kernelStatePtr->KernelParams.iCurbeLength = sizeof(SfdCurbe);
1430 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
1431 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
1432 kernelStatePtr->KernelParams.iIdCount = 1;
1433 kernelStatePtr->KernelParams.iInlineDataLength = 0;
1434
1435 kernelStatePtr->dwCurbeOffset = stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
1436 kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
1437 kernelStatePtr->KernelParams.iSize = kernelSize;
1438
1439 CODECHAL_ENCODE_CHK_STATUS_RETURN(stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
1440 stateHeapInterface,
1441 kernelStatePtr->KernelParams.iBTCount,
1442 &kernelStatePtr->dwSshSize,
1443 &kernelStatePtr->dwBindingTableSize));
1444
1445 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(stateHeapInterface, kernelStatePtr));
1446
1447 return eStatus;
1448 }
1449
Initialize(CodechalSetting * settings)1450 MOS_STATUS CodechalVdencAvcStateG12::Initialize(CodechalSetting * settings)
1451 {
1452 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1453
1454 CODECHAL_ENCODE_FUNCTION_ENTER;
1455
1456 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencAvcState::Initialize(settings));
1457
1458 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
1459 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
1460 MOS_UserFeature_ReadValue_ID(
1461 nullptr,
1462 __MEDIA_USER_FEATURE_VALUE_VDENC_ULTRA_MODE_ENABLE_ID,
1463 &userFeatureData,
1464 m_osInterface->pOsContext);
1465 m_vdencUltraModeEnable = userFeatureData.bData == 1;
1466
1467 return eStatus;
1468 }
1469
ProcessRoiDeltaQp()1470 bool CodechalVdencAvcStateG12::ProcessRoiDeltaQp()
1471 {
1472 CODECHAL_ENCODE_FUNCTION_ENTER;
1473
1474 // Intialize ROIDistinctDeltaQp to be min expected delta qp, setting to -128
1475 // Check if forceQp is needed or not
1476 // forceQp is enabled if there are greater than 3 distinct delta qps or if the deltaqp is beyond range (-8, 7)
1477 for (auto k = 0; k < m_maxNumRoi; k++)
1478 {
1479 m_avcPicParam->ROIDistinctDeltaQp[k] = -128;
1480 }
1481
1482 int32_t numQp = 0;
1483 for (int32_t i = 0; i < m_avcPicParam->NumROI; i++)
1484 {
1485 bool dqpNew = true;
1486
1487 //Get distinct delta Qps among all ROI regions, index 0 having the lowest delta qp
1488 int32_t k = numQp - 1;
1489 for (; k >= 0; k--)
1490 {
1491 if (m_avcPicParam->ROI[i].PriorityLevelOrDQp == m_avcPicParam->ROIDistinctDeltaQp[k] ||
1492 m_avcPicParam->ROI[i].PriorityLevelOrDQp == 0)
1493 {
1494 dqpNew = false;
1495 break;
1496 }
1497 else if (m_avcPicParam->ROI[i].PriorityLevelOrDQp < m_avcPicParam->ROIDistinctDeltaQp[k])
1498 {
1499 continue;
1500 }
1501 else
1502 {
1503 break;
1504 }
1505 }
1506
1507 if (dqpNew)
1508 {
1509 for (int32_t j = numQp - 1; (j >= k + 1 && j >= 0); j--)
1510 {
1511 m_avcPicParam->ROIDistinctDeltaQp[j + 1] = m_avcPicParam->ROIDistinctDeltaQp[j];
1512 }
1513 m_avcPicParam->ROIDistinctDeltaQp[k + 1] = m_avcPicParam->ROI[i].PriorityLevelOrDQp;
1514 numQp++;
1515 }
1516 }
1517
1518 //Set the ROI DeltaQp to zero for remaining array elements
1519 for (auto k = numQp; k < m_maxNumRoi; k++)
1520 {
1521 m_avcPicParam->ROIDistinctDeltaQp[k] = 0;
1522 }
1523 m_avcPicParam->NumROIDistinctDeltaQp = (int8_t)numQp;
1524
1525 // return whether is native ROI or not
1526 return !(numQp > m_maxNumNativeRoi || m_avcPicParam->ROIDistinctDeltaQp[0] < -8 || m_avcPicParam->ROIDistinctDeltaQp[numQp - 1] > 7);
1527 }
1528
IsMBBRCControlEnabled()1529 bool CodechalVdencAvcStateG12::IsMBBRCControlEnabled()
1530 {
1531 return m_mbBrcEnabled;
1532 }
1533
1534
CheckSupportedFormat(PMOS_SURFACE surface)1535 bool CodechalVdencAvcStateG12::CheckSupportedFormat(PMOS_SURFACE surface)
1536 {
1537 CODECHAL_ENCODE_FUNCTION_ENTER;
1538
1539 bool colorFormatSupported = true;
1540 if (IS_Y_MAJOR_TILE_FORMAT(surface->TileType))
1541 {
1542 switch (surface->Format)
1543 {
1544 case Format_NV12:
1545 break;
1546 default:
1547 colorFormatSupported = false;
1548 break;
1549 }
1550 }
1551 else if (surface->TileType == MOS_TILE_LINEAR)
1552 {
1553 switch (surface->Format)
1554 {
1555 case Format_NV12:
1556 case Format_YUY2:
1557 case Format_YUYV:
1558 case Format_YVYU:
1559 case Format_UYVY:
1560 case Format_VYUY:
1561 case Format_AYUV:
1562 case Format_A8R8G8B8:
1563 case Format_A8B8G8R8:
1564 break;
1565 default:
1566 colorFormatSupported = false;
1567 break;
1568 }
1569 }
1570 else
1571 {
1572 colorFormatSupported = false;
1573 }
1574
1575 return colorFormatSupported;
1576 }
1577
GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params,PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)1578 MOS_STATUS CodechalVdencAvcStateG12::GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params, PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)
1579 {
1580 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1581
1582 CODECHAL_ENCODE_FUNCTION_ENTER;
1583
1584 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
1585 CODECHAL_ENCODE_CHK_NULL_RETURN(trellisQuantParams);
1586
1587 trellisQuantParams->dwTqEnabled = TrellisQuantizationEnable[params->ucTargetUsage];
1588 trellisQuantParams->dwTqRounding = trellisQuantParams->dwTqEnabled ? TrellisQuantizationRounding[params->ucTargetUsage] : 0;
1589
1590 return eStatus;
1591 }
1592
AddHucOutputRegistersHandling(MmioRegistersHuc * mmioRegisters,PMOS_COMMAND_BUFFER cmdBuffer,bool addToEncodeStatus)1593 MOS_STATUS CodechalVdencAvcStateG12::AddHucOutputRegistersHandling(
1594 MmioRegistersHuc* mmioRegisters,
1595 PMOS_COMMAND_BUFFER cmdBuffer,
1596 bool addToEncodeStatus)
1597 {
1598 CODECHAL_ENCODE_FUNCTION_ENTER;
1599
1600 CODECHAL_ENCODE_CHK_NULL_RETURN(mmioRegisters);
1601 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
1602
1603 CODECHAL_ENCODE_CHK_STATUS_RETURN(StoreHucErrorStatus(mmioRegisters, cmdBuffer, addToEncodeStatus));
1604 CODECHAL_ENCODE_CHK_STATUS_RETURN(InsertConditionalBBEndWithHucErrorStatus(cmdBuffer));
1605
1606 return MOS_STATUS_SUCCESS;
1607 }
1608
InsertConditionalBBEndWithHucErrorStatus(PMOS_COMMAND_BUFFER cmdBuffer)1609 MOS_STATUS CodechalVdencAvcStateG12::InsertConditionalBBEndWithHucErrorStatus(PMOS_COMMAND_BUFFER cmdBuffer)
1610 {
1611 CODECHAL_ENCODE_FUNCTION_ENTER;
1612
1613 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
1614
1615 MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS miEnhancedConditionalBatchBufferEndParams;
1616
1617 MOS_ZeroMemory(
1618 &miEnhancedConditionalBatchBufferEndParams,
1619 sizeof(MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS));
1620
1621 miEnhancedConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_resHucErrorStatusBuffer;
1622
1623 miEnhancedConditionalBatchBufferEndParams.dwParamsType = MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS::ENHANCED_PARAMS;
1624 miEnhancedConditionalBatchBufferEndParams.enableEndCurrentBatchBuffLevel = false;
1625 miEnhancedConditionalBatchBufferEndParams.compareOperation = MAD_EQUAL_IDD;
1626
1627 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiConditionalBatchBufferEndCmd(
1628 cmdBuffer,
1629 (PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS)(&miEnhancedConditionalBatchBufferEndParams)));
1630
1631 return MOS_STATUS_SUCCESS;
1632 }
1633
SetDmemHuCBrcInitReset()1634 MOS_STATUS CodechalVdencAvcStateG12::SetDmemHuCBrcInitReset()
1635 {
1636 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1637
1638 CODECHAL_ENCODE_FUNCTION_ENTER;
1639
1640 // Setup BRC DMEM
1641 MOS_LOCK_PARAMS lockFlagsWriteOnly;
1642 memset(&lockFlagsWriteOnly, 0, sizeof(MOS_LOCK_PARAMS));
1643 lockFlagsWriteOnly.WriteOnly = 1;
1644 auto hucVDEncBrcInitDmem = (BrcInitDmem *)m_osInterface->pfnLockResource(
1645 m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx], &lockFlagsWriteOnly);
1646
1647 CODECHAL_ENCODE_CHK_NULL_RETURN(hucVDEncBrcInitDmem);
1648 memset(hucVDEncBrcInitDmem, 0, sizeof(BrcInitDmem));
1649
1650 SetDmemHuCBrcInitResetImpl<BrcInitDmem>(hucVDEncBrcInitDmem);
1651
1652 // enable fractional QP by extended rho domain setting
1653 hucVDEncBrcInitDmem->INIT_FracQPEnable_U8 = (uint8_t)m_vdencInterface->IsRhoDomainStatsEnabled();
1654 // enable fractional QP for TCBRC
1655 if ((m_avcPicParam->TargetFrameSize > 0) && (m_lookaheadDepth == 0))
1656 hucVDEncBrcInitDmem->INIT_FracQPEnable_U8 = 1;
1657
1658 hucVDEncBrcInitDmem->INIT_SinglePassOnly = m_vdencSinglePassEnable ? true : false;
1659
1660 if (m_avcSeqParam->ScenarioInfo == ESCENARIO_GAMESTREAMING)
1661 {
1662 if (m_avcSeqParam->RateControlMethod == RATECONTROL_VBR)
1663 {
1664 m_avcSeqParam->MaxBitRate = m_avcSeqParam->TargetBitRate;
1665 }
1666
1667 // Disable delta QP adaption for non-VCM/ICQ/LowDelay until we have better algorithm
1668 if ((m_avcSeqParam->RateControlMethod != RATECONTROL_VCM) &&
1669 (m_avcSeqParam->RateControlMethod != RATECONTROL_ICQ) &&
1670 (m_avcSeqParam->FrameSizeTolerance != EFRAMESIZETOL_EXTREMELY_LOW))
1671 {
1672 hucVDEncBrcInitDmem->INIT_DeltaQP_Adaptation_U8 = 0;
1673 }
1674
1675 hucVDEncBrcInitDmem->INIT_New_DeltaQP_Adaptation_U8 = 1;
1676 }
1677
1678 if (((m_avcSeqParam->TargetUsage & 0x07) == TARGETUSAGE_BEST_SPEED) &&
1679 (m_avcSeqParam->FrameWidth >= m_singlePassMinFrameWidth) &&
1680 (m_avcSeqParam->FrameHeight >= m_singlePassMinFrameHeight) &&
1681 (m_avcSeqParam->FramesPer100Sec >= m_singlePassMinFramePer100s))
1682 {
1683 hucVDEncBrcInitDmem->INIT_SinglePassOnly = true;
1684 }
1685
1686 hucVDEncBrcInitDmem->INIT_LookaheadDepth_U8 = m_lookaheadDepth;
1687
1688 //Override the DistQPDelta setting
1689 if (m_mbBrcEnabled)
1690 {
1691 if (m_avcSeqParam->FrameSizeTolerance == EFRAMESIZETOL_EXTREMELY_LOW)
1692 {
1693 MOS_SecureMemcpy(hucVDEncBrcInitDmem->INIT_DistQPDelta_I8, 4 * sizeof(int8_t), (void*)m_brcInitDistQpDeltaI8LowDelay, 4 * sizeof(int8_t));
1694 }
1695 else
1696 {
1697 MOS_SecureMemcpy(hucVDEncBrcInitDmem->INIT_DistQPDelta_I8, 4 * sizeof(int8_t), (void*)m_brcInitDistQpDeltaI8, 4 * sizeof(int8_t));
1698 }
1699 }
1700
1701 CODECHAL_DEBUG_TOOL(
1702 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcInitParam(hucVDEncBrcInitDmem));
1703 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpParsedBRCInitDmem(hucVDEncBrcInitDmem));
1704 )
1705
1706 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx]);
1707
1708 return eStatus;
1709 }
1710
DeltaQPUpdate(uint8_t QpModulationStrength)1711 MOS_STATUS CodechalVdencAvcStateG12::DeltaQPUpdate(uint8_t QpModulationStrength)
1712 {
1713 CODECHAL_ENCODE_FUNCTION_ENTER;
1714
1715 m_qpModulationStrength = QpModulationStrength;
1716
1717 return MOS_STATUS_SUCCESS;
1718 }
1719
SetDmemHuCBrcUpdate()1720 MOS_STATUS CodechalVdencAvcStateG12::SetDmemHuCBrcUpdate()
1721 {
1722 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1723
1724 CODECHAL_ENCODE_FUNCTION_ENTER;
1725
1726 // Program update DMEM
1727 MOS_LOCK_PARAMS lockFlags;
1728 memset(&lockFlags, 0, sizeof(MOS_LOCK_PARAMS));
1729 lockFlags.WriteOnly = 1;
1730 auto hucVDEncBrcDmem = (BrcUpdateDmem *)m_osInterface->pfnLockResource(
1731 m_osInterface, &m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass], &lockFlags);
1732 CODECHAL_ENCODE_CHK_NULL_RETURN(hucVDEncBrcDmem);
1733 SetDmemHuCBrcUpdateImpl<BrcUpdateDmem>(hucVDEncBrcDmem);
1734
1735 if (hucVDEncBrcDmem->UPD_CurrFrameType_U8 == 1 && m_avcPicParam->RefPicFlag == 1)
1736 hucVDEncBrcDmem->UPD_CurrFrameType_U8 = 3; // separated type for reference B
1737
1738 MOS_LOCK_PARAMS lockFlagsReadOnly;
1739 MOS_ZeroMemory(&lockFlagsReadOnly, sizeof(MOS_LOCK_PARAMS));
1740 lockFlagsReadOnly.ReadOnly = 1;
1741 auto initDmem = (BrcInitDmem *)m_osInterface->pfnLockResource(
1742 m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx], &lockFlagsReadOnly);
1743 CODECHAL_ENCODE_CHK_NULL_RETURN(initDmem);
1744
1745 if (initDmem->INIT_AdaptiveHMEExtensionEnable_U8)
1746 {
1747 hucVDEncBrcDmem->HME0XOffset_I8 = 32;
1748 hucVDEncBrcDmem->HME0YOffset_I8 = 24;
1749 hucVDEncBrcDmem->HME1XOffset_I8 = -32;
1750 hucVDEncBrcDmem->HME1YOffset_I8 = -24;
1751 }
1752
1753 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx]);
1754
1755 if (m_16xMeSupported && (m_pictureCodingType == P_TYPE))
1756 {
1757 hucVDEncBrcDmem->HmeDistAvailable_U8 = 1;
1758 }
1759 hucVDEncBrcDmem->UPD_WidthInMB_U16 = m_picWidthInMb;
1760 hucVDEncBrcDmem->UPD_HeightInMB_U16 = m_picHeightInMb;
1761
1762 hucVDEncBrcDmem->MOTION_ADAPTIVE_G4 = (m_avcSeqParam->ScenarioInfo == ESCENARIO_GAMESTREAMING) || ((m_avcPicParam->TargetFrameSize > 0) && (m_lookaheadDepth == 0)); // GS or TCBRC
1763 hucVDEncBrcDmem->UPD_CQMEnabled_U8 = m_avcSeqParam->seq_scaling_matrix_present_flag || m_avcPicParam->pic_scaling_matrix_present_flag;
1764
1765 hucVDEncBrcDmem->UPD_LA_TargetSize_U32 = m_avcPicParam->TargetFrameSize << 3;
1766
1767 if (m_lookaheadDepth > 0)
1768 {
1769 DeltaQPUpdate(m_avcPicParam->QpModulationStrength);
1770 hucVDEncBrcDmem->EnableLookAhead = 1;
1771 hucVDEncBrcDmem->UPD_LA_TargetFulness_U32 = m_targetBufferFulness;
1772 hucVDEncBrcDmem->UPD_Delta_U8 = m_qpModulationStrength;
1773 }
1774
1775 // Temporal fix because of DDI flag deprication
1776 // Use Cloud Gaming mode by default
1777 hucVDEncBrcDmem->UPD_TCBRC_SCENARIO_U8 = 0;
1778
1779 hucVDEncBrcDmem->UPD_NumSlicesForRounding = GetAdaptiveRoundingNumSlices();
1780 hucVDEncBrcDmem->UPD_UserMaxFramePB = 2 * m_avcPicParam->TargetFrameSize;
1781
1782 CODECHAL_DEBUG_TOOL(
1783 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcUpdateParam(hucVDEncBrcDmem));
1784 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpParsedBRCUpdateDmem(hucVDEncBrcDmem));
1785 )
1786
1787 m_osInterface->pfnUnlockResource(m_osInterface, &(m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass]));
1788
1789 return eStatus;
1790 }
1791
LoadMvCost(uint8_t qp)1792 MOS_STATUS CodechalVdencAvcStateG12::LoadMvCost(uint8_t qp)
1793 {
1794 CODECHAL_ENCODE_FUNCTION_ENTER;
1795
1796 for (uint8_t i = 0; i < 8; i++)
1797 {
1798 m_vdEncMvCost[i] = Map44LutValue((uint32_t)(m_mvCostSkipBiasQPel[0][i]), 0x6f);
1799 }
1800
1801 if (!m_vdencBrcEnabled)
1802 {
1803 if (qp == 47 || qp == 48 || qp == 49)
1804 {
1805 for (uint8_t i = 3; i < 8; i++)
1806 {
1807 m_vdEncMvCost[i] = Map44LutValue((uint32_t)(m_mvCostSkipBiasQPel[1][i]), 0x6f);
1808 }
1809 }
1810 if (qp == 50 || qp == 51)
1811 {
1812 for (uint8_t i = 3; i < 8; i++)
1813 {
1814 m_vdEncMvCost[i] = Map44LutValue((uint32_t)(m_mvCostSkipBiasQPel[2][i]), 0x6f);
1815 }
1816 }
1817 }
1818
1819 return MOS_STATUS_SUCCESS;
1820 }
1821
LoadHmeMvCost(uint8_t qp)1822 MOS_STATUS CodechalVdencAvcStateG12::LoadHmeMvCost(uint8_t qp)
1823 {
1824 CODECHAL_ENCODE_FUNCTION_ENTER;
1825
1826 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS avcSeqParams = m_avcSeqParam;
1827 const uint32_t(*vdencHmeCostTable)[CODEC_AVC_NUM_QP];
1828 if (avcSeqParams->ScenarioInfo == ESCENARIO_DISPLAYREMOTING)
1829 {
1830 vdencHmeCostTable = m_hmeCostDisplayRemote;
1831 }
1832 else
1833 {
1834 vdencHmeCostTable = m_hmeCost;
1835 }
1836
1837 for (uint8_t i = 0; i < 8; i++)
1838 {
1839 m_vdEncHmeMvCost[i] = Map44LutValue(*(vdencHmeCostTable[i] + qp), 0x6f);
1840 }
1841
1842 return MOS_STATUS_SUCCESS;
1843 }
1844
LoadHmeMvCostTable(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS seqParams,uint8_t hmeMVCostTable[8][42])1845 MOS_STATUS CodechalVdencAvcStateG12::LoadHmeMvCostTable(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS seqParams, uint8_t hmeMVCostTable[8][42])
1846 {
1847 CODECHAL_ENCODE_FUNCTION_ENTER;
1848
1849 const uint32_t(*vdencHmeCostTable)[CODEC_AVC_NUM_QP];
1850 if ((m_avcSeqParam->ScenarioInfo == ESCENARIO_DISPLAYREMOTING) || (m_avcSeqParam->RateControlMethod == RATECONTROL_QVBR))
1851 {
1852 vdencHmeCostTable = m_hmeCostDisplayRemote;
1853 }
1854 else
1855 {
1856 vdencHmeCostTable = m_hmeCost;
1857 }
1858
1859 for (uint8_t i = 0; i < 8; i++)
1860 {
1861 for (uint8_t j = 0; j < 42; j++)
1862 {
1863 hmeMVCostTable[i][j] = Map44LutValue(*(vdencHmeCostTable[i] + j + 10), 0x6f);
1864 }
1865 }
1866
1867 return MOS_STATUS_SUCCESS;
1868 }
1869
AddVdencWalkerStateCmd(PMOS_COMMAND_BUFFER cmdBuffer)1870 MOS_STATUS CodechalVdencAvcStateG12::AddVdencWalkerStateCmd(
1871 PMOS_COMMAND_BUFFER cmdBuffer)
1872 {
1873 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1874
1875 CODECHAL_ENCODE_FUNCTION_ENTER;
1876
1877 MHW_VDBOX_VDENC_WALKER_STATE_PARAMS_G12 vdencWalkerStateParams;
1878 auto avcSlcParams = m_avcSliceParams;
1879 auto avcPicParams = m_avcPicParams[avcSlcParams->pic_parameter_set_id];
1880 auto avcSeqParams = m_avcSeqParams[avcPicParams->seq_parameter_set_id];
1881
1882 vdencWalkerStateParams.Mode = CODECHAL_ENCODE_MODE_AVC;
1883 vdencWalkerStateParams.pAvcSeqParams = avcSeqParams;
1884 vdencWalkerStateParams.pAvcSlcParams = m_avcSliceParams;
1885 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencWalkerStateCmd(cmdBuffer, &vdencWalkerStateParams));
1886
1887 return eStatus;
1888 }
1889
CalculateVdencCommandsSize()1890 MOS_STATUS CodechalVdencAvcStateG12::CalculateVdencCommandsSize()
1891 {
1892 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1893
1894 CODECHAL_ENCODE_FUNCTION_ENTER;
1895
1896 MHW_VDBOX_STATE_CMDSIZE_PARAMS_G12 stateCmdSizeParams;
1897 uint32_t vdencPictureStatesSize, vdencPicturePatchListSize;
1898 uint32_t vdencSliceStatesSize, vdencSlicePatchListSize;
1899 m_hwInterface->GetHxxStateCommandSize(
1900 CODECHAL_ENCODE_MODE_AVC,
1901 (uint32_t*)&vdencPictureStatesSize,
1902 (uint32_t*)&vdencPicturePatchListSize,
1903 &stateCmdSizeParams);
1904
1905 m_pictureStatesSize += vdencPictureStatesSize;
1906 m_picturePatchListSize += vdencPicturePatchListSize;
1907
1908 // Picture Level Commands
1909 m_hwInterface->GetVdencStateCommandsDataSize(
1910 CODECHAL_ENCODE_MODE_AVC,
1911 (uint32_t*)&vdencPictureStatesSize,
1912 (uint32_t*)&vdencPicturePatchListSize);
1913
1914 m_pictureStatesSize += vdencPictureStatesSize;
1915 m_picturePatchListSize += vdencPicturePatchListSize;
1916
1917 #if USE_CODECHAL_DEBUG_TOOL
1918 // for ModifyEncodedFrameSizeWithFakeHeaderSize
1919 // total sum is 368 (108*2 + 152)
1920 if (m_hucInterface && m_enableFakeHrdSize)
1921 m_pictureStatesSize +=
1922 // 2x AddBufferWithIMMValue to change frame size
1923 (
1924 mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize +
1925 mhw_mi_g12_X::MI_LOAD_REGISTER_MEM_CMD::byteSize +
1926 mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 3 +
1927 mhw_mi_g12_X::MI_MATH_CMD::byteSize + sizeof(MHW_MI_ALU_PARAMS) * 4 +
1928 mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize
1929 ) * 2 +
1930 // SetBufferWithIMMValueU16 to change header size
1931 ( mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize +
1932 mhw_mi_g12_X::MI_LOAD_REGISTER_MEM_CMD::byteSize +
1933 mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 5 +
1934 2 * (mhw_mi_g12_X::MI_MATH_CMD::byteSize + sizeof(MHW_MI_ALU_PARAMS) * 4) +
1935 mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize);
1936 #endif
1937
1938 // Slice Level Commands
1939 m_hwInterface->GetVdencPrimitiveCommandsDataSize(
1940 CODECHAL_ENCODE_MODE_AVC,
1941 (uint32_t*)&vdencSliceStatesSize,
1942 (uint32_t*)&vdencSlicePatchListSize
1943 );
1944
1945 m_sliceStatesSize += vdencSliceStatesSize;
1946 m_slicePatchListSize += vdencSlicePatchListSize;
1947
1948 return eStatus;
1949 }
1950
SendPrologWithFrameTracking(PMOS_COMMAND_BUFFER cmdBuffer,bool frameTracking,MHW_MI_MMIOREGISTERS * mmioRegister)1951 MOS_STATUS CodechalVdencAvcStateG12::SendPrologWithFrameTracking(
1952 PMOS_COMMAND_BUFFER cmdBuffer,
1953 bool frameTracking,
1954 MHW_MI_MMIOREGISTERS *mmioRegister)
1955 {
1956 MHW_MI_FORCE_WAKEUP_PARAMS forceWakeupParams;
1957 MOS_ZeroMemory(&forceWakeupParams, sizeof(MHW_MI_FORCE_WAKEUP_PARAMS));
1958 forceWakeupParams.bMFXPowerWellControl = true;
1959 forceWakeupParams.bMFXPowerWellControlMask = true;
1960 forceWakeupParams.bHEVCPowerWellControl = false;
1961 forceWakeupParams.bHEVCPowerWellControlMask = true;
1962 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiForceWakeupCmd(
1963 cmdBuffer,
1964 &forceWakeupParams));
1965
1966 if (MOS_VE_SUPPORTED(m_osInterface) && cmdBuffer->Attributes.pAttriVe)
1967 {
1968 PMOS_CMD_BUF_ATTRI_VE attriExt =
1969 (PMOS_CMD_BUF_ATTRI_VE)(cmdBuffer->Attributes.pAttriVe);
1970 attriExt->bUseVirtualEngineHint = true;
1971 attriExt->VEngineHintParams.NeedSyncWithPrevious = 1;
1972 }
1973
1974 return CodechalVdencAvcState::SendPrologWithFrameTracking(cmdBuffer, frameTracking, mmioRegister);
1975 }
1976
InitMmcState()1977 MOS_STATUS CodechalVdencAvcStateG12::InitMmcState()
1978 {
1979 CODECHAL_ENCODE_FUNCTION_ENTER;
1980 #ifdef _MMC_SUPPORTED
1981 m_mmcState = MOS_New(CodechalMmcEncodeAvcG12, m_hwInterface, this);
1982 CODECHAL_ENCODE_CHK_NULL_RETURN(m_mmcState);
1983 #endif
1984 return MOS_STATUS_SUCCESS;
1985 }
1986
CheckResChangeAndCsc()1987 MOS_STATUS CodechalVdencAvcStateG12::CheckResChangeAndCsc()
1988 {
1989 CODECHAL_ENCODE_FUNCTION_ENTER;
1990
1991 if (m_cscDsState && m_rawSurface.Format == Format_A8R8G8B8)
1992 {
1993 uint64_t alignedSize = MOS_MAX((uint64_t)m_picWidthInMb * CODECHAL_MACROBLOCK_WIDTH * 4, (uint64_t)m_rawSurface.dwPitch) *
1994 ((uint64_t)m_picHeightInMb * CODECHAL_MACROBLOCK_HEIGHT);
1995
1996 if (m_rawSurface.OsResource.iSize < alignedSize)
1997 {
1998 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_cscDsState->SurfaceNeedsExtraCopy());
1999 }
2000 }
2001
2002 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncoderState::CheckResChangeAndCsc());
2003 return MOS_STATUS_SUCCESS;
2004 }
2005
SetMfxAvcImgStateParams(MHW_VDBOX_AVC_IMG_PARAMS & param)2006 void CodechalVdencAvcStateG12::SetMfxAvcImgStateParams(MHW_VDBOX_AVC_IMG_PARAMS& param)
2007 {
2008 CodechalVdencAvcState::SetMfxAvcImgStateParams(param);
2009
2010 PMHW_VDBOX_AVC_IMG_PARAMS_G12 paramsG12 = static_cast<PMHW_VDBOX_AVC_IMG_PARAMS_G12>(¶m);
2011
2012 paramsG12->bVDEncUltraModeEnabled = m_vdencUltraModeEnable;
2013 param.bPerMBStreamOut = m_perMBStreamOutEnable;
2014 if (((m_avcSeqParam->TargetUsage & 0x07) == TARGETUSAGE_BEST_SPEED) &&
2015 (m_avcSeqParam->FrameWidth >= m_singlePassMinFrameWidth) &&
2016 (m_avcSeqParam->FrameHeight >= m_singlePassMinFrameHeight) &&
2017 (m_avcSeqParam->FramesPer100Sec >=m_singlePassMinFramePer100s))
2018 {
2019 paramsG12->bVDEncUltraModeEnabled = true;
2020 }
2021 paramsG12->oneOnOneMapping = m_oneOnOneMapping;
2022 paramsG12->bStreamInMbQpEnabled = m_encodeParams.bMbQpDataEnabled;
2023 }
2024
CreateMhwVdboxStateCmdsizeParams()2025 PMHW_VDBOX_STATE_CMDSIZE_PARAMS CodechalVdencAvcStateG12::CreateMhwVdboxStateCmdsizeParams()
2026 {
2027 PMHW_VDBOX_STATE_CMDSIZE_PARAMS cmdSizeParams = MOS_New(MHW_VDBOX_STATE_CMDSIZE_PARAMS_G12);
2028
2029 return cmdSizeParams;
2030 }
2031
CreateMhwVdboxAvcImgParams()2032 PMHW_VDBOX_AVC_IMG_PARAMS CodechalVdencAvcStateG12::CreateMhwVdboxAvcImgParams()
2033 {
2034 PMHW_VDBOX_AVC_IMG_PARAMS avcImgParams = MOS_New(MHW_VDBOX_AVC_IMG_PARAMS_G12);
2035
2036 return avcImgParams;
2037 }
2038
CreateMhwVdboxVdencWalkerStateParams()2039 PMHW_VDBOX_VDENC_WALKER_STATE_PARAMS CodechalVdencAvcStateG12::CreateMhwVdboxVdencWalkerStateParams()
2040 {
2041 PMHW_VDBOX_VDENC_WALKER_STATE_PARAMS vdencWalkerStateParams = MOS_New(MHW_VDBOX_VDENC_WALKER_STATE_PARAMS_G12);
2042
2043 return vdencWalkerStateParams;
2044 }
2045
InitKernelStateMe()2046 MOS_STATUS CodechalVdencAvcStateG12::InitKernelStateMe()
2047 {
2048 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
2049 m_hmeKernel = MOS_New(CodechalKernelHmeG12, this);
2050 CODECHAL_ENCODE_CHK_NULL_RETURN(m_hmeKernel);
2051 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hmeKernel->Initialize(
2052 GetCommonKernelHeaderAndSizeG12,
2053 m_kernelBase,
2054 m_kuidCommon));
2055 #endif
2056 return MOS_STATUS_SUCCESS;
2057 }
2058
ExecuteMeKernel()2059 MOS_STATUS CodechalVdencAvcStateG12::ExecuteMeKernel()
2060 {
2061 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
2062 if (m_hmeKernel && m_hmeKernel->Is4xMeEnabled())
2063 {
2064 CodechalKernelHme::CurbeParam curbeParam = {};
2065 curbeParam.subPelMode = 3;
2066 curbeParam.currOriginalPic = m_avcPicParam->CurrOriginalPic;
2067 curbeParam.qpPrimeY = m_avcPicParam->pic_init_qp_minus26 + 26 + m_avcSliceParams->slice_qp_delta;
2068 curbeParam.targetUsage = m_avcSeqParam->TargetUsage;
2069 curbeParam.maxMvLen = CodecHalAvcEncode_GetMaxMvLen(m_avcSeqParam->Level);
2070
2071 AdjustNumRefIdx(curbeParam.numRefIdxL0Minus1, curbeParam.numRefIdxL1Minus1);
2072
2073 auto slcParams = m_avcSliceParams;
2074 curbeParam.list0RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_0);
2075 curbeParam.list0RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_1);
2076 curbeParam.list0RefID2FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_2);
2077 curbeParam.list0RefID3FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_3);
2078 curbeParam.list0RefID4FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_4);
2079 curbeParam.list0RefID5FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_5);
2080 curbeParam.list0RefID6FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_6);
2081 curbeParam.list0RefID7FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_7);
2082 curbeParam.list1RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_0);
2083 curbeParam.list1RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_1);
2084
2085 CodechalKernelHme::SurfaceParams surfaceParam = {};
2086 surfaceParam.mbaffEnabled = m_mbaffEnabled;
2087 surfaceParam.numRefIdxL0ActiveMinus1 = m_avcSliceParams->num_ref_idx_l0_active_minus1;
2088 surfaceParam.numRefIdxL1ActiveMinus1 = m_avcSliceParams->num_ref_idx_l1_active_minus1;
2089 surfaceParam.verticalLineStride = m_verticalLineStride;
2090 surfaceParam.verticalLineStrideOffset = m_verticalLineStrideOffset;
2091 surfaceParam.refList = &m_refList[0];
2092 surfaceParam.picIdx = &m_picIdx[0];
2093 surfaceParam.currOriginalPic = &m_currOriginalPic;
2094 surfaceParam.refL0List = &(m_avcSliceParams->RefPicList[LIST_0][0]);
2095 surfaceParam.refL1List = &(m_avcSliceParams->RefPicList[LIST_1][0]);
2096 surfaceParam.vdencStreamInEnabled = m_vdencEnabled && (m_16xMeSupported || m_staticFrameDetectionInUse);
2097 surfaceParam.meVdencStreamInBuffer = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
2098 surfaceParam.vdencStreamInSurfaceSize = MOS_BYTES_TO_DWORDS(m_picHeightInMb * m_picWidthInMb * 64);
2099
2100 if (m_hmeKernel->Is16xMeEnabled())
2101 {
2102 m_lastTaskInPhase = false;
2103 if (m_hmeKernel->Is32xMeEnabled())
2104 {
2105 surfaceParam.downScaledWidthInMb = m_downscaledWidthInMb32x;
2106 surfaceParam.downScaledHeightInMb = m_downscaledFrameFieldHeightInMb32x;
2107 surfaceParam.downScaledBottomFieldOffset = m_scaled32xBottomFieldOffset;
2108 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hmeKernel->Execute(curbeParam, surfaceParam, CodechalKernelHme::HmeLevel::hmeLevel32x));
2109 }
2110 surfaceParam.downScaledWidthInMb = m_downscaledWidthInMb16x;
2111 surfaceParam.downScaledHeightInMb = m_downscaledFrameFieldHeightInMb16x;
2112 surfaceParam.downScaledBottomFieldOffset = m_scaled16xBottomFieldOffset;
2113 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hmeKernel->Execute(curbeParam, surfaceParam, CodechalKernelHme::HmeLevel::hmeLevel16x));
2114 }
2115
2116 // On-demand sync for VDEnc SHME StreamIn surface
2117 auto syncParams = g_cInitSyncParams;
2118 syncParams.GpuContext = m_renderContext;
2119 syncParams.presSyncResource = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
2120
2121 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnResourceWait(m_osInterface, &syncParams));
2122 m_osInterface->pfnSetResourceSyncTag(m_osInterface, &syncParams);
2123
2124 // HME StreamIn
2125 m_lastTaskInPhase = !m_staticFrameDetectionInUse;
2126
2127 surfaceParam.downScaledWidthInMb = m_downscaledWidthInMb4x;
2128 surfaceParam.downScaledHeightInMb = m_downscaledFrameFieldHeightInMb4x;
2129 surfaceParam.downScaledBottomFieldOffset = m_scaledBottomFieldOffset;
2130 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hmeKernel->Execute(curbeParam, surfaceParam, CodechalKernelHme::HmeLevel::hmeLevel4x));
2131 m_vdencStreamInEnabled = true;
2132 }
2133 #endif
2134 return MOS_STATUS_SUCCESS;
2135 }
2136
UpdateCmdBufAttribute(PMOS_COMMAND_BUFFER cmdBuffer,bool renderEngineInUse)2137 MOS_STATUS CodechalVdencAvcStateG12::UpdateCmdBufAttribute(
2138 PMOS_COMMAND_BUFFER cmdBuffer,
2139 bool renderEngineInUse)
2140 {
2141 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2142
2143 // should not be there. Will remove it in the next change
2144 CODECHAL_ENCODE_FUNCTION_ENTER;
2145 if (MOS_VE_SUPPORTED(m_osInterface) && cmdBuffer->Attributes.pAttriVe)
2146 {
2147 PMOS_CMD_BUF_ATTRI_VE attriExt =
2148 (PMOS_CMD_BUF_ATTRI_VE)(cmdBuffer->Attributes.pAttriVe);
2149
2150 memset(attriExt, 0, sizeof(MOS_CMD_BUF_ATTRI_VE));
2151 attriExt->bUseVirtualEngineHint =
2152 attriExt->VEngineHintParams.NeedSyncWithPrevious = !renderEngineInUse;
2153 }
2154
2155 return eStatus;
2156 }
2157
AddMediaVfeCmd(PMOS_COMMAND_BUFFER cmdBuffer,SendKernelCmdsParams * params)2158 MOS_STATUS CodechalVdencAvcStateG12::AddMediaVfeCmd(
2159 PMOS_COMMAND_BUFFER cmdBuffer,
2160 SendKernelCmdsParams *params)
2161 {
2162 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
2163
2164 MHW_VFE_PARAMS_G12 vfeParams = {};
2165 vfeParams.pKernelState = params->pKernelState;
2166 vfeParams.eVfeSliceDisable = MHW_VFE_SLICE_ALL;
2167 vfeParams.dwMaximumNumberofThreads = m_encodeVfeMaxThreads;
2168 vfeParams.bFusedEuDispatch = false; // legacy mode
2169
2170 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_renderEngineInterface->AddMediaVfeCmd(cmdBuffer, &vfeParams));
2171
2172 return MOS_STATUS_SUCCESS;
2173 }
2174
SetMfxPipeModeSelectParams(const CODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS & genericParam,MHW_VDBOX_PIPE_MODE_SELECT_PARAMS & param)2175 void CodechalVdencAvcStateG12::SetMfxPipeModeSelectParams(
2176 const CODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS& genericParam,
2177 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& param)
2178 {
2179 CodechalEncodeAvcBase::SetMfxPipeModeSelectParams(genericParam, param);
2180
2181 auto avcPicParams = m_avcPicParams[m_avcSliceParams->pic_parameter_set_id];
2182 auto avcSeqParams = m_avcSeqParams[avcPicParams->seq_parameter_set_id];
2183 auto paramGen12 = ((MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G12 *)¶m);
2184
2185 if (avcSeqParams->EnableStreamingBufferLLC || avcSeqParams->EnableStreamingBufferDDR)
2186 {
2187 paramGen12->bStreamingBufferEnabled = true;
2188 }
2189 }
2190
CopyMBQPDataToStreamIn(CODECHAL_VDENC_STREAMIN_STATE * pData,uint8_t * pInputData)2191 void CodechalVdencAvcStateG12::CopyMBQPDataToStreamIn(CODECHAL_VDENC_STREAMIN_STATE* pData, uint8_t* pInputData)
2192 {
2193 for (uint32_t curY = 0; curY < m_picHeightInMb; curY++)
2194 {
2195 for (uint32_t curX = 0; curX < m_picWidthInMb; curX++)
2196 {
2197 pData->DW0.RegionOfInterestRoiSelection = 0;
2198 pData->DW1.Qpprimey = *(pInputData + m_encodeParams.psMbQpDataSurface->dwPitch * curY + curX);
2199 pData++;
2200 }
2201 }
2202 }
2203
2204 #if USE_CODECHAL_DEBUG_TOOL
PopulateBrcInitParam(void * cmd)2205 MOS_STATUS CodechalVdencAvcStateG12::PopulateBrcInitParam(
2206 void *cmd)
2207 {
2208 CODECHAL_DEBUG_FUNCTION_ENTER;
2209
2210 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
2211
2212 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
2213 {
2214 return MOS_STATUS_SUCCESS;
2215 }
2216
2217 BrcInitDmem * dmem = (BrcInitDmem *)cmd;
2218
2219 if (m_pictureCodingType == I_TYPE)
2220 {
2221 m_avcPar->MBBRCEnable = m_mbBrcEnabled;
2222 m_avcPar->MBRC = m_mbBrcEnabled;
2223 m_avcPar->BitRate = dmem->INIT_TargetBitrate_U32;
2224 m_avcPar->InitVbvFullnessInBit = dmem->INIT_InitBufFull_U32;
2225 m_avcPar->MaxBitRate = dmem->INIT_MaxRate_U32;
2226 m_avcPar->VbvSzInBit = dmem->INIT_BufSize_U32;
2227 m_avcPar->UserMaxFrame = dmem->INIT_ProfileLevelMaxFrame_U32;
2228 m_avcPar->SlidingWindowEnable = dmem->INIT_SlidingWidowRCEnable_U8;
2229 m_avcPar->SlidingWindowSize = dmem->INIT_SlidingWindowSize_U8;
2230 m_avcPar->SlidingWindowMaxRateRatio = dmem->INIT_SlidingWindowMaxRateRatio_U8;
2231 m_avcPar->LowDelayGoldenFrameBoost = dmem->INIT_LowDelayGoldenFrameBoost_U8;
2232 m_avcPar->TopQPDeltaThrforAdaptive2Pass = dmem->INIT_TopQPDeltaThrForAdapt2Pass_U8;
2233 m_avcPar->BotQPDeltaThrforAdaptive2Pass = dmem->INIT_BotQPDeltaThrForAdapt2Pass_U8;
2234 m_avcPar->TopFrmSzPctThrforAdaptive2Pass = dmem->INIT_TopFrmSzThrForAdapt2Pass_U8;
2235 m_avcPar->BotFrmSzPctThrforAdaptive2Pass = dmem->INIT_BotFrmSzThrForAdapt2Pass_U8;
2236 m_avcPar->MBHeaderCompensation = dmem->INIT_MBHeaderCompensation_U8;
2237 m_avcPar->QPSelectMethodforFirstPass = dmem->INIT_QPSelectForFirstPass_U8;
2238 m_avcPar->MBQpCtrl = (dmem->INIT_MbQpCtrl_U8 > 0) ? true : false;
2239 m_avcPar->QPMax = dmem->INIT_MaxQP_U16;
2240 m_avcPar->QPMin = dmem->INIT_MinQP_U16;
2241 m_avcPar->HrdConformanceCheckDisable = (dmem->INIT_HRDConformanceCheckDisable_U8 > 0) ? true : false;
2242 m_avcPar->ICQReEncode = (dmem->INIT_ICQReEncode_U8 > 0) ? true : false;
2243 m_avcPar->AdaptiveCostAdjustEnable = (dmem->INIT_AdaptiveCostEnable_U8 > 0) ? true : false;
2244 m_avcPar->AdaptiveHMEExtension = (dmem->INIT_AdaptiveHMEExtensionEnable_U8 > 0) ? true : false;
2245 m_avcPar->StreamInStaticRegion = dmem->INIT_StaticRegionStreamIn_U8;
2246 ;
2247 m_avcPar->ScenarioInfo = dmem->INIT_ScenarioInfo_U8;
2248 ;
2249 }
2250
2251 return MOS_STATUS_SUCCESS;
2252 }
2253
PopulateBrcUpdateParam(void * cmd)2254 MOS_STATUS CodechalVdencAvcStateG12::PopulateBrcUpdateParam(
2255 void *cmd)
2256 {
2257 CODECHAL_DEBUG_FUNCTION_ENTER;
2258
2259 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
2260
2261 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
2262 {
2263 return MOS_STATUS_SUCCESS;
2264 }
2265
2266 BrcUpdateDmem * dmem = (BrcUpdateDmem *)cmd;
2267
2268 if (m_pictureCodingType == I_TYPE)
2269 {
2270 m_avcPar->EnableMultipass = (dmem->UPD_MaxNumPass_U8 > 0) ? true : false;
2271 m_avcPar->MaxNumPakPasses = dmem->UPD_MaxNumPass_U8;
2272 m_avcPar->SceneChgDetectEn = (dmem->UPD_SceneChgDetectEn_U8 > 0) ? true : false;
2273 m_avcPar->SceneChgPrevIntraPctThresh = dmem->UPD_SceneChgPrevIntraPctThreshold_U8;
2274 m_avcPar->SceneChgCurIntraPctThresh = dmem->UPD_SceneChgCurIntraPctThreshold_U8;
2275 m_avcPar->SceneChgWidth0 = dmem->UPD_SceneChgWidth_U8[0];
2276 m_avcPar->SceneChgWidth1 = dmem->UPD_SceneChgWidth_U8[1];
2277 m_avcPar->SliceSizeThr = dmem->UPD_SLCSZ_TARGETSLCSZ_U16;
2278 m_avcPar->SliceMaxSize = dmem->UPD_TargetSliceSize_U16;
2279 }
2280 else if (m_pictureCodingType == P_TYPE)
2281 {
2282 m_avcPar->Transform8x8PDisable = (dmem->UPD_DisablePFrame8x8Transform_U8 > 0) ? true : false;
2283 }
2284
2285 return MOS_STATUS_SUCCESS;
2286 }
2287
PopulateEncParam(uint8_t meMethod,void * cmd)2288 MOS_STATUS CodechalVdencAvcStateG12::PopulateEncParam(
2289 uint8_t meMethod,
2290 void *cmd)
2291 {
2292 CODECHAL_DEBUG_FUNCTION_ENTER;
2293
2294 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
2295
2296 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
2297 {
2298 return MOS_STATUS_SUCCESS;
2299 }
2300
2301 uint8_t *data = nullptr;
2302 MOS_LOCK_PARAMS lockFlags;
2303 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
2304 lockFlags.ReadOnly = 1;
2305
2306 if (m_vdencBrcEnabled)
2307 {
2308 // BRC case: VDENC IMG STATE is updated by HuC FW
2309 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
2310 data = data + mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize;
2311 }
2312 else
2313 {
2314 // CQP case: VDENC IMG STATE is updated by driver or SFD kernel
2315 if (!m_staticFrameDetectionInUse)
2316 {
2317 data = m_batchBufferForVdencImgStat[m_currRecycledBufIdx].pData;
2318 data = data + mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize;
2319 }
2320 else
2321 {
2322 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencSfdImageStateReadBuffer, &lockFlags);
2323 }
2324 }
2325
2326 CODECHAL_DEBUG_CHK_NULL(data);
2327
2328 mhw_vdbox_vdenc_g12_X::VDENC_IMG_STATE_CMD vdencCmd;
2329 vdencCmd = *(mhw_vdbox_vdenc_g12_X::VDENC_IMG_STATE_CMD *)(data);
2330
2331 if (m_pictureCodingType == I_TYPE)
2332 {
2333 m_avcPar->BlockBasedSkip = vdencCmd.DW4.BlockBasedSkipEnabled;
2334 m_avcPar->VDEncPerfMode = vdencCmd.DW1.VdencPerfmode;
2335 }
2336 else if (m_pictureCodingType == P_TYPE)
2337 {
2338 m_avcPar->SubPelMode = vdencCmd.DW4.SubPelMode;
2339 m_avcPar->FTQBasedSkip = vdencCmd.DW4.ForwardTransformSkipCheckEnable;
2340 m_avcPar->BiMixDisable = vdencCmd.DW1.BidirectionalMixDisable;
2341 m_avcPar->SurvivedSkipCost = (vdencCmd.DW8.NonSkipZeroMvCostAdded << 1) + vdencCmd.DW8.NonSkipMbModeCostAdded;
2342 m_avcPar->UniMixDisable = vdencCmd.DW2.UnidirectionalMixDisable;
2343 m_avcPar->VdencExtPakObjDisable = !vdencCmd.DW1.VdencExtendedPakObjCmdEnable;
2344 m_avcPar->PPMVDisable = vdencCmd.DW34.PpmvDisable;
2345 }
2346
2347 if (data)
2348 {
2349 if (m_vdencBrcEnabled)
2350 {
2351 m_osInterface->pfnUnlockResource(
2352 m_osInterface,
2353 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
2354 }
2355 else
2356 {
2357 if (m_staticFrameDetectionInUse)
2358 {
2359 m_osInterface->pfnUnlockResource(
2360 m_osInterface,
2361 &m_resVdencSfdImageStateReadBuffer);
2362 }
2363 }
2364 }
2365
2366 return MOS_STATUS_SUCCESS;
2367 }
2368
PopulatePakParam(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER secondLevelBatchBuffer)2369 MOS_STATUS CodechalVdencAvcStateG12::PopulatePakParam(
2370 PMOS_COMMAND_BUFFER cmdBuffer,
2371 PMHW_BATCH_BUFFER secondLevelBatchBuffer)
2372 {
2373 CODECHAL_DEBUG_FUNCTION_ENTER;
2374
2375 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
2376
2377 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
2378 {
2379 return MOS_STATUS_SUCCESS;
2380 }
2381
2382 uint8_t *data = nullptr;
2383 MOS_LOCK_PARAMS lockFlags;
2384 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
2385 lockFlags.ReadOnly = 1;
2386
2387 if (cmdBuffer != nullptr)
2388 {
2389 data = (uint8_t*)(cmdBuffer->pCmdPtr - (mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize / sizeof(uint32_t)));
2390 }
2391 else if (secondLevelBatchBuffer != nullptr)
2392 {
2393 data = secondLevelBatchBuffer->pData;
2394 }
2395 else
2396 {
2397 data = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
2398 }
2399
2400 CODECHAL_DEBUG_CHK_NULL(data);
2401
2402 mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD mfxCmd;
2403 mfxCmd = *(mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD *)(data);
2404
2405 if (m_pictureCodingType == I_TYPE)
2406 {
2407 m_avcPar->TrellisQuantizationEnable = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
2408 m_avcPar->EnableAdaptiveTrellisQuantization = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
2409 m_avcPar->TrellisQuantizationRounding = mfxCmd.DW5.TrellisQuantizationRoundingTqr;
2410 m_avcPar->TrellisQuantizationChromaDisable = mfxCmd.DW5.TrellisQuantizationChromaDisableTqchromadisable;
2411 m_avcPar->ExtendedRhoDomainEn = mfxCmd.DW17.ExtendedRhodomainStatisticsEnable;
2412 }
2413
2414 if (data && (cmdBuffer == nullptr) && (secondLevelBatchBuffer == nullptr))
2415 {
2416 m_osInterface->pfnUnlockResource(
2417 m_osInterface,
2418 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
2419 }
2420
2421 return MOS_STATUS_SUCCESS;
2422 }
2423
2424 #define FIELD_TO_SS(field_name) ss << std::setfill(' ') << std::setw(25) << std::left << std::string(#field_name) + ": " << (int64_t)dmem->field_name << std::endl;
2425 #define ARRAY_TO_SS(arr_name) \
2426 { \
2427 size_t size = sizeof(dmem->arr_name); \
2428 ss << std::setfill(' ') << std::setw(25) << std::left << std::string(#arr_name) + ": "; \
2429 ss << "{ " << (int64_t)dmem->arr_name[0]; \
2430 for (size_t i = 1; i < sizeof(dmem->arr_name); ++i) \
2431 ss << ", " << (int64_t)dmem->arr_name[i]; \
2432 ss << " };" << std::endl; \
2433 }
2434
DumpParsedBRCInitDmem(BrcInitDmem * dmem)2435 MOS_STATUS CodechalVdencAvcStateG12::DumpParsedBRCInitDmem(BrcInitDmem* dmem)
2436 {
2437 CODECHAL_DEBUG_FUNCTION_ENTER;
2438 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
2439
2440 // To make sure that DMEM doesn't changed and parsed dump contains all DMEM fields
2441 CODECHAL_DEBUG_ASSERT(sizeof(dmem->RSVD2) == 55);
2442
2443 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrHuCDmem))
2444 {
2445 return MOS_STATUS_SUCCESS;
2446 }
2447
2448 std::stringstream ss;
2449
2450 FIELD_TO_SS(BRCFunc_U8);
2451 FIELD_TO_SS(OpenSourceEnable_U8);
2452 ARRAY_TO_SS(RVSD);
2453 FIELD_TO_SS(INIT_BRCFlag_U16);
2454 FIELD_TO_SS(Reserved);
2455 FIELD_TO_SS(INIT_FrameWidth_U16);
2456 FIELD_TO_SS(INIT_FrameHeight_U16);
2457 FIELD_TO_SS(INIT_TargetBitrate_U32);
2458 FIELD_TO_SS(INIT_MinRate_U32);
2459 FIELD_TO_SS(INIT_MaxRate_U32);
2460 FIELD_TO_SS(INIT_BufSize_U32);
2461 FIELD_TO_SS(INIT_InitBufFull_U32);
2462 FIELD_TO_SS(INIT_ProfileLevelMaxFrame_U32);
2463 FIELD_TO_SS(INIT_FrameRateM_U32);
2464 FIELD_TO_SS(INIT_FrameRateD_U32);
2465 FIELD_TO_SS(INIT_GopP_U16);
2466 FIELD_TO_SS(INIT_GopB_U16);
2467 FIELD_TO_SS(INIT_MinQP_U16);
2468 FIELD_TO_SS(INIT_MaxQP_U16);
2469 ARRAY_TO_SS(INIT_DevThreshPB0_S8);
2470 ARRAY_TO_SS(INIT_DevThreshVBR0_S8);
2471 ARRAY_TO_SS(INIT_DevThreshI0_S8);
2472 FIELD_TO_SS(INIT_InitQPIP);
2473
2474 FIELD_TO_SS(INIT_NotUseRhoDm_U8);
2475 FIELD_TO_SS(INIT_InitQPB);
2476 FIELD_TO_SS(INIT_MbQpCtrl_U8);
2477 FIELD_TO_SS(INIT_SliceSizeCtrlEn_U8);
2478 ARRAY_TO_SS(INIT_IntraQPDelta_I8);
2479 FIELD_TO_SS(INIT_SkipQPDelta_I8);
2480 ARRAY_TO_SS(INIT_DistQPDelta_I8);
2481 FIELD_TO_SS(INIT_OscillationQpDelta_U8);
2482 FIELD_TO_SS(INIT_HRDConformanceCheckDisable_U8);
2483 FIELD_TO_SS(INIT_SkipFrameEnableFlag);
2484 FIELD_TO_SS(INIT_TopQPDeltaThrForAdapt2Pass_U8);
2485 FIELD_TO_SS(INIT_TopFrmSzThrForAdapt2Pass_U8);
2486 FIELD_TO_SS(INIT_BotFrmSzThrForAdapt2Pass_U8);
2487 FIELD_TO_SS(INIT_QPSelectForFirstPass_U8);
2488 FIELD_TO_SS(INIT_MBHeaderCompensation_U8);
2489 FIELD_TO_SS(INIT_OverShootCarryFlag_U8);
2490 FIELD_TO_SS(INIT_OverShootSkipFramePct_U8);
2491 ARRAY_TO_SS(INIT_EstRateThreshP0_U8);
2492 ARRAY_TO_SS(INIT_EstRateThreshB0_U8);
2493 ARRAY_TO_SS(INIT_EstRateThreshI0_U8);
2494 FIELD_TO_SS(INIT_FracQPEnable_U8);
2495 FIELD_TO_SS(INIT_ScenarioInfo_U8);
2496 FIELD_TO_SS(INIT_StaticRegionStreamIn_U8);
2497 FIELD_TO_SS(INIT_DeltaQP_Adaptation_U8);
2498 FIELD_TO_SS(INIT_MaxCRFQualityFactor_U8);
2499 FIELD_TO_SS(INIT_CRFQualityFactor_U8);
2500 FIELD_TO_SS(INIT_BotQPDeltaThrForAdapt2Pass_U8);
2501 FIELD_TO_SS(INIT_SlidingWindowSize_U8);
2502 FIELD_TO_SS(INIT_SlidingWidowRCEnable_U8);
2503 FIELD_TO_SS(INIT_SlidingWindowMaxRateRatio_U8);
2504 FIELD_TO_SS(INIT_LowDelayGoldenFrameBoost_U8);
2505 FIELD_TO_SS(INIT_AdaptiveCostEnable_U8);
2506 FIELD_TO_SS(INIT_AdaptiveHMEExtensionEnable_U8);
2507 FIELD_TO_SS(INIT_ICQReEncode_U8);
2508 FIELD_TO_SS(INIT_LookaheadDepth_U8);
2509 FIELD_TO_SS(INIT_SinglePassOnly);
2510 FIELD_TO_SS(INIT_New_DeltaQP_Adaptation_U8);
2511 ARRAY_TO_SS(RSVD2);
2512
2513 std::string bufName = std::string("ENC-HucDmemInit_Parsed_PASS") + std::to_string((uint32_t)m_currPass);
2514 CODECHAL_DEBUG_CHK_STATUS(m_debugInterface->DumpStringStream(ss, bufName.c_str(), MediaDbgAttr::attrHuCDmem));
2515
2516 return MOS_STATUS_SUCCESS;
2517 }
2518
DumpParsedBRCUpdateDmem(BrcUpdateDmem * dmem)2519 MOS_STATUS CodechalVdencAvcStateG12::DumpParsedBRCUpdateDmem(BrcUpdateDmem* dmem)
2520 {
2521 CODECHAL_DEBUG_FUNCTION_ENTER;
2522 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
2523
2524 // To make sure that DMEM doesn't changed and parsed dump contains all DMEM fields
2525 CODECHAL_DEBUG_ASSERT(sizeof(dmem->RSVD2) == 4);
2526
2527 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrHuCDmem))
2528 {
2529 return MOS_STATUS_SUCCESS;
2530 }
2531
2532 std::stringstream ss;
2533
2534 FIELD_TO_SS(BRCFunc_U8);
2535 ARRAY_TO_SS(RSVD);
2536 FIELD_TO_SS(UPD_TARGETSIZE_U32);
2537 FIELD_TO_SS(UPD_FRAMENUM_U32);
2538 FIELD_TO_SS(UPD_PeakTxBitsPerFrame_U32);
2539 FIELD_TO_SS(UPD_FrameBudget_U32);
2540 FIELD_TO_SS(FrameByteCount);
2541 FIELD_TO_SS(TimingBudgetOverflow);
2542 FIELD_TO_SS(ImgStatusCtrl);
2543 FIELD_TO_SS(IPCMNonConformant);
2544
2545 ARRAY_TO_SS(UPD_startGAdjFrame_U16);
2546 ARRAY_TO_SS(UPD_MBBudget_U16);
2547 FIELD_TO_SS(UPD_SLCSZ_TARGETSLCSZ_U16);
2548 ARRAY_TO_SS(UPD_SLCSZ_UPD_THRDELTAI_U16);
2549 ARRAY_TO_SS(UPD_SLCSZ_UPD_THRDELTAP_U16);
2550 FIELD_TO_SS(UPD_NumOfFramesSkipped_U16);
2551 FIELD_TO_SS(UPD_SkipFrameSize_U16);
2552 FIELD_TO_SS(UPD_StaticRegionPct_U16);
2553 ARRAY_TO_SS(UPD_gRateRatioThreshold_U8);
2554 FIELD_TO_SS(UPD_CurrFrameType_U8);
2555 ARRAY_TO_SS(UPD_startGAdjMult_U8);
2556 ARRAY_TO_SS(UPD_startGAdjDiv_U8);
2557 ARRAY_TO_SS(UPD_gRateRatioThresholdQP_U8);
2558 FIELD_TO_SS(UPD_PAKPassNum_U8);
2559 FIELD_TO_SS(UPD_MaxNumPass_U8);
2560 ARRAY_TO_SS(UPD_SceneChgWidth_U8);
2561 FIELD_TO_SS(UPD_SceneChgDetectEn_U8);
2562 FIELD_TO_SS(UPD_SceneChgPrevIntraPctThreshold_U8);
2563 FIELD_TO_SS(UPD_SceneChgCurIntraPctThreshold_U8);
2564 FIELD_TO_SS(UPD_IPAverageCoeff_U8);
2565 FIELD_TO_SS(UPD_MinQpAdjustment_U8);
2566 FIELD_TO_SS(UPD_TimingBudgetCheck_U8);
2567 ARRAY_TO_SS(reserved_I8);
2568 FIELD_TO_SS(UPD_CQP_QpValue_U8);
2569 FIELD_TO_SS(UPD_CQP_FracQp_U8);
2570 FIELD_TO_SS(UPD_HMEDetectionEnable_U8);
2571 FIELD_TO_SS(UPD_HMECostEnable_U8);
2572 FIELD_TO_SS(UPD_DisablePFrame8x8Transform_U8);
2573 FIELD_TO_SS(RSVD3);
2574 FIELD_TO_SS(UPD_ROISource_U8);
2575 FIELD_TO_SS(RSVD4);
2576 FIELD_TO_SS(UPD_TargetSliceSize_U16);
2577 FIELD_TO_SS(UPD_MaxNumSliceAllowed_U16);
2578 FIELD_TO_SS(UPD_SLBB_Size_U16);
2579 FIELD_TO_SS(UPD_SLBB_B_Offset_U16);
2580 FIELD_TO_SS(UPD_AvcImgStateOffset_U16);
2581 FIELD_TO_SS(reserved_u16);
2582 FIELD_TO_SS(NumOfSlice);
2583
2584 FIELD_TO_SS(AveHmeDist_U16);
2585 FIELD_TO_SS(HmeDistAvailable_U8);
2586 FIELD_TO_SS(DisableDMA);
2587 FIELD_TO_SS(AdditionalFrameSize_U16);
2588 FIELD_TO_SS(AddNALHeaderSizeInternally_U8);
2589 FIELD_TO_SS(UPD_RoiQpViaForceQp_U8);
2590 FIELD_TO_SS(CABACZeroInsertionSize_U32);
2591 FIELD_TO_SS(MiniFramePaddingSize_U32);
2592 FIELD_TO_SS(UPD_WidthInMB_U16);
2593 FIELD_TO_SS(UPD_HeightInMB_U16);
2594 ARRAY_TO_SS(UPD_ROIQpDelta_I8);
2595
2596 FIELD_TO_SS(HME0XOffset_I8);
2597 FIELD_TO_SS(HME0YOffset_I8);
2598 FIELD_TO_SS(HME1XOffset_I8);
2599 FIELD_TO_SS(HME1YOffset_I8);
2600 FIELD_TO_SS(MOTION_ADAPTIVE_G4);
2601 FIELD_TO_SS(EnableLookAhead);
2602 FIELD_TO_SS(UPD_LA_Data_Offset_U8);
2603 FIELD_TO_SS(UPD_CQMEnabled_U8);
2604 FIELD_TO_SS(UPD_LA_TargetSize_U32);
2605 FIELD_TO_SS(UPD_LA_TargetFulness_U32);
2606 FIELD_TO_SS(UPD_Delta_U8);
2607 FIELD_TO_SS(UPD_ROM_CURRENT_U8);
2608 FIELD_TO_SS(UPD_ROM_ZERO_U8);
2609 FIELD_TO_SS(UPD_TCBRC_SCENARIO_U8);
2610 FIELD_TO_SS(UPD_EnableFineGrainLA);
2611 FIELD_TO_SS(UPD_DeltaQpDcOffset);
2612 FIELD_TO_SS(UPD_NumSlicesForRounding);
2613 FIELD_TO_SS(UPD_UserMaxFramePB);
2614 ARRAY_TO_SS(RSVD2);
2615
2616 std::string bufName = std::string("ENC-HucDmemUpdate_Parsed_PASS") + std::to_string((uint32_t)m_currPass);
2617 CODECHAL_DEBUG_CHK_STATUS(m_debugInterface->DumpStringStream(ss, bufName.c_str(), MediaDbgAttr::attrHuCDmem));
2618
2619 return MOS_STATUS_SUCCESS;
2620 }
2621 #undef FIELD_TO_SS
2622 #undef ARRAY_TO_SS
2623
ModifyEncodedFrameSizeWithFakeHeaderSize(PMOS_COMMAND_BUFFER cmdBuffer)2624 MOS_STATUS CodechalVdencAvcStateG12::ModifyEncodedFrameSizeWithFakeHeaderSize( PMOS_COMMAND_BUFFER cmdBuffer)
2625 {
2626 CODECHAL_ENCODE_FUNCTION_ENTER;
2627
2628 if (!m_fakeIFrameHrdSize && !m_fakePBFrameHrdSize)
2629 return MOS_STATUS_SUCCESS;
2630
2631 uint32_t fakeHeaderSizeInBytes = (m_pictureCodingType == I_TYPE) ? m_fakeIFrameHrdSize : m_fakePBFrameHrdSize;
2632
2633 //calculate all frame headers size, including 1st slice header
2634 CODECHAL_ENCODE_CHK_NULL_RETURN(m_encodeParams.pBSBuffer);
2635 uint32_t totalHeaderSize = uint32_t(m_encodeParams.pBSBuffer->pCurrent - m_encodeParams.pBSBuffer->pBase);
2636
2637 // change encdode frame size for next frame and next pass
2638 for (int i = 0; i < 2; i++)
2639 {
2640 if (m_resVdencBrcUpdateDmemBufferPtr[i] == nullptr)
2641 continue;
2642 CODECHAL_ENCODE_CHK_STATUS_RETURN(AddBufferWithIMMValue(
2643 cmdBuffer,
2644 m_resVdencBrcUpdateDmemBufferPtr[i],
2645 sizeof(uint32_t) * 5,
2646 fakeHeaderSizeInBytes - totalHeaderSize,
2647 true));
2648 }
2649
2650 // change headers size (U16)
2651 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetBufferWithIMMValueU16(
2652 cmdBuffer,
2653 m_resPakStatsBuffer,
2654 0,
2655 fakeHeaderSizeInBytes * 8,
2656 0)); // second or first word in dword
2657
2658 return MOS_STATUS_SUCCESS;
2659 }
2660 #endif
2661