1 /*
2 * Copyright (c) 2011-2017, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_encode_avc_g8.cpp
24 //! \brief This file implements the C++ class/interface for Gen8 platform's AVC
25 //! DualPipe encoding to be used across CODECHAL components.
26 //!
27
28 #include "codechal_encode_avc_g8.h"
29 #include "igcodeckrn_g8.h"
30
31 //enums begin
32 typedef enum _BINDING_TABLE_OFFSET_BRC_UPDATE
33 {
34 BRC_UPDATE_HISTORY = 0,
35 BRC_UPDATE_PAK_STATISTICS_OUTPUT = 1,
36 BRC_UPDATE_IMAGE_STATE_READ = 2,
37 BRC_UPDATE_IMAGE_STATE_WRITE = 3,
38 BRC_UPDATE_MBENC_CURBE_READ = 4,
39 BRC_UPDATE_MBENC_CURBE_WRITE = 5,
40 BRC_UPDATE_DISTORTION = 6,
41 BRC_UPDATE_CONSTANT_DATA = 7,
42 BRC_UPDATE_MB_QP = 8,
43 BRC_UPDATE_NUM_SURFACES = 9
44 } BINDING_TABLE_OFFSET_BRC_UPDATE;
45 //enums end
46
47 //structure begin
48 typedef struct _KERNEL_HEADER_CM {
49 int nKernelCount;
50
51 // Quality mode for Frame/Field
52 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_I;
53 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_P;
54 CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_B;
55 // Normal mode for Frame/Field
56 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_I;
57 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_P;
58 CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_B;
59 // Performance modes for Frame/Field
60 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_I;
61 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_P;
62 CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_B;
63 // Modes for Frame/Field
64 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_I;
65 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_P;
66 CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_B;
67 // HME
68 CODECHAL_KERNEL_HEADER AVC_ME_P;
69 CODECHAL_KERNEL_HEADER AVC_ME_B;
70 // DownScaling
71 CODECHAL_KERNEL_HEADER PLY_DScale_PLY;
72 CODECHAL_KERNEL_HEADER PLY_DScale_2f_PLY_2f;
73 // BRC frame
74 CODECHAL_KERNEL_HEADER InitFrameBRC;
75 CODECHAL_KERNEL_HEADER FrameENCUpdate;
76 // BRC Reset frame
77 CODECHAL_KERNEL_HEADER BRC_ResetFrame;
78 // BRC I Frame Distortion
79 CODECHAL_KERNEL_HEADER BRC_IFrame_Dist;
80 // BRCBlockCopy
81 CODECHAL_KERNEL_HEADER BRCBlockCopy;
82 // 2x DownScaling
83 CODECHAL_KERNEL_HEADER PLY_2xDScale_PLY;
84 CODECHAL_KERNEL_HEADER PLY_2xDScale_2f_PLY_2f;
85 // Static frame detection Kernel
86 CODECHAL_KERNEL_HEADER AVC_StaticFrameDetection;
87 } KERNEL_HEADER_CM, *PKERNEL_HEADER_CM;
88
89 typedef struct _BRC_INIT_RESET_CURBE
90 {
91 union
92 {
93 struct
94 {
95 uint32_t ProfileLevelMaxFrame : MOS_BITFIELD_RANGE( 0,31 );
96 };
97 struct
98 {
99 uint32_t Value;
100 };
101 } DW0;
102
103 union
104 {
105 struct
106 {
107 uint32_t InitBufFullInBits : MOS_BITFIELD_RANGE( 0,31 );
108 };
109 struct
110 {
111 uint32_t Value;
112 };
113 } DW1;
114
115 union
116 {
117 struct
118 {
119 uint32_t BufSizeInBits : MOS_BITFIELD_RANGE( 0,31 );
120 };
121 struct
122 {
123 uint32_t Value;
124 };
125 } DW2;
126
127 union
128 {
129 struct
130 {
131 uint32_t AverageBitRate : MOS_BITFIELD_RANGE( 0,31 );
132 };
133 struct
134 {
135 uint32_t Value;
136 };
137 } DW3;
138
139 union
140 {
141 struct
142 {
143 uint32_t MaxBitRate : MOS_BITFIELD_RANGE( 0,31 );
144 };
145 struct
146 {
147 uint32_t Value;
148 };
149 } DW4;
150
151 union
152 {
153 struct
154 {
155 uint32_t MinBitRate : MOS_BITFIELD_RANGE( 0,31 );
156 };
157 struct
158 {
159 uint32_t Value;
160 };
161 } DW5;
162
163 union
164 {
165 struct
166 {
167 uint32_t FrameRateM : MOS_BITFIELD_RANGE( 0,31 );
168 };
169 struct
170 {
171 uint32_t Value;
172 };
173 } DW6;
174
175 union
176 {
177 struct
178 {
179 uint32_t FrameRateD : MOS_BITFIELD_RANGE( 0,31 );
180 };
181 struct
182 {
183 uint32_t Value;
184 };
185 } DW7;
186
187 union
188 {
189 struct
190 {
191 uint32_t BRCFlag : MOS_BITFIELD_RANGE( 0,15 );
192 uint32_t GopP : MOS_BITFIELD_RANGE( 16,31 );
193 };
194 struct
195 {
196 uint32_t Value;
197 };
198 } DW8;
199
200 union
201 {
202 struct
203 {
204 uint32_t GopB : MOS_BITFIELD_RANGE( 0,15 );
205 uint32_t FrameWidthInBytes : MOS_BITFIELD_RANGE( 16,31 );
206 };
207 struct
208 {
209 uint32_t Value;
210 };
211 } DW9;
212
213 union
214 {
215 struct
216 {
217 uint32_t FrameHeightInBytes : MOS_BITFIELD_RANGE( 0,15 );
218 uint32_t AVBRAccuracy : MOS_BITFIELD_RANGE( 16,31 );
219 };
220 struct
221 {
222 uint32_t Value;
223 };
224 } DW10;
225
226 union
227 {
228 struct
229 {
230 uint32_t AVBRConvergence : MOS_BITFIELD_RANGE( 0,15 );
231 uint32_t MinQP : MOS_BITFIELD_RANGE( 16,31 );
232 };
233 struct
234 {
235 uint32_t Value;
236 };
237 } DW11;
238
239 union
240 {
241 struct
242 {
243 uint32_t MaxQP : MOS_BITFIELD_RANGE( 0,15 );
244 uint32_t NoSlices : MOS_BITFIELD_RANGE( 16,31 );
245 };
246 struct
247 {
248 uint32_t Value;
249 };
250 } DW12;
251
252 union
253 {
254 struct
255 {
256 uint32_t InstantRateThreshold0ForP : MOS_BITFIELD_RANGE( 0, 7 );
257 uint32_t InstantRateThreshold1ForP : MOS_BITFIELD_RANGE( 8,15 );
258 uint32_t InstantRateThreshold2ForP : MOS_BITFIELD_RANGE( 16,23 );
259 uint32_t InstantRateThreshold3ForP : MOS_BITFIELD_RANGE( 24,31 );
260 };
261 struct
262 {
263 uint32_t Value;
264 };
265 } DW13;
266
267 union
268 {
269 struct
270 {
271 uint32_t InstantRateThreshold0ForB : MOS_BITFIELD_RANGE( 0, 7 );
272 uint32_t InstantRateThreshold1ForB : MOS_BITFIELD_RANGE( 8,15 );
273 uint32_t InstantRateThreshold2ForB : MOS_BITFIELD_RANGE( 16,23 );
274 uint32_t InstantRateThreshold3ForB : MOS_BITFIELD_RANGE( 24,31 );
275 };
276 struct
277 {
278 uint32_t Value;
279 };
280 } DW14;
281
282 union
283 {
284 struct
285 {
286 uint32_t InstantRateThreshold0ForI : MOS_BITFIELD_RANGE( 0, 7 );
287 uint32_t InstantRateThreshold1ForI : MOS_BITFIELD_RANGE( 8,15 );
288 uint32_t InstantRateThreshold2ForI : MOS_BITFIELD_RANGE( 16,23 );
289 uint32_t InstantRateThreshold3ForI : MOS_BITFIELD_RANGE( 24,31 );
290 };
291 struct
292 {
293 uint32_t Value;
294 };
295 } DW15;
296
297 union
298 {
299 struct
300 {
301 uint32_t DeviationThreshold0ForPandB : MOS_BITFIELD_RANGE( 0, 7 ); // Signed byte
302 uint32_t DeviationThreshold1ForPandB : MOS_BITFIELD_RANGE( 8,15 ); // Signed byte
303 uint32_t DeviationThreshold2ForPandB : MOS_BITFIELD_RANGE( 16,23 ); // Signed byte
304 uint32_t DeviationThreshold3ForPandB : MOS_BITFIELD_RANGE( 24,31 ); // Signed byte
305 };
306 struct
307 {
308 uint32_t Value;
309 };
310 } DW16;
311
312 union
313 {
314 struct
315 {
316 uint32_t DeviationThreshold4ForPandB : MOS_BITFIELD_RANGE( 0, 7 ); // Signed byte
317 uint32_t DeviationThreshold5ForPandB : MOS_BITFIELD_RANGE( 8,15 ); // Signed byte
318 uint32_t DeviationThreshold6ForPandB : MOS_BITFIELD_RANGE( 16,23 ); // Signed byte
319 uint32_t DeviationThreshold7ForPandB : MOS_BITFIELD_RANGE( 24,31 ); // Signed byte
320 };
321 struct
322 {
323 uint32_t Value;
324 };
325 } DW17;
326
327 union
328 {
329 struct
330 {
331 uint32_t DeviationThreshold0ForVBR : MOS_BITFIELD_RANGE( 0, 7 ); // Signed byte
332 uint32_t DeviationThreshold1ForVBR : MOS_BITFIELD_RANGE( 8,15 ); // Signed byte
333 uint32_t DeviationThreshold2ForVBR : MOS_BITFIELD_RANGE( 16,23 ); // Signed byte
334 uint32_t DeviationThreshold3ForVBR : MOS_BITFIELD_RANGE( 24,31 ); // Signed byte
335 };
336 struct
337 {
338 uint32_t Value;
339 };
340 } DW18;
341
342 union
343 {
344 struct
345 {
346 uint32_t DeviationThreshold4ForVBR : MOS_BITFIELD_RANGE( 0, 7 ); // Signed byte
347 uint32_t DeviationThreshold5ForVBR : MOS_BITFIELD_RANGE( 8,15 ); // Signed byte
348 uint32_t DeviationThreshold6ForVBR : MOS_BITFIELD_RANGE( 16,23 ); // Signed byte
349 uint32_t DeviationThreshold7ForVBR : MOS_BITFIELD_RANGE( 24,31 ); // Signed byte
350 };
351 struct
352 {
353 uint32_t Value;
354 };
355 } DW19;
356
357 union
358 {
359 struct
360 {
361 uint32_t DeviationThreshold0ForI : MOS_BITFIELD_RANGE(0, 7); // Signed byte
362 uint32_t DeviationThreshold1ForI : MOS_BITFIELD_RANGE(8, 15); // Signed byte
363 uint32_t DeviationThreshold2ForI : MOS_BITFIELD_RANGE(16, 23); // Signed byte
364 uint32_t DeviationThreshold3ForI : MOS_BITFIELD_RANGE(24, 31); // Signed byte
365 };
366 struct
367 {
368 uint32_t Value;
369 };
370 } DW20;
371
372 union
373 {
374 struct
375 {
376 uint32_t DeviationThreshold4ForI : MOS_BITFIELD_RANGE( 0, 7 ); // Signed byte
377 uint32_t DeviationThreshold5ForI : MOS_BITFIELD_RANGE( 8,15 ); // Signed byte
378 uint32_t DeviationThreshold6ForI : MOS_BITFIELD_RANGE( 16,23 ); // Signed byte
379 uint32_t DeviationThreshold7ForI : MOS_BITFIELD_RANGE( 24,31 ); // Signed byte
380 };
381 struct
382 {
383 uint32_t Value;
384 };
385 } DW21;
386
387 union
388 {
389 struct
390 {
391 uint32_t InitialQPForI : MOS_BITFIELD_RANGE( 0, 7 ); // Signed byte
392 uint32_t InitialQPForP : MOS_BITFIELD_RANGE( 8,15 ); // Signed byte
393 uint32_t InitialQPForB : MOS_BITFIELD_RANGE( 16,23 ); // Signed byte
394 uint32_t SlidingWindowSize : MOS_BITFIELD_RANGE( 24,31 ); // unsigned byte
395 };
396 struct
397 {
398 uint32_t Value;
399 };
400 } DW22;
401
402 union
403 {
404 struct
405 {
406 uint32_t ACQP : MOS_BITFIELD_RANGE( 0,31 );
407 };
408 struct
409 {
410 uint32_t Value;
411 };
412 } DW23;
413 } BRC_INIT_RESET_CURBE, *PBRC_INIT_RESET_CURBE;
414 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(BRC_INIT_RESET_CURBE)) == 24);
415
416 typedef struct _BRC_UPDATE_CURBE_G8
417 {
418 union
419 {
420 struct
421 {
422 uint32_t TargetSize : MOS_BITFIELD_RANGE( 0,31 );
423 };
424 struct
425 {
426 uint32_t Value;
427 };
428 } DW0;
429
430 union
431 {
432 struct
433 {
434 uint32_t FrameNumber : MOS_BITFIELD_RANGE( 0,31 );
435 };
436 struct
437 {
438 uint32_t Value;
439 };
440 } DW1;
441
442 union
443 {
444 struct
445 {
446 uint32_t SizeofPicHeaders : MOS_BITFIELD_RANGE( 0,31 );
447 };
448 struct
449 {
450 uint32_t Value;
451 };
452 } DW2;
453
454 union
455 {
456 struct
457 {
458 uint32_t startGAdjFrame0 : MOS_BITFIELD_RANGE( 0,15 );
459 uint32_t startGAdjFrame1 : MOS_BITFIELD_RANGE( 16,31 );
460 };
461 struct
462 {
463 uint32_t Value;
464 };
465 } DW3;
466
467 union
468 {
469 struct
470 {
471 uint32_t startGAdjFrame2 : MOS_BITFIELD_RANGE( 0,15 );
472 uint32_t startGAdjFrame3 : MOS_BITFIELD_RANGE( 16,31 );
473 };
474 struct
475 {
476 uint32_t Value;
477 };
478 } DW4;
479
480 union
481 {
482 struct
483 {
484 uint32_t TargetSizeFlag : MOS_BITFIELD_RANGE( 0, 7 );
485 uint32_t BRCFlag : MOS_BITFIELD_RANGE( 8,15 );
486 uint32_t MaxNumPAKs : MOS_BITFIELD_RANGE( 16,23 );
487 uint32_t CurrFrameType : MOS_BITFIELD_RANGE( 24,31 );
488 };
489 struct
490 {
491 uint32_t Value;
492 };
493 } DW5;
494
495 union
496 {
497 struct
498 {
499 uint32_t NumSkipFrames : MOS_BITFIELD_RANGE( 0, 7 );
500 uint32_t MinimumQP : MOS_BITFIELD_RANGE( 8,15 );
501 uint32_t MaximumQP : MOS_BITFIELD_RANGE( 16,23 );
502 uint32_t EnableForceToSkip : MOS_BITFIELD_BIT( 24 );
503 uint32_t EnableSlidingWindow : MOS_BITFIELD_BIT( 25 );
504 uint32_t Reserved : MOS_BITFIELD_RANGE( 26,31 );
505 };
506 struct
507 {
508 uint32_t Value;
509 };
510 } DW6;
511
512 union
513 {
514 struct
515 {
516 uint32_t SizeSkipFrames : MOS_BITFIELD_RANGE( 0,31 );
517 };
518 struct
519 {
520 uint32_t Value;
521 };
522 } DW7;
523
524 union
525 {
526 struct
527 {
528 uint32_t StartGlobalAdjustMult0 : MOS_BITFIELD_RANGE( 0, 7 );
529 uint32_t StartGlobalAdjustMult1 : MOS_BITFIELD_RANGE( 8,15 );
530 uint32_t StartGlobalAdjustMult2 : MOS_BITFIELD_RANGE( 16,23 );
531 uint32_t StartGlobalAdjustMult3 : MOS_BITFIELD_RANGE( 24,31 );
532 };
533 struct
534 {
535 uint32_t Value;
536 };
537 } DW8;
538
539 union
540 {
541 struct
542 {
543 uint32_t StartGlobalAdjustMult4 : MOS_BITFIELD_RANGE( 0, 7 );
544 uint32_t StartGlobalAdjustDiv0 : MOS_BITFIELD_RANGE( 8,15 );
545 uint32_t StartGlobalAdjustDiv1 : MOS_BITFIELD_RANGE( 16,23 );
546 uint32_t StartGlobalAdjustDiv2 : MOS_BITFIELD_RANGE( 24,31 );
547 };
548 struct
549 {
550 uint32_t Value;
551 };
552 } DW9;
553
554 union
555 {
556 struct
557 {
558 uint32_t StartGlobalAdjustDiv3 : MOS_BITFIELD_RANGE( 0, 7 );
559 uint32_t StartGlobalAdjustDiv4 : MOS_BITFIELD_RANGE( 8,15 );
560 uint32_t QPThreshold0 : MOS_BITFIELD_RANGE( 16,23 );
561 uint32_t QPThreshold1 : MOS_BITFIELD_RANGE( 24,31 );
562 };
563 struct
564 {
565 uint32_t Value;
566 };
567 } DW10;
568
569 union
570 {
571 struct
572 {
573 uint32_t QPThreshold2 : MOS_BITFIELD_RANGE( 0, 7 );
574 uint32_t QPThreshold3 : MOS_BITFIELD_RANGE( 8,15 );
575 uint32_t gRateRatioThreshold0 : MOS_BITFIELD_RANGE( 16,23 );
576 uint32_t gRateRatioThreshold1 : MOS_BITFIELD_RANGE( 24,31 );
577 };
578 struct
579 {
580 uint32_t Value;
581 };
582 } DW11;
583
584 union
585 {
586 struct
587 {
588 uint32_t gRateRatioThreshold2 : MOS_BITFIELD_RANGE( 0, 7 );
589 uint32_t gRateRatioThreshold3 : MOS_BITFIELD_RANGE( 8,15 );
590 uint32_t gRateRatioThreshold4 : MOS_BITFIELD_RANGE( 16,23 );
591 uint32_t gRateRatioThreshold5 : MOS_BITFIELD_RANGE( 24,31 );
592 };
593 struct
594 {
595 uint32_t Value;
596 };
597 } DW12;
598
599 union
600 {
601 struct
602 {
603 uint32_t gRateRatioThresholdQP0 : MOS_BITFIELD_RANGE( 0, 7 );
604 uint32_t gRateRatioThresholdQP1 : MOS_BITFIELD_RANGE( 8,15 );
605 uint32_t gRateRatioThresholdQP2 : MOS_BITFIELD_RANGE( 16,23 );
606 uint32_t gRateRatioThresholdQP3 : MOS_BITFIELD_RANGE( 24,31 );
607 };
608 struct
609 {
610 uint32_t Value;
611 };
612 } DW13;
613
614 union
615 {
616 struct
617 {
618 uint32_t gRateRatioThresholdQP4 : MOS_BITFIELD_RANGE( 0, 7 );
619 uint32_t gRateRatioThresholdQP5 : MOS_BITFIELD_RANGE( 8,15 );
620 uint32_t gRateRatioThresholdQP6 : MOS_BITFIELD_RANGE( 16,23 );
621 uint32_t QPIndexOfCurPic : MOS_BITFIELD_RANGE( 24,31 );
622 };
623 struct
624 {
625 uint32_t Value;
626 };
627 } DW14;
628
629 union
630 {
631 struct
632 {
633 uint32_t QPIntraRefresh : MOS_BITFIELD_RANGE( 0, 7 );
634 uint32_t IntraRefreshMode : MOS_BITFIELD_RANGE( 8,15 );
635 uint32_t Reserved1 : MOS_BITFIELD_RANGE( 16,23 );
636 uint32_t Reserved2 : MOS_BITFIELD_RANGE( 24,31 );
637 };
638 struct
639 {
640 uint32_t Value;
641 };
642 } DW15;
643
644 union
645 {
646 struct
647 {
648 uint32_t IntraRefreshYPos : MOS_BITFIELD_RANGE( 0,15 );
649 uint32_t IntraRefreshXPos : MOS_BITFIELD_RANGE( 16,31 );
650 };
651 struct
652 {
653 uint32_t Value;
654 };
655 } DW16;
656
657 union
658 {
659 struct
660 {
661 uint32_t IntraRefreshHeight : MOS_BITFIELD_RANGE( 0,15 );
662 uint32_t IntraRefreshWidth : MOS_BITFIELD_RANGE( 16,31 );
663 };
664 struct
665 {
666 uint32_t Value;
667 };
668 } DW17;
669
670 union
671 {
672 struct
673 {
674 uint32_t IntraRefreshOffFrames : MOS_BITFIELD_RANGE( 0,15 );
675 uint32_t Reserved : MOS_BITFIELD_RANGE( 16,31 );
676 };
677 struct
678 {
679 uint32_t Value;
680 };
681 } DW18;
682
683 union
684 {
685 struct
686 {
687 uint32_t UserMaxFrame : MOS_BITFIELD_RANGE( 0,31 );
688 };
689 struct
690 {
691 uint32_t Value;
692 };
693 } DW19;
694
695 union
696 {
697 struct
698 {
699 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
700 };
701 struct
702 {
703 uint32_t Value;
704 };
705 } DW20;
706
707 union
708 {
709 struct
710 {
711 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
712 };
713 struct
714 {
715 uint32_t Value;
716 };
717 } DW21;
718
719 union
720 {
721 struct
722 {
723 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
724 };
725 struct
726 {
727 uint32_t Value;
728 };
729 } DW22;
730
731 union
732 {
733 struct
734 {
735 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
736 };
737 struct
738 {
739 uint32_t Value;
740 };
741 } DW23;
742 } BRC_UPDATE_CURBE, *PBRC_UPDATE_CURBE;
743 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(BRC_UPDATE_CURBE)) == 24);
744
745 typedef struct _AVC_ME_CURBE_CM
746 {
747 // DW0
748 union
749 {
750 struct
751 {
752 uint32_t SkipModeEn : MOS_BITFIELD_BIT( 0 );
753 uint32_t AdaptiveEn : MOS_BITFIELD_BIT( 1 );
754 uint32_t BiMixDis : MOS_BITFIELD_BIT( 2 );
755 uint32_t : MOS_BITFIELD_RANGE( 3, 4 );
756 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT( 5 );
757 uint32_t : MOS_BITFIELD_BIT( 6 );
758 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT( 7 );
759 uint32_t : MOS_BITFIELD_RANGE( 8,23 );
760 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE( 24,31 );
761 };
762 struct
763 {
764 uint32_t Value;
765 };
766 } DW0;
767
768 // DW1
769 union
770 {
771 struct
772 {
773 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE( 0, 5 );
774 uint32_t : MOS_BITFIELD_RANGE( 6,15 );
775 uint32_t BiWeight : MOS_BITFIELD_RANGE( 16,21 );
776 uint32_t : MOS_BITFIELD_RANGE( 22,27 );
777 uint32_t UniMixDisable : MOS_BITFIELD_BIT( 28 );
778 uint32_t : MOS_BITFIELD_RANGE( 29,31 );
779 };
780 struct
781 {
782 uint32_t Value;
783 };
784 } DW1;
785
786 // DW2
787 union
788 {
789 struct
790 {
791 uint32_t MaxLenSP : MOS_BITFIELD_RANGE( 0, 7 );
792 uint32_t MaxNumSU : MOS_BITFIELD_RANGE( 8,15 );
793 uint32_t : MOS_BITFIELD_RANGE( 16,31 );
794 };
795 struct
796 {
797 uint32_t Value;
798 };
799 } DW2;
800
801 // DW3
802 union
803 {
804 struct
805 {
806 uint32_t SrcSize : MOS_BITFIELD_RANGE( 0, 1 );
807 uint32_t : MOS_BITFIELD_RANGE( 2, 3 );
808 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE( 4, 5 );
809 uint32_t SrcAccess : MOS_BITFIELD_BIT( 6 );
810 uint32_t RefAccess : MOS_BITFIELD_BIT( 7 );
811 uint32_t SearchCtrl : MOS_BITFIELD_RANGE( 8,10 );
812 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT( 11 );
813 uint32_t SubPelMode : MOS_BITFIELD_RANGE( 12,13 );
814 uint32_t SkipType : MOS_BITFIELD_BIT( 14 );
815 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT( 15 );
816 uint32_t InterChromaMode : MOS_BITFIELD_BIT( 16 );
817 uint32_t FTEnable : MOS_BITFIELD_BIT( 17 );
818 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT( 18 );
819 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT( 19 );
820 uint32_t InterSAD : MOS_BITFIELD_RANGE( 20,21 );
821 uint32_t IntraSAD : MOS_BITFIELD_RANGE( 22,23 );
822 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE( 24,30 );
823 uint32_t : MOS_BITFIELD_BIT( 31 );
824 };
825 struct
826 {
827 uint32_t Value;
828 };
829 } DW3;
830
831 // DW4
832 union
833 {
834 struct
835 {
836 uint32_t : MOS_BITFIELD_RANGE( 0, 7 );
837 uint32_t PictureHeightMinus1 : MOS_BITFIELD_RANGE( 8,15 );
838 uint32_t PictureWidth : MOS_BITFIELD_RANGE( 16,23 );
839 uint32_t : MOS_BITFIELD_RANGE( 24,31 );
840 };
841 struct
842 {
843 uint32_t Value;
844 };
845 } DW4;
846
847 // DW5
848 union
849 {
850 struct
851 {
852 uint32_t : MOS_BITFIELD_RANGE( 0, 7 );
853 uint32_t QpPrimeY : MOS_BITFIELD_RANGE( 8,15 );
854 uint32_t RefWidth : MOS_BITFIELD_RANGE( 16,23 );
855 uint32_t RefHeight : MOS_BITFIELD_RANGE( 24,31 );
856
857 };
858 struct
859 {
860 uint32_t Value;
861 };
862 } DW5;
863
864 // DW6
865 union
866 {
867 struct
868 {
869 uint32_t : MOS_BITFIELD_RANGE( 0, 2 );
870 uint32_t WriteDistortions : MOS_BITFIELD_BIT( 3 );
871 uint32_t UseMvFromPrevStep : MOS_BITFIELD_BIT( 4 );
872 uint32_t : MOS_BITFIELD_RANGE( 5, 7 );
873 uint32_t SuperCombineDist : MOS_BITFIELD_RANGE( 8,15 );
874 uint32_t MaxVmvR : MOS_BITFIELD_RANGE( 16,31 );
875 };
876 struct
877 {
878 uint32_t Value;
879 };
880 } DW6;
881
882 // DW7
883 union
884 {
885 struct
886 {
887 uint32_t : MOS_BITFIELD_RANGE( 0,15 );
888 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE( 16,17 );
889 uint32_t BilinearEnable : MOS_BITFIELD_BIT( 18 );
890 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT( 19 );
891 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT( 20 );
892 uint32_t AConlyHAAR : MOS_BITFIELD_BIT( 21 );
893 uint32_t RefIDCostMode : MOS_BITFIELD_BIT( 22 );
894 uint32_t : MOS_BITFIELD_BIT( 23 );
895 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE( 24,31 );
896 };
897 struct
898 {
899 uint32_t Value;
900 };
901 } DW7;
902
903 // DW8
904 union
905 {
906 struct
907 {
908 uint32_t Mode0Cost : MOS_BITFIELD_RANGE( 0, 7 );
909 uint32_t Mode1Cost : MOS_BITFIELD_RANGE( 8,15 );
910 uint32_t Mode2Cost : MOS_BITFIELD_RANGE( 16,23 );
911 uint32_t Mode3Cost : MOS_BITFIELD_RANGE( 24,31 );
912 };
913 struct
914 {
915 uint32_t Value;
916 };
917 } DW8;
918
919 // DW9
920 union
921 {
922 struct
923 {
924 uint32_t Mode4Cost : MOS_BITFIELD_RANGE( 0, 7 );
925 uint32_t Mode5Cost : MOS_BITFIELD_RANGE( 8,15 );
926 uint32_t Mode6Cost : MOS_BITFIELD_RANGE( 16,23 );
927 uint32_t Mode7Cost : MOS_BITFIELD_RANGE( 24,31 );
928 };
929 struct
930 {
931 uint32_t Value;
932 };
933 } DW9;
934
935 // DW10
936 union
937 {
938 struct
939 {
940 uint32_t Mode8Cost : MOS_BITFIELD_RANGE( 0, 7 );
941 uint32_t Mode9Cost : MOS_BITFIELD_RANGE( 8,15 );
942 uint32_t RefIDCost : MOS_BITFIELD_RANGE( 16,23 );
943 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE( 24,31 );
944 };
945 struct
946 {
947 uint32_t Value;
948 };
949 } DW10;
950
951 // DW11
952 union
953 {
954 struct
955 {
956 uint32_t MV0Cost : MOS_BITFIELD_RANGE( 0, 7 );
957 uint32_t MV1Cost : MOS_BITFIELD_RANGE( 8,15 );
958 uint32_t MV2Cost : MOS_BITFIELD_RANGE( 16,23 );
959 uint32_t MV3Cost : MOS_BITFIELD_RANGE( 24,31 );
960 };
961 struct
962 {
963 uint32_t Value;
964 };
965 } DW11;
966
967 // DW12
968 union
969 {
970 struct
971 {
972 uint32_t MV4Cost : MOS_BITFIELD_RANGE( 0, 7 );
973 uint32_t MV5Cost : MOS_BITFIELD_RANGE( 8,15 );
974 uint32_t MV6Cost : MOS_BITFIELD_RANGE( 16,23 );
975 uint32_t MV7Cost : MOS_BITFIELD_RANGE( 24,31 );
976 };
977 struct
978 {
979 uint32_t Value;
980 };
981 } DW12;
982
983 // DW13
984 union
985 {
986 struct
987 {
988 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE( 0, 7 );
989 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE( 8,15 );
990 uint32_t ActualMBWidth : MOS_BITFIELD_RANGE( 16,23 );
991 uint32_t ActualMBHeight : MOS_BITFIELD_RANGE( 24,31 );
992 };
993 struct
994 {
995 uint32_t Value;
996 };
997 } DW13;
998
999 // DW14
1000 union
1001 {
1002 struct
1003 {
1004 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT( 0 );
1005 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT( 1 );
1006 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT( 2 );
1007 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT( 3 );
1008 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT( 4 );
1009 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT( 5 );
1010 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT( 6 );
1011 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT( 7 );
1012 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT( 8 );
1013 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT( 9 );
1014 uint32_t : MOS_BITFIELD_RANGE( 10,31 );
1015 };
1016 struct
1017 {
1018 uint32_t Value;
1019 };
1020 } DW14;
1021
1022 // DW15
1023 union
1024 {
1025 struct
1026 {
1027 uint32_t PrevMvReadPosFactor : MOS_BITFIELD_RANGE( 0, 7 );
1028 uint32_t MvShiftFactor : MOS_BITFIELD_RANGE( 8, 15 );
1029 uint32_t Reserved : MOS_BITFIELD_RANGE( 16,31 );
1030 };
1031 struct
1032 {
1033 uint32_t Value;
1034 };
1035 } DW15;
1036
1037 struct
1038 {
1039 // DW16
1040 union
1041 {
1042 struct
1043 {
1044 SearchPathDelta SPDelta_0;
1045 SearchPathDelta SPDelta_1;
1046 SearchPathDelta SPDelta_2;
1047 SearchPathDelta SPDelta_3;
1048 };
1049 struct
1050 {
1051 uint32_t Value;
1052 };
1053 } DW16;
1054
1055 // DW17
1056 union
1057 {
1058 struct
1059 {
1060 SearchPathDelta SPDelta_4;
1061 SearchPathDelta SPDelta_5;
1062 SearchPathDelta SPDelta_6;
1063 SearchPathDelta SPDelta_7;
1064 };
1065 struct
1066 {
1067 uint32_t Value;
1068 };
1069 } DW17;
1070
1071 // DW18
1072 union
1073 {
1074 struct
1075 {
1076 SearchPathDelta SPDelta_8;
1077 SearchPathDelta SPDelta_9;
1078 SearchPathDelta SPDelta_10;
1079 SearchPathDelta SPDelta_11;
1080 };
1081 struct
1082 {
1083 uint32_t Value;
1084 };
1085 } DW18;
1086
1087 // DW19
1088 union
1089 {
1090 struct
1091 {
1092 SearchPathDelta SPDelta_12;
1093 SearchPathDelta SPDelta_13;
1094 SearchPathDelta SPDelta_14;
1095 SearchPathDelta SPDelta_15;
1096 };
1097 struct
1098 {
1099 uint32_t Value;
1100 };
1101 } DW19;
1102
1103 // DW20
1104 union
1105 {
1106 struct
1107 {
1108 SearchPathDelta SPDelta_16;
1109 SearchPathDelta SPDelta_17;
1110 SearchPathDelta SPDelta_18;
1111 SearchPathDelta SPDelta_19;
1112 };
1113 struct
1114 {
1115 uint32_t Value;
1116 };
1117 } DW20;
1118
1119 // DW21
1120 union
1121 {
1122 struct
1123 {
1124 SearchPathDelta SPDelta_20;
1125 SearchPathDelta SPDelta_21;
1126 SearchPathDelta SPDelta_22;
1127 SearchPathDelta SPDelta_23;
1128 };
1129 struct
1130 {
1131 uint32_t Value;
1132 };
1133 } DW21;
1134
1135 // DW22
1136 union
1137 {
1138 struct
1139 {
1140 SearchPathDelta SPDelta_24;
1141 SearchPathDelta SPDelta_25;
1142 SearchPathDelta SPDelta_26;
1143 SearchPathDelta SPDelta_27;
1144 };
1145 struct
1146 {
1147 uint32_t Value;
1148 };
1149 } DW22;
1150
1151 // DW23
1152 union
1153 {
1154 struct
1155 {
1156 SearchPathDelta SPDelta_28;
1157 SearchPathDelta SPDelta_29;
1158 SearchPathDelta SPDelta_30;
1159 SearchPathDelta SPDelta_31;
1160 };
1161 struct
1162 {
1163 uint32_t Value;
1164 };
1165 } DW23;
1166
1167 // DW24
1168 union
1169 {
1170 struct
1171 {
1172 SearchPathDelta SPDelta_32;
1173 SearchPathDelta SPDelta_33;
1174 SearchPathDelta SPDelta_34;
1175 SearchPathDelta SPDelta_35;
1176 };
1177 struct
1178 {
1179 uint32_t Value;
1180 };
1181 } DW24;
1182
1183 // DW25
1184 union
1185 {
1186 struct
1187 {
1188 SearchPathDelta SPDelta_36;
1189 SearchPathDelta SPDelta_37;
1190 SearchPathDelta SPDelta_38;
1191 SearchPathDelta SPDelta_39;
1192 };
1193 struct
1194 {
1195 uint32_t Value;
1196 };
1197 } DW25;
1198
1199 // DW26
1200 union
1201 {
1202 struct
1203 {
1204 SearchPathDelta SPDelta_40;
1205 SearchPathDelta SPDelta_41;
1206 SearchPathDelta SPDelta_42;
1207 SearchPathDelta SPDelta_43;
1208 };
1209 struct
1210 {
1211 uint32_t Value;
1212 };
1213 } DW26;
1214
1215 // DW27
1216 union
1217 {
1218 struct
1219 {
1220 SearchPathDelta SPDelta_44;
1221 SearchPathDelta SPDelta_45;
1222 SearchPathDelta SPDelta_46;
1223 SearchPathDelta SPDelta_47;
1224 };
1225 struct
1226 {
1227 uint32_t Value;
1228 };
1229 } DW27;
1230
1231 // DW28
1232 union
1233 {
1234 struct
1235 {
1236 SearchPathDelta SPDelta_48;
1237 SearchPathDelta SPDelta_49;
1238 SearchPathDelta SPDelta_50;
1239 SearchPathDelta SPDelta_51;
1240 };
1241 struct
1242 {
1243 uint32_t Value;
1244 };
1245 } DW28;
1246
1247 // DW29
1248 union
1249 {
1250 struct
1251 {
1252 SearchPathDelta SPDelta_52;
1253 SearchPathDelta SPDelta_53;
1254 SearchPathDelta SPDelta_54;
1255 SearchPathDelta SPDelta_55;
1256 };
1257 struct
1258 {
1259 uint32_t Value;
1260 };
1261 } DW29;
1262 } SPDelta;
1263
1264 // DW30
1265 union
1266 {
1267 struct
1268 {
1269 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
1270 };
1271 struct
1272 {
1273 uint32_t Value;
1274 };
1275 } DW30;
1276
1277 // DW31
1278 union
1279 {
1280 struct
1281 {
1282 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
1283 };
1284 struct
1285 {
1286 uint32_t Value;
1287 };
1288 } DW31;
1289
1290 // DW32
1291 union
1292 {
1293 struct
1294 {
1295 uint32_t _4xMeMvOutputDataSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
1296 };
1297 struct
1298 {
1299 uint32_t Value;
1300 };
1301 } DW32;
1302
1303 // DW33
1304 union
1305 {
1306 struct
1307 {
1308 uint32_t _16xOr32xMeMvInputDataSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
1309 };
1310 struct
1311 {
1312 uint32_t Value;
1313 };
1314 } DW33;
1315
1316 // DW34
1317 union
1318 {
1319 struct
1320 {
1321 uint32_t _4xMeOutputDistSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
1322 };
1323 struct
1324 {
1325 uint32_t Value;
1326 };
1327 } DW34;
1328
1329 // DW35
1330 union
1331 {
1332 struct
1333 {
1334 uint32_t _4xMeOutputBrcDistSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
1335 };
1336 struct
1337 {
1338 uint32_t Value;
1339 };
1340 } DW35;
1341
1342 // DW36
1343 union
1344 {
1345 struct
1346 {
1347 uint32_t VMEFwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
1348 };
1349 struct
1350 {
1351 uint32_t Value;
1352 };
1353 } DW36;
1354
1355 // DW37
1356 union
1357 {
1358 struct
1359 {
1360 uint32_t VMEBwdInterPredictionSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
1361 };
1362 struct
1363 {
1364 uint32_t Value;
1365 };
1366 } DW37;
1367
1368 // DW38
1369 union
1370 {
1371 struct
1372 {
1373 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
1374 };
1375 struct
1376 {
1377 uint32_t Value;
1378 };
1379 } DW38;
1380
1381 } ME_CURBE_CM, *PME_CURBE_CM;
1382 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(ME_CURBE_CM)) == 39);
1383
1384 typedef struct _MBENC_CURBE_CM
1385 {
1386 // DW0
1387 union
1388 {
1389 struct
1390 {
1391 uint32_t SkipModeEn : MOS_BITFIELD_BIT( 0 );
1392 uint32_t AdaptiveEn : MOS_BITFIELD_BIT( 1 );
1393 uint32_t BiMixDis : MOS_BITFIELD_BIT( 2 );
1394 uint32_t : MOS_BITFIELD_RANGE( 3, 4 );
1395 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT( 5 );
1396 uint32_t : MOS_BITFIELD_BIT( 6 );
1397 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT( 7 );
1398 uint32_t : MOS_BITFIELD_RANGE( 8,23 );
1399 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE( 24,31 );
1400 };
1401 struct
1402 {
1403 uint32_t Value;
1404 };
1405 } DW0;
1406
1407 // DW1
1408 union
1409 {
1410 struct
1411 {
1412 uint32_t MaxNumMVs : MOS_BITFIELD_RANGE( 0, 5 );
1413 uint32_t : MOS_BITFIELD_RANGE( 6,15 );
1414 uint32_t BiWeight : MOS_BITFIELD_RANGE( 16,21 );
1415 uint32_t : MOS_BITFIELD_RANGE( 22,27 );
1416 uint32_t UniMixDisable : MOS_BITFIELD_BIT( 28 );
1417 uint32_t : MOS_BITFIELD_RANGE( 29,31 );
1418 };
1419 struct
1420 {
1421 uint32_t Value;
1422 };
1423 } DW1;
1424
1425 // DW2
1426 union
1427 {
1428 struct
1429 {
1430 uint32_t LenSP : MOS_BITFIELD_RANGE( 0, 7 );
1431 uint32_t MaxNumSU : MOS_BITFIELD_RANGE( 8,15 );
1432 uint32_t PicWidth : MOS_BITFIELD_RANGE( 16,31 );
1433 };
1434 struct
1435 {
1436 uint32_t Value;
1437 };
1438 } DW2;
1439
1440 // DW3
1441 union
1442 {
1443 struct
1444 {
1445 uint32_t SrcSize : MOS_BITFIELD_RANGE( 0, 1 );
1446 uint32_t : MOS_BITFIELD_RANGE( 2, 3 );
1447 uint32_t MbTypeRemap : MOS_BITFIELD_RANGE( 4, 5 );
1448 uint32_t SrcAccess : MOS_BITFIELD_BIT( 6 );
1449 uint32_t RefAccess : MOS_BITFIELD_BIT( 7 );
1450 uint32_t SearchCtrl : MOS_BITFIELD_RANGE( 8,10 );
1451 uint32_t DualSearchPathOption : MOS_BITFIELD_BIT( 11 );
1452 uint32_t SubPelMode : MOS_BITFIELD_RANGE( 12,13 );
1453 uint32_t SkipType : MOS_BITFIELD_BIT( 14 );
1454 uint32_t DisableFieldCacheAlloc : MOS_BITFIELD_BIT( 15 );
1455 uint32_t InterChromaMode : MOS_BITFIELD_BIT( 16 );
1456 uint32_t FTEnable : MOS_BITFIELD_BIT( 17 );
1457 uint32_t BMEDisableFBR : MOS_BITFIELD_BIT( 18 );
1458 uint32_t BlockBasedSkipEnable : MOS_BITFIELD_BIT( 19 );
1459 uint32_t InterSAD : MOS_BITFIELD_RANGE( 20,21 );
1460 uint32_t IntraSAD : MOS_BITFIELD_RANGE( 22,23 );
1461 uint32_t SubMbPartMask : MOS_BITFIELD_RANGE( 24,30 );
1462 uint32_t : MOS_BITFIELD_BIT( 31 );
1463 };
1464 struct
1465 {
1466 uint32_t Value;
1467 };
1468 } DW3;
1469
1470 // DW4
1471 union
1472 {
1473 struct
1474 {
1475 uint32_t PicHeightMinus1 : MOS_BITFIELD_RANGE( 0,15 );
1476 uint32_t MvRestrictionInSliceEnable : MOS_BITFIELD_BIT( 16 );
1477 uint32_t DeltaMvEnable : MOS_BITFIELD_BIT( 17 );
1478 uint32_t TrueDistortionEnable : MOS_BITFIELD_BIT( 18 );
1479 uint32_t EnableWavefrontOptimization : MOS_BITFIELD_BIT( 19);
1480 uint32_t : MOS_BITFIELD_BIT( 20);
1481 uint32_t EnableIntraCostScalingForStaticFrame: MOS_BITFIELD_BIT( 21);
1482 uint32_t EnableIntraRefresh : MOS_BITFIELD_BIT( 22);
1483 uint32_t Reserved : MOS_BITFIELD_BIT( 23);
1484 uint32_t EnableDirtyRect : MOS_BITFIELD_BIT( 24);
1485 uint32_t bCurFldIDR : MOS_BITFIELD_BIT( 25 );
1486 uint32_t ConstrainedIntraPredFlag : MOS_BITFIELD_BIT( 26 );
1487 uint32_t FieldParityFlag : MOS_BITFIELD_BIT( 27 );
1488 uint32_t HMEEnable : MOS_BITFIELD_BIT( 28 );
1489 uint32_t PictureType : MOS_BITFIELD_RANGE( 29,30 );
1490 uint32_t UseActualRefQPValue : MOS_BITFIELD_BIT( 31 );
1491 };
1492 struct
1493 {
1494 uint32_t Value;
1495 };
1496 } DW4;
1497
1498 // DW5
1499 union
1500 {
1501 struct
1502 {
1503 uint32_t SliceMbHeight : MOS_BITFIELD_RANGE( 0,15 );
1504 uint32_t RefWidth : MOS_BITFIELD_RANGE( 16,23 );
1505 uint32_t RefHeight : MOS_BITFIELD_RANGE( 24,31 );
1506 };
1507 struct
1508 {
1509 uint32_t Value;
1510 };
1511 } DW5;
1512
1513 // DW6
1514 union
1515 {
1516 struct
1517 {
1518 uint32_t BatchBufferEnd : MOS_BITFIELD_RANGE( 0,31 );
1519 };
1520 struct
1521 {
1522 uint32_t Value;
1523 };
1524 } DW6;
1525
1526 // DW7
1527 union
1528 {
1529 struct
1530 {
1531 uint32_t IntraPartMask : MOS_BITFIELD_RANGE( 0, 4 );
1532 uint32_t NonSkipZMvAdded : MOS_BITFIELD_BIT( 5 );
1533 uint32_t NonSkipModeAdded : MOS_BITFIELD_BIT( 6 );
1534 uint32_t LumaIntraSrcCornerSwap : MOS_BITFIELD_BIT( 7 );
1535 uint32_t : MOS_BITFIELD_RANGE( 8,15 );
1536 uint32_t MVCostScaleFactor : MOS_BITFIELD_RANGE( 16,17 );
1537 uint32_t BilinearEnable : MOS_BITFIELD_BIT( 18 );
1538 uint32_t SrcFieldPolarity : MOS_BITFIELD_BIT( 19 );
1539 uint32_t WeightedSADHAAR : MOS_BITFIELD_BIT( 20 );
1540 uint32_t AConlyHAAR : MOS_BITFIELD_BIT( 21 );
1541 uint32_t RefIDCostMode : MOS_BITFIELD_BIT( 22 );
1542 uint32_t : MOS_BITFIELD_BIT( 23 );
1543 uint32_t SkipCenterMask : MOS_BITFIELD_RANGE( 24,31 );
1544 };
1545 struct
1546 {
1547 uint32_t Value;
1548 };
1549 } DW7;
1550
1551 struct
1552 {
1553 // DW8
1554 union
1555 {
1556 struct
1557 {
1558 uint32_t Mode0Cost : MOS_BITFIELD_RANGE( 0, 7 );
1559 uint32_t Mode1Cost : MOS_BITFIELD_RANGE( 8,15 );
1560 uint32_t Mode2Cost : MOS_BITFIELD_RANGE( 16,23 );
1561 uint32_t Mode3Cost : MOS_BITFIELD_RANGE( 24,31 );
1562 };
1563 struct
1564 {
1565 uint32_t Value;
1566 };
1567 } DW8;
1568
1569 // DW9
1570 union
1571 {
1572 struct
1573 {
1574 uint32_t Mode4Cost : MOS_BITFIELD_RANGE( 0, 7 );
1575 uint32_t Mode5Cost : MOS_BITFIELD_RANGE( 8,15 );
1576 uint32_t Mode6Cost : MOS_BITFIELD_RANGE( 16,23 );
1577 uint32_t Mode7Cost : MOS_BITFIELD_RANGE( 24,31 );
1578 };
1579 struct
1580 {
1581 uint32_t Value;
1582 };
1583 } DW9;
1584
1585 // DW10
1586 union
1587 {
1588 struct
1589 {
1590 uint32_t Mode8Cost : MOS_BITFIELD_RANGE( 0, 7 );
1591 uint32_t Mode9Cost : MOS_BITFIELD_RANGE( 8,15 );
1592 uint32_t RefIDCost : MOS_BITFIELD_RANGE( 16,23 );
1593 uint32_t ChromaIntraModeCost : MOS_BITFIELD_RANGE( 24,31 );
1594 };
1595 struct
1596 {
1597 uint32_t Value;
1598 };
1599 } DW10;
1600
1601 // DW11
1602 union
1603 {
1604 struct
1605 {
1606 uint32_t MV0Cost : MOS_BITFIELD_RANGE( 0, 7 );
1607 uint32_t MV1Cost : MOS_BITFIELD_RANGE( 8,15 );
1608 uint32_t MV2Cost : MOS_BITFIELD_RANGE( 16,23 );
1609 uint32_t MV3Cost : MOS_BITFIELD_RANGE( 24,31 );
1610 };
1611 struct
1612 {
1613 uint32_t Value;
1614 };
1615 } DW11;
1616
1617 // DW12
1618 union
1619 {
1620 struct
1621 {
1622 uint32_t MV4Cost : MOS_BITFIELD_RANGE( 0, 7 );
1623 uint32_t MV5Cost : MOS_BITFIELD_RANGE( 8,15 );
1624 uint32_t MV6Cost : MOS_BITFIELD_RANGE( 16,23 );
1625 uint32_t MV7Cost : MOS_BITFIELD_RANGE( 24,31 );
1626 };
1627 struct
1628 {
1629 uint32_t Value;
1630 };
1631 } DW12;
1632
1633 // DW13
1634 union
1635 {
1636 struct
1637 {
1638 uint32_t QpPrimeY : MOS_BITFIELD_RANGE( 0, 7 );
1639 uint32_t QpPrimeCb : MOS_BITFIELD_RANGE( 8,15 );
1640 uint32_t QpPrimeCr : MOS_BITFIELD_RANGE( 16,23 );
1641 uint32_t TargetSizeInWord : MOS_BITFIELD_RANGE( 24,31 );
1642 };
1643 struct
1644 {
1645 uint32_t Value;
1646 };
1647 } DW13;
1648
1649 // DW14
1650 union
1651 {
1652 struct
1653 {
1654 uint32_t SICFwdTransCoeffThreshold_0 : MOS_BITFIELD_RANGE( 0,15 );
1655 uint32_t SICFwdTransCoeffThreshold_1 : MOS_BITFIELD_RANGE( 16,23 );
1656 uint32_t SICFwdTransCoeffThreshold_2 : MOS_BITFIELD_RANGE( 24,31 );
1657 };
1658 struct
1659 {
1660 uint32_t Value;
1661 };
1662 } DW14;
1663
1664 // DW15
1665 union
1666 {
1667 struct
1668 {
1669 uint32_t SICFwdTransCoeffThreshold_3 : MOS_BITFIELD_RANGE( 0, 7 );
1670 uint32_t SICFwdTransCoeffThreshold_4 : MOS_BITFIELD_RANGE( 8,15 );
1671 uint32_t SICFwdTransCoeffThreshold_5 : MOS_BITFIELD_RANGE( 16,23 );
1672 uint32_t SICFwdTransCoeffThreshold_6 : MOS_BITFIELD_RANGE( 24,31 ); // Highest Freq
1673 };
1674 struct
1675 {
1676 uint32_t Value;
1677 };
1678 } DW15;
1679 } ModeMvCost;
1680
1681 struct
1682 {
1683 // DW16
1684 union
1685 {
1686 struct
1687 {
1688 SearchPathDelta SPDelta_0;
1689 SearchPathDelta SPDelta_1;
1690 SearchPathDelta SPDelta_2;
1691 SearchPathDelta SPDelta_3;
1692 };
1693 struct
1694 {
1695 uint32_t Value;
1696 };
1697 } DW16;
1698
1699 // DW17
1700 union
1701 {
1702 struct
1703 {
1704 SearchPathDelta SPDelta_4;
1705 SearchPathDelta SPDelta_5;
1706 SearchPathDelta SPDelta_6;
1707 SearchPathDelta SPDelta_7;
1708 };
1709 struct
1710 {
1711 uint32_t Value;
1712 };
1713 } DW17;
1714
1715 // DW18
1716 union
1717 {
1718 struct
1719 {
1720 SearchPathDelta SPDelta_8;
1721 SearchPathDelta SPDelta_9;
1722 SearchPathDelta SPDelta_10;
1723 SearchPathDelta SPDelta_11;
1724 };
1725 struct
1726 {
1727 uint32_t Value;
1728 };
1729 } DW18;
1730
1731 // DW19
1732 union
1733 {
1734 struct
1735 {
1736 SearchPathDelta SPDelta_12;
1737 SearchPathDelta SPDelta_13;
1738 SearchPathDelta SPDelta_14;
1739 SearchPathDelta SPDelta_15;
1740 };
1741 struct
1742 {
1743 uint32_t Value;
1744 };
1745 } DW19;
1746
1747 // DW20
1748 union
1749 {
1750 struct
1751 {
1752 SearchPathDelta SPDelta_16;
1753 SearchPathDelta SPDelta_17;
1754 SearchPathDelta SPDelta_18;
1755 SearchPathDelta SPDelta_19;
1756 };
1757 struct
1758 {
1759 uint32_t Value;
1760 };
1761 } DW20;
1762
1763 // DW21
1764 union
1765 {
1766 struct
1767 {
1768 SearchPathDelta SPDelta_20;
1769 SearchPathDelta SPDelta_21;
1770 SearchPathDelta SPDelta_22;
1771 SearchPathDelta SPDelta_23;
1772 };
1773 struct
1774 {
1775 uint32_t Value;
1776 };
1777 } DW21;
1778
1779 // DW22
1780 union
1781 {
1782 struct
1783 {
1784 SearchPathDelta SPDelta_24;
1785 SearchPathDelta SPDelta_25;
1786 SearchPathDelta SPDelta_26;
1787 SearchPathDelta SPDelta_27;
1788 };
1789 struct
1790 {
1791 uint32_t Value;
1792 };
1793 } DW22;
1794
1795 // DW23
1796 union
1797 {
1798 struct
1799 {
1800 SearchPathDelta SPDelta_28;
1801 SearchPathDelta SPDelta_29;
1802 SearchPathDelta SPDelta_30;
1803 SearchPathDelta SPDelta_31;
1804 };
1805 struct
1806 {
1807 uint32_t Value;
1808 };
1809 } DW23;
1810
1811 // DW24
1812 union
1813 {
1814 struct
1815 {
1816 SearchPathDelta SPDelta_32;
1817 SearchPathDelta SPDelta_33;
1818 SearchPathDelta SPDelta_34;
1819 SearchPathDelta SPDelta_35;
1820 };
1821 struct
1822 {
1823 uint32_t Value;
1824 };
1825 } DW24;
1826
1827 // DW25
1828 union
1829 {
1830 struct
1831 {
1832 SearchPathDelta SPDelta_36;
1833 SearchPathDelta SPDelta_37;
1834 SearchPathDelta SPDelta_38;
1835 SearchPathDelta SPDelta_39;
1836 };
1837 struct
1838 {
1839 uint32_t Value;
1840 };
1841 } DW25;
1842
1843 // DW26
1844 union
1845 {
1846 struct
1847 {
1848 SearchPathDelta SPDelta_40;
1849 SearchPathDelta SPDelta_41;
1850 SearchPathDelta SPDelta_42;
1851 SearchPathDelta SPDelta_43;
1852 };
1853 struct
1854 {
1855 uint32_t Value;
1856 };
1857 } DW26;
1858
1859 // DW27
1860 union
1861 {
1862 struct
1863 {
1864 SearchPathDelta SPDelta_44;
1865 SearchPathDelta SPDelta_45;
1866 SearchPathDelta SPDelta_46;
1867 SearchPathDelta SPDelta_47;
1868 };
1869 struct
1870 {
1871 uint32_t Value;
1872 };
1873 } DW27;
1874
1875 // DW28
1876 union
1877 {
1878 struct
1879 {
1880 SearchPathDelta SPDelta_48;
1881 SearchPathDelta SPDelta_49;
1882 SearchPathDelta SPDelta_50;
1883 SearchPathDelta SPDelta_51;
1884 };
1885 struct
1886 {
1887 uint32_t Value;
1888 };
1889 } DW28;
1890
1891 // DW29
1892 union
1893 {
1894 struct
1895 {
1896 SearchPathDelta SPDelta_52;
1897 SearchPathDelta SPDelta_53;
1898 SearchPathDelta SPDelta_54;
1899 SearchPathDelta SPDelta_55;
1900 };
1901 struct
1902 {
1903 uint32_t Value;
1904 };
1905 } DW29;
1906
1907 // DW30
1908 union
1909 {
1910 struct
1911 {
1912 uint32_t Intra4x4ModeMask : MOS_BITFIELD_RANGE( 0, 8 );
1913 uint32_t : MOS_BITFIELD_RANGE( 9,15 );
1914 uint32_t Intra8x8ModeMask : MOS_BITFIELD_RANGE( 16,24 );
1915 uint32_t : MOS_BITFIELD_RANGE( 25,31 );
1916 };
1917 struct
1918 {
1919 uint32_t Value;
1920 };
1921 } DW30;
1922
1923 // DW31
1924 union
1925 {
1926 struct
1927 {
1928 uint32_t Intra16x16ModeMask : MOS_BITFIELD_RANGE( 0, 3 );
1929 uint32_t IntraChromaModeMask : MOS_BITFIELD_RANGE( 4, 7 );
1930 uint32_t IntraComputeType : MOS_BITFIELD_RANGE( 8, 9 );
1931 uint32_t : MOS_BITFIELD_RANGE( 10,31 );
1932 };
1933 struct
1934 {
1935 uint32_t Value;
1936 };
1937 } DW31;
1938 } SPDelta;
1939
1940 // DW32
1941 union
1942 {
1943 struct
1944 {
1945 uint32_t SkipVal : MOS_BITFIELD_RANGE( 0,15 );
1946 uint32_t MultiPredL0Disable : MOS_BITFIELD_RANGE( 16,23 );
1947 uint32_t MultiPredL1Disable : MOS_BITFIELD_RANGE( 24,31 );
1948 };
1949 struct
1950 {
1951 uint32_t Value;
1952 };
1953 } DW32;
1954
1955 // DW33
1956 union
1957 {
1958 struct
1959 {
1960 uint32_t Intra16x16NonDCPredPenalty : MOS_BITFIELD_RANGE( 0,7 );
1961 uint32_t Intra8x8NonDCPredPenalty : MOS_BITFIELD_RANGE( 8,15 );
1962 uint32_t Intra4x4NonDCPredPenalty : MOS_BITFIELD_RANGE( 16,23 );
1963 uint32_t : MOS_BITFIELD_RANGE( 24,31 );
1964 };
1965 struct
1966 {
1967 uint32_t Value;
1968 };
1969 } DW33;
1970
1971 // DW34
1972 union
1973 {
1974 struct
1975 {
1976 uint32_t List0RefID0FieldParity : MOS_BITFIELD_BIT( 0 );
1977 uint32_t List0RefID1FieldParity : MOS_BITFIELD_BIT( 1 );
1978 uint32_t List0RefID2FieldParity : MOS_BITFIELD_BIT( 2 );
1979 uint32_t List0RefID3FieldParity : MOS_BITFIELD_BIT( 3 );
1980 uint32_t List0RefID4FieldParity : MOS_BITFIELD_BIT( 4 );
1981 uint32_t List0RefID5FieldParity : MOS_BITFIELD_BIT( 5 );
1982 uint32_t List0RefID6FieldParity : MOS_BITFIELD_BIT( 6 );
1983 uint32_t List0RefID7FieldParity : MOS_BITFIELD_BIT( 7 );
1984 uint32_t List1RefID0FrameFieldFlag : MOS_BITFIELD_BIT( 8 );
1985 uint32_t List1RefID1FrameFieldFlag : MOS_BITFIELD_BIT( 9 );
1986 uint32_t IntraRefreshEn : MOS_BITFIELD_RANGE( 10,11 );
1987 uint32_t ArbitraryNumMbsPerSlice : MOS_BITFIELD_BIT( 12 );
1988 uint32_t ForceNonSkipMbEnable : MOS_BITFIELD_BIT( 13 );
1989 uint32_t DisableEncSkipCheck : MOS_BITFIELD_BIT( 14 );
1990 uint32_t EnableDirectBiasAdjustment : MOS_BITFIELD_BIT( 15 );
1991 uint32_t EnableGlobalMotionBiasAdjustment: MOS_BITFIELD_BIT( 16 );
1992 uint32_t bForceToSkip : MOS_BITFIELD_BIT( 17 );
1993 uint32_t : MOS_BITFIELD_RANGE( 18,23 );
1994 uint32_t List1RefID0FieldParity : MOS_BITFIELD_BIT( 24 );
1995 uint32_t List1RefID1FieldParity : MOS_BITFIELD_BIT( 25 );
1996 uint32_t MADEnableFlag : MOS_BITFIELD_BIT( 26 );
1997 uint32_t ROIEnableFlag : MOS_BITFIELD_BIT( 27 );
1998 uint32_t EnableMBFlatnessChkOptimization : MOS_BITFIELD_BIT( 28 );
1999 uint32_t bDirectMode : MOS_BITFIELD_BIT( 29 );
2000 uint32_t MBBrcEnable : MOS_BITFIELD_BIT( 30 );
2001 uint32_t bOriginalBff : MOS_BITFIELD_BIT( 31 );
2002 };
2003 struct
2004 {
2005 uint32_t Value;
2006 };
2007 } DW34;
2008
2009 // DW35
2010 union
2011 {
2012 struct
2013 {
2014 uint32_t PanicModeMBThreshold : MOS_BITFIELD_RANGE( 0,15 );
2015 uint32_t SmallMbSizeInWord : MOS_BITFIELD_RANGE( 16,23 );
2016 uint32_t LargeMbSizeInWord : MOS_BITFIELD_RANGE( 24,31 );
2017 };
2018 struct
2019 {
2020 uint32_t Value;
2021 };
2022 } DW35;
2023
2024 // DW36
2025 union
2026 {
2027 struct
2028 {
2029 uint32_t NumRefIdxL0MinusOne : MOS_BITFIELD_RANGE( 0, 7 );
2030 uint32_t HMECombinedExtraSUs : MOS_BITFIELD_RANGE( 8,15 );
2031 uint32_t NumRefIdxL1MinusOne : MOS_BITFIELD_RANGE( 16,23 );
2032 uint32_t : MOS_BITFIELD_RANGE( 24,27 );
2033 uint32_t IsFwdFrameShortTermRef : MOS_BITFIELD_BIT( 28 );
2034 uint32_t CheckAllFractionalEnable : MOS_BITFIELD_BIT( 29 );
2035 uint32_t HMECombineOverlap : MOS_BITFIELD_RANGE( 30,31 );
2036 };
2037 struct
2038 {
2039 uint32_t Value;
2040 };
2041 } DW36;
2042
2043 // DW37
2044 union
2045 {
2046 struct
2047 {
2048 uint32_t SkipModeEn : MOS_BITFIELD_BIT( 0 );
2049 uint32_t AdaptiveEn : MOS_BITFIELD_BIT( 1 );
2050 uint32_t BiMixDis : MOS_BITFIELD_BIT( 2 );
2051 uint32_t : MOS_BITFIELD_RANGE( 3, 4 );
2052 uint32_t EarlyImeSuccessEn : MOS_BITFIELD_BIT( 5 );
2053 uint32_t : MOS_BITFIELD_BIT( 6 );
2054 uint32_t T8x8FlagForInterEn : MOS_BITFIELD_BIT( 7 );
2055 uint32_t : MOS_BITFIELD_RANGE( 8,23 );
2056 uint32_t EarlyImeStop : MOS_BITFIELD_RANGE( 24,31 );
2057 };
2058 struct
2059 {
2060 uint32_t Value;
2061 };
2062 } DW37;
2063
2064 // DW38
2065 union
2066 {
2067 struct
2068 {
2069 uint32_t LenSP : MOS_BITFIELD_RANGE( 0, 7 );
2070 uint32_t MaxNumSU : MOS_BITFIELD_RANGE( 8,15 );
2071 uint32_t RefThreshold : MOS_BITFIELD_RANGE( 16,31 );
2072 };
2073 struct
2074 {
2075 uint32_t Value;
2076 };
2077 } DW38;
2078
2079 // DW39
2080 union
2081 {
2082 struct
2083 {
2084 uint32_t : MOS_BITFIELD_RANGE( 0, 7 );
2085 uint32_t HMERefWindowsCombThreshold : MOS_BITFIELD_RANGE( 8,15 );
2086 uint32_t RefWidth : MOS_BITFIELD_RANGE( 16,23 );
2087 uint32_t RefHeight : MOS_BITFIELD_RANGE( 24,31 );
2088 };
2089 struct
2090 {
2091 uint32_t Value;
2092 };
2093 } DW39;
2094
2095 // DW40
2096 union
2097 {
2098 struct
2099 {
2100 uint32_t DistScaleFactorRefID0List0 : MOS_BITFIELD_RANGE( 0,15 );
2101 uint32_t DistScaleFactorRefID1List0 : MOS_BITFIELD_RANGE( 16,31 );
2102 };
2103 struct
2104 {
2105 uint32_t Value;
2106 };
2107 } DW40;
2108
2109 // DW41
2110 union
2111 {
2112 struct
2113 {
2114 uint32_t DistScaleFactorRefID2List0 : MOS_BITFIELD_RANGE( 0,15 );
2115 uint32_t DistScaleFactorRefID3List0 : MOS_BITFIELD_RANGE( 16,31 );
2116 };
2117 struct
2118 {
2119 uint32_t Value;
2120 };
2121 } DW41;
2122
2123 // DW42
2124 union
2125 {
2126 struct
2127 {
2128 uint32_t DistScaleFactorRefID4List0 : MOS_BITFIELD_RANGE( 0,15 );
2129 uint32_t DistScaleFactorRefID5List0 : MOS_BITFIELD_RANGE( 16,31 );
2130 };
2131 struct
2132 {
2133 uint32_t Value;
2134 };
2135 } DW42;
2136
2137 // DW43
2138 union
2139 {
2140 struct
2141 {
2142 uint32_t DistScaleFactorRefID6List0 : MOS_BITFIELD_RANGE( 0,15 );
2143 uint32_t DistScaleFactorRefID7List0 : MOS_BITFIELD_RANGE( 16,31 );
2144 };
2145 struct
2146 {
2147 uint32_t Value;
2148 };
2149 } DW43;
2150
2151 // DW44
2152 union
2153 {
2154 struct
2155 {
2156 uint32_t ActualQPValueForRefID0List0 : MOS_BITFIELD_RANGE( 0, 7 );
2157 uint32_t ActualQPValueForRefID1List0 : MOS_BITFIELD_RANGE( 8,15 );
2158 uint32_t ActualQPValueForRefID2List0 : MOS_BITFIELD_RANGE( 16,23 );
2159 uint32_t ActualQPValueForRefID3List0 : MOS_BITFIELD_RANGE( 24,31 );
2160 };
2161 struct
2162 {
2163 uint32_t Value;
2164 };
2165 } DW44;
2166
2167 // DW45
2168 union
2169 {
2170 struct
2171 {
2172 uint32_t ActualQPValueForRefID4List0 : MOS_BITFIELD_RANGE( 0, 7 );
2173 uint32_t ActualQPValueForRefID5List0 : MOS_BITFIELD_RANGE( 8,15 );
2174 uint32_t ActualQPValueForRefID6List0 : MOS_BITFIELD_RANGE( 16,23 );
2175 uint32_t ActualQPValueForRefID7List0 : MOS_BITFIELD_RANGE( 24,31 );
2176 };
2177 struct
2178 {
2179 uint32_t Value;
2180 };
2181 } DW45;
2182
2183 // DW46
2184 union
2185 {
2186 struct
2187 {
2188 uint32_t ActualQPValueForRefID0List1 : MOS_BITFIELD_RANGE( 0, 7 );
2189 uint32_t ActualQPValueForRefID1List1 : MOS_BITFIELD_RANGE( 8,15 );
2190 uint32_t RefCost : MOS_BITFIELD_RANGE( 16,31 );
2191 };
2192 struct
2193 {
2194 uint32_t Value;
2195 };
2196 } DW46;
2197
2198 // DW47
2199 union
2200 {
2201 struct
2202 {
2203 uint32_t MbQpReadFactor : MOS_BITFIELD_RANGE( 0, 7 );
2204 uint32_t IntraCostSF : MOS_BITFIELD_RANGE( 8,15 );
2205 uint32_t MaxVmvR : MOS_BITFIELD_RANGE( 16,31 );
2206 };
2207 struct
2208 {
2209 uint32_t Value;
2210 };
2211 } DW47;
2212
2213 //DW48
2214 union
2215 {
2216 struct
2217 {
2218 uint32_t IntraRefreshMBx : MOS_BITFIELD_RANGE( 0, 15 );
2219 uint32_t IntraRefreshUnitInMBMinus1 : MOS_BITFIELD_RANGE( 16,23 );
2220 uint32_t IntraRefreshQPDelta : MOS_BITFIELD_RANGE( 24,31 );
2221 };
2222 struct
2223 {
2224 uint32_t Value;
2225 };
2226 } DW48;
2227
2228 // DW49
2229 union
2230 {
2231 struct
2232 {
2233 uint32_t ROI1_X_left : MOS_BITFIELD_RANGE( 0,15 );
2234 uint32_t ROI1_Y_top : MOS_BITFIELD_RANGE( 16,31 );
2235 };
2236 struct
2237 {
2238 uint32_t Value;
2239 };
2240 } DW49;
2241
2242 // DW50
2243 union
2244 {
2245 struct
2246 {
2247 uint32_t ROI1_X_right : MOS_BITFIELD_RANGE( 0,15 );
2248 uint32_t ROI1_Y_bottom : MOS_BITFIELD_RANGE( 16,31 );
2249 };
2250 struct
2251 {
2252 uint32_t Value;
2253 };
2254 } DW50;
2255
2256 // DW51
2257 union
2258 {
2259 struct
2260 {
2261 uint32_t ROI2_X_left : MOS_BITFIELD_RANGE( 0,15 );
2262 uint32_t ROI2_Y_top : MOS_BITFIELD_RANGE( 16,31 );
2263 };
2264 struct
2265 {
2266 uint32_t Value;
2267 };
2268 } DW51;
2269
2270 // DW52
2271 union
2272 {
2273 struct
2274 {
2275 uint32_t ROI2_X_right : MOS_BITFIELD_RANGE( 0,15 );
2276 uint32_t ROI2_Y_bottom : MOS_BITFIELD_RANGE( 16,31 );
2277 };
2278 struct
2279 {
2280 uint32_t Value;
2281 };
2282 } DW52;
2283
2284 // DW53
2285 union
2286 {
2287 struct
2288 {
2289 uint32_t ROI3_X_left : MOS_BITFIELD_RANGE( 0,15 );
2290 uint32_t ROI3_Y_top : MOS_BITFIELD_RANGE( 16,31 );
2291 };
2292 struct
2293 {
2294 uint32_t Value;
2295 };
2296 } DW53;
2297
2298 // DW54
2299 union
2300 {
2301 struct
2302 {
2303 uint32_t ROI3_X_right : MOS_BITFIELD_RANGE( 0,15 );
2304 uint32_t ROI3_Y_bottom : MOS_BITFIELD_RANGE( 16,31 );
2305 };
2306 struct
2307 {
2308 uint32_t Value;
2309 };
2310 } DW54;
2311
2312 // DW55
2313 union
2314 {
2315 struct
2316 {
2317 uint32_t ROI4_X_left : MOS_BITFIELD_RANGE( 0,15 );
2318 uint32_t ROI4_Y_top : MOS_BITFIELD_RANGE( 16,31 );
2319 };
2320 struct
2321 {
2322 uint32_t Value;
2323 };
2324 } DW55;
2325
2326 // DW56
2327 union
2328 {
2329 struct
2330 {
2331 uint32_t ROI4_X_right : MOS_BITFIELD_RANGE( 0,15 );
2332 uint32_t ROI4_Y_bottom : MOS_BITFIELD_RANGE( 16,31 );
2333 };
2334 struct
2335 {
2336 uint32_t Value;
2337 };
2338 } DW56;
2339
2340 // DW57
2341 union
2342 {
2343 struct
2344 {
2345 uint32_t ROI1_dQpPrimeY : MOS_BITFIELD_RANGE( 0, 7 );
2346 uint32_t ROI2_dQpPrimeY : MOS_BITFIELD_RANGE( 8,15 );
2347 uint32_t ROI3_dQpPrimeY : MOS_BITFIELD_RANGE( 16,23 );
2348 uint32_t ROI4_dQpPrimeY : MOS_BITFIELD_RANGE( 24,31 );
2349 };
2350 struct
2351 {
2352 uint32_t Value;
2353 };
2354 } DW57;
2355
2356 // DW58
2357 union
2358 {
2359 struct
2360 {
2361 uint32_t HMEMVCostScalingFactor : MOS_BITFIELD_RANGE( 0, 7 );
2362 uint32_t Reserved : MOS_BITFIELD_RANGE( 8, 15 );
2363 uint32_t IntraRefreshMBy : MOS_BITFIELD_RANGE( 16, 31 );
2364 };
2365 struct
2366 {
2367 uint32_t Value;
2368 };
2369 } DW58;
2370
2371 // DW59
2372 union
2373 {
2374 struct
2375 {
2376 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
2377 };
2378 struct
2379 {
2380 uint32_t Value;
2381 };
2382 } DW59;
2383
2384 // DW60
2385 union
2386 {
2387 struct
2388 {
2389 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31);
2390 };
2391 struct
2392 {
2393 uint32_t Value;
2394 };
2395 } DW60;
2396
2397 // DW61
2398 union
2399 {
2400 struct
2401 {
2402 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31);
2403 };
2404 struct
2405 {
2406 uint32_t Value;
2407 };
2408 } DW61;
2409
2410 // DW62
2411 union
2412 {
2413 struct
2414 {
2415 uint32_t Reserved : MOS_BITFIELD_RANGE(0, 31);
2416 };
2417 struct
2418 {
2419 uint32_t Value;
2420 };
2421 } DW62;
2422
2423 // DW63
2424 union
2425 {
2426 struct
2427 {
2428 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
2429 };
2430 struct
2431 {
2432 uint32_t Value;
2433 };
2434 } DW63;
2435
2436 // DW64
2437 union
2438 {
2439 struct
2440 {
2441 uint32_t L1ListRef0PictureCodingType : MOS_BITFIELD_RANGE( 0, 1 ); // 0-invalid, 1-TFF, 2-invalid, 3-BFF
2442 uint32_t Reserved : MOS_BITFIELD_RANGE( 2,31 );
2443 };
2444 struct
2445 {
2446 uint32_t Value;
2447 };
2448 } DW64;
2449
2450 // DW65
2451 union
2452 {
2453 struct
2454 {
2455 uint32_t IPCM_QP0 : MOS_BITFIELD_RANGE( 0, 7 );
2456 uint32_t IPCM_QP1 : MOS_BITFIELD_RANGE( 8,15 );
2457 uint32_t IPCM_QP2 : MOS_BITFIELD_RANGE( 16,23 );
2458 uint32_t IPCM_QP3 : MOS_BITFIELD_RANGE( 24,31 );
2459 };
2460 struct
2461 {
2462 uint32_t Value;
2463 };
2464 } DW65;
2465
2466 // DW66
2467 union
2468 {
2469 struct
2470 {
2471 uint32_t IPCM_QP4 : MOS_BITFIELD_RANGE( 0, 7 );
2472 uint32_t Reserved : MOS_BITFIELD_RANGE( 8,15 );
2473 uint32_t IPCM_Thresh0 : MOS_BITFIELD_RANGE( 16,31 );
2474 };
2475 struct
2476 {
2477 uint32_t Value;
2478 };
2479 } DW66;
2480
2481 // DW67
2482 union
2483 {
2484 struct
2485 {
2486 uint32_t IPCM_Thresh1 : MOS_BITFIELD_RANGE( 0,15 );
2487 uint32_t IPCM_Thresh2 : MOS_BITFIELD_RANGE( 16,31 );
2488 };
2489 struct
2490 {
2491 uint32_t Value;
2492 };
2493 } DW67;
2494
2495 // DW68
2496 union
2497 {
2498 struct
2499 {
2500 uint32_t IPCM_Thresh3 : MOS_BITFIELD_RANGE( 0,15 );
2501 uint32_t IPCM_Thresh4 : MOS_BITFIELD_RANGE( 16,31 );
2502 };
2503 struct
2504 {
2505 uint32_t Value;
2506 };
2507 } DW68;
2508
2509 // DW69
2510 union
2511 {
2512 struct
2513 {
2514 uint32_t BottomFieldOffsetL1ListRef0MV : MOS_BITFIELD_RANGE( 0,31 );
2515 };
2516 struct
2517 {
2518 uint32_t Value;
2519 };
2520 } DW69;
2521
2522 // DW70
2523 union
2524 {
2525 struct
2526 {
2527 uint32_t BottomFieldOffsetL1ListRef0MBCode : MOS_BITFIELD_RANGE( 0,31 );
2528 };
2529 struct
2530 {
2531 uint32_t Value;
2532 };
2533 } DW70;
2534
2535 // DW71
2536 union
2537 {
2538 struct
2539 {
2540 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
2541 };
2542 struct
2543 {
2544 uint32_t Value;
2545 };
2546 } DW71;
2547
2548 // DW72
2549 union
2550 {
2551 struct
2552 {
2553 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
2554 };
2555 struct
2556 {
2557 uint32_t Value;
2558 };
2559 } DW72;
2560
2561 // DW73
2562 union
2563 {
2564 struct
2565 {
2566 uint32_t MBDataSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2567 };
2568 struct
2569 {
2570 uint32_t Value;
2571 };
2572 } DW73;
2573
2574 // DW74
2575 union
2576 {
2577 struct
2578 {
2579 uint32_t MVDataSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2580 };
2581 struct
2582 {
2583 uint32_t Value;
2584 };
2585 } DW74;
2586
2587 // DW75
2588 union
2589 {
2590 struct
2591 {
2592 uint32_t IDistSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2593 };
2594 struct
2595 {
2596 uint32_t Value;
2597 };
2598 } DW75;
2599
2600 // DW76
2601 union
2602 {
2603 struct
2604 {
2605 uint32_t SrcYSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2606 };
2607 struct
2608 {
2609 uint32_t Value;
2610 };
2611 } DW76;
2612
2613 // DW77
2614 union
2615 {
2616 struct
2617 {
2618 uint32_t MBSpecificDataSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2619 };
2620 struct
2621 {
2622 uint32_t Value;
2623 };
2624 } DW77;
2625
2626 // DW78
2627 union
2628 {
2629 struct
2630 {
2631 uint32_t AuxVmeOutSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2632 };
2633 struct
2634 {
2635 uint32_t Value;
2636 };
2637 } DW78;
2638
2639 // DW79
2640 union
2641 {
2642 struct
2643 {
2644 uint32_t CurrRefPicSelSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2645 };
2646 struct
2647 {
2648 uint32_t Value;
2649 };
2650 } DW79;
2651
2652 // DW80
2653 union
2654 {
2655 struct
2656 {
2657 uint32_t HMEMVPredFwdBwdSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2658 };
2659 struct
2660 {
2661 uint32_t Value;
2662 };
2663 } DW80;
2664
2665 // DW81
2666 union
2667 {
2668 struct
2669 {
2670 uint32_t HMEDistSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2671 };
2672 struct
2673 {
2674 uint32_t Value;
2675 };
2676 } DW81;
2677
2678 // DW82
2679 union
2680 {
2681 struct
2682 {
2683 uint32_t SliceMapSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2684 };
2685 struct
2686 {
2687 uint32_t Value;
2688 };
2689 } DW82;
2690
2691 // DW83
2692 union
2693 {
2694 struct
2695 {
2696 uint32_t FwdFrmMBDataSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2697 };
2698 struct
2699 {
2700 uint32_t Value;
2701 };
2702 } DW83;
2703
2704 // DW84
2705 union
2706 {
2707 struct
2708 {
2709 uint32_t FwdFrmMVSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2710 };
2711 struct
2712 {
2713 uint32_t Value;
2714 };
2715 } DW84;
2716
2717 // DW85
2718 union
2719 {
2720 struct
2721 {
2722 uint32_t MBQPBuffer : MOS_BITFIELD_RANGE( 0,31 );
2723 };
2724 struct
2725 {
2726 uint32_t Value;
2727 };
2728 } DW85;
2729
2730 // DW86
2731 union
2732 {
2733 struct
2734 {
2735 uint32_t MBBRCLut : MOS_BITFIELD_RANGE( 0,31 );
2736 };
2737 struct
2738 {
2739 uint32_t Value;
2740 };
2741 } DW86;
2742
2743 // DW87
2744 union
2745 {
2746 struct
2747 {
2748 uint32_t VMEInterPredictionSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2749 };
2750 struct
2751 {
2752 uint32_t Value;
2753 };
2754 } DW87;
2755
2756 // DW88
2757 union
2758 {
2759 struct
2760 {
2761 uint32_t VMEInterPredictionMRSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2762 };
2763 struct
2764 {
2765 uint32_t Value;
2766 };
2767 } DW88;
2768
2769 // DW89
2770 union
2771 {
2772 struct
2773 {
2774 uint32_t FlatnessChkSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2775 };
2776 struct
2777 {
2778 uint32_t Value;
2779 };
2780 } DW89;
2781
2782 // DW90
2783 union
2784 {
2785 struct
2786 {
2787 uint32_t MADSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2788 };
2789 struct
2790 {
2791 uint32_t Value;
2792 };
2793 } DW90;
2794
2795 // DW91
2796 union
2797 {
2798 struct
2799 {
2800 uint32_t ForceNonSkipMBmapSurface : MOS_BITFIELD_RANGE( 0,31 );
2801 };
2802 struct
2803 {
2804 uint32_t Value;
2805 };
2806 } DW91;
2807
2808 // DW92
2809 union
2810 {
2811 struct
2812 {
2813 uint32_t ReservedIndex : MOS_BITFIELD_RANGE( 0,31 );
2814 };
2815 struct
2816 {
2817 uint32_t Value;
2818 };
2819 } DW92;
2820
2821 // DW93
2822 union
2823 {
2824 struct
2825 {
2826 uint32_t BRCCurbeSurfIndex : MOS_BITFIELD_RANGE( 0,31 );
2827 };
2828 struct
2829 {
2830 uint32_t Value;
2831 };
2832 } DW93;
2833
2834 // DW94
2835 union
2836 {
2837 struct
2838 {
2839 uint32_t StaticDetectionOutputBufferIndex: MOS_BITFIELD_RANGE( 0,31 );
2840 };
2841 struct
2842 {
2843 uint32_t Value;
2844 };
2845 } DW94;
2846
2847 // DW95
2848 union
2849 {
2850 struct
2851 {
2852 uint32_t Reserved : MOS_BITFIELD_RANGE( 0,31 );
2853 };
2854 struct
2855 {
2856 uint32_t Value;
2857 };
2858 } DW95;
2859
2860 } MBENC_CURBE_CM, *PMBENC_CURBE_CM;
2861 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(MBENC_CURBE_CM)) == CodechalEncodeAvcEncG8::m_mbencCurbeSizeInDword);
2862
2863 typedef struct _BRC_BLOCK_COPY_CURBE_CM
2864 {
2865 // uint32_t 0
2866 union
2867 {
2868 struct
2869 {
2870 uint32_t BlockHeight : 16;
2871 uint32_t BufferOffset : 16;
2872 };
2873 struct
2874 {
2875 uint32_t Value;
2876 };
2877 } DW0;
2878
2879 // uint32_t 1
2880 union
2881 {
2882 struct
2883 {
2884 uint32_t SrcSurfaceIndex;
2885 };
2886 struct
2887 {
2888 uint32_t Value;
2889 };
2890 } DW1;
2891
2892 // uint32_t 2
2893 union
2894 {
2895 struct
2896 {
2897 uint32_t DstSurfaceIndex;
2898 };
2899 struct
2900 {
2901 uint32_t Value;
2902 };
2903 } DW2;
2904
2905 // uint64_t PADDING
2906 struct
2907 {
2908 uint32_t Reserved;
2909 } PADDING;
2910 } BRC_BLOCK_COPY_CURBE_CM, *PBRC_BLOCK_COPY_CURBE_CM;
2911 //structure end
2912
2913 //viarables begin
2914 const uint32_t CodechalEncodeAvcEncG8::m_initMBEncCurbeCmNormalIFrame[m_mbencCurbeSizeInDword] =
2915 {
2916 0x00000082, 0x00000000, 0x00003910, 0x00a83000, 0x00000000, 0x28300000, 0x05000000, 0x00000000,
2917 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2918 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2919 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2920 0x80800000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28301000,
2921 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
2922 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2923 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2924 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2925 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2926 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2927 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
2928 };
2929
2930 const uint32_t CodechalEncodeAvcEncG8::m_initMBEncCurbeCmNormalIField[m_mbencCurbeSizeInDword] =
2931 {
2932 0x00000082, 0x00000000, 0x00003910, 0x00a830c0, 0x02000000, 0x28300000, 0x05000000, 0x00000000,
2933 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2934 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2935 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2936 0x80800000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28301000,
2937 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
2938 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2939 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2940 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2941 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2942 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2943 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
2944 };
2945
2946 const uint32_t CodechalEncodeAvcEncG8::m_initMBEncCurbeCmNormalPFrame[m_mbencCurbeSizeInDword] =
2947 {
2948 0x000000a3, 0x00000008, 0x00003910, 0x00ae3000, 0x30000000, 0x28300000, 0x05000000, 0x01400060,
2949 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2950 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2951 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2952 0x80010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x60000000, 0x000000a1, 0x00003900, 0x28301000,
2953 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000002,
2954 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2955 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2956 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2957 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2958 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2959 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
2960 };
2961
2962 const uint32_t CodechalEncodeAvcEncG8::m_initMBEncCurbeCmNormalPField[m_mbencCurbeSizeInDword] =
2963 {
2964 0x000000a3, 0x00000008, 0x00003910, 0x00ae30c0, 0x30000000, 0x28300000, 0x05000000, 0x01400060,
2965 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2966 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2967 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2968 0x80010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x000000a1, 0x00003900, 0x28301000,
2969 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x04000002,
2970 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2971 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2972 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2973 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2974 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2975 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
2976 };
2977
2978 const uint32_t CodechalEncodeAvcEncG8:: m_initMBEncCurbeCmNormalBFrame[m_mbencCurbeSizeInDword] =
2979 {
2980 0x000000a3, 0x00200008, 0x00003910, 0x00aa7700, 0x50020000, 0x20200000, 0x05000000, 0xff400000,
2981 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2982 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2983 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2984 0x01010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x60000000, 0x000000a1, 0x00003900, 0x28301000,
2985 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000002,
2986 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2987 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2988 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2989 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2990 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2991 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
2992 };
2993
2994 const uint32_t CodechalEncodeAvcEncG8:: m_initMBEncCurbeCmNormalBField[m_mbencCurbeSizeInDword] =
2995 {
2996 0x000000a3, 0x00200008, 0x00003919, 0x00aa77c0, 0x50020000, 0x20200000, 0x05000000, 0xff400000,
2997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2998 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2999 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3000 0x01010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x000000a1, 0x00003900, 0x28301000,
3001 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x04000002,
3002 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3003 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3004 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3005 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
3006 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
3007 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
3008 };
3009
3010 // AVC I_DIST CURBE init data for G8 CM Kernel
3011 const uint32_t CodechalEncodeAvcEncG8::m_initMBEncCurbeCmIFrameDist[m_mbencCurbeSizeInDword] =
3012 {
3013 0x00000082, 0x00200008, 0x001e3910, 0x00a83000, 0x90000000, 0x28300000, 0x00000000, 0x00000000,
3014 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00000000, 0x00000000,
3015 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3016 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
3017 0x80800000, 0x00000000, 0x00000800, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28300000,
3018 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3019 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3020 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3021 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3022 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
3023 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
3024 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
3025 };
3026
3027 // AVC ME CURBE init data for G8 CM Kernel
3028 const uint32_t CodechalEncodeAvcEncG8::m_initMeCurbeCm[39] =
3029 {
3030 0x00000000, 0x00200010, 0x00003939, 0x77a43000, 0x00000000, 0x28300000, 0x00000000, 0x00000000,
3031 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3032 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3033 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3034 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
3035 };
3036
3037 const int32_t CodechalEncodeAvcEncG8::m_brcBtCounts[CODECHAL_ENCODE_BRC_IDX_NUM] = {
3038 CODECHAL_ENCODE_AVC_BRC_INIT_RESET_NUM_SURFACES,
3039 BRC_UPDATE_NUM_SURFACES,
3040 CODECHAL_ENCODE_AVC_BRC_INIT_RESET_NUM_SURFACES,
3041 MBENC_NUM_SURFACES_CM,
3042 CODECHAL_ENCODE_AVC_BRC_BLOCK_COPY_NUM_SURFACES,
3043 0 // MbBRCUpdate kernel starting GEN9
3044 };
3045
3046 const int32_t CodechalEncodeAvcEncG8::m_brcCurbeSize[CODECHAL_ENCODE_BRC_IDX_NUM] = {
3047 (sizeof(BRC_INIT_RESET_CURBE)),
3048 (sizeof(BRC_UPDATE_CURBE)),
3049 (sizeof(BRC_INIT_RESET_CURBE)),
3050 (sizeof(MBENC_CURBE_CM)),
3051 (sizeof(BRC_BLOCK_COPY_CURBE_CM)),
3052 0 // MbBRCUpdate kernel starting GEN9
3053 };
3054
3055 const uint32_t CodechalEncodeAvcEncG8::m_trellisQuantizationRounding[NUM_TARGET_USAGE_MODES] =
3056 {
3057 0, 6, 0, 0, 0, 0, 0, 0
3058 };
3059
3060 static const CODECHAL_ENCODE_AVC_IPCM_THRESHOLD initIpcmThresholdTable[5] =
3061 {
3062 { 2, 3000 },
3063 { 4, 3600 },
3064 { 6, 5000 },
3065 { 10, 7500 },
3066 { 18, 9000 },
3067 };
3068
3069 static const BRC_INIT_RESET_CURBE initBrcInitResetCurbe =
3070 {
3071 // uint32_t 0
3072 {
3073 {
3074 0
3075 }
3076 },
3077
3078 // uint32_t 1
3079 {
3080 {
3081 0
3082 }
3083 },
3084
3085 // uint32_t 2
3086 {
3087 {
3088 0
3089 }
3090 },
3091
3092 // uint32_t 3
3093 {
3094 {
3095 0
3096 }
3097 },
3098
3099 // uint32_t 4
3100 {
3101 {
3102 0
3103 }
3104 },
3105
3106 // uint32_t 5
3107 {
3108 {
3109 0
3110 }
3111 },
3112
3113 // uint32_t 6
3114 {
3115 {
3116 0
3117 }
3118 },
3119
3120 // uint32_t 7
3121 {
3122 {
3123 0
3124 }
3125 },
3126
3127 // uint32_t 8
3128 {
3129 {
3130 0,
3131 0
3132 }
3133 },
3134
3135 // uint32_t 9
3136 {
3137 {
3138 0,
3139 0
3140 }
3141 },
3142
3143 // uint32_t 10
3144 {
3145 {
3146 0,
3147 0
3148 }
3149 },
3150
3151 // uint32_t 11
3152 {
3153 {
3154 0,
3155 1
3156 }
3157 },
3158
3159 // uint32_t 12
3160 {
3161 {
3162 51,
3163 0
3164 }
3165 },
3166
3167 // uint32_t 13
3168 {
3169 {
3170 40,
3171 60,
3172 80,
3173 120
3174 }
3175 },
3176
3177 // uint32_t 14
3178 {
3179 {
3180 35,
3181 60,
3182 80,
3183 120
3184 }
3185 },
3186
3187 // uint32_t 15
3188 {
3189 {
3190 40,
3191 60,
3192 90,
3193 115
3194 }
3195 },
3196
3197 // uint32_t 16
3198 {
3199 {
3200 0,
3201 0,
3202 0,
3203 0
3204 }
3205 },
3206
3207 // uint32_t 17
3208 {
3209 {
3210 0,
3211 0,
3212 0,
3213 0
3214 }
3215 },
3216
3217 // uint32_t 18
3218 {
3219 {
3220 0,
3221 0,
3222 0,
3223 0
3224 }
3225 },
3226
3227 // uint32_t 19
3228 {
3229 {
3230 0,
3231 0,
3232 0,
3233 0
3234 }
3235 },
3236
3237 // uint32_t 20
3238 {
3239 {
3240 0,
3241 0,
3242 0,
3243 0
3244 }
3245 },
3246
3247 // uint32_t 21
3248 {
3249 {
3250 0,
3251 0,
3252 0,
3253 0
3254 }
3255 },
3256
3257 // uint32_t 22
3258 {
3259 {
3260 0,
3261 0,
3262 0,
3263 0
3264 }
3265 },
3266
3267 // uint32_t 23
3268 {
3269 {
3270 0
3271 }
3272 }
3273 };
3274
3275 static const BRC_UPDATE_CURBE initBrcUpdateCurbe =
3276 {
3277 // uint32_t 0
3278 {
3279 {
3280 0
3281 }
3282 },
3283
3284 // uint32_t 1
3285 {
3286 {
3287 0
3288 }
3289 },
3290
3291 // uint32_t 2
3292 {
3293 {
3294 0
3295 }
3296 },
3297
3298 // uint32_t 3
3299 {
3300 {
3301 10,
3302 50
3303 }
3304 },
3305
3306 // uint32_t 4
3307 {
3308 {
3309 100,
3310 150
3311 }
3312 },
3313
3314 // uint32_t 5
3315 {
3316 {
3317 0,
3318 0,
3319 0,
3320 0
3321 }
3322 },
3323
3324 // uint32_t 6
3325 {
3326 {
3327 0,
3328 0,
3329 0,
3330 0,
3331 0,
3332 0
3333 }
3334 },
3335
3336 // uint32_t 7
3337 {
3338 {
3339 0
3340 }
3341 },
3342
3343 // uint32_t 8
3344 {
3345 {
3346 1,
3347 1,
3348 3,
3349 2
3350 }
3351 },
3352
3353 // uint32_t 9
3354 {
3355 {
3356 1,
3357 40,
3358 5,
3359 5
3360 }
3361 },
3362
3363 // uint32_t 10
3364 {
3365 {
3366 3,
3367 1,
3368 7,
3369 18
3370 }
3371 },
3372
3373 // uint32_t 11
3374 {
3375 {
3376 25,
3377 37,
3378 40,
3379 75
3380 }
3381 },
3382
3383 // uint32_t 12
3384 {
3385 {
3386 97,
3387 103,
3388 125,
3389 160
3390 }
3391 },
3392
3393 // uint32_t 13
3394 {
3395 {
3396 MOS_BITFIELD_VALUE((uint32_t)-3, 8),
3397 MOS_BITFIELD_VALUE((uint32_t)-2, 8),
3398 MOS_BITFIELD_VALUE((uint32_t)-1, 8),
3399 0
3400 }
3401 },
3402
3403 // uint32_t 14
3404 {
3405 {
3406 1,
3407 2,
3408 3,
3409 0xff
3410 }
3411 },
3412
3413 // uint32_t 15
3414 {
3415 {
3416 0,
3417 0,
3418 0,
3419 0
3420 }
3421 },
3422
3423 // uint32_t 16
3424 {
3425 {
3426 0,
3427 0
3428 }
3429 },
3430
3431 // uint32_t 17
3432 {
3433 {
3434 0,
3435 0
3436 }
3437 },
3438
3439 // uint32_t 18
3440 {
3441 {
3442 0,
3443 0
3444 }
3445 },
3446
3447 // uint32_t 19
3448 {
3449 {
3450 0
3451 }
3452 },
3453
3454 // uint32_t 20
3455 {
3456 {
3457 0
3458 }
3459 },
3460
3461 // uint32_t 21
3462 {
3463 {
3464 0
3465 }
3466 },
3467
3468 // uint32_t 22
3469 {
3470 {
3471 0
3472 }
3473 },
3474
3475 // uint32_t 23
3476 {
3477 {
3478 0
3479 }
3480 },
3481 };
3482 //variables end
CodechalEncodeAvcEncG8(CodechalHwInterface * hwInterface,CodechalDebugInterface * debugInterface,PCODECHAL_STANDARD_INFO standardInfo)3483 CodechalEncodeAvcEncG8::CodechalEncodeAvcEncG8(
3484 CodechalHwInterface * hwInterface,
3485 CodechalDebugInterface *debugInterface,
3486 PCODECHAL_STANDARD_INFO standardInfo) : CodechalEncodeAvcEnc(hwInterface, debugInterface, standardInfo)
3487 {
3488 CODECHAL_ENCODE_FUNCTION_ENTER;
3489
3490 m_kernelBase = (uint8_t *)IGCODECKRN_G8;
3491 AddIshSize(m_kuid, m_kernelBase);
3492
3493 m_cmKernelEnable = true;
3494 bBrcSplitEnable = false;
3495 bHighTextureModeCostEnable = false;
3496 m_feiEnable = CodecHalIsFeiEncode(m_codecFunction);
3497
3498 this->pfnGetKernelHeaderAndSize = this->GetKernelHeaderAndSize;
3499
3500 m_needCheckCpEnabled = true;
3501 }
3502
GetKernelHeaderAndSize(void * pvBinary,EncOperation operation,uint32_t krnStateIdx,void * pvKrnHeader,uint32_t * pdwKrnSize)3503 MOS_STATUS CodechalEncodeAvcEncG8::GetKernelHeaderAndSize(
3504 void *pvBinary,
3505 EncOperation operation,
3506 uint32_t krnStateIdx,
3507 void *pvKrnHeader,
3508 uint32_t *pdwKrnSize)
3509 {
3510 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3511
3512 CODECHAL_ENCODE_FUNCTION_ENTER;
3513
3514 CODECHAL_ENCODE_CHK_NULL_RETURN(pvBinary);
3515 CODECHAL_ENCODE_CHK_NULL_RETURN(pvKrnHeader);
3516 CODECHAL_ENCODE_CHK_NULL_RETURN(pdwKrnSize);
3517
3518 auto kernelHeaderTable = (PKERNEL_HEADER_CM)pvBinary;
3519 auto invalidaEntry = &(kernelHeaderTable->AVC_StaticFrameDetection) + 1;
3520 uint32_t nextKrnOffset = *pdwKrnSize;
3521
3522 PCODECHAL_KERNEL_HEADER currKrnHeader = nullptr, nextKrnHeader = nullptr;
3523
3524 if (operation == ENC_SCALING4X)
3525 {
3526 currKrnHeader = &kernelHeaderTable->PLY_DScale_PLY;
3527 }
3528 else if (operation == ENC_SCALING2X)
3529 {
3530 currKrnHeader = &kernelHeaderTable->PLY_2xDScale_PLY;
3531 }
3532 else if (operation == ENC_ME)
3533 {
3534 currKrnHeader = &kernelHeaderTable->AVC_ME_P;
3535 }
3536 else if (operation == ENC_BRC)
3537 {
3538 currKrnHeader = &kernelHeaderTable->InitFrameBRC;
3539 }
3540 else if (operation == ENC_MBENC)
3541 {
3542 currKrnHeader = &kernelHeaderTable->AVCMBEnc_Qlty_I;
3543 }
3544 else if (operation == ENC_MBENC_ADV)
3545 {
3546 currKrnHeader = &kernelHeaderTable->AVCMBEnc_Adv_I;
3547 }
3548 else if (operation == ENC_SFD)
3549 {
3550 currKrnHeader = &kernelHeaderTable->AVC_StaticFrameDetection;
3551 }
3552 else
3553 {
3554 CODECHAL_ENCODE_ASSERTMESSAGE("Unsupported ENC mode requested");
3555 eStatus = MOS_STATUS_INVALID_PARAMETER;
3556 }
3557
3558 if (currKrnHeader == nullptr)
3559 {
3560 eStatus = MOS_STATUS_INVALID_PARAMETER;
3561 return eStatus;
3562 }
3563
3564 currKrnHeader += krnStateIdx;
3565 *((PCODECHAL_KERNEL_HEADER)pvKrnHeader) = *currKrnHeader;
3566
3567 nextKrnHeader = (currKrnHeader + 1);
3568 if (nextKrnHeader < invalidaEntry)
3569 {
3570 nextKrnOffset = nextKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT;
3571 }
3572 *pdwKrnSize = nextKrnOffset - (currKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
3573
3574 return eStatus;
3575 }
3576
~CodechalEncodeAvcEncG8()3577 CodechalEncodeAvcEncG8::~CodechalEncodeAvcEncG8()
3578 {
3579 CODECHAL_ENCODE_FUNCTION_ENTER;
3580 }
3581
InitializeState()3582 MOS_STATUS CodechalEncodeAvcEncG8::InitializeState()
3583 {
3584 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3585 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcEnc::InitializeState());
3586
3587 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
3588 MOS_STATUS regReadStatus;
3589
3590 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3591 regReadStatus = MOS_UserFeature_ReadValue_ID(
3592 nullptr,
3593 __MEDIA_USER_FEATURE_VALUE_AVC_ENCODE_INTRA_REFRESH_QP_THRESHOLD_ID,
3594 &userFeatureData,
3595 m_osInterface->pOsContext);
3596 dwIntraRefreshQpThreshold = (MOS_STATUS_SUCCESS == regReadStatus) ? userFeatureData.i32Data : (CODEC_AVC_NUM_QP - 1);
3597
3598 bWeightedPredictionSupported = false;
3599 m_brcHistoryBufferSize = m_initBrcHistoryBufferSize;
3600 dwBrcConstantSurfaceWidth = m_brcConstantSurfaceWidth;
3601 dwBrcConstantSurfaceHeight = m_brcConstantSurfaceHeight;
3602 bPerMbSFD = false;
3603 m_forceBrcMbStatsEnabled = false;
3604 return eStatus;
3605 }
3606
InitMbBrcConstantDataBuffer(PCODECHAL_ENCODE_AVC_INIT_MBBRC_CONSTANT_DATA_BUFFER_PARAMS params)3607 MOS_STATUS CodechalEncodeAvcEncG8::InitMbBrcConstantDataBuffer(PCODECHAL_ENCODE_AVC_INIT_MBBRC_CONSTANT_DATA_BUFFER_PARAMS params)
3608 {
3609 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3610
3611 CODECHAL_ENCODE_FUNCTION_ENTER;
3612
3613 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3614 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pOsInterface);
3615 CODECHAL_ENCODE_CHK_NULL_RETURN(params->presBrcConstantDataBuffer);
3616
3617 MOS_LOCK_PARAMS lockFlags;
3618 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
3619 lockFlags.WriteOnly = 1;
3620 auto data = (uint32_t*)params->pOsInterface->pfnLockResource(
3621 params->pOsInterface,
3622 params->presBrcConstantDataBuffer,
3623 &lockFlags);
3624 CODECHAL_ENCODE_CHK_NULL_RETURN(data);
3625
3626 // 16 DWs per QP value
3627 uint32_t size = 16 * CODEC_AVC_NUM_QP;
3628 if (params->bPreProcEnable)
3629 {
3630 eStatus = MOS_SecureMemcpy(data, size * sizeof(uint32_t), (void*)PreProcFtqLut_Cm_Common, size * sizeof(uint32_t));
3631 if (eStatus != MOS_STATUS_SUCCESS)
3632 {
3633 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3634 return eStatus;
3635 }
3636 }
3637 else
3638 {
3639 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pPicParams);
3640
3641 uint8_t tableIdx = params->wPictureCodingType - 1;
3642 bool blockBaseSkipEn = params->dwMbEncBlockBasedSkipEn ? true : false;
3643 bool transform8x8ModeFlag = params->pPicParams->transform_8x8_mode_flag ? true : false;
3644
3645 if (tableIdx >= 3)
3646 {
3647 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid input parameter.");
3648 eStatus = MOS_STATUS_INVALID_PARAMETER;
3649 return eStatus;
3650 }
3651
3652 eStatus = MOS_SecureMemcpy(data, size * sizeof(uint32_t), (void*)MBBrcConstantData_Cm_Common[tableIdx], size * sizeof(uint32_t));
3653 if (eStatus != MOS_STATUS_SUCCESS)
3654 {
3655 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3656 return eStatus;
3657 }
3658
3659 auto dataBk = data;
3660 switch (params->wPictureCodingType)
3661 {
3662 case I_TYPE:
3663 for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3664 {
3665 // Writing to DW0 in each sub-array of 16 DWs
3666 if(params->bOldModeCostEnable)
3667 {
3668 *data = (uint32_t)OldIntraModeCost_Cm_Common[qp];
3669 }
3670 data += 16;
3671 }
3672 break;
3673 case P_TYPE:
3674 case B_TYPE:
3675 for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3676 {
3677 if(params->wPictureCodingType == P_TYPE)
3678 {
3679 // Writing to DW3 in each sub-array of 16 DWs
3680 if (params->bSkipBiasAdjustmentEnable)
3681 {
3682 *(data + 3) = (uint32_t)MvCost_PSkipAdjustment_Cm_Common[qp];
3683 }
3684 }
3685
3686 // Writing to DW9 in each sub-array of 16 DWs
3687 if(params->pAvcQCParams && params->pAvcQCParams->NonFTQSkipThresholdLUTInput)
3688 {
3689 *(data + 9) = (uint32_t)CalcSkipVal((params->dwMbEncBlockBasedSkipEn ? true : false),
3690 (transform8x8ModeFlag ? true : false),
3691 (uint16_t)(params->pAvcQCParams->NonFTQSkipThresholdLUT[qp]));
3692 }
3693 else if(params->wPictureCodingType == P_TYPE)
3694 {
3695 *(data + 9) = (uint32_t)SkipVal_P_Common[blockBaseSkipEn][transform8x8ModeFlag][qp];
3696 }
3697 else
3698 {
3699 *(data + 9) = (uint32_t)SkipVal_B_Common[blockBaseSkipEn][transform8x8ModeFlag][qp];
3700 }
3701
3702 // Writing to DW10 in each sub-array of 16 DWs
3703 if (params->bAdaptiveIntraScalingEnable)
3704 {
3705 *(data + 10) = (uint32_t)AdaptiveIntraScalingFactor_Cm_Common[qp];
3706 }
3707 else
3708 {
3709 *(data + 10) = (uint32_t)IntraScalingFactor_Cm_Common[qp];
3710 }
3711 data += 16;
3712 }
3713 break;
3714 default:
3715 break;
3716 }
3717
3718 data = dataBk;
3719 for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3720 {
3721 if(params->pAvcQCParams && params->pAvcQCParams->FTQSkipThresholdLUTInput)
3722 {
3723 *(data + 6) = ((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp])
3724 | (((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp]) << 16)
3725 | (((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp]) << 24);
3726 *(data + 7) = ((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp])
3727 | (((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp]) << 8)
3728 | (((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp]) << 16)
3729 | (((uint32_t)params->pAvcQCParams->FTQSkipThresholdLUT[qp]) << 24);
3730 }
3731
3732 if (params->bEnableKernelTrellis)
3733 {
3734 // Writing uint32_t 11 and uint32_t 12 with Lambda values
3735 *(data + 11) = (uint32_t)params->Lambda[qp][0];
3736 *(data + 12) = (uint32_t)params->Lambda[qp][1];
3737 }
3738 data += 16;
3739 }
3740 }
3741
3742 params->pOsInterface->pfnUnlockResource(
3743 params->pOsInterface,
3744 params->presBrcConstantDataBuffer);
3745
3746 return eStatus;
3747 }
3748
InitKernelStateWP()3749 MOS_STATUS CodechalEncodeAvcEncG8::InitKernelStateWP()
3750 {
3751 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3752
3753 CODECHAL_ENCODE_FUNCTION_ENTER;
3754 CODECHAL_ENCODE_CHK_NULL_RETURN(m_kernelBase);
3755
3756 uint8_t* kernelBinary;
3757 uint32_t kernelSize;
3758
3759 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuid, &kernelBinary, &kernelSize);
3760 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
3761
3762 CODECHAL_KERNEL_HEADER currKrnHeader;
3763 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetKernelHeaderAndSize(
3764 kernelBinary,
3765 ENC_WP,
3766 0,
3767 &currKrnHeader,
3768 &kernelSize));
3769
3770 pWPKernelState= MOS_New(MHW_KERNEL_STATE);
3771 CODECHAL_ENCODE_CHK_NULL_RETURN(pWPKernelState);
3772
3773 auto kernelStatePtr = pWPKernelState;
3774
3775 kernelStatePtr->KernelParams.iBTCount = WP_NUM_SURFACES;
3776 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
3777 kernelStatePtr->KernelParams.iCurbeLength = sizeof(WP_CURBE);
3778 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
3779 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
3780 kernelStatePtr->KernelParams.iIdCount = 1;
3781 kernelStatePtr->KernelParams.iInlineDataLength = 0;
3782 kernelStatePtr->dwCurbeOffset = m_stateHeapInterface->pStateHeapInterface->m_wSizeOfCmdInterfaceDescriptorData;
3783 kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
3784 kernelStatePtr->KernelParams.iSize = kernelSize;
3785 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
3786 m_stateHeapInterface,
3787 kernelStatePtr->KernelParams.iBTCount,
3788 &kernelStatePtr->dwSshSize,
3789 &kernelStatePtr->dwBindingTableSize));
3790
3791 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(m_stateHeapInterface, kernelStatePtr));
3792 return eStatus;
3793 }
3794
GetMbEncKernelStateIdx(CodechalEncodeIdOffsetParams * params,uint32_t * kernelOffset)3795 MOS_STATUS CodechalEncodeAvcEncG8::GetMbEncKernelStateIdx(CodechalEncodeIdOffsetParams* params, uint32_t* kernelOffset)
3796 {
3797 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3798
3799 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3800 CODECHAL_ENCODE_CHK_NULL_RETURN(kernelOffset);
3801
3802 *kernelOffset = MBENC_I_OFFSET_CM;
3803
3804 if (params->EncFunctionType == CODECHAL_MEDIA_STATE_ENC_ADV)
3805 {
3806 *kernelOffset +=
3807 MBENC_TARGET_USAGE_CM * m_mbencNumTargetUsages;
3808 }
3809 else
3810 {
3811 if (params->EncFunctionType == CODECHAL_MEDIA_STATE_ENC_NORMAL)
3812 {
3813 *kernelOffset += MBENC_TARGET_USAGE_CM;
3814 }
3815 else if (params->EncFunctionType == CODECHAL_MEDIA_STATE_ENC_PERFORMANCE)
3816 {
3817 *kernelOffset += MBENC_TARGET_USAGE_CM * 2;
3818 }
3819 }
3820
3821 if (params->wPictureCodingType == P_TYPE)
3822 {
3823 *kernelOffset += MBENC_P_OFFSET_CM;
3824 }
3825 else if (params->wPictureCodingType == B_TYPE)
3826 {
3827 *kernelOffset += MBENC_B_OFFSET_CM;
3828 }
3829
3830 return eStatus;
3831
3832 }
3833
InitBrcConstantBuffer(PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params)3834 MOS_STATUS CodechalEncodeAvcEncG8::InitBrcConstantBuffer(
3835 PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params)
3836 {
3837 CODECHAL_ENCODE_FUNCTION_ENTER;
3838
3839 if (bMultiRefQpEnabled)
3840 {
3841 return InitBrcConstantBufferMultiRefQP(params);
3842 }
3843 else
3844 {
3845 return CodechalEncodeAvcEnc::InitBrcConstantBuffer(params);
3846 }
3847 }
3848
InitBrcConstantBufferMultiRefQP(PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params)3849 MOS_STATUS CodechalEncodeAvcEncG8::InitBrcConstantBufferMultiRefQP(
3850 PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params)
3851 {
3852
3853 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3854
3855 CODECHAL_ENCODE_FUNCTION_ENTER;
3856
3857 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3858 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pOsInterface);
3859 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pPicParams);
3860
3861 uint8_t tableIdx = params->wPictureCodingType - 1;
3862 if(tableIdx >= 3)
3863 {
3864 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid input parameter.");
3865 eStatus = MOS_STATUS_INVALID_PARAMETER;
3866 return eStatus;
3867 }
3868 MOS_LOCK_PARAMS lockFlags;
3869 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
3870 lockFlags.WriteOnly = 1;
3871 auto data = (uint8_t*)params->pOsInterface->pfnLockResource(
3872 params->pOsInterface,
3873 ¶ms->sBrcConstantDataBuffer.OsResource,
3874 &lockFlags);
3875 CODECHAL_ENCODE_CHK_NULL_RETURN(data);
3876
3877 MOS_ZeroMemory(data, params->sBrcConstantDataBuffer.dwWidth * params->sBrcConstantDataBuffer.dwHeight);
3878
3879 // Fill surface with QP Adjustment table, Distortion threshold table, MaxFrame threshold table, Distortion QP Adjustment Table
3880 eStatus = MOS_SecureMemcpy(
3881 data,
3882 sizeof(m_qpDistMaxFrameAdjustmentCm),
3883 (void*)m_qpDistMaxFrameAdjustmentCm,
3884 sizeof(m_qpDistMaxFrameAdjustmentCm));
3885 if(eStatus != MOS_STATUS_SUCCESS)
3886 {
3887 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3888 return eStatus;
3889 }
3890
3891 data += sizeof(m_qpDistMaxFrameAdjustmentCm);
3892 bool blockBaseSkipEn = params->dwMbEncBlockBasedSkipEn ? true : false;
3893 bool transform8x8ModeFlag = params->pPicParams->transform_8x8_mode_flag ? true : false;
3894 // Fill surface with Skip Threshold Table
3895 switch(params->wPictureCodingType)
3896 {
3897 case P_TYPE:
3898 eStatus = MOS_SecureMemcpy(
3899 data,
3900 m_brcConstantSurfaceEarlySkipTableSize,
3901 (void*)&SkipVal_P_Common[blockBaseSkipEn][transform8x8ModeFlag][0],
3902 m_brcConstantSurfaceEarlySkipTableSize);
3903 if(eStatus != MOS_STATUS_SUCCESS)
3904 {
3905 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3906 return eStatus;
3907 }
3908 break;
3909 case B_TYPE:
3910 eStatus = MOS_SecureMemcpy(
3911 data,
3912 m_brcConstantSurfaceEarlySkipTableSize,
3913 (void*)&SkipVal_B_Common[blockBaseSkipEn][transform8x8ModeFlag][0],
3914 m_brcConstantSurfaceEarlySkipTableSize);
3915 if(eStatus != MOS_STATUS_SUCCESS)
3916 {
3917 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3918 return eStatus;
3919 }
3920 break;
3921 default:
3922 // do nothing for I TYPE
3923 break;
3924 }
3925
3926 if((params->wPictureCodingType != I_TYPE) && (params->pAvcQCParams!= nullptr) && (params->pAvcQCParams->NonFTQSkipThresholdLUTInput))
3927 {
3928 for(uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3929 {
3930 *(data+ 1 + (qp * 2)) = (uint8_t) CalcSkipVal((params->dwMbEncBlockBasedSkipEn ? true : false),
3931 (params->pPicParams->transform_8x8_mode_flag ? true : false), (uint16_t)(params->pAvcQCParams->NonFTQSkipThresholdLUT[qp]));
3932 }
3933 }
3934
3935 data += m_brcConstantSurfaceEarlySkipTableSize;
3936
3937 // Fill surface with QP list
3938
3939 // Initialize to -1 (0xff)
3940 MOS_FillMemory(data, m_brcConstantSurfaceQpList0, 0xff);
3941 MOS_FillMemory(data
3942 + m_brcConstantSurfaceQpList0
3943 + m_brcConstantSurfaceQpList0Reserved,
3944 m_brcConstantSurfaceQpList1, 0xff);
3945
3946 switch(params->wPictureCodingType)
3947 {
3948 case B_TYPE:
3949 data += (m_brcConstantSurfaceQpList0 + m_brcConstantSurfaceQpList0Reserved);
3950
3951 for (uint8_t refIdx = 0;refIdx <= params->pAvcSlcParams->num_ref_idx_l1_active_minus1;refIdx++)
3952 {
3953 CODEC_PICTURE refPic = params->pAvcSlcParams->RefPicList[LIST_1][refIdx];
3954 if (!CodecHal_PictureIsInvalid(refPic) && params->pAvcPicIdx[refPic.FrameIdx].bValid)
3955 {
3956 *(data + refIdx) = params->pAvcPicIdx[refPic.FrameIdx].ucPicIdx;
3957 }
3958 }
3959 data -= (m_brcConstantSurfaceQpList0 + m_brcConstantSurfaceQpList0Reserved);
3960 // break statement omitted intentionally
3961 case P_TYPE:
3962 for (uint8_t refIdx = 0;refIdx <= params->pAvcSlcParams->num_ref_idx_l0_active_minus1;refIdx++)
3963 {
3964 CODEC_PICTURE refPic = params->pAvcSlcParams->RefPicList[LIST_0][refIdx];
3965 if (!CodecHal_PictureIsInvalid(refPic) && params->pAvcPicIdx[refPic.FrameIdx].bValid)
3966 {
3967 *(data + refIdx) = params->pAvcPicIdx[refPic.FrameIdx].ucPicIdx;
3968 }
3969 }
3970 break;
3971 default:
3972 // do nothing for I type
3973 break;
3974 }
3975
3976 data += (m_brcConstantSurfaceQpList0 + m_brcConstantSurfaceQpList0Reserved
3977 + m_brcConstantSurfaceQpList1 + m_brcConstantSurfaceQpList1Reserved);
3978
3979 // Fill surface with Mode cost and MV cost
3980 eStatus = MOS_SecureMemcpy(
3981 data,
3982 m_brcConstantSurfacModeMvCostSize,
3983 (void*)ModeMvCost_Cm[tableIdx],
3984 m_brcConstantSurfacModeMvCostSize);
3985 if(eStatus != MOS_STATUS_SUCCESS)
3986 {
3987 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3988 return eStatus;
3989 }
3990
3991 // If old mode cost is used the update the table
3992 if(params->wPictureCodingType == I_TYPE && params->bOldModeCostEnable)
3993 {
3994 auto pdwDataTemp = (uint32_t*) data;
3995 for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3996 {
3997 // Writing to DW0 in each sub-array of 16 DWs
3998 *pdwDataTemp = (uint32_t)OldIntraModeCost_Cm_Common[qp];
3999 pdwDataTemp += 16;
4000 }
4001 }
4002
4003 if(params->pAvcQCParams)
4004 {
4005 for(uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
4006 {
4007 if(params->pAvcQCParams->FTQSkipThresholdLUTInput)
4008 {
4009 *(data + (qp *32) + 24) =
4010 *(data + (qp *32) + 25) =
4011 *(data + (qp *32) + 27) =
4012 *(data + (qp *32) + 28) =
4013 *(data + (qp *32) + 29) =
4014 *(data + (qp *32) + 30) =
4015 *(data + (qp *32) + 31) = params->pAvcQCParams->FTQSkipThresholdLUT[qp];
4016 }
4017 }
4018 }
4019
4020 data += m_brcConstantSurfacModeMvCostSize;
4021
4022 // Fill surface with Refcost
4023 eStatus = MOS_SecureMemcpy(
4024 data,
4025 m_brcConstantSurfaceRefCostSize,
4026 (void*)&RefCost_MultiRefQp[tableIdx][0],
4027 m_brcConstantSurfaceRefCostSize);
4028 if(eStatus != MOS_STATUS_SUCCESS)
4029 {
4030 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
4031 return eStatus;
4032 }
4033 data += m_brcConstantSurfaceRefCostSize;
4034
4035 //Fill surface with Intra cost scaling Factor
4036 if(params->bAdaptiveIntraScalingEnable)
4037 {
4038 eStatus = MOS_SecureMemcpy(
4039 data,
4040 m_brcConstantSurfaceIntraCostScalingFactor,
4041 (void*)&AdaptiveIntraScalingFactor_Cm_Common[0],
4042 m_brcConstantSurfaceIntraCostScalingFactor);
4043 if(eStatus != MOS_STATUS_SUCCESS)
4044 {
4045 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
4046 return eStatus;
4047 }
4048 }
4049 else
4050 {
4051 eStatus = MOS_SecureMemcpy(
4052 data,
4053 m_brcConstantSurfaceIntraCostScalingFactor,
4054 (void*)&IntraScalingFactor_Cm_Common[0],
4055 m_brcConstantSurfaceIntraCostScalingFactor);
4056 if(eStatus != MOS_STATUS_SUCCESS)
4057 {
4058 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
4059 return eStatus;
4060 }
4061 }
4062
4063 params->pOsInterface->pfnUnlockResource(
4064 params->pOsInterface,
4065 ¶ms->sBrcConstantDataBuffer.OsResource);
4066
4067 return eStatus;
4068
4069 }
4070
GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params,PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)4071 MOS_STATUS CodechalEncodeAvcEncG8::GetTrellisQuantization(
4072 PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params,
4073 PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)
4074 {
4075 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4076
4077 CODECHAL_ENCODE_FUNCTION_ENTER;
4078
4079 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
4080 CODECHAL_ENCODE_CHK_NULL_RETURN(trellisQuantParams);
4081
4082 trellisQuantParams->dwTqEnabled = TrellisQuantizationEnable[params->ucTargetUsage];
4083 trellisQuantParams->dwTqRounding =
4084 trellisQuantParams->dwTqEnabled ? m_trellisQuantizationRounding[params->ucTargetUsage] : 0;
4085 // If AdaptiveTrellisQuantization is enabled then disable trellis quantization for
4086 // B-frames with QP > 26 only in CQP mode
4087 if(trellisQuantParams->dwTqEnabled
4088 && EnableAdaptiveTrellisQuantization[params->ucTargetUsage]
4089 && params->wPictureCodingType == B_TYPE
4090 && !params->bBrcEnabled && params->ucQP > 26)
4091 {
4092 trellisQuantParams->dwTqEnabled = 0;
4093 trellisQuantParams->dwTqRounding = 0;
4094 }
4095 return eStatus;
4096
4097 }
4098
InitKernelStateMe()4099 MOS_STATUS CodechalEncodeAvcEncG8::InitKernelStateMe()
4100 {
4101 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4102
4103 CODECHAL_ENCODE_FUNCTION_ENTER;
4104 uint8_t* kernelBinary;
4105 uint32_t kernelSize;
4106
4107 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuid, &kernelBinary, &kernelSize);
4108 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
4109
4110 for (uint32_t krnStateIdx = 0; krnStateIdx < 2; krnStateIdx++)
4111 {
4112 auto kernelStatePtr = &m_meKernelStates[krnStateIdx];
4113
4114 CODECHAL_KERNEL_HEADER currKrnHeader;
4115 CODECHAL_ENCODE_CHK_STATUS_RETURN(pfnGetKernelHeaderAndSize(
4116 kernelBinary,
4117 ENC_ME,
4118 krnStateIdx,
4119 &currKrnHeader,
4120 &kernelSize));
4121
4122 kernelStatePtr->KernelParams.iBTCount = ME_NUM_SURFACES_CM;
4123 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
4124 kernelStatePtr->KernelParams.iCurbeLength = sizeof(ME_CURBE_CM);
4125 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
4126 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
4127 kernelStatePtr->KernelParams.iIdCount = 1;
4128
4129 kernelStatePtr->dwCurbeOffset = m_stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
4130 kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
4131 kernelStatePtr->KernelParams.iSize = kernelSize;
4132 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
4133 m_stateHeapInterface,
4134 kernelStatePtr->KernelParams.iBTCount,
4135 &kernelStatePtr->dwSshSize,
4136 &kernelStatePtr->dwBindingTableSize));
4137
4138 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(m_stateHeapInterface, kernelStatePtr));
4139 }
4140
4141 // Until a better way can be found, maintain old binding table structures
4142 auto bindingTable = &m_meBindingTable;
4143 bindingTable->dwMEMVDataSurface = ME_MV_DATA_SURFACE_CM;
4144 bindingTable->dw16xMEMVDataSurface = ME_16x_MV_DATA_SURFACE_CM;
4145 bindingTable->dw32xMEMVDataSurface = ME_32x_MV_DATA_SURFACE_CM;
4146 bindingTable->dwMEDist = ME_DISTORTION_SURFACE_CM;
4147 bindingTable->dwMEBRCDist = ME_BRC_DISTORTION_CM;
4148 bindingTable->dwMECurrForFwdRef = ME_CURR_FOR_FWD_REF_CM;
4149 bindingTable->dwMEFwdRefPicIdx[0] = ME_FWD_REF_IDX0_CM;
4150 bindingTable->dwMEFwdRefPicIdx[1] = ME_FWD_REF_IDX1_CM;
4151 bindingTable->dwMEFwdRefPicIdx[2] = ME_FWD_REF_IDX2_CM;
4152 bindingTable->dwMEFwdRefPicIdx[3] = ME_FWD_REF_IDX3_CM;
4153 bindingTable->dwMEFwdRefPicIdx[4] = ME_FWD_REF_IDX4_CM;
4154 bindingTable->dwMEFwdRefPicIdx[5] = ME_FWD_REF_IDX5_CM;
4155 bindingTable->dwMEFwdRefPicIdx[6] = ME_FWD_REF_IDX6_CM;
4156 bindingTable->dwMEFwdRefPicIdx[7] = ME_FWD_REF_IDX7_CM;
4157 bindingTable->dwMECurrForBwdRef = ME_CURR_FOR_BWD_REF_CM;
4158 bindingTable->dwMEBwdRefPicIdx[0] = ME_BWD_REF_IDX0_CM;
4159 bindingTable->dwMEBwdRefPicIdx[1] = ME_BWD_REF_IDX1_CM;
4160
4161 return eStatus;
4162 }
4163
InitKernelStateMbEnc()4164 MOS_STATUS CodechalEncodeAvcEncG8::InitKernelStateMbEnc()
4165 {
4166 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4167
4168 CODECHAL_ENCODE_FUNCTION_ENTER;
4169
4170 dwNumMbEncEncKrnStates = MBENC_TARGET_USAGE_CM * m_mbencNumTargetUsagesCm;
4171 dwNumMbEncEncKrnStates += MBENC_TARGET_USAGE_CM;
4172 pMbEncKernelStates =
4173 MOS_NewArray(MHW_KERNEL_STATE, dwNumMbEncEncKrnStates);
4174 CODECHAL_ENCODE_CHK_NULL_RETURN(pMbEncKernelStates);
4175
4176 uint8_t* kernelBinary;
4177 uint32_t kernelSize;
4178
4179 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuid, &kernelBinary, &kernelSize);
4180 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
4181
4182 auto kernelStatePtr = pMbEncKernelStates;
4183 for (uint32_t krnStateIdx = 0; krnStateIdx < dwNumMbEncEncKrnStates; krnStateIdx++)
4184 {
4185 bool kernelState = (krnStateIdx >= MBENC_TARGET_USAGE_CM * m_mbencNumTargetUsagesCm);
4186 CODECHAL_KERNEL_HEADER currKrnHeader;
4187 CODECHAL_ENCODE_CHK_STATUS_RETURN(pfnGetKernelHeaderAndSize(
4188 kernelBinary,
4189 (kernelState ? ENC_MBENC_ADV : ENC_MBENC),
4190 (kernelState ? krnStateIdx - MBENC_TARGET_USAGE_CM * m_mbencNumTargetUsagesCm : krnStateIdx),
4191 &currKrnHeader,
4192 &kernelSize));
4193
4194 kernelStatePtr->KernelParams.iBTCount = MBENC_NUM_SURFACES_CM;
4195 auto renderEngineInterface = m_hwInterface->GetRenderInterface();
4196 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
4197 kernelStatePtr->KernelParams.iCurbeLength = sizeof(MBENC_CURBE_CM);
4198 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
4199 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
4200 kernelStatePtr->KernelParams.iIdCount = 1;
4201
4202 auto stateHeapInterface = m_renderEngineInterface->m_stateHeapInterface;
4203 kernelStatePtr->dwCurbeOffset = stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
4204 kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
4205 kernelStatePtr->KernelParams.iSize = kernelSize;
4206
4207 CODECHAL_ENCODE_CHK_STATUS_RETURN(stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
4208 stateHeapInterface,
4209 kernelStatePtr->KernelParams.iBTCount,
4210 &kernelStatePtr->dwSshSize,
4211 &kernelStatePtr->dwBindingTableSize));
4212
4213 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(stateHeapInterface, kernelStatePtr));
4214
4215 kernelStatePtr++;
4216 }
4217
4218 // Until a better way can be found, maintain old binding table structures
4219 auto bindingTable = &MbEncBindingTable;
4220
4221 bindingTable->dwAvcMBEncMfcAvcPakObj = MBENC_MFC_AVC_PAK_OBJ_CM;
4222 bindingTable->dwAvcMBEncIndMVData = MBENC_IND_MV_DATA_CM;
4223 bindingTable->dwAvcMBEncBRCDist = MBENC_BRC_DISTORTION_CM;
4224 bindingTable->dwAvcMBEncCurrY = MBENC_CURR_Y_CM;
4225 bindingTable->dwAvcMBEncCurrUV = MBENC_CURR_UV_CM;
4226 bindingTable->dwAvcMBEncMbSpecificData = MBENC_MB_SPECIFIC_DATA_CM;
4227
4228 bindingTable->dwAvcMBEncRefPicSelectL0 = MBENC_REFPICSELECT_L0_CM;
4229 bindingTable->dwAvcMBEncMVDataFromME = MBENC_MV_DATA_FROM_ME_CM;
4230 bindingTable->dwAvcMBEncMEDist = MBENC_4xME_DISTORTION_CM;
4231 bindingTable->dwAvcMBEncSliceMapData = MBENC_SLICEMAP_DATA_CM;
4232 bindingTable->dwAvcMBEncBwdRefMBData = MBENC_FWD_MB_DATA_CM;
4233 bindingTable->dwAvcMBEncBwdRefMVData = MBENC_FWD_MV_DATA_CM;
4234 bindingTable->dwAvcMBEncMbBrcConstData = MBENC_MBBRC_CONST_DATA_CM;
4235 bindingTable->dwAvcMBEncFlatnessChk = MBENC_FLATNESS_CHECK_CM;
4236 bindingTable->dwAvcMBEncMADData = MBENC_MAD_DATA_CM;
4237 bindingTable->dwAvcMBEncAdv = MBENC_ADV_WA_DATA_CM;
4238 bindingTable->dwAvcMBEncMbNonSkipMap = MBENC_FORCE_NONSKIP_MB_MAP_CM;
4239 bindingTable->dwAvcMbEncBRCCurbeData = MBENC_BRC_CURBE_DATA_CM;
4240
4241 // Frame
4242 bindingTable->dwAvcMBEncMbQpFrame = MBENC_MBQP_CM;
4243 bindingTable->dwAvcMBEncCurrPicFrame[0] = MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_CM;
4244 bindingTable->dwAvcMBEncFwdPicFrame[0] = MBENC_VME_INTER_PRED_FWD_PIC_IDX0_CM;
4245 bindingTable->dwAvcMBEncBwdPicFrame[0] = MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_CM;
4246 bindingTable->dwAvcMBEncFwdPicFrame[1] = MBENC_VME_INTER_PRED_FWD_PIC_IDX1_CM;
4247 bindingTable->dwAvcMBEncBwdPicFrame[1] = MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_CM;
4248 bindingTable->dwAvcMBEncFwdPicFrame[2] = MBENC_VME_INTER_PRED_FWD_PIC_IDX2_CM;
4249 bindingTable->dwAvcMBEncFwdPicFrame[3] = MBENC_VME_INTER_PRED_FWD_PIC_IDX3_CM;
4250 bindingTable->dwAvcMBEncFwdPicFrame[4] = MBENC_VME_INTER_PRED_FWD_PIC_IDX4_CM;
4251 bindingTable->dwAvcMBEncFwdPicFrame[5] = MBENC_VME_INTER_PRED_FWD_PIC_IDX5_CM;
4252 bindingTable->dwAvcMBEncFwdPicFrame[6] = MBENC_VME_INTER_PRED_FWD_PIC_IDX6_CM;
4253 bindingTable->dwAvcMBEncFwdPicFrame[7] = MBENC_VME_INTER_PRED_FWD_PIC_IDX7_CM;
4254 bindingTable->dwAvcMBEncCurrPicFrame[1] = MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_CM;
4255 bindingTable->dwAvcMBEncBwdPicFrame[2] = MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_CM;
4256 bindingTable->dwAvcMBEncBwdPicFrame[3] = MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_CM;
4257
4258 // Field
4259 bindingTable->dwAvcMBEncMbQpField = MBENC_MBQP_CM;
4260 bindingTable->dwAvcMBEncFieldCurrPic[0] = MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_CM;
4261 bindingTable->dwAvcMBEncFwdPicTopField[0] = MBENC_VME_INTER_PRED_FWD_PIC_IDX0_CM;
4262 bindingTable->dwAvcMBEncBwdPicTopField[0] = MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_CM;
4263 bindingTable->dwAvcMBEncFwdPicBotField[0] = MBENC_VME_INTER_PRED_FWD_PIC_IDX0_CM;
4264 bindingTable->dwAvcMBEncBwdPicBotField[0] = MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_CM;
4265 bindingTable->dwAvcMBEncFwdPicTopField[1] = MBENC_VME_INTER_PRED_FWD_PIC_IDX1_CM;
4266 bindingTable->dwAvcMBEncBwdPicTopField[1] = MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_CM;
4267 bindingTable->dwAvcMBEncFwdPicBotField[1] = MBENC_VME_INTER_PRED_FWD_PIC_IDX1_CM;
4268 bindingTable->dwAvcMBEncBwdPicBotField[1] = MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_CM;
4269 bindingTable->dwAvcMBEncFwdPicTopField[2] = MBENC_VME_INTER_PRED_FWD_PIC_IDX2_CM;
4270 bindingTable->dwAvcMBEncFwdPicBotField[2] = MBENC_VME_INTER_PRED_FWD_PIC_IDX2_CM;
4271 bindingTable->dwAvcMBEncFwdPicTopField[3] = MBENC_VME_INTER_PRED_FWD_PIC_IDX3_CM;
4272 bindingTable->dwAvcMBEncFwdPicBotField[3] = MBENC_VME_INTER_PRED_FWD_PIC_IDX3_CM;
4273 bindingTable->dwAvcMBEncFwdPicTopField[4] = MBENC_VME_INTER_PRED_FWD_PIC_IDX4_CM;
4274 bindingTable->dwAvcMBEncFwdPicBotField[4] = MBENC_VME_INTER_PRED_FWD_PIC_IDX4_CM;
4275 bindingTable->dwAvcMBEncFwdPicTopField[5] = MBENC_VME_INTER_PRED_FWD_PIC_IDX5_CM;
4276 bindingTable->dwAvcMBEncFwdPicBotField[5] = MBENC_VME_INTER_PRED_FWD_PIC_IDX5_CM;
4277 bindingTable->dwAvcMBEncFwdPicTopField[6] = MBENC_VME_INTER_PRED_FWD_PIC_IDX6_CM;
4278 bindingTable->dwAvcMBEncFwdPicBotField[6] = MBENC_VME_INTER_PRED_FWD_PIC_IDX6_CM;
4279 bindingTable->dwAvcMBEncFwdPicTopField[7] = MBENC_VME_INTER_PRED_FWD_PIC_IDX7_CM;
4280 bindingTable->dwAvcMBEncFwdPicBotField[7] = MBENC_VME_INTER_PRED_FWD_PIC_IDX7_CM;
4281 bindingTable->dwAvcMBEncFieldCurrPic[1] = MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_CM;
4282 bindingTable->dwAvcMBEncBwdPicTopField[2] = MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_CM;
4283 bindingTable->dwAvcMBEncBwdPicBotField[2] = MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_CM;
4284 bindingTable->dwAvcMBEncBwdPicTopField[3] = MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_CM;
4285 bindingTable->dwAvcMBEncBwdPicBotField[3] = MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_CM;
4286
4287 return eStatus;
4288 }
4289
SetCurbeAvcWP(PCODECHAL_ENCODE_AVC_WP_CURBE_PARAMS params)4290 MOS_STATUS CodechalEncodeAvcEncG8::SetCurbeAvcWP(PCODECHAL_ENCODE_AVC_WP_CURBE_PARAMS params)
4291 {
4292 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4293
4294 CODECHAL_ENCODE_FUNCTION_ENTER;
4295
4296 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
4297
4298 auto seqParams = m_avcSeqParam;
4299 CODECHAL_ENCODE_ASSERT(seqParams->TargetUsage < NUM_TARGET_USAGE_MODES);
4300
4301 WP_CURBE cmd;
4302 MOS_ZeroMemory(&cmd, sizeof(WP_CURBE));
4303 // Weights[i][j][k][m] is interpreted as:
4304 // i refers to reference picture list 0 or 1
4305 // j refers to reference list entry 0-31;
4306 // k refers to data for the luma (Y) component when it is 0, the Cb chroma component when it is 1 and the Cr chroma component when it is 2;
4307 // m refers to weight when it is 0 and offset when it is 1
4308 //
4309 auto slcParams = m_avcSliceParams;
4310 cmd.DW0.DefaultWeight = slcParams->Weights[params->RefPicListIdx][params->WPIdx][0][0];
4311 cmd.DW0.DefaultOffset = slcParams->Weights[params->RefPicListIdx][params->WPIdx][0][1];
4312
4313 cmd.DW49.Log2WeightDenom = slcParams->luma_log2_weight_denom;
4314 cmd.DW49.ROI_enabled = 0;
4315
4316 cmd.DW50.InputSurface = WP_INPUT_REF_SURFACE;
4317 cmd.DW51.OutputSurface = WP_OUTPUT_SCALED_SURFACE;
4318 auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
4319 auto kernelState = pWPKernelState;
4320 CODECHAL_ENCODE_CHK_STATUS_RETURN(kernelState->m_dshRegion.AddData(
4321 &cmd,
4322 kernelState->dwCurbeOffset,
4323 sizeof(cmd)));
4324
4325 return eStatus;
4326 }
4327
SetCurbeAvcMbEnc(PCODECHAL_ENCODE_AVC_MBENC_CURBE_PARAMS params)4328 MOS_STATUS CodechalEncodeAvcEncG8::SetCurbeAvcMbEnc(
4329 PCODECHAL_ENCODE_AVC_MBENC_CURBE_PARAMS params)
4330 {
4331 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4332
4333 CODECHAL_ENCODE_FUNCTION_ENTER;
4334
4335 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
4336 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pPicParams);
4337 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pSeqParams);
4338 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pSlcParams);
4339 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pdwBlockBasedSkipEn);
4340
4341 auto picParams = params->pPicParams;
4342 auto seqParams = params->pSeqParams;
4343 auto slcParams = params->pSlcParams;
4344
4345 CODECHAL_ENCODE_ASSERT(seqParams->TargetUsage < NUM_TARGET_USAGE_MODES);
4346
4347 // set sliceQp to MAX_SLICE_QP for MbEnc kernel, we can use it to verify whether QP is changed or not
4348 uint8_t sliceQp = (params->bUseMbEncAdvKernel && params->bBrcEnabled) ? CODECHAL_ENCODE_AVC_MAX_SLICE_QP : picParams->pic_init_qp_minus26 + 26 + slcParams->slice_qp_delta;
4349 bool framePicture = CodecHal_PictureIsFrame(picParams->CurrOriginalPic);
4350 bool bottomField = CodecHal_PictureIsBottomField(picParams->CurrOriginalPic);
4351
4352 MBENC_CURBE_CM cmd;
4353 if (params->bMbEncIFrameDistEnabled)
4354 {
4355 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4356 &cmd,
4357 sizeof(MBENC_CURBE_CM),
4358 m_initMBEncCurbeCmIFrameDist,
4359 sizeof(MBENC_CURBE_CM)));
4360 }
4361 else
4362 {
4363 switch (m_pictureCodingType)
4364 {
4365 case I_TYPE:
4366 if (framePicture)
4367 {
4368 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4369 &cmd,
4370 sizeof(MBENC_CURBE_CM),
4371 m_initMBEncCurbeCmNormalIFrame,
4372 sizeof(MBENC_CURBE_CM)));
4373 }
4374 else
4375 {
4376 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4377 &cmd,
4378 sizeof(MBENC_CURBE_CM),
4379 m_initMBEncCurbeCmNormalIField,
4380 sizeof(MBENC_CURBE_CM)));
4381 }
4382 break;
4383
4384 case P_TYPE:
4385 if (framePicture)
4386 {
4387 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4388 &cmd,
4389 sizeof(MBENC_CURBE_CM),
4390 m_initMBEncCurbeCmNormalPFrame,
4391 sizeof(MBENC_CURBE_CM)));
4392 }
4393 else
4394 {
4395 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4396 &cmd,
4397 sizeof(MBENC_CURBE_CM),
4398 m_initMBEncCurbeCmNormalPField,
4399 sizeof(MBENC_CURBE_CM)));
4400 }
4401 break;
4402
4403 case B_TYPE:
4404 if (framePicture)
4405 {
4406 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4407 &cmd,
4408 sizeof(MBENC_CURBE_CM),
4409 m_initMBEncCurbeCmNormalBFrame,
4410 sizeof(MBENC_CURBE_CM)));
4411 }
4412 else
4413 {
4414 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
4415 &cmd,
4416 sizeof(MBENC_CURBE_CM),
4417 m_initMBEncCurbeCmNormalBField,
4418 sizeof(MBENC_CURBE_CM)));
4419 }
4420 break;
4421
4422 default:
4423 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid picture coding type.");
4424 eStatus = MOS_STATUS_UNKNOWN;
4425 return eStatus;
4426 }
4427 }
4428
4429 // r1
4430 cmd.DW0.AdaptiveEn =
4431 cmd.DW37.AdaptiveEn = EnableAdaptiveSearch[seqParams->TargetUsage];
4432 cmd.DW0.T8x8FlagForInterEn =
4433 cmd.DW37.T8x8FlagForInterEn = picParams->transform_8x8_mode_flag;
4434 cmd.DW2.LenSP = MaxLenSP[seqParams->TargetUsage];
4435 cmd.DW38.LenSP = 0; // MBZ
4436 cmd.DW3.SrcAccess =
4437 cmd.DW3.RefAccess = framePicture ? 0 : 1;
4438 if (m_pictureCodingType != I_TYPE && bFTQEnable)
4439 {
4440 if(params->pAvcQCParams && params->pAvcQCParams->FTQOverride)
4441 {
4442 cmd.DW3.FTEnable = params->pAvcQCParams->FTQEnable;
4443 }
4444 else
4445 {
4446 if (m_pictureCodingType == P_TYPE)
4447 {
4448 cmd.DW3.FTEnable = FTQBasedSkip[seqParams->TargetUsage] & 0x01;
4449 }
4450 else // B_TYPE
4451 {
4452 cmd.DW3.FTEnable = (FTQBasedSkip[seqParams->TargetUsage] >> 1) & 0x01;
4453 }
4454 }
4455 }
4456 else
4457 {
4458 cmd.DW3.FTEnable = 0;
4459 }
4460 if (picParams->UserFlags.bDisableSubMBPartition)
4461 {
4462 cmd.DW3.SubMbPartMask = CODECHAL_ENCODE_AVC_DISABLE_4X4_SUB_MB_PARTITION | CODECHAL_ENCODE_AVC_DISABLE_4X8_SUB_MB_PARTITION | CODECHAL_ENCODE_AVC_DISABLE_8X4_SUB_MB_PARTITION;
4463 }
4464 cmd.DW2.PicWidth = params->wPicWidthInMb;
4465 cmd.DW4.PicHeightMinus1 = params->wFieldFrameHeightInMb - 1;
4466 cmd.DW4.EnableIntraCostScalingForStaticFrame = params->bStaticFrameDetectionEnabled;
4467 cmd.DW4.FieldParityFlag = bottomField;
4468 cmd.DW4.bCurFldIDR = !framePicture && (picParams->bIdrPic || m_firstFieldIdrPic);
4469 cmd.DW4.ConstrainedIntraPredFlag = picParams->constrained_intra_pred_flag;
4470 cmd.DW4.HMEEnable = m_hmeEnabled;
4471 cmd.DW4.PictureType = m_pictureCodingType - 1;
4472 cmd.DW4.UseActualRefQPValue = m_hmeEnabled && (MRDisableQPCheck[seqParams->TargetUsage] == 0);
4473 cmd.DW5.SliceMbHeight = params->usSliceHeight;
4474 cmd.DW7.IntraPartMask = picParams->transform_8x8_mode_flag ? 0 : 0x2; // Disable 8x8 if flag is not set
4475 cmd.DW7.SrcFieldPolarity = bottomField;
4476
4477 uint8_t tableIdx;
4478 // r2
4479 if (params->bMbEncIFrameDistEnabled)
4480 {
4481 cmd.DW6.BatchBufferEnd = 0;
4482 }
4483 else
4484 {
4485 tableIdx = m_pictureCodingType - 1;
4486 eStatus = MOS_SecureMemcpy(&(cmd.ModeMvCost), 8 * sizeof(uint32_t), ModeMvCost_Cm[tableIdx][sliceQp], 8 * sizeof(uint32_t));
4487 if (eStatus != MOS_STATUS_SUCCESS)
4488 {
4489 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
4490 return eStatus;
4491 }
4492
4493 if (m_pictureCodingType == I_TYPE && bOldModeCostEnable)
4494 {
4495 // Old intra mode cost needs to be used if bOldModeCostEnable is 1
4496 cmd.ModeMvCost.DW8.Value = OldIntraModeCost_Cm_Common[sliceQp];
4497 }
4498 else if (m_skipBiasAdjustmentEnable)
4499 {
4500 // Load different MvCost for P picture when SkipBiasAdjustment is enabled
4501 // No need to check for P picture as the flag is only enabled for P picture
4502 cmd.ModeMvCost.DW11.Value = MvCost_PSkipAdjustment_Cm_Common[sliceQp];
4503 }
4504 }
4505
4506 if(params->pAvcQCParams && params->pAvcQCParams->FTQSkipThresholdLUTInput)
4507 {
4508 cmd.ModeMvCost.DW14.SICFwdTransCoeffThreshold_0 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4509 cmd.ModeMvCost.DW14.SICFwdTransCoeffThreshold_1 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4510 cmd.ModeMvCost.DW14.SICFwdTransCoeffThreshold_2 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4511 cmd.ModeMvCost.DW15.SICFwdTransCoeffThreshold_3 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4512 cmd.ModeMvCost.DW15.SICFwdTransCoeffThreshold_4 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4513 cmd.ModeMvCost.DW15.SICFwdTransCoeffThreshold_5 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4514 cmd.ModeMvCost.DW15.SICFwdTransCoeffThreshold_6 = params->pAvcQCParams->FTQSkipThresholdLUT[sliceQp];
4515 }
4516
4517 // r3 & r4
4518 if (params->bMbEncIFrameDistEnabled)
4519 {
4520 cmd.SPDelta.DW31.IntraComputeType = 1;
4521 }
4522 else
4523 {
4524 tableIdx = (m_pictureCodingType == B_TYPE) ? 1 : 0;
4525 uint8_t meMethod =
4526 (m_pictureCodingType == B_TYPE) ? m_bMeMethodGeneric[seqParams->TargetUsage] : m_meMethodGeneric[seqParams->TargetUsage];
4527 eStatus = MOS_SecureMemcpy(&(cmd.SPDelta), 16 * sizeof(uint32_t), m_encodeSearchPath[tableIdx][meMethod], 16 * sizeof(uint32_t));
4528 if (eStatus != MOS_STATUS_SUCCESS)
4529 {
4530 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
4531 return eStatus;
4532 }
4533 }
4534
4535 // r5
4536 if(m_pictureCodingType != I_TYPE && params->pAvcQCParams && params->pAvcQCParams->NonFTQSkipThresholdLUTInput)
4537 {
4538 cmd.DW32.SkipVal = (uint16_t) CalcSkipVal(cmd.DW3.BlockBasedSkipEnable, picParams->transform_8x8_mode_flag,
4539 params->pAvcQCParams->NonFTQSkipThresholdLUT[sliceQp]);
4540
4541 }
4542 else
4543 {
4544 if (m_pictureCodingType == P_TYPE)
4545 {
4546 cmd.DW32.SkipVal = SkipVal_P_Common
4547 [cmd.DW3.BlockBasedSkipEnable]
4548 [picParams->transform_8x8_mode_flag]
4549 [sliceQp];
4550 }
4551 else if (m_pictureCodingType == B_TYPE)
4552 {
4553 cmd.DW32.SkipVal = SkipVal_B_Common
4554 [cmd.DW3.BlockBasedSkipEnable]
4555 [picParams->transform_8x8_mode_flag]
4556 [sliceQp];
4557 }
4558 }
4559
4560 cmd.ModeMvCost.DW13.QpPrimeY = sliceQp;
4561 // QpPrimeCb and QpPrimeCr are not used by Kernel. Following settings are for CModel matching.
4562 cmd.ModeMvCost.DW13.QpPrimeCb = sliceQp;
4563 cmd.ModeMvCost.DW13.QpPrimeCr = sliceQp;
4564 cmd.ModeMvCost.DW13.TargetSizeInWord = 0xff; // hardcoded for BRC disabled
4565
4566 if (bMultiPredEnable && (m_pictureCodingType != I_TYPE))
4567 {
4568 switch (MultiPred[seqParams->TargetUsage])
4569 {
4570 case 0: // Disable multipred for both P & B picture types
4571 cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4572 cmd.DW32.MultiPredL1Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4573 break;
4574
4575 case 1: // Enable multipred for P pictures only
4576 cmd.DW32.MultiPredL0Disable = (m_pictureCodingType == P_TYPE) ? CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4577 cmd.DW32.MultiPredL1Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4578 break;
4579
4580 case 2: // Enable multipred for B pictures only
4581 cmd.DW32.MultiPredL0Disable = (m_pictureCodingType == B_TYPE) ?
4582 CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4583 cmd.DW32.MultiPredL1Disable = (m_pictureCodingType == B_TYPE) ?
4584 CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4585 break;
4586
4587 case 3: // Enable multipred for both P & B picture types
4588 cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE;
4589 cmd.DW32.MultiPredL1Disable = (m_pictureCodingType == B_TYPE) ?
4590 CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4591 break;
4592 }
4593 }
4594 else
4595 {
4596 cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4597 cmd.DW32.MultiPredL1Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4598 }
4599
4600 if (!framePicture)
4601 {
4602 if (m_pictureCodingType != I_TYPE)
4603 {
4604 cmd.DW34.List0RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_0);
4605 cmd.DW34.List0RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_1);
4606 cmd.DW34.List0RefID2FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_2);
4607 cmd.DW34.List0RefID3FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_3);
4608 cmd.DW34.List0RefID4FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_4);
4609 cmd.DW34.List0RefID5FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_5);
4610 cmd.DW34.List0RefID6FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_6);
4611 cmd.DW34.List0RefID7FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_7);
4612 }
4613 if (m_pictureCodingType == B_TYPE)
4614 {
4615 cmd.DW34.List1RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_0);
4616 cmd.DW34.List1RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_1);
4617 }
4618 }
4619
4620 if (m_pictureCodingType == B_TYPE)
4621 {
4622 cmd.DW34.List1RefID0FrameFieldFlag = GetRefPicFieldFlag(params, LIST_1, CODECHAL_ENCODE_REF_ID_0);
4623 cmd.DW34.List1RefID1FrameFieldFlag = GetRefPicFieldFlag(params, LIST_1, CODECHAL_ENCODE_REF_ID_1);
4624 cmd.DW34.bDirectMode = slcParams->direct_spatial_mv_pred_flag;
4625 }
4626 cmd.DW34.bOriginalBff = framePicture ? 0 :
4627 ((m_firstField && (bottomField)) || (!m_firstField && (!bottomField)));
4628 cmd.DW34.EnableMBFlatnessChkOptimization = m_flatnessCheckEnabled;
4629 cmd.DW34.ROIEnableFlag = params->bRoiEnabled;
4630 cmd.DW34.MADEnableFlag = m_madEnabled;
4631 cmd.DW34.MBBrcEnable = bMbBrcEnabled || bMbQpDataEnabled;
4632 cmd.DW34.ArbitraryNumMbsPerSlice = m_arbitraryNumMbsInSlice;
4633 cmd.DW34.ForceNonSkipMbEnable = params->bMbDisableSkipMapEnabled;
4634 if(params->pAvcQCParams && !cmd.DW34.ForceNonSkipMbEnable) // ignore DisableEncSkipCheck if Mb Disable Skip Map is available
4635 {
4636 cmd.DW34.DisableEncSkipCheck = params->pAvcQCParams->skipCheckDisable;
4637 }
4638 cmd.DW36.CheckAllFractionalEnable = bCAFEnable;
4639 cmd.DW38.RefThreshold = m_refThreshold;
4640 cmd.DW39.HMERefWindowsCombThreshold = (m_pictureCodingType == B_TYPE) ?
4641 HMEBCombineLen[seqParams->TargetUsage] : HMECombineLen[seqParams->TargetUsage];
4642
4643 // Default:2 used for MBBRC (MB QP Surface width and height are 4x downscaled picture in MB unit * 4 bytes)
4644 // 0 used for MBQP data surface (MB QP Surface width and height are same as the input picture size in MB unit * 1bytes)
4645 cmd.DW47.MbQpReadFactor = bMbQpDataEnabled ? 0 : 2;
4646
4647 // Those fields are not really used for I_dist kernel,
4648 // but set them to 0 to get bit-exact match with kernel prototype
4649 if (params->bMbEncIFrameDistEnabled)
4650 {
4651 cmd.ModeMvCost.DW13.QpPrimeY = 0;
4652 cmd.ModeMvCost.DW13.QpPrimeCb = 0;
4653 cmd.ModeMvCost.DW13.QpPrimeCr = 0;
4654 cmd.DW33.Intra16x16NonDCPredPenalty = 0;
4655 cmd.DW33.Intra4x4NonDCPredPenalty = 0;
4656 cmd.DW33.Intra8x8NonDCPredPenalty = 0;
4657 }
4658
4659 //r6
4660 if (cmd.DW4.UseActualRefQPValue)
4661 {
4662 cmd.DW44.ActualQPValueForRefID0List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_0);
4663 cmd.DW44.ActualQPValueForRefID1List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_1);
4664 cmd.DW44.ActualQPValueForRefID2List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_2);
4665 cmd.DW44.ActualQPValueForRefID3List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_3);
4666 cmd.DW45.ActualQPValueForRefID4List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_4);
4667 cmd.DW45.ActualQPValueForRefID5List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_5);
4668 cmd.DW45.ActualQPValueForRefID6List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_6);
4669 cmd.DW45.ActualQPValueForRefID7List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_7);
4670 cmd.DW46.ActualQPValueForRefID0List1 = AVCGetQPValueFromRefList(params, LIST_1, CODECHAL_ENCODE_REF_ID_0);
4671 cmd.DW46.ActualQPValueForRefID1List1 = AVCGetQPValueFromRefList(params, LIST_1, CODECHAL_ENCODE_REF_ID_1);
4672 }
4673
4674 tableIdx = m_pictureCodingType - 1;
4675 cmd.DW46.RefCost = RefCost_MultiRefQp[tableIdx][sliceQp];
4676
4677 // Picture Coding Type dependent parameters
4678 if (m_pictureCodingType == I_TYPE)
4679 {
4680 cmd.DW0.SkipModeEn = 0;
4681 cmd.DW37.SkipModeEn = 0;
4682 cmd.DW36.HMECombineOverlap = 0;
4683 cmd.DW47.IntraCostSF = 16; // This is not used but recommended to set this to 16 by Kernel team
4684 cmd.DW34.EnableDirectBiasAdjustment = 0;
4685 cmd.DW34.EnableGlobalMotionBiasAdjustment = 0;
4686 }
4687 else if (m_pictureCodingType == P_TYPE)
4688 {
4689 cmd.DW1.MaxNumMVs = GetMaxMvsPer2Mb(seqParams->Level) / 2;
4690 cmd.DW3.BMEDisableFBR = 1;
4691 cmd.DW5.RefWidth = SearchX[seqParams->TargetUsage];
4692 cmd.DW5.RefHeight = SearchY[seqParams->TargetUsage];
4693 cmd.DW7.NonSkipZMvAdded = 1;
4694 cmd.DW7.NonSkipModeAdded = 1;
4695 cmd.DW7.SkipCenterMask = 1;
4696 cmd.DW47.IntraCostSF =
4697 bAdaptiveIntraScalingEnable ?
4698 AdaptiveIntraScalingFactor_Cm_Common[sliceQp] :
4699 IntraScalingFactor_Cm_Common[sliceQp];
4700 cmd.DW47.MaxVmvR = (framePicture) ? CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) * 4 : (CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) >> 1) * 4;
4701 cmd.DW36.HMECombineOverlap = 1;
4702 cmd.DW36.NumRefIdxL0MinusOne = bMultiPredEnable ? slcParams->num_ref_idx_l0_active_minus1 : 0;
4703 cmd.DW39.RefWidth = SearchX[seqParams->TargetUsage];
4704 cmd.DW39.RefHeight = SearchY[seqParams->TargetUsage];
4705 cmd.DW34.EnableDirectBiasAdjustment = 0;
4706 if(params->pAvcQCParams)
4707 {
4708 cmd.DW34.EnableGlobalMotionBiasAdjustment = params->pAvcQCParams->globalMotionBiasAdjustmentEnable;
4709 if(cmd.DW34.EnableGlobalMotionBiasAdjustment)
4710 {
4711 cmd.DW58.HMEMVCostScalingFactor = params->pAvcQCParams->HMEMVCostScalingFactor;
4712 }
4713 }
4714 }
4715 else
4716 {
4717 // B_TYPE
4718 cmd.DW1.MaxNumMVs = GetMaxMvsPer2Mb(seqParams->Level) / 2;
4719 cmd.DW1.BiWeight = m_biWeight;
4720 cmd.DW3.SearchCtrl = 7;
4721 cmd.DW3.SkipType = 1;
4722 cmd.DW5.RefWidth = BSearchX[seqParams->TargetUsage];
4723 cmd.DW5.RefHeight = BSearchY[seqParams->TargetUsage];
4724 cmd.DW7.SkipCenterMask = 0xFF;
4725 cmd.DW47.IntraCostSF =
4726 bAdaptiveIntraScalingEnable ?
4727 AdaptiveIntraScalingFactor_Cm_Common[sliceQp] :
4728 IntraScalingFactor_Cm_Common[sliceQp];
4729 cmd.DW47.MaxVmvR = (framePicture) ? CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) * 4 : (CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) >> 1) * 4;
4730 cmd.DW36.HMECombineOverlap = 1;
4731 // Checking if the forward frame (List 1 index 0) is a short term reference
4732 {
4733 CODEC_PICTURE codecHalPic = params->pSlcParams->RefPicList[LIST_1][0];
4734 if (codecHalPic.PicFlags != PICTURE_INVALID &&
4735 codecHalPic.FrameIdx != CODECHAL_ENCODE_AVC_INVALID_PIC_ID &&
4736 params->pPicIdx[codecHalPic.FrameIdx].bValid)
4737 {
4738 // Although its name is FWD, it actually means the future frame or the backward reference frame
4739 cmd.DW36.IsFwdFrameShortTermRef = CodecHal_PictureIsShortTermRef(params->pPicParams->RefFrameList[codecHalPic.FrameIdx]);
4740 }
4741 else
4742 {
4743 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid backward reference frame.");
4744 eStatus = MOS_STATUS_INVALID_PARAMETER;
4745 return eStatus;
4746 }
4747 }
4748 cmd.DW36.NumRefIdxL0MinusOne = bMultiPredEnable ? slcParams->num_ref_idx_l0_active_minus1 : 0;
4749 cmd.DW36.NumRefIdxL1MinusOne = bMultiPredEnable ? slcParams->num_ref_idx_l1_active_minus1 : 0;
4750 cmd.DW39.RefWidth = BSearchX[seqParams->TargetUsage];
4751 cmd.DW39.RefHeight = BSearchY[seqParams->TargetUsage];
4752 cmd.DW40.DistScaleFactorRefID0List0 = m_distScaleFactorList0[0];
4753 cmd.DW40.DistScaleFactorRefID1List0 = m_distScaleFactorList0[1];
4754 cmd.DW41.DistScaleFactorRefID2List0 = m_distScaleFactorList0[2];
4755 cmd.DW41.DistScaleFactorRefID3List0 = m_distScaleFactorList0[3];
4756 cmd.DW42.DistScaleFactorRefID4List0 = m_distScaleFactorList0[4];
4757 cmd.DW42.DistScaleFactorRefID5List0 = m_distScaleFactorList0[5];
4758 cmd.DW43.DistScaleFactorRefID6List0 = m_distScaleFactorList0[6];
4759 cmd.DW43.DistScaleFactorRefID7List0 = m_distScaleFactorList0[7];
4760
4761 if(params->pAvcQCParams)
4762 {
4763 cmd.DW34.EnableDirectBiasAdjustment = params->pAvcQCParams->directBiasAdjustmentEnable;
4764 if(cmd.DW34.EnableDirectBiasAdjustment)
4765 {
4766 cmd.DW7.NonSkipModeAdded = 1;
4767 cmd.DW7.NonSkipZMvAdded = 1;
4768 }
4769
4770 cmd.DW34.EnableGlobalMotionBiasAdjustment = params->pAvcQCParams->globalMotionBiasAdjustmentEnable;
4771 if(cmd.DW34.EnableGlobalMotionBiasAdjustment)
4772 {
4773 cmd.DW58.HMEMVCostScalingFactor = params->pAvcQCParams->HMEMVCostScalingFactor;
4774 }
4775 }
4776 {
4777 CODEC_PICTURE refPic;
4778 refPic = slcParams->RefPicList[LIST_1][0];
4779 cmd.DW64.L1ListRef0PictureCodingType = m_refList[m_picIdx[refPic.FrameIdx].ucPicIdx]->ucAvcPictureCodingType;
4780 if(framePicture && ((cmd.DW64.L1ListRef0PictureCodingType == CODEC_AVC_PIC_CODING_TYPE_TFF_FIELD) || (cmd.DW64.L1ListRef0PictureCodingType == CODEC_AVC_PIC_CODING_TYPE_BFF_FIELD)))
4781 {
4782 uint16_t fieldHeightInMb = (params->wFieldFrameHeightInMb + 1) >> 1;
4783 cmd.DW69.BottomFieldOffsetL1ListRef0MV = MOS_ALIGN_CEIL(fieldHeightInMb * params->wPicWidthInMb * (32 * 4), 0x1000);
4784 cmd.DW70.BottomFieldOffsetL1ListRef0MBCode = fieldHeightInMb * params->wPicWidthInMb * 64;
4785 }
4786 }
4787 }
4788
4789 *params->pdwBlockBasedSkipEn = cmd.DW3.BlockBasedSkipEnable;
4790
4791 if (ROLLING_I_SQUARE == picParams->EnableRollingIntraRefresh && !params->bSquareRollingIEnabled)
4792 {
4793 picParams->EnableRollingIntraRefresh = false;
4794 }
4795
4796 if (picParams->EnableRollingIntraRefresh)
4797 {
4798 /* Multiple predictor should be completely disabled for the RollingI feature. This does not lead to much quality drop for P frames especially for TU as 1 */
4799 cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
4800
4801 /* Pass the same IntraRefreshUnit to the kernel w/o the adjustment by -1, so as to have an overlap of one MB row or column of Intra macroblocks
4802 across one P frame to another P frame, as needed by the RollingI algo */
4803 if (ROLLING_I_SQUARE == picParams->EnableRollingIntraRefresh && RATECONTROL_CQP != seqParams->RateControlMethod)
4804 {
4805 /*BRC update kernel updates these CURBE to MBEnc*/
4806 cmd.DW4.EnableIntraRefresh = false;
4807 cmd.DW34.IntraRefreshEn = ROLLING_I_DISABLED;
4808 cmd.DW48.IntraRefreshMBx = 0; /* MB column number */
4809 cmd.DW58.IntraRefreshMBy = 0; /* MB row number */
4810 }
4811 else
4812 {
4813 cmd.DW4.EnableIntraRefresh = true;
4814 cmd.DW34.IntraRefreshEn = picParams->EnableRollingIntraRefresh;
4815 cmd.DW48.IntraRefreshMBx = picParams->IntraRefreshMBx; /* MB column number */
4816 cmd.DW58.IntraRefreshMBy = picParams->IntraRefreshMBy; /* MB row number */
4817 }
4818 cmd.DW48.IntraRefreshUnitInMBMinus1 = picParams->IntraRefreshUnitinMB;
4819 cmd.DW48.IntraRefreshQPDelta = picParams->IntraRefreshQPDelta;
4820 }
4821 else
4822 {
4823 cmd.DW34.IntraRefreshEn = 0;
4824 }
4825
4826 if (true == params->bRoiEnabled)
4827 {
4828 cmd.DW49.ROI1_X_left = picParams->ROI[0].Left;
4829 cmd.DW49.ROI1_Y_top = picParams->ROI[0].Top;
4830 cmd.DW50.ROI1_X_right = picParams->ROI[0].Right;
4831 cmd.DW50.ROI1_Y_bottom = picParams->ROI[0].Bottom;
4832
4833 cmd.DW51.ROI2_X_left = picParams->ROI[1].Left;
4834 cmd.DW51.ROI2_Y_top = picParams->ROI[1].Top;
4835 cmd.DW52.ROI2_X_right = picParams->ROI[1].Right;
4836 cmd.DW52.ROI2_Y_bottom = picParams->ROI[1].Bottom;
4837
4838 cmd.DW53.ROI3_X_left = picParams->ROI[2].Left;
4839 cmd.DW53.ROI3_Y_top = picParams->ROI[2].Top;
4840 cmd.DW54.ROI3_X_right = picParams->ROI[2].Right;
4841 cmd.DW54.ROI3_Y_bottom = picParams->ROI[2].Bottom;
4842
4843 cmd.DW55.ROI4_X_left = picParams->ROI[3].Left;
4844 cmd.DW55.ROI4_Y_top = picParams->ROI[3].Top;
4845 cmd.DW56.ROI4_X_right = picParams->ROI[3].Right;
4846 cmd.DW56.ROI4_Y_bottom = picParams->ROI[3].Bottom;
4847
4848 if ( bBrcEnabled == false)
4849 {
4850 uint16_t numROI = picParams->NumROI;
4851 char priorityLevelOrDQp[CODECHAL_ENCODE_AVC_MAX_ROI_NUMBER] = { 0 };
4852
4853 // cqp case
4854 for (uint32_t i = 0; i < numROI; i += 1)
4855 {
4856 char dQpRoi = picParams->ROI[i].PriorityLevelOrDQp;
4857
4858 // clip qp roi in order to have (qp + qpY) in range [0, 51]
4859 priorityLevelOrDQp[i] = (char)CodecHal_Clip3(-sliceQp, CODECHAL_ENCODE_AVC_MAX_SLICE_QP - sliceQp, dQpRoi);
4860 }
4861
4862 cmd.DW57.ROI1_dQpPrimeY = priorityLevelOrDQp[0];
4863 cmd.DW57.ROI2_dQpPrimeY = priorityLevelOrDQp[1];
4864 cmd.DW57.ROI3_dQpPrimeY = priorityLevelOrDQp[2];
4865 cmd.DW57.ROI4_dQpPrimeY = priorityLevelOrDQp[3];
4866 }
4867 else
4868 {
4869 // kernel does not support BRC case
4870 cmd.DW34.ROIEnableFlag = 0;
4871 }
4872 }
4873 else if( params->bDirtyRoiEnabled )
4874 {
4875 // enable Dirty Rect flag
4876 cmd.DW4.EnableDirtyRect = true;
4877
4878 cmd.DW49.ROI1_X_left = params->pPicParams->DirtyROI[0].Left;
4879 cmd.DW49.ROI1_Y_top = params->pPicParams->DirtyROI[0].Top;
4880 cmd.DW50.ROI1_X_right = params->pPicParams->DirtyROI[0].Right;
4881 cmd.DW50.ROI1_Y_bottom = params->pPicParams->DirtyROI[0].Bottom;
4882
4883 cmd.DW51.ROI2_X_left = params->pPicParams->DirtyROI[1].Left;
4884 cmd.DW51.ROI2_Y_top = params->pPicParams->DirtyROI[1].Top;
4885 cmd.DW52.ROI2_X_right = params->pPicParams->DirtyROI[1].Right;
4886 cmd.DW52.ROI2_Y_bottom = params->pPicParams->DirtyROI[1].Bottom;
4887
4888 cmd.DW53.ROI3_X_left = params->pPicParams->DirtyROI[2].Left;
4889 cmd.DW53.ROI3_Y_top = params->pPicParams->DirtyROI[2].Top;
4890 cmd.DW54.ROI3_X_right = params->pPicParams->DirtyROI[2].Right;
4891 cmd.DW54.ROI3_Y_bottom = params->pPicParams->DirtyROI[2].Bottom;
4892
4893 cmd.DW55.ROI4_X_left = params->pPicParams->DirtyROI[3].Left;
4894 cmd.DW55.ROI4_Y_top = params->pPicParams->DirtyROI[3].Top;
4895 cmd.DW56.ROI4_X_right = params->pPicParams->DirtyROI[3].Right;
4896 cmd.DW56.ROI4_Y_bottom = params->pPicParams->DirtyROI[3].Bottom;
4897 }
4898
4899 //IPCM QP and threshold
4900 cmd.DW65.IPCM_QP0 = initIpcmThresholdTable[0].QP;
4901 cmd.DW65.IPCM_QP1 = initIpcmThresholdTable[1].QP;
4902 cmd.DW65.IPCM_QP2 = initIpcmThresholdTable[2].QP;
4903 cmd.DW65.IPCM_QP3 = initIpcmThresholdTable[3].QP;
4904 cmd.DW66.IPCM_QP4 = initIpcmThresholdTable[4].QP;
4905 cmd.DW66.IPCM_Thresh0 = initIpcmThresholdTable[0].Threshold;
4906 cmd.DW67.IPCM_Thresh1 = initIpcmThresholdTable[1].Threshold;
4907 cmd.DW67.IPCM_Thresh2 = initIpcmThresholdTable[2].Threshold;
4908 cmd.DW68.IPCM_Thresh3 = initIpcmThresholdTable[3].Threshold;
4909 cmd.DW68.IPCM_Thresh4 = initIpcmThresholdTable[4].Threshold;
4910
4911 cmd.DW73.MBDataSurfIndex = MBENC_MFC_AVC_PAK_OBJ_CM;
4912 cmd.DW74.MVDataSurfIndex = MBENC_IND_MV_DATA_CM;
4913 cmd.DW75.IDistSurfIndex = MBENC_BRC_DISTORTION_CM;
4914 cmd.DW76.SrcYSurfIndex = MBENC_CURR_Y_CM;
4915 cmd.DW77.MBSpecificDataSurfIndex = MBENC_MB_SPECIFIC_DATA_CM;
4916 cmd.DW78.AuxVmeOutSurfIndex = MBENC_AUX_VME_OUT_CM;
4917 cmd.DW79.CurrRefPicSelSurfIndex = MBENC_REFPICSELECT_L0_CM;
4918 cmd.DW80.HMEMVPredFwdBwdSurfIndex = MBENC_MV_DATA_FROM_ME_CM;
4919 cmd.DW81.HMEDistSurfIndex = MBENC_4xME_DISTORTION_CM;
4920 // NNDOTO: DW68 works for SKL too as recpicselectl0 and slicemap both have BTI 10,
4921 // this comment can be removed once SKL kernels are upto date with all BDW kernel features
4922 cmd.DW82.SliceMapSurfIndex = MBENC_SLICEMAP_DATA_CM;
4923 cmd.DW83.FwdFrmMBDataSurfIndex = MBENC_FWD_MB_DATA_CM;
4924 cmd.DW84.FwdFrmMVSurfIndex = MBENC_FWD_MV_DATA_CM;
4925 cmd.DW85.MBQPBuffer = MBENC_MBQP_CM;
4926 cmd.DW86.MBBRCLut = MBENC_MBBRC_CONST_DATA_CM;
4927 cmd.DW87.VMEInterPredictionSurfIndex = MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_CM;
4928 cmd.DW88.VMEInterPredictionMRSurfIndex = MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_CM;
4929 cmd.DW89.FlatnessChkSurfIndex = MBENC_FLATNESS_CHECK_CM;
4930 cmd.DW90.MADSurfIndex = MBENC_MAD_DATA_CM;
4931 cmd.DW91.ForceNonSkipMBmapSurface = MBENC_FORCE_NONSKIP_MB_MAP_CM;
4932 cmd.DW92.ReservedIndex = MBENC_ADV_WA_DATA_CM;
4933 cmd.DW93.BRCCurbeSurfIndex = MBENC_BRC_CURBE_DATA_CM;
4934 cmd.DW94.StaticDetectionOutputBufferIndex = MBENC_STATIC_FRAME_DETECTION_OUTPUT_CM;
4935
4936 auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
4937 CODECHAL_ENCODE_CHK_NULL_RETURN(stateHeapInterface);
4938
4939 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
4940 &cmd,
4941 params->pKernelState->dwCurbeOffset,
4942 sizeof(cmd)));
4943
4944 return eStatus;
4945 }
4946
SetCurbeAvcBrcInitReset(PCODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_PARAMS params)4947 MOS_STATUS CodechalEncodeAvcEncG8::SetCurbeAvcBrcInitReset(PCODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_PARAMS params)
4948 {
4949
4950 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4951 CODECHAL_ENCODE_FUNCTION_ENTER;
4952 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
4953
4954 auto picParams = m_avcPicParam;
4955 auto seqParams = m_avcSeqParam;
4956 auto vuiParams = m_avcVuiParams;
4957
4958 BRC_INIT_RESET_CURBE cmd = initBrcInitResetCurbe;
4959
4960 uint32_t profileLevelMaxFrame;
4961 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalAvcEncode_GetProfileLevelMaxFrameSize(
4962 seqParams,
4963 this,
4964 &profileLevelMaxFrame));
4965 cmd.DW0.ProfileLevelMaxFrame = profileLevelMaxFrame;
4966 cmd.DW1.InitBufFullInBits = seqParams->InitVBVBufferFullnessInBit;
4967 cmd.DW2.BufSizeInBits = seqParams->VBVBufferSizeInBit;
4968 cmd.DW3.AverageBitRate = seqParams->TargetBitRate;
4969 cmd.DW4.MaxBitRate = seqParams->MaxBitRate;
4970 cmd.DW8.GopP =
4971 (seqParams->GopRefDist) ? ((seqParams->GopPicSize - 1) / seqParams->GopRefDist) : 0;
4972 cmd.DW9.GopB = seqParams->GopPicSize - 1 - cmd.DW8.GopP;
4973 cmd.DW9.FrameWidthInBytes = m_frameWidth;
4974 cmd.DW10.FrameHeightInBytes = m_frameHeight;
4975 cmd.DW12.NoSlices = m_numSlices;
4976
4977 // if VUI present, VUI data has high priority
4978 if (seqParams->vui_parameters_present_flag && seqParams->RateControlMethod != RATECONTROL_AVBR)
4979 {
4980 cmd.DW4.MaxBitRate =
4981 ((vuiParams->bit_rate_value_minus1[0] + 1) << (6 + vuiParams->bit_rate_scale));
4982
4983 if (seqParams->RateControlMethod == RATECONTROL_CBR)
4984 {
4985 cmd.DW3.AverageBitRate = cmd.DW4.MaxBitRate;
4986 }
4987 }
4988
4989 cmd.DW6.FrameRateM = seqParams->FramesPer100Sec;
4990 cmd.DW7.FrameRateD = 100;
4991 cmd.DW8.BRCFlag = (CodecHal_PictureIsFrame(m_currOriginalPic)) ? 0 : CODECHAL_ENCODE_BRCINIT_FIELD_PIC;
4992 // MBBRC should be skipped when BRC ROI is on
4993 cmd.DW8.BRCFlag |= ( bMbBrcEnabled && ! bBrcRoiEnabled) ? 0 : CODECHAL_ENCODE_BRCINIT_DISABLE_MBBRC;
4994
4995 if (seqParams->RateControlMethod == RATECONTROL_CBR)
4996 {
4997 cmd.DW4.MaxBitRate = cmd.DW3.AverageBitRate;
4998 cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISCBR;
4999 }
5000 else if (seqParams->RateControlMethod == RATECONTROL_VBR)
5001 {
5002 if (cmd.DW4.MaxBitRate < cmd.DW3.AverageBitRate)
5003 {
5004 cmd.DW3.AverageBitRate = cmd.DW4.MaxBitRate; // Use max bit rate for HRD compliance
5005 }
5006 cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISVBR;
5007 }
5008 else if (seqParams->RateControlMethod == RATECONTROL_AVBR)
5009 {
5010 cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISAVBR;
5011 // For AVBR, max bitrate = target bitrate,
5012 cmd.DW4.MaxBitRate = cmd.DW3.AverageBitRate;
5013 }
5014 else if (seqParams->RateControlMethod == RATECONTROL_ICQ)
5015 {
5016 cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISICQ;
5017 cmd.DW23.ACQP = seqParams->ICQQualityFactor;
5018 }
5019 else if (seqParams->RateControlMethod == RATECONTROL_VCM)
5020 {
5021 cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISVCM;
5022 }
5023 else if (seqParams->RateControlMethod == RATECONTROL_QVBR)
5024 {
5025 if (cmd.DW4.MaxBitRate < cmd.DW3.AverageBitRate)
5026 {
5027 cmd.DW3.AverageBitRate = cmd.DW4.MaxBitRate; // Use max bit rate for HRD compliance
5028 }
5029 cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISQVBR;
5030 // use ICQQualityFactor to determine the larger Qp for each MB
5031 cmd.DW23.ACQP = seqParams->ICQQualityFactor;
5032 }
5033
5034 cmd.DW10.AVBRAccuracy = usAVBRAccuracy;
5035 cmd.DW11.AVBRConvergence = usAVBRConvergence;
5036
5037 // Set dynamic thresholds
5038 double inputBitsPerFrame =
5039 ((double)(cmd.DW4.MaxBitRate) * (double)(cmd.DW7.FrameRateD) /
5040 (double)(cmd.DW6.FrameRateM));
5041 if (CodecHal_PictureIsField(m_currOriginalPic))
5042 {
5043 inputBitsPerFrame *= 0.5;
5044 }
5045
5046 if (cmd.DW2.BufSizeInBits == 0)
5047 {
5048 cmd.DW2.BufSizeInBits = (uint32_t)inputBitsPerFrame * 4;
5049 }
5050
5051 if (cmd.DW1.InitBufFullInBits == 0)
5052 {
5053 cmd.DW1.InitBufFullInBits = 7 * cmd.DW2.BufSizeInBits / 8;
5054 }
5055 if (cmd.DW1.InitBufFullInBits < (uint32_t)(inputBitsPerFrame * 2))
5056 {
5057 cmd.DW1.InitBufFullInBits = (uint32_t)(inputBitsPerFrame * 2);
5058 }
5059 if (cmd.DW1.InitBufFullInBits > cmd.DW2.BufSizeInBits)
5060 {
5061 cmd.DW1.InitBufFullInBits = cmd.DW2.BufSizeInBits;
5062 }
5063
5064 if (seqParams->RateControlMethod == RATECONTROL_AVBR)
5065 {
5066 // For AVBR, Buffer size = 2*Bitrate, InitVBV = 0.75 * BufferSize
5067 cmd.DW2.BufSizeInBits = 2 * seqParams->TargetBitRate;
5068 cmd.DW1.InitBufFullInBits = (uint32_t)(0.75 * cmd.DW2.BufSizeInBits);
5069 }
5070
5071 double bpsRatio = inputBitsPerFrame / ((double)(cmd.DW2.BufSizeInBits) / 30);
5072 bpsRatio = (bpsRatio < 0.1) ? 0.1 : (bpsRatio > 3.5) ? 3.5 : bpsRatio;
5073
5074 cmd.DW16.DeviationThreshold0ForPandB = (uint32_t)(-50 * pow(0.90, bpsRatio));
5075 cmd.DW16.DeviationThreshold1ForPandB = (uint32_t)(-50 * pow(0.66, bpsRatio));
5076 cmd.DW16.DeviationThreshold2ForPandB = (uint32_t)(-50 * pow(0.46, bpsRatio));
5077 cmd.DW16.DeviationThreshold3ForPandB = (uint32_t)(-50 * pow(0.3, bpsRatio));
5078 cmd.DW17.DeviationThreshold4ForPandB = (uint32_t)(50 * pow(0.3, bpsRatio));
5079 cmd.DW17.DeviationThreshold5ForPandB = (uint32_t)(50 * pow(0.46, bpsRatio));
5080 cmd.DW17.DeviationThreshold6ForPandB = (uint32_t)(50 * pow(0.7, bpsRatio));
5081 cmd.DW17.DeviationThreshold7ForPandB = (uint32_t)(50 * pow(0.9, bpsRatio));
5082 cmd.DW18.DeviationThreshold0ForVBR = (uint32_t)(-50 * pow(0.9, bpsRatio));
5083 cmd.DW18.DeviationThreshold1ForVBR = (uint32_t)(-50 * pow(0.7, bpsRatio));
5084 cmd.DW18.DeviationThreshold2ForVBR = (uint32_t)(-50 * pow(0.5, bpsRatio));
5085 cmd.DW18.DeviationThreshold3ForVBR = (uint32_t)(-50 * pow(0.3, bpsRatio));
5086 cmd.DW19.DeviationThreshold4ForVBR = (uint32_t)(100 * pow(0.4, bpsRatio));
5087 cmd.DW19.DeviationThreshold5ForVBR = (uint32_t)(100 * pow(0.5, bpsRatio));
5088 cmd.DW19.DeviationThreshold6ForVBR = (uint32_t)(100 * pow(0.75, bpsRatio));
5089 cmd.DW19.DeviationThreshold7ForVBR = (uint32_t)(100 * pow(0.9, bpsRatio));
5090 cmd.DW20.DeviationThreshold0ForI = (uint32_t)(-50 * pow(0.8, bpsRatio));
5091 cmd.DW20.DeviationThreshold1ForI = (uint32_t)(-50 * pow(0.6, bpsRatio));
5092 cmd.DW20.DeviationThreshold2ForI = (uint32_t)(-50 * pow(0.34, bpsRatio));
5093 cmd.DW20.DeviationThreshold3ForI = (uint32_t)(-50 * pow(0.2, bpsRatio));
5094 cmd.DW21.DeviationThreshold4ForI = (uint32_t)(50 * pow(0.2, bpsRatio));
5095 cmd.DW21.DeviationThreshold5ForI = (uint32_t)(50 * pow(0.4, bpsRatio));
5096 cmd.DW21.DeviationThreshold6ForI = (uint32_t)(50 * pow(0.66, bpsRatio));
5097 cmd.DW21.DeviationThreshold7ForI = (uint32_t)(50 * pow(0.9, bpsRatio));
5098
5099 cmd.DW22.SlidingWindowSize = dwSlidingWindowSize;
5100
5101 if ( bBrcInit)
5102 {
5103 *params->pdBrcInitCurrentTargetBufFullInBits = cmd.DW1.InitBufFullInBits;
5104 }
5105
5106 *params->pdwBrcInitResetBufSizeInBits = cmd.DW2.BufSizeInBits;
5107 *params->pdBrcInitResetInputBitsPerFrame = inputBitsPerFrame;
5108 auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
5109 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
5110 &cmd,
5111 params->pKernelState->dwCurbeOffset,
5112 sizeof(cmd)));
5113
5114 return eStatus;
5115 }
5116
SetCurbeAvcFrameBrcUpdate(PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params)5117 MOS_STATUS CodechalEncodeAvcEncG8::SetCurbeAvcFrameBrcUpdate(PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params)
5118 {
5119 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5120
5121 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
5122 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
5123 CODECHAL_ENCODE_CHK_NULL_RETURN(m_avcPicParam);
5124
5125 BRC_UPDATE_CURBE cmd = initBrcUpdateCurbe;
5126
5127 cmd.DW5.TargetSizeFlag = 0;
5128 if (*params->pdBrcInitCurrentTargetBufFullInBits > (double)dwBrcInitResetBufSizeInBits)
5129 {
5130 *params->pdBrcInitCurrentTargetBufFullInBits -= (double)dwBrcInitResetBufSizeInBits;
5131 cmd.DW5.TargetSizeFlag = 1;
5132 }
5133
5134 // skipped frame handling
5135 if (params->dwNumSkipFrames)
5136 {
5137 // pass num/size of skipped frames to update BRC
5138 cmd.DW6.NumSkipFrames = params->dwNumSkipFrames;
5139 cmd.DW7.SizeSkipFrames = params->dwSizeSkipFrames;
5140
5141 // account for skipped frame in calculating CurrentTargetBufFullInBits
5142 *params->pdBrcInitCurrentTargetBufFullInBits += dBrcInitResetInputBitsPerFrame * params->dwNumSkipFrames;
5143 }
5144
5145 cmd.DW0.TargetSize = (uint32_t)(*params->pdBrcInitCurrentTargetBufFullInBits);
5146 cmd.DW1.FrameNumber = m_storeData - 1;
5147 cmd.DW2.SizeofPicHeaders = m_headerBytesInserted << 3; // kernel uses how many bits instead of bytes
5148 cmd.DW5.CurrFrameType =
5149 ((m_pictureCodingType - 2) < 0) ? 2 : (m_pictureCodingType - 2);
5150 cmd.DW5.BRCFlag =
5151 (CodecHal_PictureIsTopField(m_currOriginalPic)) ? brcUpdateIsField :
5152 ((CodecHal_PictureIsBottomField(m_currOriginalPic)) ? (brcUpdateIsField | brcUpdateIsBottomField) : 0);
5153 cmd.DW5.BRCFlag |= (m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef) ?
5154 brcUpdateIsReference : 0;
5155
5156 if (bMultiRefQpEnabled)
5157 {
5158 cmd.DW5.BRCFlag |= brcUpdateIsActualQp;
5159 cmd.DW14.QPIndexOfCurPic = m_currOriginalPic.FrameIdx;
5160 }
5161
5162 cmd.DW5.MaxNumPAKs = m_hwInterface->GetMfxInterface()->GetBrcNumPakPasses();
5163
5164 cmd.DW6.MinimumQP = params->ucMinQP;
5165 cmd.DW6.MaximumQP = params->ucMaxQP;
5166 cmd.DW6.EnableForceToSkip = (bForceToSkipEnable && !m_avcPicParam->bDisableFrameSkip);
5167 auto seqParams = m_avcSeqParam;
5168 cmd.DW6.EnableSlidingWindow = (seqParams->FrameSizeTolerance == EFRAMESIZETOL_LOW);
5169
5170 *params->pdBrcInitCurrentTargetBufFullInBits += dBrcInitResetInputBitsPerFrame;
5171
5172 if (seqParams->RateControlMethod == RATECONTROL_AVBR)
5173 {
5174 cmd.DW3.startGAdjFrame0 = (uint32_t)((10 * usAVBRConvergence) / (double)150);
5175 cmd.DW3.startGAdjFrame1 = (uint32_t)((50 * usAVBRConvergence) / (double)150);
5176 cmd.DW4.startGAdjFrame2 = (uint32_t)((100 * usAVBRConvergence) / (double)150);
5177 cmd.DW4.startGAdjFrame3 = (uint32_t)((150 * usAVBRConvergence) / (double)150);
5178 cmd.DW11.gRateRatioThreshold0 =
5179 (uint32_t)((100 - (usAVBRAccuracy / (double)30)*(100 - 40)));
5180 cmd.DW11.gRateRatioThreshold1 =
5181 (uint32_t)((100 - (usAVBRAccuracy / (double)30)*(100 - 75)));
5182 cmd.DW12.gRateRatioThreshold2 = (uint32_t)((100 - (usAVBRAccuracy / (double)30)*(100 - 97)));
5183 cmd.DW12.gRateRatioThreshold3 = (uint32_t)((100 + (usAVBRAccuracy / (double)30)*(103 - 100)));
5184 cmd.DW12.gRateRatioThreshold4 = (uint32_t)((100 + (usAVBRAccuracy / (double)30)*(125 - 100)));
5185 cmd.DW12.gRateRatioThreshold5 = (uint32_t)((100 + (usAVBRAccuracy / (double)30)*(160 - 100)));
5186 }
5187
5188 auto picParams = m_avcPicParam;
5189 //Rolling Intra Refresh
5190 //BRC controls only for square region rolling I, it does not control for others (Row and Column)
5191 if (ROLLING_I_SQUARE == picParams->EnableRollingIntraRefresh && params->bSquareRollingIEnabled)
5192 {
5193 cmd.DW15.IntraRefreshMode = BRC_ROLLING_I_SQUARE;
5194 cmd.DW15.QPIntraRefresh = params->dwIntraRefreshQpThreshold;
5195
5196 //BRC kernel tracks x and y pos
5197 cmd.DW16.IntraRefreshXPos = 0;
5198 cmd.DW16.IntraRefreshYPos = 0;
5199 cmd.DW17.IntraRefreshHeight = picParams->IntraRefreshUnitinMB;
5200 cmd.DW17.IntraRefreshWidth = picParams->IntraRefreshUnitinMB;
5201 }
5202 else
5203 {
5204 cmd.DW15.IntraRefreshMode = BRC_ROLLING_I_DISABLED;
5205 }
5206 uint32_t profileLevelMaxFrame;
5207 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalAvcEncode_GetProfileLevelMaxFrameSize(
5208 seqParams,
5209 this,
5210 &profileLevelMaxFrame));
5211
5212 cmd.DW19.UserMaxFrame = profileLevelMaxFrame;
5213
5214 auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
5215
5216 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
5217 &cmd,
5218 params->pKernelState->dwCurbeOffset,
5219 sizeof(cmd)));
5220
5221 return eStatus;
5222 }
5223
SendAvcBrcFrameUpdateSurfaces(PMOS_COMMAND_BUFFER cmdBuffer,PCODECHAL_ENCODE_AVC_BRC_UPDATE_SURFACE_PARAMS params)5224 MOS_STATUS CodechalEncodeAvcEncG8::SendAvcBrcFrameUpdateSurfaces(PMOS_COMMAND_BUFFER cmdBuffer, PCODECHAL_ENCODE_AVC_BRC_UPDATE_SURFACE_PARAMS params)
5225 {
5226 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5227 CODECHAL_ENCODE_FUNCTION_ENTER;
5228
5229 m_stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
5230
5231 auto avcBrcUpdateBindingTable = params->pBrcUpdateBindingTable;
5232 auto mbencKernelState = params->pBrcBuffers->pMbEncKernelStateInUse;
5233 auto kernelState = params->pKernelState;
5234
5235 CODECHAL_SURFACE_CODEC_PARAMS surfaceCodecParams;
5236 // BRC history buffer
5237 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5238 surfaceCodecParams.presBuffer = ¶ms->pBrcBuffers->resBrcHistoryBuffer;
5239 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(params->dwBrcHistoryBufferSize);
5240 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcHistoryBuffer;
5241 surfaceCodecParams.bIsWritable = true;
5242 surfaceCodecParams.bRenderTarget = true;
5243 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5244 m_hwInterface,
5245 cmdBuffer,
5246 &surfaceCodecParams,
5247 kernelState));
5248
5249 // PAK Statistics buffer
5250 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5251 surfaceCodecParams.presBuffer = ¶ms->pBrcBuffers->resBrcPakStatisticBuffer[0];
5252 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(params->dwBrcPakStatisticsSize);
5253 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcPakStatisticsOutputBuffer;
5254 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5255 m_hwInterface,
5256 cmdBuffer,
5257 &surfaceCodecParams,
5258 kernelState));
5259
5260 // PAK IMG_STATEs buffer - read only
5261 uint32_t size = MOS_BYTES_TO_DWORDS(BRC_IMG_STATE_SIZE_PER_PASS * m_hwInterface->GetMfxInterface()->GetBrcNumPakPasses());
5262 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5263 surfaceCodecParams.presBuffer =
5264 ¶ms->pBrcBuffers->resBrcImageStatesReadBuffer[params->ucCurrRecycledBufIdx];
5265 surfaceCodecParams.dwSize = size;
5266 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcImageStateReadBuffer;
5267 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5268 m_hwInterface,
5269 cmdBuffer,
5270 &surfaceCodecParams,
5271 kernelState));
5272
5273 // PAK IMG_STATEs buffer - write only
5274 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5275 surfaceCodecParams.presBuffer = ¶ms->pBrcBuffers->resBrcImageStatesWriteBuffer;
5276 surfaceCodecParams.dwSize = size;
5277 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcImageStateWriteBuffer;
5278 surfaceCodecParams.bIsWritable = true;
5279 surfaceCodecParams.bRenderTarget = true;
5280 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5281 m_hwInterface,
5282 cmdBuffer,
5283 &surfaceCodecParams,
5284 kernelState));
5285
5286 MOS_RESOURCE *dsh = nullptr;
5287 CODECHAL_ENCODE_CHK_NULL_RETURN(dsh = mbencKernelState->m_dshRegion.GetResource());
5288
5289 // BRC ENC CURBE Buffer - read only
5290 size = MOS_ALIGN_CEIL(
5291 mbencKernelState->KernelParams.iCurbeLength,
5292 m_hwInterface->GetRenderInterface()->m_stateHeapInterface->pStateHeapInterface->GetCurbeAlignment());
5293 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5294 surfaceCodecParams.presBuffer = dsh;
5295 surfaceCodecParams.dwOffset =
5296 mbencKernelState->m_dshRegion.GetOffset() +
5297 mbencKernelState->dwCurbeOffset;
5298 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(size);
5299 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcMbEncCurbeReadBuffer;
5300 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5301 m_hwInterface,
5302 cmdBuffer,
5303 &surfaceCodecParams,
5304 kernelState));
5305
5306 // BRC ENC CURBE Buffer - write only
5307 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5308 if (params->bUseAdvancedDsh)
5309 {
5310 surfaceCodecParams.presBuffer = params->presMbEncCurbeBuffer;
5311 }
5312 else
5313 {
5314 surfaceCodecParams.presBuffer = dsh;
5315 surfaceCodecParams.dwOffset =
5316 mbencKernelState->m_dshRegion.GetOffset() +
5317 mbencKernelState->dwCurbeOffset;
5318 }
5319 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(size);
5320 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcMbEncCurbeWriteData;
5321 surfaceCodecParams.bRenderTarget = true;
5322 surfaceCodecParams.bIsWritable = true;
5323 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5324 m_hwInterface,
5325 cmdBuffer,
5326 &surfaceCodecParams,
5327 kernelState));
5328
5329 // AVC_ME BRC Distortion data buffer - input/output
5330 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5331 surfaceCodecParams.bIs2DSurface = true;
5332 surfaceCodecParams.bMediaBlockRW = true;
5333 surfaceCodecParams.psSurface = ¶ms->pBrcBuffers->sMeBrcDistortionBuffer;
5334 surfaceCodecParams.dwOffset = params->pBrcBuffers->dwMeBrcDistortionBottomFieldOffset;
5335 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcDistortionBuffer;
5336 surfaceCodecParams.bRenderTarget = true;
5337 surfaceCodecParams.bIsWritable = true;
5338 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5339 m_hwInterface,
5340 cmdBuffer,
5341 &surfaceCodecParams,
5342 kernelState));
5343
5344 // BRC Constant Data Surface
5345 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5346 surfaceCodecParams.bIs2DSurface = true;
5347 surfaceCodecParams.bMediaBlockRW = true;
5348 surfaceCodecParams.psSurface =
5349 ¶ms->pBrcBuffers->sBrcConstantDataBuffer[params->ucCurrRecycledBufIdx];
5350 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwFrameBrcConstantData;
5351 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5352 m_hwInterface,
5353 cmdBuffer,
5354 &surfaceCodecParams,
5355 kernelState));
5356
5357 // AVC MB QP data buffer
5358 if (params->bMbBrcEnabled)
5359 {
5360 params->pBrcBuffers->sBrcMbQpBuffer.dwWidth = MOS_ALIGN_CEIL((params->dwDownscaledWidthInMb4x * 4), 64);
5361 params->pBrcBuffers->sBrcMbQpBuffer.dwHeight =
5362 MOS_ALIGN_CEIL((params->dwDownscaledFrameFieldHeightInMb4x * 4), 8);
5363 params->pBrcBuffers->sBrcMbQpBuffer.dwPitch = params->pBrcBuffers->sBrcMbQpBuffer.dwWidth;
5364
5365 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5366 surfaceCodecParams.bIs2DSurface = true;
5367 surfaceCodecParams.bMediaBlockRW = true;
5368 surfaceCodecParams.psSurface = ¶ms->pBrcBuffers->sBrcMbQpBuffer;
5369 surfaceCodecParams.dwOffset = params->pBrcBuffers->dwBrcMbQpBottomFieldOffset;
5370 surfaceCodecParams.dwBindingTableOffset = avcBrcUpdateBindingTable->dwMbBrcMbQpBuffer;
5371 surfaceCodecParams.bIsWritable = true;
5372 surfaceCodecParams.bRenderTarget = true;
5373 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5374 m_hwInterface,
5375 cmdBuffer,
5376 &surfaceCodecParams,
5377 kernelState));
5378 }
5379 return eStatus;
5380 }
5381
SetCurbeAvcBrcBlockCopy(PCODECHAL_ENCODE_AVC_BRC_BLOCK_COPY_CURBE_PARAMS params)5382 MOS_STATUS CodechalEncodeAvcEncG8::SetCurbeAvcBrcBlockCopy(PCODECHAL_ENCODE_AVC_BRC_BLOCK_COPY_CURBE_PARAMS params)
5383 {
5384 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5385 CODECHAL_ENCODE_FUNCTION_ENTER;
5386
5387 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
5388 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
5389
5390 BRC_BLOCK_COPY_CURBE_CM cmd;
5391 MOS_ZeroMemory(&cmd, sizeof(cmd));
5392
5393 cmd.DW0.BufferOffset = params->dwBufferOffset;
5394 cmd.DW0.BlockHeight = params->dwBlockHeight;
5395 cmd.DW1.SrcSurfaceIndex = 0x00;
5396 cmd.DW2.DstSurfaceIndex = 0x01;
5397
5398 auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
5399
5400 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
5401 &cmd,
5402 params->pKernelState->dwCurbeOffset,
5403 sizeof(cmd)));
5404
5405 return eStatus;
5406 }
5407
SendAvcMbEncSurfaces(PMOS_COMMAND_BUFFER cmdBuffer,PCODECHAL_ENCODE_AVC_MBENC_SURFACE_PARAMS params)5408 MOS_STATUS CodechalEncodeAvcEncG8::SendAvcMbEncSurfaces(PMOS_COMMAND_BUFFER cmdBuffer, PCODECHAL_ENCODE_AVC_MBENC_SURFACE_PARAMS params)
5409 {
5410 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5411
5412 CODECHAL_ENCODE_FUNCTION_ENTER;
5413
5414 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
5415 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
5416 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pAvcSlcParams);
5417 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ppRefList);
5418 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pCurrOriginalPic);
5419 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pCurrReconstructedPic);
5420 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psCurrPicSurface);
5421 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pAvcPicIdx);
5422 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pMbEncBindingTable);
5423 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
5424
5425 bool currBottomField = CodecHal_PictureIsBottomField(*(params->pCurrOriginalPic)) ? 1 : 0;
5426
5427 uint8_t vDirection;
5428
5429 if (params->bMbEncIFrameDistInUse)
5430 {
5431 vDirection = CODECHAL_VDIRECTION_FRAME;
5432 }
5433 else
5434 {
5435 vDirection = (CodecHal_PictureIsFrame(*(params->pCurrOriginalPic))) ? CODECHAL_VDIRECTION_FRAME :
5436 (currBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD;
5437 }
5438
5439 // PAK Obj command buffer
5440
5441 CODECHAL_SURFACE_CODEC_PARAMS surfaceCodecParams;
5442 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5443 auto currPicRefListEntry = params->ppRefList[params->pCurrReconstructedPic->FrameIdx];
5444 auto mbCodeBuffer = &currPicRefListEntry->resRefMbCodeBuffer;
5445 auto avcMbEncBindingTable = params->pMbEncBindingTable;
5446 uint32_t size = params->dwFrameWidthInMb * params->dwFrameFieldHeightInMb * 16 * 4; // 11DW + 5DW padding
5447 surfaceCodecParams.presBuffer = mbCodeBuffer;
5448 surfaceCodecParams.dwSize = size;
5449 surfaceCodecParams.dwOffset = params->dwMbCodeBottomFieldOffset;
5450 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncMfcAvcPakObj;
5451 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_PAK_OBJECT_ENCODE].Value;
5452 surfaceCodecParams.bRenderTarget = true;
5453 surfaceCodecParams.bIsWritable = true;
5454 auto kernelState = params->pKernelState;
5455 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5456 m_hwInterface,
5457 cmdBuffer,
5458 &surfaceCodecParams,
5459 kernelState));
5460
5461 // MV data buffer
5462 size = params->dwFrameWidthInMb * params->dwFrameFieldHeightInMb * 32 * 4;
5463 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5464 auto mvDataBuffer = &currPicRefListEntry->resRefMvDataBuffer;
5465 surfaceCodecParams.presBuffer = mvDataBuffer;
5466 surfaceCodecParams.dwSize = size;
5467 surfaceCodecParams.dwOffset = params->dwMvBottomFieldOffset;
5468 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
5469 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncIndMVData;
5470 surfaceCodecParams.bRenderTarget = true;
5471 surfaceCodecParams.bIsWritable = true;
5472 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5473 m_hwInterface,
5474 cmdBuffer,
5475 &surfaceCodecParams,
5476 kernelState));
5477
5478 // Current Picture Y
5479 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5480 surfaceCodecParams.bIs2DSurface = true;
5481 surfaceCodecParams.bMediaBlockRW = true; // Use media block RW for DP 2D surface access
5482 surfaceCodecParams.bUseUVPlane = true;
5483 surfaceCodecParams.psSurface = params->psCurrPicSurface;
5484 surfaceCodecParams.dwOffset = params->dwCurrPicSurfaceOffset;
5485 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_CURR_ENCODE].Value;
5486 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncCurrY;
5487 surfaceCodecParams.dwUVBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncCurrUV;
5488 surfaceCodecParams.dwVerticalLineStride = params->dwVerticalLineStride;
5489 surfaceCodecParams.dwVerticalLineStrideOffset = params->dwVerticalLineStrideOffset;
5490
5491 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5492 m_hwInterface,
5493 cmdBuffer,
5494 &surfaceCodecParams,
5495 kernelState));
5496
5497 // AVC_ME MV data buffer
5498 if (params->bHmeEnabled)
5499 {
5500 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps4xMeMvDataBuffer);
5501
5502 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5503 surfaceCodecParams.bIs2DSurface = true;
5504 surfaceCodecParams.bMediaBlockRW = true;
5505 surfaceCodecParams.psSurface = params->ps4xMeMvDataBuffer;
5506 surfaceCodecParams.dwOffset = params->dwMeMvBottomFieldOffset;
5507 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
5508 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncMVDataFromME;
5509 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5510 m_hwInterface,
5511 cmdBuffer,
5512 &surfaceCodecParams,
5513 kernelState));
5514
5515 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps4xMeDistortionBuffer);
5516
5517 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5518 surfaceCodecParams.bIs2DSurface = true;
5519 surfaceCodecParams.bMediaBlockRW = true;
5520 surfaceCodecParams.psSurface = params->ps4xMeDistortionBuffer;
5521 surfaceCodecParams.dwOffset = params->dwMeDistortionBottomFieldOffset;
5522 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_ME_DISTORTION_ENCODE].Value;
5523 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncMEDist;
5524 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5525 m_hwInterface,
5526 cmdBuffer,
5527 &surfaceCodecParams,
5528 kernelState));
5529 }
5530
5531 if (params->bMbConstDataBufferInUse)
5532 {
5533 // 16 DWs per QP value
5534 size = 16 * 52 * sizeof(uint32_t);
5535
5536 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5537 surfaceCodecParams.presBuffer = params->presMbBrcConstDataBuffer;
5538 surfaceCodecParams.dwSize = size;
5539 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncMbBrcConstData;
5540 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5541 m_hwInterface,
5542 cmdBuffer,
5543 &surfaceCodecParams,
5544 kernelState));
5545 }
5546 bool currFieldPicture = CodecHal_PictureIsField(*(params->pCurrOriginalPic)) ? 1 : 0;
5547 if (params->bMbQpBufferInUse)
5548 {
5549 // AVC MB BRC QP buffer
5550 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5551 surfaceCodecParams.bIs2DSurface = true;
5552 surfaceCodecParams.bMediaBlockRW = true;
5553 surfaceCodecParams.psSurface = params->psMbQpBuffer;
5554 surfaceCodecParams.dwOffset = params->dwMbQpBottomFieldOffset;
5555 surfaceCodecParams.dwBindingTableOffset = currFieldPicture ? avcMbEncBindingTable->dwAvcMBEncMbQpField :
5556 avcMbEncBindingTable->dwAvcMBEncMbQpFrame;
5557 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5558 m_hwInterface,
5559 cmdBuffer,
5560 &surfaceCodecParams,
5561 kernelState));
5562 }
5563
5564 // Current Picture Y - VME
5565 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5566 surfaceCodecParams.bUseAdvState = true;
5567 surfaceCodecParams.psSurface = params->psCurrPicSurface;
5568 surfaceCodecParams.dwOffset = params->dwCurrPicSurfaceOffset;
5569 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_CURR_ENCODE].Value;
5570 surfaceCodecParams.dwBindingTableOffset = currFieldPicture ?
5571 avcMbEncBindingTable->dwAvcMBEncFieldCurrPic[0] : avcMbEncBindingTable->dwAvcMBEncCurrPicFrame[0];
5572 surfaceCodecParams.ucVDirection = vDirection;
5573
5574 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5575 m_hwInterface,
5576 cmdBuffer,
5577 &surfaceCodecParams,
5578 kernelState));
5579
5580 surfaceCodecParams.dwBindingTableOffset = currFieldPicture ?
5581 avcMbEncBindingTable->dwAvcMBEncFieldCurrPic[1] : avcMbEncBindingTable->dwAvcMBEncCurrPicFrame[1];
5582 surfaceCodecParams.ucVDirection = vDirection;
5583 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5584 m_hwInterface,
5585 cmdBuffer,
5586 &surfaceCodecParams,
5587 kernelState));
5588
5589 uint32_t refBindingTableOffset;
5590 uint8_t refVDirection;
5591 // Setup references 1...n
5592 // LIST 0 references
5593 for (uint8_t refIdx = 0; refIdx <= params->pAvcSlcParams->num_ref_idx_l0_active_minus1; refIdx++)
5594 {
5595 CODEC_PICTURE refPic = params->pAvcSlcParams->RefPicList[LIST_0][refIdx];
5596 if (!CodecHal_PictureIsInvalid(refPic) && params->pAvcPicIdx[refPic.FrameIdx].bValid)
5597 {
5598 uint8_t refPicIdx = params->pAvcPicIdx[refPic.FrameIdx].ucPicIdx;
5599 bool refBottomField = (CodecHal_PictureIsBottomField(refPic)) ? 1 : 0;
5600 // Program the surface based on current picture's field/frame mode
5601 if (currFieldPicture) // if current picture is field
5602 {
5603 if (refBottomField)
5604 {
5605 refVDirection = CODECHAL_VDIRECTION_BOT_FIELD;
5606 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncFwdPicBotField[refIdx];
5607 }
5608 else
5609 {
5610 refVDirection = CODECHAL_VDIRECTION_TOP_FIELD;
5611 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncFwdPicTopField[refIdx];
5612 }
5613 }
5614 else // if current picture is frame
5615 {
5616 refVDirection = CODECHAL_VDIRECTION_FRAME;
5617 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncFwdPicFrame[refIdx];
5618 }
5619
5620 // Picture Y VME
5621 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5622 surfaceCodecParams.bUseAdvState = true;
5623 surfaceCodecParams.dwWidthInUse = params->dwFrameWidthInMb * 16;
5624 surfaceCodecParams.dwHeightInUse = params->dwFrameHeightInMb * 16;
5625 if((params->bUseWeightedSurfaceForL0) &&
5626 (params->pAvcSlcParams->luma_weight_flag[LIST_0] & (1<<refIdx)) &&
5627 (refIdx < CODEC_AVC_MAX_FORWARD_WP_FRAME))
5628 {
5629 surfaceCodecParams.psSurface = ¶ms->pWeightedPredOutputPicSelectList[CODEC_AVC_WP_OUTPUT_L0_START + refIdx].sBuffer;
5630 }
5631 else
5632 {
5633 surfaceCodecParams.psSurface = ¶ms->ppRefList[refPicIdx]->sRefBuffer;
5634 }
5635 surfaceCodecParams.dwBindingTableOffset = refBindingTableOffset;
5636 surfaceCodecParams.ucVDirection = refVDirection;
5637 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Value;
5638
5639 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5640 m_hwInterface,
5641 cmdBuffer,
5642 &surfaceCodecParams,
5643 kernelState));
5644 }
5645 }
5646 // Setup references 1...n
5647 // LIST 1 references
5648 for (uint8_t refIdx = 0; refIdx <= params->pAvcSlcParams->num_ref_idx_l1_active_minus1; refIdx++)
5649 {
5650 uint32_t refMbCodeBottomFieldOffsetUsed;
5651 uint32_t refMvBottomFieldOffsetUsed;
5652 if (!currFieldPicture && refIdx > 0)
5653 {
5654 // Only 1 LIST 1 reference required here since only single ref is supported in frame case
5655 break;
5656 }
5657
5658 CODEC_PICTURE refPic = params->pAvcSlcParams->RefPicList[LIST_1][refIdx];
5659 if (!CodecHal_PictureIsInvalid(refPic) && params->pAvcPicIdx[refPic.FrameIdx].bValid)
5660 {
5661 uint8_t refPicIdx = params->pAvcPicIdx[refPic.FrameIdx].ucPicIdx;
5662 bool refBottomField = (CodecHal_PictureIsBottomField(refPic)) ? 1 : 0;
5663 // Program the surface based on current picture's field/frame mode
5664 if (currFieldPicture) // if current picture is field
5665 {
5666 if (refBottomField)
5667 {
5668 refVDirection = CODECHAL_VDIRECTION_BOT_FIELD;
5669 uint32_t refMbCodeBottomFieldOffset = params->dwFrameFieldHeightInMb * params->dwFrameWidthInMb * 64;
5670 refMbCodeBottomFieldOffsetUsed = refMbCodeBottomFieldOffset;
5671 uint32_t refMvBottomFieldOffset = MOS_ALIGN_CEIL(params->dwFrameFieldHeightInMb * params->dwFrameWidthInMb * (32 * 4), 0x1000);
5672 refMvBottomFieldOffsetUsed = refMvBottomFieldOffset;
5673 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdPicBotField[refIdx];
5674 }
5675 else
5676 {
5677 refVDirection = CODECHAL_VDIRECTION_TOP_FIELD;
5678 refMbCodeBottomFieldOffsetUsed = 0;
5679 refMvBottomFieldOffsetUsed = 0;
5680 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdPicTopField[refIdx];
5681 }
5682 }
5683 else // if current picture is frame
5684 {
5685 refVDirection = CODECHAL_VDIRECTION_FRAME;
5686 refMbCodeBottomFieldOffsetUsed = 0;
5687 refMvBottomFieldOffsetUsed = 0;
5688 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdPicFrame[refIdx];
5689 }
5690
5691 // Picture Y VME
5692 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5693 surfaceCodecParams.bUseAdvState = true;
5694 surfaceCodecParams.dwWidthInUse = params->dwFrameWidthInMb * 16;
5695 surfaceCodecParams.dwHeightInUse = params->dwFrameHeightInMb * 16;
5696 if((params->bUseWeightedSurfaceForL1) &&
5697 (params->pAvcSlcParams->luma_weight_flag[LIST_1] & (1<<refIdx)) &&
5698 (refIdx < CODEC_AVC_MAX_BACKWARD_WP_FRAME))
5699 {
5700 surfaceCodecParams.psSurface = ¶ms->pWeightedPredOutputPicSelectList[CODEC_AVC_WP_OUTPUT_L1_START + refIdx].sBuffer;
5701 }
5702 else
5703 {
5704 surfaceCodecParams.psSurface = ¶ms->ppRefList[refPicIdx]->sRefBuffer;
5705 }
5706 surfaceCodecParams.dwBindingTableOffset = refBindingTableOffset;
5707 surfaceCodecParams.ucVDirection = refVDirection;
5708 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Value;
5709
5710 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5711 m_hwInterface,
5712 cmdBuffer,
5713 &surfaceCodecParams,
5714 kernelState));
5715
5716 if (refIdx == 0)
5717 {
5718 if(currFieldPicture && (params->ppRefList[refPicIdx]->ucAvcPictureCodingType == CODEC_AVC_PIC_CODING_TYPE_FRAME || params->ppRefList[refPicIdx]->ucAvcPictureCodingType == CODEC_AVC_PIC_CODING_TYPE_INVALID))
5719 {
5720 refMbCodeBottomFieldOffsetUsed = 0;
5721 refMvBottomFieldOffsetUsed = 0;
5722 }
5723 // MB data buffer
5724 size = params->dwFrameWidthInMb * params->dwFrameFieldHeightInMb * 16 * 4;
5725 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5726 surfaceCodecParams.dwSize = size;
5727 surfaceCodecParams.presBuffer = ¶ms->ppRefList[refPicIdx]->resRefMbCodeBuffer;
5728 surfaceCodecParams.dwOffset = refMbCodeBottomFieldOffsetUsed;
5729 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_PAK_OBJECT_ENCODE].Value;
5730 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdRefMBData;
5731 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5732 m_hwInterface,
5733 cmdBuffer,
5734 &surfaceCodecParams,
5735 kernelState));
5736
5737 // MV data buffer
5738 size = params->dwFrameWidthInMb * params->dwFrameFieldHeightInMb * 32 * 4;
5739 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5740 surfaceCodecParams.dwSize = size;
5741 surfaceCodecParams.presBuffer = ¶ms->ppRefList[refPicIdx]->resRefMvDataBuffer;
5742 surfaceCodecParams.dwOffset = refMvBottomFieldOffsetUsed;
5743 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
5744 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdRefMVData;
5745 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5746 m_hwInterface,
5747 cmdBuffer,
5748 &surfaceCodecParams,
5749 kernelState));
5750 }
5751
5752 if (refIdx < CODECHAL_ENCODE_NUM_MAX_VME_L1_REF)
5753 {
5754 if (currFieldPicture)
5755 {
5756 // The binding table contains multiple entries for IDX0 backwards references
5757 if (refBottomField)
5758 {
5759 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdPicBotField[refIdx + CODECHAL_ENCODE_NUM_MAX_VME_L1_REF];
5760 }
5761 else
5762 {
5763 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdPicTopField[refIdx + CODECHAL_ENCODE_NUM_MAX_VME_L1_REF];
5764 }
5765 }
5766 else
5767 {
5768 refBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBwdPicFrame[refIdx + CODECHAL_ENCODE_NUM_MAX_VME_L1_REF];
5769 }
5770
5771 // Picture Y VME
5772 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5773 surfaceCodecParams.bUseAdvState = true;
5774 surfaceCodecParams.dwWidthInUse = params->dwFrameWidthInMb * 16;
5775 surfaceCodecParams.dwHeightInUse = params->dwFrameHeightInMb * 16;
5776 surfaceCodecParams.psSurface = ¶ms->ppRefList[refPicIdx]->sRefBuffer;
5777 surfaceCodecParams.dwBindingTableOffset = refBindingTableOffset;
5778 surfaceCodecParams.ucVDirection = refVDirection;
5779 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Value;
5780
5781 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5782 m_hwInterface,
5783 cmdBuffer,
5784 &surfaceCodecParams,
5785 kernelState));
5786 }
5787 }
5788 }
5789
5790 // BRC distortion data buffer for I frame
5791 if (params->bMbEncIFrameDistInUse)
5792 {
5793 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5794 surfaceCodecParams.bIs2DSurface = true;
5795 surfaceCodecParams.bMediaBlockRW = true;
5796 surfaceCodecParams.psSurface = params->psMeBrcDistortionBuffer;
5797 surfaceCodecParams.dwOffset = params->dwMeBrcDistortionBottomFieldOffset;
5798 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncBRCDist;
5799 surfaceCodecParams.bIsWritable = true;
5800 surfaceCodecParams.bRenderTarget = true;
5801 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5802 m_hwInterface,
5803 cmdBuffer,
5804 &surfaceCodecParams,
5805 kernelState));
5806 }
5807
5808 // RefPicSelect of Current Picture
5809 if (params->bUsedAsRef)
5810 {
5811 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5812 surfaceCodecParams.bIs2DSurface = true;
5813 surfaceCodecParams.bMediaBlockRW = true;
5814 surfaceCodecParams.psSurface = &currPicRefListEntry->pRefPicSelectListEntry->sBuffer;
5815 surfaceCodecParams.psSurface->dwHeight = MOS_ALIGN_CEIL(surfaceCodecParams.psSurface->dwHeight, 8);
5816 surfaceCodecParams.dwOffset = params->dwRefPicSelectBottomFieldOffset;
5817 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncRefPicSelectL0;
5818 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Value;
5819 surfaceCodecParams.bRenderTarget = true;
5820 surfaceCodecParams.bIsWritable = true;
5821 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5822 m_hwInterface,
5823 cmdBuffer,
5824 &surfaceCodecParams,
5825 kernelState));
5826 }
5827
5828 if (params->bFlatnessCheckEnabled)
5829 {
5830 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5831 surfaceCodecParams.bIs2DSurface = true;
5832 surfaceCodecParams.bMediaBlockRW = true;
5833 surfaceCodecParams.psSurface = params->psFlatnessCheckSurface;
5834 surfaceCodecParams.dwOffset = currBottomField ? params->dwFlatnessCheckBottomFieldOffset : 0;
5835 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncFlatnessChk;
5836 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_FLATNESS_CHECK_ENCODE].Value;
5837 surfaceCodecParams.bRenderTarget = true;
5838 surfaceCodecParams.bIsWritable = true;
5839 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5840 m_hwInterface,
5841 cmdBuffer,
5842 &surfaceCodecParams,
5843 kernelState));
5844 }
5845
5846 if (params->bMADEnabled)
5847 {
5848 size = CODECHAL_MAD_BUFFER_SIZE;
5849
5850 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5851 surfaceCodecParams.bRawSurface = true;
5852 surfaceCodecParams.dwSize = size;
5853 surfaceCodecParams.presBuffer = params->presMADDataBuffer;
5854 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncMADData;
5855 surfaceCodecParams.bRenderTarget = true;
5856 surfaceCodecParams.bIsWritable = true;
5857 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5858 m_hwInterface,
5859 cmdBuffer,
5860 &surfaceCodecParams,
5861 kernelState));
5862 }
5863
5864 if (params->bUseMbEncAdvKernel)
5865 {
5866 auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
5867 // For BRC the new BRC surface is used
5868 if (params->bUseAdvancedDsh)
5869 {
5870 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5871 surfaceCodecParams.presBuffer = params->presMbEncCurbeBuffer;
5872 uint32_t curbeSize = MOS_ALIGN_CEIL(
5873 params->pKernelState->KernelParams.iCurbeLength,
5874 m_hwInterface->GetRenderInterface()->m_stateHeapInterface->pStateHeapInterface->GetCurbeAlignment());
5875 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(curbeSize);
5876 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMbEncBRCCurbeData;
5877 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MBENC_CURBE_ENCODE].Value;
5878 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5879 m_hwInterface,
5880 cmdBuffer,
5881 &surfaceCodecParams,
5882 kernelState));
5883 }
5884 else // For CQP the DSH CURBE is used
5885 {
5886 MOS_RESOURCE *dsh = nullptr;
5887 CODECHAL_ENCODE_CHK_NULL_RETURN(dsh = params->pKernelState->m_dshRegion.GetResource());
5888 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5889 surfaceCodecParams.presBuffer = dsh;
5890 surfaceCodecParams.dwOffset =
5891 params->pKernelState->m_dshRegion.GetOffset() +
5892 params->pKernelState->dwCurbeOffset;
5893 uint32_t curbeSize = MOS_ALIGN_CEIL(
5894 params->pKernelState->KernelParams.iCurbeLength,
5895 m_hwInterface->GetRenderInterface()->m_stateHeapInterface->pStateHeapInterface->GetCurbeAlignment());
5896 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(curbeSize);
5897 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMbEncBRCCurbeData;
5898 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MBENC_CURBE_ENCODE].Value;
5899 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5900 m_hwInterface,
5901 cmdBuffer,
5902 &surfaceCodecParams,
5903 kernelState));
5904 }
5905 }
5906
5907 if (params->bArbitraryNumMbsInSlice)
5908 {
5909 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5910 surfaceCodecParams.bIs2DSurface = true;
5911 surfaceCodecParams.bMediaBlockRW = true;
5912 surfaceCodecParams.psSurface = params->psSliceMapSurface;
5913 surfaceCodecParams.bRenderTarget = false;
5914 surfaceCodecParams.bIsWritable = false;
5915 surfaceCodecParams.dwOffset = currBottomField ? params->dwSliceMapBottomFieldOffset : 0;
5916 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncSliceMapData;
5917
5918 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5919 m_hwInterface,
5920 cmdBuffer,
5921 &surfaceCodecParams,
5922 kernelState));
5923 }
5924
5925 if(!params->bMbEncIFrameDistInUse)
5926 {
5927 if( params->bMbDisableSkipMapEnabled )
5928 {
5929 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5930 surfaceCodecParams.bIs2DSurface = true;
5931 surfaceCodecParams.bMediaBlockRW = true;
5932 surfaceCodecParams.psSurface = params->psMbDisableSkipMapSurface;
5933 surfaceCodecParams.dwOffset = 0;
5934 surfaceCodecParams.dwBindingTableOffset = avcMbEncBindingTable->dwAvcMBEncMbNonSkipMap;
5935 surfaceCodecParams.dwCacheabilityControl =
5936 m_hwInterface->ComposeSurfaceCacheabilityControl(
5937 MOS_CODEC_RESOURCE_USAGE_MBDISABLE_SKIPMAP_CODEC,
5938 codechalLLC);
5939 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5940 m_hwInterface,
5941 cmdBuffer,
5942 &surfaceCodecParams,
5943 kernelState));
5944 }
5945
5946 if( params->bStaticFrameDetectionEnabled )
5947 {
5948 // static frame detection output surface
5949 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
5950 surfaceCodecParams.presBuffer = params->presSFDOutputBuffer;
5951 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS( m_sfdOutputBufferSize );
5952 surfaceCodecParams.dwOffset = 0;
5953 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_ME_DISTORTION_ENCODE].Value;
5954 surfaceCodecParams.dwBindingTableOffset = MBENC_STATIC_FRAME_DETECTION_OUTPUT_CM;
5955 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5956 m_hwInterface,
5957 cmdBuffer,
5958 &surfaceCodecParams,
5959 kernelState));
5960 }
5961 }
5962
5963 return eStatus;
5964 }
5965
SendAvcWPSurfaces(PMOS_COMMAND_BUFFER cmdBuffer,PCODECHAL_ENCODE_AVC_WP_SURFACE_PARAMS params)5966 MOS_STATUS CodechalEncodeAvcEncG8::SendAvcWPSurfaces(PMOS_COMMAND_BUFFER cmdBuffer, PCODECHAL_ENCODE_AVC_WP_SURFACE_PARAMS params)
5967 {
5968 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5969
5970 CODECHAL_ENCODE_FUNCTION_ENTER;
5971
5972 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
5973 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
5974 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psInputRefBuffer);
5975 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psOutputScaledBuffer);
5976
5977 CODECHAL_SURFACE_CODEC_PARAMS surfaceParams;
5978 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
5979 surfaceParams.bIs2DSurface = true;
5980 surfaceParams.bMediaBlockRW = true;
5981 surfaceParams.psSurface = params->psInputRefBuffer;// Input surface
5982 surfaceParams.bIsWritable = false;
5983 surfaceParams.bRenderTarget = false;
5984 surfaceParams.dwBindingTableOffset = WP_INPUT_REF_SURFACE;
5985 surfaceParams.dwVerticalLineStride = params->dwVerticalLineStride;
5986 surfaceParams.dwVerticalLineStrideOffset = params->dwVerticalLineStrideOffset;
5987 surfaceParams.ucVDirection = params->ucVDirection;
5988 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
5989 m_hwInterface,
5990 cmdBuffer,
5991 &surfaceParams,
5992 params->pKernelState));
5993
5994 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
5995 surfaceParams.bIs2DSurface = true;
5996 surfaceParams.bMediaBlockRW = true;
5997 surfaceParams.psSurface = params->psOutputScaledBuffer;// output surface
5998 surfaceParams.bIsWritable = true;
5999 surfaceParams.bRenderTarget = true;
6000 surfaceParams.dwBindingTableOffset = WP_OUTPUT_SCALED_SURFACE;
6001 surfaceParams.dwVerticalLineStride = params->dwVerticalLineStride;
6002 surfaceParams.dwVerticalLineStrideOffset = params->dwVerticalLineStrideOffset;
6003 surfaceParams.ucVDirection = params->ucVDirection;
6004 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6005 m_hwInterface,
6006 cmdBuffer,
6007 &surfaceParams,
6008 params->pKernelState));
6009
6010 return eStatus;
6011 }
6012
SendMeSurfaces(PMOS_COMMAND_BUFFER cmdBuffer,MeSurfaceParams * params)6013 MOS_STATUS CodechalEncodeAvcEncG8::SendMeSurfaces (
6014 PMOS_COMMAND_BUFFER cmdBuffer,
6015 MeSurfaceParams* params)
6016 {
6017 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6018 CODECHAL_ENCODE_FUNCTION_ENTER;
6019
6020 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
6021 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
6022 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pCurrOriginalPic);
6023 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps4xMeMvDataBuffer);
6024 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psMeBrcDistortionBuffer);
6025
6026 CODECHAL_MEDIA_STATE_TYPE encMediaStateType = (params->b32xMeInUse) ? CODECHAL_MEDIA_STATE_32X_ME :
6027 params->b16xMeInUse ? CODECHAL_MEDIA_STATE_16X_ME : CODECHAL_MEDIA_STATE_4X_ME;
6028
6029 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pMeBindingTable);
6030 auto meBindingTable = params->pMeBindingTable;
6031
6032 bool currFieldPicture = CodecHal_PictureIsField(*(params->pCurrOriginalPic)) ? 1 : 0;
6033 bool currBottomField = CodecHal_PictureIsBottomField(*(params->pCurrOriginalPic)) ? 1 : 0;
6034 uint8_t currVDirection = (!currFieldPicture) ? CODECHAL_VDIRECTION_FRAME :
6035 ((currBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD);
6036
6037 PMOS_SURFACE currScaledSurface = nullptr;
6038 PMOS_SURFACE meMvDataBuffer = nullptr;
6039 uint32_t meMvBottomFieldOffset;
6040 uint32_t currScaledBottomFieldOffset;
6041
6042 if (params->b32xMeInUse)
6043 {
6044 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps32xMeMvDataBuffer);
6045 currScaledSurface = m_trackedBuf->Get32xDsSurface(CODEC_CURR_TRACKED_BUFFER);
6046 meMvDataBuffer = params->ps32xMeMvDataBuffer;
6047 meMvBottomFieldOffset = params->dw32xMeMvBottomFieldOffset;
6048 currScaledBottomFieldOffset = params->dw32xScaledBottomFieldOffset;
6049 }
6050 else if (params->b16xMeInUse)
6051 {
6052 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps16xMeMvDataBuffer);
6053 currScaledSurface = m_trackedBuf->Get16xDsSurface(CODEC_CURR_TRACKED_BUFFER);
6054 meMvDataBuffer = params->ps16xMeMvDataBuffer;
6055 meMvBottomFieldOffset = params->dw16xMeMvBottomFieldOffset;
6056 currScaledBottomFieldOffset = params->dw16xScaledBottomFieldOffset;
6057 }
6058 else
6059 {
6060 currScaledSurface = m_trackedBuf->Get4xDsSurface(CODEC_CURR_TRACKED_BUFFER);
6061 meMvDataBuffer = params->ps4xMeMvDataBuffer;
6062 meMvBottomFieldOffset = params->dw4xMeMvBottomFieldOffset;
6063 currScaledBottomFieldOffset = params->dw4xScaledBottomFieldOffset;
6064 }
6065
6066 // Reference height and width information should be taken from the current scaled surface rather
6067 // than from the reference scaled surface in the case of PAFF.
6068 auto refScaledSurface = *currScaledSurface;
6069
6070 uint32_t width = MOS_ALIGN_CEIL(params->dwDownscaledWidthInMb * 32, 64);
6071 uint32_t height = params->dwDownscaledHeightInMb * 4 * CODECHAL_ENCODE_ME_DATA_SIZE_MULTIPLIER;
6072
6073 // Force the values
6074 meMvDataBuffer->dwWidth = width;
6075 meMvDataBuffer->dwHeight = height;
6076 meMvDataBuffer->dwPitch = width;
6077 CODECHAL_SURFACE_CODEC_PARAMS surfaceParams;
6078 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6079 surfaceParams.bIs2DSurface = true;
6080 surfaceParams.bMediaBlockRW = true;
6081 surfaceParams.psSurface = meMvDataBuffer;
6082 surfaceParams.dwOffset = meMvBottomFieldOffset;
6083 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
6084 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEMVDataSurface;
6085 surfaceParams.bIsWritable = true;
6086 surfaceParams.bRenderTarget = true;
6087 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6088 m_hwInterface,
6089 cmdBuffer,
6090 &surfaceParams,
6091 params->pKernelState));
6092
6093 if (params->b16xMeInUse && params->b32xMeEnabled)
6094 {
6095 // Pass 32x MV to 16x ME operation
6096 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6097 surfaceParams.bIs2DSurface = true;
6098 surfaceParams.bMediaBlockRW = true;
6099 surfaceParams.psSurface = params->ps32xMeMvDataBuffer;
6100 surfaceParams.dwOffset =
6101 currBottomField ? params->dw32xMeMvBottomFieldOffset : 0;
6102 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
6103 surfaceParams.dwBindingTableOffset = meBindingTable->dw32xMEMVDataSurface;
6104 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6105 m_hwInterface,
6106 cmdBuffer,
6107 &surfaceParams,
6108 params->pKernelState));
6109 }
6110 else if (!params->b32xMeInUse && params->b16xMeEnabled)
6111 {
6112 // Pass 16x MV to 4x ME operation
6113 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6114 surfaceParams.bIs2DSurface = true;
6115 surfaceParams.bMediaBlockRW = true;
6116 surfaceParams.psSurface = params->ps16xMeMvDataBuffer;
6117 surfaceParams.dwOffset =
6118 currBottomField ? params->dw16xMeMvBottomFieldOffset : 0;
6119 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
6120 surfaceParams.dwBindingTableOffset = meBindingTable->dw16xMEMVDataSurface;
6121 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6122 m_hwInterface,
6123 cmdBuffer,
6124 &surfaceParams,
6125 params->pKernelState));
6126 }
6127
6128 // Insert Distortion buffers only for 4xMe case
6129 if (!params->b32xMeInUse && !params->b16xMeInUse)
6130 {
6131 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6132 surfaceParams.bIs2DSurface = true;
6133 surfaceParams.bMediaBlockRW = true;
6134 surfaceParams.psSurface = params->psMeBrcDistortionBuffer;
6135 surfaceParams.dwOffset = params->dwMeBrcDistortionBottomFieldOffset;
6136 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEBRCDist;
6137 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_BRC_ME_DISTORTION_ENCODE].Value;
6138 surfaceParams.bIsWritable = true;
6139 surfaceParams.bRenderTarget = true;
6140 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6141 m_hwInterface,
6142 cmdBuffer,
6143 &surfaceParams,
6144 params->pKernelState));
6145
6146 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6147 surfaceParams.bIs2DSurface = true;
6148 surfaceParams.bMediaBlockRW = true;
6149 surfaceParams.psSurface = params->psMeDistortionBuffer;
6150 surfaceParams.dwOffset = params->dwMeDistortionBottomFieldOffset;
6151 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEDist;
6152 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_ME_DISTORTION_ENCODE].Value;
6153 surfaceParams.bIsWritable = true;
6154 surfaceParams.bRenderTarget = true;
6155 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6156 m_hwInterface,
6157 cmdBuffer,
6158 &surfaceParams,
6159 params->pKernelState));
6160 }
6161 uint32_t refScaledBottomFieldOffset;
6162 // Setup references 1...n
6163 // LIST 0 references
6164 for (uint8_t refIdx = 0; refIdx <= params->dwNumRefIdxL0ActiveMinus1; refIdx++)
6165 {
6166 auto refPic = params->pL0RefFrameList[refIdx];
6167
6168 if (!CodecHal_PictureIsInvalid(refPic) && params->pPicIdx[refPic.FrameIdx].bValid)
6169 {
6170 if (refIdx == 0)
6171 {
6172 // Current Picture Y - VME
6173 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6174 surfaceParams.bUseAdvState = true;
6175 surfaceParams.psSurface = currScaledSurface;
6176 surfaceParams.dwOffset = currBottomField ? currScaledBottomFieldOffset : 0;
6177 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_CURR_ENCODE].Value;
6178 surfaceParams.dwBindingTableOffset = meBindingTable->dwMECurrForFwdRef;
6179 surfaceParams.ucVDirection = currVDirection;
6180 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6181 m_hwInterface,
6182 cmdBuffer,
6183 &surfaceParams,
6184 params->pKernelState));
6185 }
6186
6187 bool refFieldPicture = CodecHal_PictureIsField(refPic) ? 1 : 0;
6188 bool refBottomField = (CodecHal_PictureIsBottomField(refPic)) ? 1 : 0;
6189 uint8_t refPicIdx = params->pPicIdx[refPic.FrameIdx].ucPicIdx;
6190 uint8_t scaledIdx = params->ppRefList[refPicIdx]->ucScalingIdx;
6191 if (params->b32xMeInUse)
6192 {
6193 PMOS_SURFACE surface = nullptr;
6194 CODECHAL_ENCODE_CHK_NULL_RETURN(surface = m_trackedBuf->Get32xDsSurface(scaledIdx));
6195 refScaledSurface.OsResource = surface->OsResource;
6196 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
6197 }
6198 else if (params->b16xMeInUse)
6199 {
6200 PMOS_SURFACE surface = nullptr;
6201 CODECHAL_ENCODE_CHK_NULL_RETURN(surface = m_trackedBuf->Get16xDsSurface(scaledIdx));
6202 refScaledSurface.OsResource = surface->OsResource;
6203 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
6204 }
6205 else
6206 {
6207 PMOS_SURFACE surface = nullptr;
6208 CODECHAL_ENCODE_CHK_NULL_RETURN(surface = m_trackedBuf->Get4xDsSurface(scaledIdx));
6209 refScaledSurface.OsResource = surface->OsResource;
6210 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
6211 }
6212
6213 // L0 Reference Picture Y - VME
6214 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6215 surfaceParams.bUseAdvState = true;
6216 surfaceParams.psSurface = &refScaledSurface;
6217 surfaceParams.dwOffset = refBottomField ? refScaledBottomFieldOffset : 0;
6218 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Value;
6219 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEFwdRefPicIdx[refIdx];
6220 surfaceParams.ucVDirection = !currFieldPicture ? CODECHAL_VDIRECTION_FRAME :
6221 ((refBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD);
6222 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6223 m_hwInterface,
6224 cmdBuffer,
6225 &surfaceParams,
6226 params->pKernelState));
6227 }
6228 }
6229
6230 // Setup references 1...n
6231 // LIST 1 references
6232 for (uint8_t refIdx = 0; refIdx <= params->dwNumRefIdxL1ActiveMinus1; refIdx++)
6233 {
6234 auto refPic = params->pL1RefFrameList[refIdx];
6235
6236 if (!CodecHal_PictureIsInvalid(refPic) && params->pPicIdx[refPic.FrameIdx].bValid)
6237 {
6238 if (refIdx == 0)
6239 {
6240 // Current Picture Y - VME
6241 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6242 surfaceParams.bUseAdvState = true;
6243 surfaceParams.psSurface = currScaledSurface;
6244 surfaceParams.dwOffset = currBottomField ? currScaledBottomFieldOffset : 0;
6245 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_CURR_ENCODE].Value;
6246 surfaceParams.dwBindingTableOffset = meBindingTable->dwMECurrForBwdRef;
6247 surfaceParams.ucVDirection = currVDirection;
6248 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6249 m_hwInterface,
6250 cmdBuffer,
6251 &surfaceParams,
6252 params->pKernelState));
6253 }
6254
6255 bool refFieldPicture = CodecHal_PictureIsField(refPic) ? 1 : 0;
6256 bool refBottomField = (CodecHal_PictureIsBottomField(refPic)) ? 1 : 0;
6257 uint8_t refPicIdx = params->pPicIdx[refPic.FrameIdx].ucPicIdx;
6258 uint8_t scaledIdx = params->ppRefList[refPicIdx]->ucScalingIdx;
6259 if (params->b32xMeInUse)
6260 {
6261 PMOS_SURFACE surface = nullptr;
6262 CODECHAL_ENCODE_CHK_NULL_RETURN(surface = m_trackedBuf->Get32xDsSurface(scaledIdx));
6263 refScaledSurface.OsResource = surface->OsResource;
6264 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
6265 }
6266 else if (params->b16xMeInUse)
6267 {
6268 PMOS_SURFACE surface = nullptr;
6269 CODECHAL_ENCODE_CHK_NULL_RETURN(surface = m_trackedBuf->Get16xDsSurface(scaledIdx));
6270 refScaledSurface.OsResource = surface->OsResource;
6271 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
6272 }
6273 else
6274 {
6275 PMOS_SURFACE surface = nullptr;
6276 CODECHAL_ENCODE_CHK_NULL_RETURN(surface = m_trackedBuf->Get4xDsSurface(scaledIdx));
6277 refScaledSurface.OsResource = surface->OsResource;
6278 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
6279 }
6280
6281 // L1 Reference Picture Y - VME
6282 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6283 surfaceParams.bUseAdvState = true;
6284 surfaceParams.psSurface = &refScaledSurface;
6285 surfaceParams.dwOffset = refBottomField ? refScaledBottomFieldOffset : 0;
6286 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_REF_ENCODE].Value;
6287 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEBwdRefPicIdx[refIdx];
6288 surfaceParams.ucVDirection = (!currFieldPicture) ? CODECHAL_VDIRECTION_FRAME :
6289 ((refBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD);
6290 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
6291 m_hwInterface,
6292 cmdBuffer,
6293 &surfaceParams,
6294 params->pKernelState));
6295 }
6296 }
6297 return eStatus;
6298 }
6299
InitKernelStateBrc()6300 MOS_STATUS CodechalEncodeAvcEncG8::InitKernelStateBrc()
6301 {
6302 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6303
6304 CODECHAL_ENCODE_FUNCTION_ENTER;
6305
6306 uint8_t* kernelBinary;
6307 uint32_t kernelSize;
6308
6309 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuid, &kernelBinary, &kernelSize);
6310 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
6311
6312 // no extra MbBRCUpdate kernel for GEN8
6313 for (uint32_t krnStateIdx = 0; krnStateIdx < CODECHAL_ENCODE_BRC_IDX_NUM - 1; krnStateIdx++)
6314 {
6315 auto kernelStatePtr = &BrcKernelStates[krnStateIdx];
6316
6317 CODECHAL_KERNEL_HEADER currKrnHeader;
6318 CODECHAL_ENCODE_CHK_STATUS_RETURN(pfnGetKernelHeaderAndSize(
6319 kernelBinary,
6320 ENC_BRC,
6321 krnStateIdx,
6322 &currKrnHeader,
6323 &kernelSize));
6324
6325 auto renderEngineInterface = m_hwInterface->GetRenderInterface();
6326 auto stateHeapInterface = m_renderEngineInterface->m_stateHeapInterface;
6327 CODECHAL_ENCODE_CHK_NULL_RETURN(stateHeapInterface);
6328
6329 kernelStatePtr->KernelParams.iBTCount = m_brcBtCounts[krnStateIdx];
6330 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
6331 kernelStatePtr->KernelParams.iCurbeLength = m_brcCurbeSize[krnStateIdx];
6332 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
6333 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
6334 kernelStatePtr->KernelParams.iIdCount = 1;
6335
6336 kernelStatePtr->dwCurbeOffset = stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
6337 kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
6338 kernelStatePtr->KernelParams.iSize = kernelSize;
6339
6340 CODECHAL_ENCODE_CHK_STATUS_RETURN(stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
6341 stateHeapInterface,
6342 kernelStatePtr->KernelParams.iBTCount,
6343 &kernelStatePtr->dwSshSize,
6344 &kernelStatePtr->dwBindingTableSize));
6345
6346 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(stateHeapInterface, kernelStatePtr));
6347 }
6348
6349 // Until a better way can be found, maintain old binding table structures
6350 auto bindingTable = &BrcUpdateBindingTable;
6351 bindingTable->dwFrameBrcHistoryBuffer = BRC_UPDATE_HISTORY;
6352 bindingTable->dwFrameBrcPakStatisticsOutputBuffer = BRC_UPDATE_PAK_STATISTICS_OUTPUT;
6353 bindingTable->dwFrameBrcImageStateReadBuffer = BRC_UPDATE_IMAGE_STATE_READ;
6354 bindingTable->dwFrameBrcImageStateWriteBuffer = BRC_UPDATE_IMAGE_STATE_WRITE;
6355 bindingTable->dwFrameBrcMbEncCurbeReadBuffer = BRC_UPDATE_MBENC_CURBE_READ;
6356 bindingTable->dwFrameBrcMbEncCurbeWriteData = BRC_UPDATE_MBENC_CURBE_WRITE;
6357 bindingTable->dwFrameBrcDistortionBuffer = BRC_UPDATE_DISTORTION;
6358 bindingTable->dwFrameBrcConstantData = BRC_UPDATE_CONSTANT_DATA;
6359 bindingTable->dwMbBrcMbQpBuffer = BRC_UPDATE_MB_QP;
6360
6361 return eStatus;
6362 }
6363
SetCurbeMe(MeCurbeParams * params)6364 MOS_STATUS CodechalEncodeAvcEncG8::SetCurbeMe(MeCurbeParams* params)
6365 {
6366 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6367 CODECHAL_ENCODE_FUNCTION_ENTER;
6368
6369 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
6370 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
6371 CODECHAL_ENCODE_ASSERT(m_avcSeqParam->TargetUsage <= NUM_TARGET_USAGE_MODES);
6372
6373 uint8_t mvShiftFactor = 0;
6374 uint8_t prevMvReadPosFactor = 0;
6375 bool useMvFromPrevStep;
6376 bool writeDistortions;
6377 uint32_t scaleFactor;
6378 switch (params->hmeLvl)
6379 {
6380 case HME_LEVEL_32x:
6381 useMvFromPrevStep = m_hmeFirstStep;
6382 writeDistortions = false;
6383 scaleFactor = SCALE_FACTOR_32x;
6384 mvShiftFactor = m_mvShiftFactor32x;
6385 break;
6386 case HME_LEVEL_16x:
6387 useMvFromPrevStep = (m_32xMeEnabled) ? m_hmeFollowingStep : m_hmeFirstStep;
6388 writeDistortions = false;
6389 scaleFactor = SCALE_FACTOR_16x;
6390 mvShiftFactor = m_mvShiftFactor16x;
6391 prevMvReadPosFactor = m_prevMvReadPosition16x;
6392 break;
6393 case HME_LEVEL_4x:
6394 useMvFromPrevStep = (m_16xMeEnabled) ? m_hmeFollowingStep : m_hmeFirstStep;
6395 writeDistortions = true;
6396 scaleFactor = SCALE_FACTOR_4x;
6397 mvShiftFactor = m_mvShiftFactor4x;
6398 prevMvReadPosFactor = m_prevMvReadPosition8x;
6399 break;
6400 default:
6401 eStatus = MOS_STATUS_INVALID_PARAMETER;
6402 return eStatus;
6403 break;
6404 }
6405
6406 ME_CURBE_CM cmd;
6407
6408 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
6409 &cmd,
6410 sizeof(ME_CURBE_CM),
6411 m_initMeCurbeCm,
6412 sizeof(ME_CURBE_CM)));
6413
6414 // r1
6415 //cmd.DW0.T8x8FlagForInterEn = picParams->transform_8x8_mode_flag;
6416 cmd.DW3.SubPelMode = 3;
6417 if (m_fieldScalingOutputInterleaved)
6418 {
6419 cmd.DW3.SrcAccess =
6420 cmd.DW3.RefAccess = CodecHal_PictureIsField(m_avcPicParam->CurrOriginalPic) ? 1 : 0;
6421 cmd.DW7.SrcFieldPolarity = CodecHal_PictureIsBottomField(m_avcPicParam->CurrOriginalPic) ? 1 : 0;
6422 }
6423
6424 cmd.DW4.PictureHeightMinus1 =
6425 CODECHAL_GET_HEIGHT_IN_MACROBLOCKS(m_frameFieldHeight / scaleFactor) - 1;
6426 cmd.DW4.PictureWidth =
6427 CODECHAL_GET_HEIGHT_IN_MACROBLOCKS(m_frameWidth / scaleFactor);
6428
6429 char qpPrimeY =
6430 (m_avcPicParam->pic_init_qp_minus26 + 26) +
6431 m_avcSliceParams->slice_qp_delta;
6432
6433 cmd.DW5.QpPrimeY = qpPrimeY;
6434 cmd.DW6.WriteDistortions = writeDistortions;
6435 cmd.DW6.UseMvFromPrevStep = useMvFromPrevStep;
6436
6437 cmd.DW6.SuperCombineDist = m_superCombineDistGeneric[m_avcSeqParam->TargetUsage];
6438 bool framePicture = CodecHal_PictureIsFrame(m_avcPicParam->CurrOriginalPic);
6439 cmd.DW6.MaxVmvR = (framePicture) ?
6440 CodecHalAvcEncode_GetMaxMvLen(m_avcSeqParam->Level) * 4 :
6441 (CodecHalAvcEncode_GetMaxMvLen(m_avcSeqParam->Level) >> 1) * 4;
6442
6443 if (m_pictureCodingType == B_TYPE)
6444 {
6445 // This field is irrelevant since we are not using the bi-direct search.
6446 // set it to 32
6447 cmd.DW1.BiWeight = 32;
6448 cmd.DW13.NumRefIdxL1MinusOne =
6449 m_avcSliceParams->num_ref_idx_l1_active_minus1;
6450 }
6451
6452 if (m_pictureCodingType == P_TYPE ||
6453 m_pictureCodingType == B_TYPE)
6454 {
6455 cmd.DW13.NumRefIdxL0MinusOne =
6456 m_avcSliceParams->num_ref_idx_l0_active_minus1;
6457 }
6458
6459 if (!framePicture)
6460 {
6461 auto slcParams = m_avcSliceParams;
6462 if (m_pictureCodingType != I_TYPE)
6463 {
6464 cmd.DW14.List0RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_0);
6465 cmd.DW14.List0RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_1);
6466 cmd.DW14.List0RefID2FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_2);
6467 cmd.DW14.List0RefID3FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_3);
6468 cmd.DW14.List0RefID4FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_4);
6469 cmd.DW14.List0RefID5FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_5);
6470 cmd.DW14.List0RefID6FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_6);
6471 cmd.DW14.List0RefID7FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_7);
6472 }
6473 if (m_pictureCodingType == B_TYPE)
6474 {
6475 cmd.DW14.List1RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_0);
6476 cmd.DW14.List1RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_1);
6477 }
6478 }
6479
6480 cmd.DW15.MvShiftFactor = mvShiftFactor;
6481 cmd.DW15.PrevMvReadPosFactor = prevMvReadPosFactor;
6482
6483 // r3 & r4
6484 uint8_t meMethod = (m_pictureCodingType == B_TYPE) ? m_bMeMethodGeneric[m_avcSeqParam->TargetUsage] : m_meMethodGeneric[m_avcSeqParam->TargetUsage];
6485 uint8_t tableIdx = (m_pictureCodingType == B_TYPE) ? 1 : 0;
6486 eStatus = MOS_SecureMemcpy(&(cmd.SPDelta), 14 * sizeof(uint32_t), m_encodeSearchPath[tableIdx][meMethod], 14 * sizeof(uint32_t));
6487 if (eStatus != MOS_STATUS_SUCCESS)
6488 {
6489 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
6490 return eStatus;
6491 }
6492
6493 // r5
6494 cmd.DW32._4xMeMvOutputDataSurfIndex = ME_MV_DATA_SURFACE_CM;
6495 cmd.DW33._16xOr32xMeMvInputDataSurfIndex = (params->hmeLvl == HME_LEVEL_32x) ?
6496 ME_32x_MV_DATA_SURFACE_CM : ME_16x_MV_DATA_SURFACE_CM;
6497 cmd.DW34._4xMeOutputDistSurfIndex = ME_DISTORTION_SURFACE_CM;
6498 cmd.DW35._4xMeOutputBrcDistSurfIndex = ME_BRC_DISTORTION_CM;
6499 cmd.DW36.VMEFwdInterPredictionSurfIndex = ME_CURR_FOR_FWD_REF_CM;
6500 cmd.DW37.VMEBwdInterPredictionSurfIndex = ME_CURR_FOR_BWD_REF_CM;
6501 cmd.DW38.Value = 0; //MBZ for BDW
6502 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
6503 &cmd,
6504 params->pKernelState->dwCurbeOffset,
6505 sizeof(cmd)));
6506
6507 return eStatus;
6508 }
6509
UpdateSSDSliceCount()6510 void CodechalEncodeAvcEncG8::UpdateSSDSliceCount()
6511 {
6512 CodechalEncodeAvcBase::UpdateSSDSliceCount();
6513
6514 uint32_t sliceCount;
6515 if ((m_frameHeight * m_frameWidth >= 1920*1080 && m_targetUsage <= 4) ||
6516 (m_frameHeight * m_frameWidth >= 1280*720 && m_targetUsage <= 2) ||
6517 (m_frameHeight * m_frameWidth >= 3840*2160))
6518 {
6519 sliceCount = 2;
6520 }
6521 else
6522 {
6523 sliceCount = 1;
6524 }
6525
6526 if (m_osInterface->pfnSetSliceCount)
6527 {
6528 m_osInterface->pfnSetSliceCount(m_osInterface, &sliceCount);
6529 }
6530 }
6531
6532