1 /*
2 * Copyright (c) 2021-2023, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codec_hw_next.cpp
24 //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across CODECHAL components.
25 //!
26 #include "codec_hw_next.h"
27 #include "codechal_setting.h"
28 #include "mos_os_cp_interface_specific.h"
29 #include "mhw_vdbox_vvcp_itf.h"
30
CodechalHwInterfaceNext(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfacesNext * mhwInterfacesNext,bool disableScalability)31 CodechalHwInterfaceNext::CodechalHwInterfaceNext(
32 PMOS_INTERFACE osInterface,
33 CODECHAL_FUNCTION codecFunction,
34 MhwInterfacesNext *mhwInterfacesNext,
35 bool disableScalability)
36 {
37 CODEC_HW_FUNCTION_ENTER;
38
39 m_avpItf = mhwInterfacesNext->m_avpItf;
40 m_vdencItf = mhwInterfacesNext->m_vdencItf;
41 m_hucItf = mhwInterfacesNext->m_hucItf;
42 m_miItf = mhwInterfacesNext->m_miItf;
43 m_hcpItf = mhwInterfacesNext->m_hcpItf;
44 m_mfxItf = mhwInterfacesNext->m_mfxItf;
45 m_renderItf = mhwInterfacesNext->m_renderItf;
46 m_vvcpItf = mhwInterfacesNext->m_vvcpItf;
47
48 CODEC_HW_ASSERT(osInterface);
49 m_osInterface = osInterface;
50
51 MOS_ZeroMemory(&m_platform, sizeof(PLATFORM));
52 m_osInterface->pfnGetPlatform(m_osInterface, &m_platform);
53
54 m_skuTable = m_osInterface->pfnGetSkuTable(m_osInterface);
55 m_waTable = m_osInterface->pfnGetWaTable(m_osInterface);
56 CODEC_HW_ASSERT(m_skuTable);
57 CODEC_HW_ASSERT(m_waTable);
58
59 MOS_ZeroMemory(&m_hucDmemDummy, sizeof(m_hucDmemDummy));
60 MOS_ZeroMemory(&m_dummyStreamIn, sizeof(m_dummyStreamIn));
61 MOS_ZeroMemory(&m_dummyStreamOut, sizeof(m_dummyStreamOut));
62 MOS_ZeroMemory(&m_conditionalBbEndDummy, sizeof(m_conditionalBbEndDummy));
63
64 // Remove legacy mhw sub interfaces.
65 m_cpInterface = mhwInterfacesNext->m_cpInterface;
66 m_veboxInterface = mhwInterfacesNext->m_veboxInterface;
67 m_sfcInterface = mhwInterfacesNext->m_sfcInterface;
68 //Prevent double free
69 mhwInterfacesNext->m_cpInterface = nullptr;
70 mhwInterfacesNext->m_veboxInterface = nullptr;
71 mhwInterfacesNext->m_sfcInterface = nullptr;
72
73 m_disableScalability = disableScalability;
74 m_userSettingPtr = osInterface->pfnGetUserSettingInstance(osInterface);
75 }
76
~CodechalHwInterfaceNext()77 CodechalHwInterfaceNext::~CodechalHwInterfaceNext()
78 {
79 CODEC_HW_FUNCTION_ENTER;
80
81 if (m_osInterface != nullptr)
82 {
83 m_osInterface->pfnFreeResource(m_osInterface, &m_hucDmemDummy);
84 m_osInterface->pfnFreeResource(m_osInterface, &m_dummyStreamIn);
85 m_osInterface->pfnFreeResource(m_osInterface, &m_dummyStreamOut);
86
87 m_osInterface->pfnFreeResource(m_osInterface, &m_conditionalBbEndDummy);
88 if (m_cpInterface)
89 {
90 m_osInterface->pfnDeleteMhwCpInterface(m_cpInterface);
91 m_cpInterface = nullptr;
92 }
93 }
94
95 if (m_veboxInterface)
96 {
97 m_veboxInterface->DestroyHeap();
98 MOS_Delete(m_veboxInterface);
99 m_veboxInterface = nullptr;
100 }
101
102 if (m_sfcInterface)
103 {
104 MOS_Delete(m_sfcInterface);
105 m_sfcInterface = nullptr;
106 }
107 }
108
Create(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfacesNext * mhwInterfacesNext,bool disableScalability)109 CodechalHwInterfaceNext* CodechalHwInterfaceNext::Create(
110 PMOS_INTERFACE osInterface,
111 CODECHAL_FUNCTION codecFunction,
112 MhwInterfacesNext* mhwInterfacesNext,
113 bool disableScalability)
114 {
115 return MOS_New(CodechalHwInterfaceNext,
116 osInterface,
117 codecFunction,
118 mhwInterfacesNext,
119 disableScalability);
120 }
121
Initialize(CodechalSetting * settings)122 MOS_STATUS CodechalHwInterfaceNext::Initialize(
123 CodechalSetting *settings)
124 {
125 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
126 MediaUserSettingSharedPtr userSettingPtr = nullptr;
127 uint32_t value = 0;
128
129 CODEC_HW_FUNCTION_ENTER;
130
131 if (UsesRenderEngine(settings->codecFunction, settings->standard) ||
132 CodecHalIsEnableFieldScaling(settings->codecFunction, settings->standard, settings->downsamplingHinted))
133 {
134 CODEC_HW_CHK_NULL_RETURN(m_renderItf);
135
136 m_stateHeapSettings.m_ishBehavior = HeapManager::Behavior::clientControlled;
137 m_stateHeapSettings.m_dshBehavior = HeapManager::Behavior::destructiveExtend;
138 // As a performance optimization keep the DSH locked always,
139 // the ISH is only accessed at device creation and thus does not need to be locked
140 m_stateHeapSettings.m_keepDshLocked = true;
141 m_stateHeapSettings.dwDshIncrement = 2 * MOS_PAGE_SIZE;
142
143 if (m_stateHeapSettings.dwIshSize > 0 &&
144 m_stateHeapSettings.dwDshSize > 0 &&
145 m_stateHeapSettings.dwNumSyncTags > 0)
146 {
147 CODEC_HW_CHK_STATUS_RETURN(m_renderItf->AllocateHeaps(
148 m_stateHeapSettings));
149 }
150 }
151
152 #if (_DEBUG || _RELEASE_INTERNAL)
153 userSettingPtr = m_osInterface->pfnGetUserSettingInstance(m_osInterface);
154 ReadUserSettingForDebug(
155 userSettingPtr,
156 value,
157 __MEDIA_USER_FEATURE_VALUE_SSEU_SETTING_OVERRIDE,
158 MediaUserSetting::Group::Device);
159
160 if (value != 0xDEADC0DE)
161 {
162 m_numRequestedEuSlicesOverride = value & 0xFF; // Bits 0-7
163 m_numRequestedSubSlicesOverride = (value >> 8) & 0xFF; // Bits 8-15
164 m_numRequestedEusOverride = (value >> 16) & 0xFFFF; // Bits 16-31
165 m_numRequestedOverride = true;
166 }
167 #endif
168
169 m_enableCodecMmc = !MEDIA_IS_WA(GetWaTable(), WaDisableCodecMmc);
170
171 return eStatus;
172 }
173
InitCacheabilityControlSettings(CODECHAL_FUNCTION codecFunction)174 MOS_STATUS CodechalHwInterfaceNext::InitCacheabilityControlSettings(
175 CODECHAL_FUNCTION codecFunction)
176 {
177 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
178
179 CODEC_HW_FUNCTION_ENTER;
180
181 CODEC_HW_CHK_NULL_RETURN(m_osInterface);
182
183 for (uint32_t i = MOS_CODEC_RESOURCE_USAGE_BEGIN_CODEC + 1; i < MOS_CODEC_RESOURCE_USAGE_END_CODEC; i++)
184 {
185 CODEC_HW_CHK_STATUS_RETURN(CachePolicyGetMemoryObject(
186 (MOS_HW_RESOURCE_DEF)i));
187 }
188
189 SetCacheabilitySettings(m_cacheabilitySettings);
190
191 bool l3CachingEnabled = !m_osInterface->bSimIsActive;
192
193 if (m_checkBankCount)
194 {
195 CODEC_HW_CHK_NULL_RETURN(m_osInterface);
196 auto gtSysInfo = m_osInterface->pfnGetGtSystemInfo(m_osInterface);
197 CODEC_HW_CHK_NULL_RETURN(gtSysInfo);
198
199 l3CachingEnabled = (gtSysInfo->L3BankCount != 0 || gtSysInfo->L3CacheSizeInKb != 0);
200 }
201
202 if (l3CachingEnabled)
203 {
204 InitL3CacheSettings();
205 }
206
207 return eStatus;
208 }
209
CachePolicyGetMemoryObject(MOS_HW_RESOURCE_DEF mosUsage)210 MOS_STATUS CodechalHwInterfaceNext::CachePolicyGetMemoryObject(
211 MOS_HW_RESOURCE_DEF mosUsage)
212 {
213 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
214
215 m_cacheabilitySettings[mosUsage].Value =
216 (m_osInterface->pfnCachePolicyGetMemoryObject(
217 mosUsage,
218 m_osInterface->pfnGetGmmClientContext(m_osInterface))).DwordValue;
219
220 return eStatus;
221 }
222
CodechalHwInterfaceNext(PMOS_INTERFACE osInterface,bool disableScalability)223 CodechalHwInterfaceNext::CodechalHwInterfaceNext(
224 PMOS_INTERFACE osInterface,
225 bool disableScalability)
226 {
227 CODEC_HW_ASSERT(osInterface);
228 m_osInterface = osInterface;
229
230 m_skuTable = m_osInterface->pfnGetSkuTable(m_osInterface);
231 m_waTable = m_osInterface->pfnGetWaTable(m_osInterface);
232 CODEC_HW_ASSERT(m_skuTable);
233 CODEC_HW_ASSERT(m_waTable);
234
235 MOS_ZeroMemory(&m_hucDmemDummy, sizeof(m_hucDmemDummy));
236 MOS_ZeroMemory(&m_dummyStreamIn, sizeof(m_dummyStreamIn));
237 MOS_ZeroMemory(&m_dummyStreamOut, sizeof(m_dummyStreamOut));
238
239 MOS_ZeroMemory(&m_conditionalBbEndDummy, sizeof(m_conditionalBbEndDummy));
240
241 m_enableCodecMmc = !MEDIA_IS_WA(GetWaTable(), WaDisableCodecMmc);
242 m_disableScalability = disableScalability;
243 }
GetAvpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)244 MOS_STATUS CodechalHwInterfaceNext::GetAvpStateCommandSize(
245 uint32_t mode,
246 uint32_t *commandsSize,
247 uint32_t *patchListSize,
248 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
249 {
250 CODEC_HW_FUNCTION_ENTER;
251
252 //calculate AVP related commands size
253 uint32_t avpCommandsSize = 0;
254 uint32_t avpPatchListSize = 0;
255 uint32_t cpCmdsize = 0;
256 uint32_t cpPatchListSize = 0;
257
258 if (m_avpItf)
259 {
260 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->GetAvpStateCmdSize(
261 (uint32_t *)&avpCommandsSize,
262 (uint32_t *)&avpPatchListSize,
263 params));
264 }
265
266 if (m_cpInterface != nullptr)
267 {
268 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
269 }
270
271 //Calc final command size
272 *commandsSize = avpCommandsSize + cpCmdsize;
273 *patchListSize = avpPatchListSize + cpPatchListSize;
274
275 return MOS_STATUS_SUCCESS;
276 }
277
GetMfxStateCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool shortFormat)278 MOS_STATUS CodechalHwInterfaceNext::GetMfxStateCommandsDataSize(
279 uint32_t mode,
280 uint32_t *commandsSize,
281 uint32_t *patchListSize,
282 bool shortFormat)
283 {
284 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
285
286 CODEC_HW_FUNCTION_ENTER;
287
288 uint32_t cpCmdsize = 0;
289 uint32_t cpPatchListSize = 0;
290
291 if (m_mfxItf)
292 {
293 CODEC_HW_CHK_STATUS_RETURN(m_mfxItf->GetMfxStateCommandsDataSize(
294 mode, (uint32_t *)commandsSize, (uint32_t *)patchListSize, shortFormat ? true : false));
295
296 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
297 }
298 *commandsSize += (uint32_t)cpCmdsize;
299 *patchListSize += (uint32_t)cpPatchListSize;
300
301 return eStatus;
302 }
303
GetAvpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)304 MOS_STATUS CodechalHwInterfaceNext::GetAvpPrimitiveCommandSize(
305 uint32_t mode,
306 uint32_t *commandsSize,
307 uint32_t *patchListSize)
308 {
309 CODEC_HW_FUNCTION_ENTER;
310
311 //calculate AVP related commands size
312 MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams;
313
314 if (mode == CODECHAL_DECODE_MODE_AV1VLD)
315 {
316 stateCmdSizeParams.bDecodeInUse = true;
317 }
318
319 uint32_t avpCommandsSize = 0;
320 uint32_t avpPatchListSize = 0;
321 uint32_t cpCmdsize = 0;
322 uint32_t cpPatchListSize = 0;
323
324 if (m_avpItf)
325 {
326 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->GetAvpPrimitiveCmdSize(
327 (uint32_t*)&avpCommandsSize,
328 (uint32_t*)&avpPatchListSize,
329 &stateCmdSizeParams));
330 }
331
332 if (m_cpInterface)
333 {
334 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
335 }
336
337 //Calc final command size
338 *commandsSize = avpCommandsSize + cpCmdsize;
339 *patchListSize = avpPatchListSize + cpPatchListSize;
340
341 return MOS_STATUS_SUCCESS;
342 }
343
GetVdencPictureSecondLevelCommandsSize(uint32_t mode,uint32_t * commandsSize)344 MOS_STATUS CodechalHwInterfaceNext::GetVdencPictureSecondLevelCommandsSize(
345 uint32_t mode,
346 uint32_t *commandsSize)
347 {
348 CODEC_HW_FUNCTION_ENTER;
349
350 uint32_t commands = 0;
351
352 MHW_MI_CHK_NULL(m_hcpItf);
353
354 uint32_t standard = CodecHal_GetStandardFromMode(mode);
355
356 if (standard == CODECHAL_VP9)
357 {
358 commands += m_hcpItf->GetHcpVp9PicStateCommandSize();
359 commands += m_hcpItf->GetHcpVp9SegmentStateCommandSize() * 8;
360 commands += 132;
361 commands += 248;
362 commands += m_sizeOfCmdBatchBufferEnd;
363 commands += 24; // padding for alignment on 64
364 }
365 else
366 {
367 MHW_ASSERTMESSAGE("Unsupported encode mode.");
368 return MOS_STATUS_UNKNOWN;
369 }
370
371 *commandsSize = commands;
372
373 return MOS_STATUS_SUCCESS;
374 }
375
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])376 MOS_STATUS CodechalHwInterfaceNext::SetCacheabilitySettings(
377 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
378 {
379 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
380
381 CODEC_HW_FUNCTION_ENTER;
382
383 /* New Mhw sub interfaces usage */
384 if (m_avpItf)
385 {
386 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->SetCacheabilitySettings(cacheabilitySettings));
387 }
388 if (m_hcpItf)
389 {
390 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->SetCacheabilitySettings(cacheabilitySettings));
391 }
392 if (m_mfxItf)
393 {
394 CODEC_HW_CHK_STATUS_RETURN(m_mfxItf->SetCacheabilitySettings(cacheabilitySettings));
395 }
396 if (m_vdencItf)
397 {
398 CODEC_HW_CHK_STATUS_RETURN(m_vdencItf->SetCacheabilitySettings(cacheabilitySettings));
399 }
400 if (m_vvcpItf != nullptr)
401 {
402 CODEC_HW_CHK_STATUS_RETURN(m_vvcpItf->SetCacheabilitySettings(cacheabilitySettings));
403 }
404
405 return eStatus;
406 }
407
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)408 MOS_STATUS CodechalHwInterfaceNext::GetHucStateCommandSize(
409 uint32_t mode,
410 uint32_t* commandsSize,
411 uint32_t* patchListSize,
412 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
413
414 {
415 MHW_FUNCTION_ENTER;
416
417 uint32_t maxSize = 0;
418 uint32_t patchListMaxSize = 0;
419 uint32_t standard = CodecHal_GetStandardFromMode(mode);
420 uint32_t numSlices = 1;
421 uint32_t numStoreDataImm = 1;
422 uint32_t numStoreReg = 1;
423
424 MHW_MI_CHK_NULL(commandsSize);
425 MHW_MI_CHK_NULL(patchListSize);
426 MHW_MI_CHK_NULL(params);
427
428 if(params->uNumStoreDataImm)
429 {
430 numStoreDataImm = params->uNumStoreDataImm;
431 }
432 if(params->uNumStoreReg)
433 {
434 numStoreReg = params->uNumStoreReg;
435 }
436
437 if (mode == CODECHAL_DECODE_MODE_HEVCVLD && params->bShortFormat)
438 {
439 numSlices = CODECHAL_HEVC_MAX_NUM_SLICES_LVL_6;
440 numStoreDataImm = 2;
441 numStoreReg = 2;
442
443 maxSize +=
444 2 * m_miItf->MHW_GETSIZE_F(MI_CONDITIONAL_BATCH_BUFFER_END)();
445
446 patchListMaxSize +=
447 2 * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_CONDITIONAL_BATCH_BUFFER_END_CMD);
448 }
449 else if (standard == CODECHAL_CENC)
450 {
451 numStoreDataImm = 3;
452 numStoreReg = 3;
453
454 maxSize +=
455 m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)() * 2 +
456 m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
457
458 patchListMaxSize +=
459 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_FLUSH_DW_CMD) * 2;
460
461 }
462 else if (mode == CODECHAL_ENCODE_MODE_VP9)
463 {
464 // for huc status 2 register and semaphore signal and reset
465 numStoreDataImm = 3;
466
467 maxSize +=
468 m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)() +
469 m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
470
471 patchListMaxSize +=
472 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_FLUSH_DW_CMD);
473 }
474 else if (mode == CODECHAL_ENCODE_MODE_AVC)
475 {
476 numStoreDataImm = 2;
477 numStoreReg = 2;
478
479 maxSize +=
480 2 * m_miItf->MHW_GETSIZE_F(MI_CONDITIONAL_BATCH_BUFFER_END)();
481
482 patchListMaxSize +=
483 2 * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_CONDITIONAL_BATCH_BUFFER_END_CMD);
484 }
485
486 maxSize +=
487 m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)() +
488 m_hucItf->MHW_GETSIZE_F(HUC_IMEM_STATE)() +
489 m_hucItf->MHW_GETSIZE_F(HUC_DMEM_STATE)() +
490 m_hucItf->MHW_GETSIZE_F(HUC_VIRTUAL_ADDR_STATE)() +
491 m_hucItf->MHW_GETSIZE_F(HUC_IND_OBJ_BASE_ADDR_STATE)() +
492 numSlices * m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)() +
493 numSlices * m_hucItf->MHW_GETSIZE_F(HUC_START)() +
494 numStoreDataImm * m_miItf->MHW_GETSIZE_F(MI_STORE_DATA_IMM)() +
495 numStoreReg * m_miItf->MHW_GETSIZE_F(MI_STORE_REGISTER_MEM)();
496
497 if(params->uNumMfxWait)
498 {
499 maxSize +=
500 params->uNumMfxWait * m_miItf->MHW_GETSIZE_F(MFX_WAIT)();
501 }
502
503 patchListMaxSize +=
504 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_PIPE_MODE_SELECT_CMD) +
505 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_IMEM_STATE_CMD) +
506 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_DMEM_STATE_CMD) +
507 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_VIRTUAL_ADDR_STATE_CMD) +
508 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_IND_OBJ_BASE_ADDR_STATE_CMD) +
509 numSlices * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_STREAM_OBJECT_CMD) +
510 numSlices * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_START_CMD) +
511 numStoreDataImm * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_STORE_DATA_IMM_CMD) +
512 numStoreReg * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_STORE_REGISTER_MEM_CMD);
513
514 if(params->uNumAddConBBEnd)
515 {
516 maxSize +=
517 params->uNumAddConBBEnd * m_miItf->MHW_GETSIZE_F(MI_CONDITIONAL_BATCH_BUFFER_END)();
518
519 patchListMaxSize +=
520 params->uNumAddConBBEnd * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_CONDITIONAL_BATCH_BUFFER_END_CMD);
521 }
522 if(params->uNumMiCopy)
523 {
524 maxSize +=
525 params->uNumMiCopy * m_miItf->MHW_GETSIZE_F(MI_COPY_MEM_MEM)();
526
527 patchListMaxSize +=
528 params->uNumMiCopy * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_COPY_MEM_MEM_CMD);
529 }
530 if(params->uNumMiFlush)
531 {
532 maxSize +=
533 params->uNumMiFlush * m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
534
535 patchListMaxSize +=
536 params->uNumMiFlush * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_FLUSH_DW_CMD);
537 }
538
539 if (params->bHucDummyStream || params->bPerformHucStreamOut)
540 {
541 uint32_t dummyTimes = params->bPerformHucStreamOut ? 2: 1;
542 for (uint32_t i = 0; i < dummyTimes; i++)
543 {
544 maxSize +=
545 m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)() +
546 m_hucItf->MHW_GETSIZE_F(HUC_IMEM_STATE)() +
547 m_hucItf->MHW_GETSIZE_F(HUC_DMEM_STATE)() +
548 m_hucItf->MHW_GETSIZE_F(HUC_VIRTUAL_ADDR_STATE)() +
549 m_hucItf->MHW_GETSIZE_F(HUC_IND_OBJ_BASE_ADDR_STATE)() +
550 m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)() +
551 m_hucItf->MHW_GETSIZE_F(HUC_START)() +
552 m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
553
554 patchListMaxSize +=
555 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_PIPE_MODE_SELECT_CMD) +
556 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_IMEM_STATE_CMD) +
557 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_DMEM_STATE_CMD) +
558 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_VIRTUAL_ADDR_STATE_CMD) +
559 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_IND_OBJ_BASE_ADDR_STATE_CMD) +
560 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_STREAM_OBJECT_CMD) +
561 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_START_CMD) +
562 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_FLUSH_DW_CMD);
563 }
564 if (params->bPerformHucStreamOut)
565 {
566 maxSize +=
567 m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)() +
568 m_hucItf->MHW_GETSIZE_F(HUC_IND_OBJ_BASE_ADDR_STATE)() +
569 m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)() +
570 4 * m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
571
572 patchListMaxSize +=
573 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_PIPE_MODE_SELECT_CMD) +
574 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_IND_OBJ_BASE_ADDR_STATE_CMD) +
575 PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::HUC_STREAM_OBJECT_CMD) +
576 4 * PATCH_LIST_COMMAND(mhw::vdbox::huc::Itf::MI_FLUSH_DW_CMD);
577 }
578 }
579
580 *commandsSize = maxSize;
581 *patchListSize = patchListMaxSize;
582
583 return MOS_STATUS_SUCCESS;
584 }
585
GetMfxPrimitiveCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)586 MOS_STATUS CodechalHwInterfaceNext::GetMfxPrimitiveCommandsDataSize(
587 uint32_t mode,
588 uint32_t *commandsSize,
589 uint32_t *patchListSize,
590 bool modeSpecific)
591 {
592 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
593
594 CODEC_HW_FUNCTION_ENTER;
595
596 uint32_t cpCmdsize = 0;
597 uint32_t cpPatchListSize = 0;
598
599 if (m_mfxItf)
600 {
601 CODEC_HW_CHK_STATUS_RETURN(m_mfxItf->GetMfxPrimitiveCommandsDataSize(
602 mode, (uint32_t*)commandsSize, (uint32_t*)patchListSize, modeSpecific ? true : false));
603
604 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
605 }
606
607 *commandsSize += (uint32_t)cpCmdsize;
608 *patchListSize += (uint32_t)cpPatchListSize;
609
610 return eStatus;
611 }
612
GetHcpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)613 MOS_STATUS CodechalHwInterfaceNext::GetHcpPrimitiveCommandSize(
614 uint32_t mode,
615 uint32_t *commandsSize,
616 uint32_t *patchListSize,
617 bool modeSpecific)
618 {
619 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
620
621 CODEC_HW_FUNCTION_ENTER;
622
623 uint32_t standard = CodecHal_GetStandardFromMode(mode);
624
625 uint32_t hcpCommandsSize = 0;
626 uint32_t hcpPatchListSize = 0;
627 uint32_t cpCmdsize = 0;
628 uint32_t cpPatchListSize = 0;
629
630 if (m_hcpItf && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
631 {
632 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->GetHcpPrimitiveCommandSize(
633 mode, &hcpCommandsSize, &hcpPatchListSize, modeSpecific ? true : false));
634
635 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
636 }
637
638 *commandsSize = hcpCommandsSize + cpCmdsize;
639 *patchListSize = hcpPatchListSize + cpPatchListSize;
640
641 return eStatus;
642 }
643
GetVvcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)644 MOS_STATUS CodechalHwInterfaceNext::GetVvcpStateCommandSize(
645 uint32_t mode,
646 uint32_t *commandsSize,
647 uint32_t *patchListSize,
648 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
649 {
650 CODEC_HW_FUNCTION_ENTER;
651
652 //calculate VVCP related commands size
653 uint32_t vvcpCommandsSize = 0;
654 uint32_t vvcpPatchListSize = 0;
655 uint32_t cpCmdsize = 0;
656 uint32_t cpPatchListSize = 0;
657
658 if (m_vvcpItf)
659 {
660 CODEC_HW_CHK_STATUS_RETURN(m_vvcpItf->GetVvcpStateCmdSize(
661 (uint32_t *)&vvcpCommandsSize,
662 (uint32_t *)&vvcpPatchListSize,
663 params));
664 }
665
666 if (m_cpInterface)
667 {
668 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
669 }
670
671 //Calc final command size
672 *commandsSize = vvcpCommandsSize + cpCmdsize;
673 *patchListSize = vvcpPatchListSize + cpPatchListSize;
674
675 return MOS_STATUS_SUCCESS;
676 }
677
GetVvcpSliceLvlCmdSize(uint32_t * sliceLvlCmdSize)678 MOS_STATUS CodechalHwInterfaceNext::GetVvcpSliceLvlCmdSize(uint32_t *sliceLvlCmdSize)
679 {
680 CODEC_HW_FUNCTION_ENTER;
681 if (m_vvcpItf)
682 {
683 CODEC_HW_CHK_STATUS_RETURN(m_vvcpItf->GetVvcpSliceLvlCmdSize(sliceLvlCmdSize));
684 }
685 return MOS_STATUS_SUCCESS;
686 }
687
GetVvcpPrimitiveCommandSize(uint32_t mode,uint32_t * sliceCommandsSize,uint32_t * slicePatchListSize,uint32_t * tileCommandsSize,uint32_t * tilePatchListSize)688 MOS_STATUS CodechalHwInterfaceNext::GetVvcpPrimitiveCommandSize(
689 uint32_t mode,
690 uint32_t *sliceCommandsSize,
691 uint32_t *slicePatchListSize,
692 uint32_t *tileCommandsSize,
693 uint32_t *tilePatchListSize)
694 {
695 CODEC_HW_FUNCTION_ENTER;
696
697 //calculate VVCP related commands size
698 uint32_t vvcpSliceCommandsSize = 0;
699 uint32_t vvcpSlicePatchListSize = 0;
700 uint32_t vvcpTileCommandsSize = 0;
701 uint32_t vvcpTilePatchListSize = 0;
702 uint32_t cpCmdsize = 0;
703 uint32_t cpPatchListSize = 0;
704
705 if (m_vvcpItf)
706 {
707 CODEC_HW_CHK_STATUS_RETURN(m_vvcpItf->GetVvcpPrimitiveCmdSize(
708 (uint32_t *)&vvcpSliceCommandsSize,
709 (uint32_t *)&vvcpSlicePatchListSize,
710 (uint32_t *)&vvcpTileCommandsSize,
711 (uint32_t *)&vvcpTilePatchListSize));
712 }
713
714 if (m_cpInterface)
715 {
716 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
717 }
718
719 //Calc final command size
720 *sliceCommandsSize = vvcpSliceCommandsSize + cpCmdsize;
721 *slicePatchListSize = vvcpSlicePatchListSize + cpPatchListSize;
722 *tileCommandsSize = vvcpTileCommandsSize;
723 *tilePatchListSize = vvcpTilePatchListSize;
724
725 return MOS_STATUS_SUCCESS;
726 }
727
AddHucDummyStreamOut(PMOS_COMMAND_BUFFER cmdBuffer)728 MOS_STATUS CodechalHwInterfaceNext::AddHucDummyStreamOut(
729 PMOS_COMMAND_BUFFER cmdBuffer)
730 {
731 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
732
733 if (!MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable))
734 {
735 return eStatus;
736 }
737
738 CODEC_HW_FUNCTION_ENTER;
739
740 CODEC_HW_CHK_NULL_RETURN(cmdBuffer);
741 CODEC_HW_CHK_NULL_RETURN(m_miItf);
742
743 if (Mos_ResourceIsNull(&m_dummyStreamOut))
744 {
745 MOS_LOCK_PARAMS lockFlags;
746 uint8_t* data;
747 MOS_ALLOC_GFXRES_PARAMS allocParamsForBufferLinear;
748
749 MOS_ZeroMemory(&allocParamsForBufferLinear, sizeof(MOS_ALLOC_GFXRES_PARAMS));
750 allocParamsForBufferLinear.Type = MOS_GFXRES_BUFFER;
751 allocParamsForBufferLinear.TileType = MOS_TILE_LINEAR;
752 allocParamsForBufferLinear.Format = Format_Buffer;
753
754 m_dmemBufSize = MHW_CACHELINE_SIZE;
755
756 allocParamsForBufferLinear.dwBytes = m_dmemBufSize;
757 allocParamsForBufferLinear.pBufName = "HucDmemBufferDummy";
758 CODEC_HW_CHK_STATUS_RETURN((MOS_STATUS)m_osInterface->pfnAllocateResource(
759 m_osInterface,
760 &allocParamsForBufferLinear,
761 &m_hucDmemDummy));
762 // set lock flag to WRITE_ONLY
763 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
764 lockFlags.WriteOnly = 1;
765 data =
766 (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, &m_hucDmemDummy, &lockFlags);
767 CODEC_HW_CHK_NULL_RETURN(data);
768 MOS_ZeroMemory(data, m_dmemBufSize);
769 *data = 8;
770 m_osInterface->pfnUnlockResource(m_osInterface, &m_hucDmemDummy);
771
772 allocParamsForBufferLinear.dwBytes = CODECHAL_CACHELINE_SIZE;
773
774 allocParamsForBufferLinear.pBufName = "HucDummyStreamInBuffer";
775 CODEC_HW_CHK_STATUS_RETURN(m_osInterface->pfnAllocateResource(
776 m_osInterface,
777 &allocParamsForBufferLinear,
778 &m_dummyStreamIn));
779 allocParamsForBufferLinear.pBufName = "HucDummyStreamOutBuffer";
780 CODEC_HW_CHK_STATUS_RETURN(m_osInterface->pfnAllocateResource(
781 m_osInterface,
782 &allocParamsForBufferLinear,
783 &m_dummyStreamOut));
784 }
785
786 auto &flushDwParams = m_miItf->MHW_GETPAR_F(MI_FLUSH_DW)();
787 flushDwParams = {};
788 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
789
790 // pipe mode select
791 auto &pipeModeSelectParams = m_hucItf->MHW_GETPAR_F(HUC_PIPE_MODE_SELECT)();
792 pipeModeSelectParams = {};
793
794 pipeModeSelectParams.mediaSoftResetCounterValue = 2400;
795
796 // pass bit-stream buffer by Ind Obj Addr command. Set size to 1 for dummy stream
797 auto &indObjParams = m_hucItf->MHW_GETPAR_F(HUC_IND_OBJ_BASE_ADDR_STATE)();
798 indObjParams = {};
799 indObjParams.DataBuffer = &m_dummyStreamIn;
800 indObjParams.DataSize = 1;
801 indObjParams.StreamOutObjectBuffer = &m_dummyStreamOut;
802 indObjParams.StreamOutObjectSize = 1;
803
804 // set stream object with stream out enabled
805 auto &streamObjParams = m_hucItf->MHW_GETPAR_F(HUC_STREAM_OBJECT)();
806 streamObjParams = {};
807 streamObjParams.IndirectStreamInDataLength = 1;
808 streamObjParams.IndirectStreamInStartAddress = 0;
809 streamObjParams.HucProcessing = true;
810 streamObjParams.IndirectStreamOutStartAddress = 0;
811 streamObjParams.StreamOut = 1;
812
813 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
814
815 auto &imemParams = m_hucItf->MHW_GETPAR_F(HUC_IMEM_STATE)();
816 imemParams = {};
817 imemParams.kernelDescriptor = VDBOX_HUC_VDENC_BRC_INIT_KERNEL_DESCRIPTOR;
818
819 // set HuC DMEM param
820 auto &dmemParams = m_hucItf->MHW_GETPAR_F(HUC_DMEM_STATE)();
821 dmemParams = {};
822 dmemParams.hucDataSource = &m_hucDmemDummy;
823 dmemParams.dataLength = m_dmemBufSize;
824 dmemParams.dmemOffset = HUC_DMEM_OFFSET_RTOS_GEMS;
825
826 auto &virtualAddrParams = m_hucItf->MHW_GETPAR_F(HUC_VIRTUAL_ADDR_STATE)();
827 virtualAddrParams = {};
828 virtualAddrParams.regionParams[0].presRegion = &m_dummyStreamOut;
829
830 streamObjParams.HucProcessing = true;
831 streamObjParams.HucBitstreamEnable = 1;
832
833 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_IMEM_STATE)(cmdBuffer));
834 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_PIPE_MODE_SELECT)(cmdBuffer));
835 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_DMEM_STATE)(cmdBuffer));
836 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_VIRTUAL_ADDR_STATE)(cmdBuffer));
837 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_IND_OBJ_BASE_ADDR_STATE)(cmdBuffer));
838 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_STREAM_OBJECT)(cmdBuffer));
839 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_START)(cmdBuffer));
840
841 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
842
843 return eStatus;
844 }
845
PerformHucStreamOut(CodechalHucStreamoutParams * hucStreamOutParams,PMOS_COMMAND_BUFFER cmdBuffer)846 MOS_STATUS CodechalHwInterfaceNext::PerformHucStreamOut(
847 CodechalHucStreamoutParams *hucStreamOutParams,
848 PMOS_COMMAND_BUFFER cmdBuffer)
849 {
850 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
851
852 CODEC_HW_FUNCTION_ENTER;
853 CODEC_HW_CHK_NULL_RETURN(cmdBuffer);
854
855 if (MEDIA_IS_SKU(m_skuTable, FtrEnableMediaKernels) && MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable))
856 {
857 CODEC_HW_CHK_STATUS_RETURN(AddHucDummyStreamOut(cmdBuffer));
858 }
859
860 // pipe mode select
861 auto &pipeModeSelectParams = m_hucItf->MHW_GETPAR_F(HUC_PIPE_MODE_SELECT)();
862 pipeModeSelectParams = {};
863 pipeModeSelectParams.mode = hucStreamOutParams->mode;
864 pipeModeSelectParams.mediaSoftResetCounterValue = 2400;
865 pipeModeSelectParams.streamOutEnabled = true;
866 if (hucStreamOutParams->segmentInfo == nullptr && m_osInterface->osCpInterface->IsCpEnabled())
867 {
868 // Disable protection control setting in huc drm
869 pipeModeSelectParams.disableProtectionSetting = true;
870 }
871
872 // Enlarge the stream in/out data size to avoid upper bound hit assert in HuC
873 hucStreamOutParams->dataSize += hucStreamOutParams->inputRelativeOffset;
874 hucStreamOutParams->streamOutObjectSize += hucStreamOutParams->outputRelativeOffset;
875
876 // pass bit-stream buffer by Ind Obj Addr command
877 auto &indObjParams = m_hucItf->MHW_GETPAR_F(HUC_IND_OBJ_BASE_ADDR_STATE)();
878 indObjParams = {};
879 indObjParams.DataBuffer = hucStreamOutParams->dataBuffer;
880 indObjParams.DataSize = MOS_ALIGN_CEIL(hucStreamOutParams->dataSize, MHW_PAGE_SIZE);
881 indObjParams.DataOffset = hucStreamOutParams->dataOffset;
882 indObjParams.StreamOutObjectBuffer = hucStreamOutParams->streamOutObjectBuffer;
883 indObjParams.StreamOutObjectSize = MOS_ALIGN_CEIL(hucStreamOutParams->streamOutObjectSize, MHW_PAGE_SIZE);
884 indObjParams.StreamOutObjectOffset = hucStreamOutParams->streamOutObjectOffset;
885
886 // set stream object with stream out enabled
887 auto &streamObjParams = m_hucItf->MHW_GETPAR_F(HUC_STREAM_OBJECT)();
888 streamObjParams = {};
889 streamObjParams.IndirectStreamInDataLength = hucStreamOutParams->indStreamInLength;
890 streamObjParams.IndirectStreamInStartAddress = hucStreamOutParams->inputRelativeOffset;
891 streamObjParams.IndirectStreamOutStartAddress = hucStreamOutParams->outputRelativeOffset;
892 streamObjParams.HucProcessing = true;
893 streamObjParams.HucBitstreamEnable = true;
894 streamObjParams.StreamOut = true;
895
896 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_PIPE_MODE_SELECT)(cmdBuffer));
897 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_IND_OBJ_BASE_ADDR_STATE)(cmdBuffer));
898 CODEC_HW_CHK_STATUS_RETURN(m_hucItf->MHW_ADDCMD_F(HUC_STREAM_OBJECT)(cmdBuffer));
899
900 // This flag is always false if huc fw is not loaded.
901 if (MEDIA_IS_SKU(m_skuTable, FtrEnableMediaKernels) &&
902 MEDIA_IS_WA(m_waTable, WaHucStreamoutOnlyDisable))
903 {
904 CODEC_HW_CHK_STATUS_RETURN(AddHucDummyStreamOut(cmdBuffer));
905 }
906
907 return eStatus;
908 }
909
ReadHcpStatus(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)910 MOS_STATUS CodechalHwInterfaceNext::ReadHcpStatus(
911 MHW_VDBOX_NODE_IND vdboxIndex,
912 const EncodeStatusReadParams ¶ms,
913 PMOS_COMMAND_BUFFER cmdBuffer)
914 {
915 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
916
917 CODEC_HW_FUNCTION_ENTER;;
918
919 CODEC_HW_CHK_NULL_RETURN(cmdBuffer);
920
921 CODEC_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
922
923 auto &par1 = m_miItf->MHW_GETPAR_F(MI_FLUSH_DW)();
924 par1 = {};
925 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
926
927 auto mmioRegisters = m_hcpItf->GetMmioRegisters(vdboxIndex);
928
929 auto &par2 = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
930 par2 = {};
931 par2.presStoreBuffer = params.resBitstreamByteCountPerFrame;
932 par2.dwOffset = params.bitstreamByteCountPerFrameOffset;
933 par2.dwRegister = mmioRegisters->hcpEncBitstreamBytecountFrameRegOffset;
934 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
935
936 auto &par3 = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
937 par3 = {};
938 par3.presStoreBuffer = params.resBitstreamSyntaxElementOnlyBitCount;
939 par3.dwOffset = params.bitstreamSyntaxElementOnlyBitCountOffset;
940 par3.dwRegister = mmioRegisters->hcpEncBitstreamSeBitcountFrameRegOffset;
941 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
942
943 auto &par4 = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
944 par4 = {};
945 par4.presStoreBuffer = params.resQpStatusCount;
946 par4.dwOffset = params.qpStatusCountOffset;
947 par4.dwRegister = mmioRegisters->hcpEncQpStatusCountRegOffset;
948 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
949
950 return eStatus;
951 }
952
ReadImageStatusForHcp(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)953 MOS_STATUS CodechalHwInterfaceNext::ReadImageStatusForHcp(
954 MHW_VDBOX_NODE_IND vdboxIndex,
955 const EncodeStatusReadParams ¶ms,
956 PMOS_COMMAND_BUFFER cmdBuffer)
957 {
958 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
959
960 CODEC_HW_FUNCTION_ENTER;
961
962 CODEC_HW_CHK_NULL_RETURN(cmdBuffer);
963
964 CODEC_HW_CHK_COND_RETURN((vdboxIndex > GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
965
966 auto mmioRegisters = m_hcpItf->GetMmioRegisters(vdboxIndex);
967
968 auto &par1 = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
969 par1 = {};
970 par1.presStoreBuffer = params.resImageStatusMask;
971 par1.dwOffset = params.imageStatusMaskOffset;
972 par1.dwRegister = mmioRegisters->hcpEncImageStatusMaskRegOffset;
973 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
974
975 auto &par2 = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
976 par2 = {};
977 par2.presStoreBuffer = params.resImageStatusCtrl;
978 par2.dwOffset = params.imageStatusCtrlOffset;
979 par2.dwRegister = mmioRegisters->hcpEncImageStatusCtrlRegOffset;
980 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
981
982 auto &par3 = m_miItf->MHW_GETPAR_F(MI_FLUSH_DW)();
983 par3 = {};
984 CODEC_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
985
986 return eStatus;
987 }
988
SetRowstoreCachingOffsets(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)989 MOS_STATUS CodechalHwInterfaceNext::SetRowstoreCachingOffsets(
990 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)
991 {
992 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
993
994 CODEC_HW_FUNCTION_ENTER;
995
996 if (m_vdencItf)
997 {
998 mhw::vdbox::vdenc::RowStorePar par = {};
999 if (rowstoreParams->Mode == CODECHAL_ENCODE_MODE_AVC)
1000 {
1001 par.mode = mhw::vdbox::vdenc::RowStorePar::AVC;
1002 par.isField = !rowstoreParams->bIsFrame;
1003 }
1004 else if (rowstoreParams->Mode == CODECHAL_ENCODE_MODE_VP9)
1005 {
1006 par.mode = mhw::vdbox::vdenc::RowStorePar::VP9;
1007 par.bitDepth = mhw::vdbox::vdenc::RowStorePar::DEPTH_8;
1008 if (rowstoreParams->ucBitDepthMinus8 == 1 || rowstoreParams->ucBitDepthMinus8 == 2)
1009 {
1010 par.bitDepth = mhw::vdbox::vdenc::RowStorePar::DEPTH_10;
1011 }
1012 else if (rowstoreParams->ucBitDepthMinus8 > 2)
1013 {
1014 par.bitDepth = mhw::vdbox::vdenc::RowStorePar::DEPTH_12;
1015 }
1016 par.frameWidth = rowstoreParams->dwPicWidth;
1017 switch (rowstoreParams->ucChromaFormat)
1018 {
1019 case HCP_CHROMA_FORMAT_MONOCHROME:
1020 par.format = mhw ::vdbox::vdenc::RowStorePar::MONOCHROME;
1021 break;
1022 case HCP_CHROMA_FORMAT_YUV420:
1023 par.format = mhw ::vdbox::vdenc::RowStorePar::YUV420;
1024 break;
1025 case HCP_CHROMA_FORMAT_YUV422:
1026 par.format = mhw ::vdbox::vdenc::RowStorePar::YUV422;
1027 break;
1028 case HCP_CHROMA_FORMAT_YUV444:
1029 par.format = mhw ::vdbox::vdenc::RowStorePar::YUV444;
1030 break;
1031 }
1032 }
1033 else if (rowstoreParams->Mode == CODECHAL_ENCODE_MODE_HEVC)
1034 {
1035 par.mode = mhw::vdbox::vdenc::RowStorePar::HEVC;
1036 par.bitDepth = mhw::vdbox::vdenc::RowStorePar::DEPTH_8;
1037 if (rowstoreParams->ucBitDepthMinus8 == 1 || rowstoreParams->ucBitDepthMinus8 == 2)
1038 {
1039 par.bitDepth = mhw::vdbox::vdenc::RowStorePar::DEPTH_10;
1040 }
1041 else if (rowstoreParams->ucBitDepthMinus8 > 2)
1042 {
1043 par.bitDepth = mhw::vdbox::vdenc::RowStorePar::DEPTH_12;
1044 }
1045 par.lcuSize = mhw ::vdbox::vdenc::RowStorePar::SIZE_OTHER;
1046 if (rowstoreParams->ucLCUSize == 32)
1047 {
1048 par.lcuSize = mhw ::vdbox::vdenc::RowStorePar::SIZE_32;
1049 }
1050 else if (rowstoreParams->ucLCUSize == 64)
1051 {
1052 par.lcuSize = mhw ::vdbox::vdenc::RowStorePar::SIZE_64;
1053 }
1054 par.frameWidth = rowstoreParams->dwPicWidth;
1055 switch (rowstoreParams->ucChromaFormat)
1056 {
1057 case HCP_CHROMA_FORMAT_MONOCHROME:
1058 par.format = mhw ::vdbox::vdenc::RowStorePar::MONOCHROME;
1059 break;
1060 case HCP_CHROMA_FORMAT_YUV420:
1061 par.format = mhw ::vdbox::vdenc::RowStorePar::YUV420;
1062 break;
1063 case HCP_CHROMA_FORMAT_YUV422:
1064 par.format = mhw ::vdbox::vdenc::RowStorePar::YUV422;
1065 break;
1066 case HCP_CHROMA_FORMAT_YUV444:
1067 par.format = mhw ::vdbox::vdenc::RowStorePar::YUV444;
1068 break;
1069 }
1070 }
1071 else if (rowstoreParams->Mode == CODECHAL_ENCODE_MODE_AV1)
1072 {
1073 par.mode = mhw::vdbox::vdenc::RowStorePar::AV1;
1074 }
1075 CODEC_HW_CHK_STATUS_RETURN(m_vdencItf->SetRowstoreCachingOffsets(par));
1076 }
1077 if (m_mfxItf)
1078 {
1079 CODEC_HW_CHK_STATUS_RETURN(m_mfxItf->GetRowstoreCachingAddrs(rowstoreParams));
1080 }
1081 if (m_hcpItf)
1082 {
1083 mhw::vdbox::hcp::HcpVdboxRowStorePar rowstoreParamsHCP = {};
1084 rowstoreParamsHCP.Mode = rowstoreParams->Mode;
1085 rowstoreParamsHCP.dwPicWidth = rowstoreParams->dwPicWidth;
1086 rowstoreParamsHCP.ucChromaFormat = rowstoreParams->ucChromaFormat;
1087 rowstoreParamsHCP.ucBitDepthMinus8 = rowstoreParams->ucBitDepthMinus8;
1088 rowstoreParamsHCP.ucLCUSize = rowstoreParams->ucLCUSize;
1089 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->SetRowstoreCachingOffsets(rowstoreParamsHCP));
1090 }
1091 if (m_avpItf)
1092 {
1093 mhw::vdbox::avp::AvpVdboxRowStorePar rowstoreParamsAVP = {};
1094 rowstoreParamsAVP.picWidth = rowstoreParams->dwPicWidth;
1095 rowstoreParamsAVP.mbaff = rowstoreParams->bMbaff;
1096 rowstoreParamsAVP.mode = rowstoreParams->Mode;
1097 rowstoreParamsAVP.bitDepthMinus8 = rowstoreParams->ucBitDepthMinus8;
1098 rowstoreParamsAVP.chromaFormat = rowstoreParams->ucChromaFormat;
1099 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->GetRowstoreCachingAddrs(rowstoreParamsAVP));
1100 }
1101
1102 if (m_vvcpItf != nullptr)
1103 {
1104 CODEC_HW_CHK_STATUS_RETURN(m_vvcpItf->GetRowstoreCachingAddrs(rowstoreParams));
1105 }
1106
1107 return eStatus;
1108 }
1109
InitL3CacheSettings()1110 MOS_STATUS CodechalHwInterfaceNext::InitL3CacheSettings()
1111 {
1112 CODEC_HW_FUNCTION_ENTER;
1113
1114 // Get default L3 cache settings
1115 CODEC_HW_CHK_STATUS_RETURN(m_renderItf->EnableL3Caching(nullptr));
1116
1117 #if (_DEBUG || _RELEASE_INTERNAL)
1118 // Override default L3 cache settings
1119 auto l3CacheConfig =
1120 m_renderItf->GetL3CacheConfig();
1121 mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS l3Overrides = {};
1122 l3Overrides.dwTcCntlReg =
1123 static_cast<mhw::render::MHW_RENDER_ENGINE_L3_CACHE_CONFIG *>(l3CacheConfig)->dwL3CacheTcCntlReg_Setting;
1124 l3Overrides.dwAllocReg =
1125 static_cast<mhw::render::MHW_RENDER_ENGINE_L3_CACHE_CONFIG *>(l3CacheConfig)->dwL3CacheAllocReg_Setting;
1126 CODEC_HW_CHK_STATUS_RETURN(InitL3ControlUserFeatureSettings(
1127 l3CacheConfig,
1128 &l3Overrides));
1129 CODEC_HW_CHK_STATUS_RETURN(m_renderItf->EnableL3Caching(
1130 &l3Overrides));
1131 #endif // (_DEBUG || _RELEASE_INTERNAL)
1132
1133 return MOS_STATUS_SUCCESS;
1134 }
1135
1136 #if (_DEBUG || _RELEASE_INTERNAL)
InitL3ControlUserFeatureSettings(mhw::render::MHW_RENDER_ENGINE_L3_CACHE_CONFIG * l3CacheConfig,mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS * l3Overrides)1137 MOS_STATUS CodechalHwInterfaceNext::InitL3ControlUserFeatureSettings(
1138 mhw::render::MHW_RENDER_ENGINE_L3_CACHE_CONFIG *l3CacheConfig,
1139 mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS *l3Overrides)
1140 {
1141 CODEC_HW_FUNCTION_ENTER;
1142
1143 CODEC_HW_CHK_NULL_RETURN(l3CacheConfig);
1144 CODEC_HW_CHK_NULL_RETURN(l3Overrides);
1145
1146 MediaUserSetting::Value outValue;
1147 ReadUserSettingForDebug(
1148 m_userSettingPtr,
1149 outValue,
1150 "Encode L3CNTLREG Override",
1151 MediaUserSetting::Group::Device,
1152 l3CacheConfig->dwL3CacheCntlReg_Setting,
1153 true);
1154 l3Overrides->dwCntlReg = outValue.Get<uint32_t>();
1155
1156 ReadUserSettingForDebug(
1157 m_userSettingPtr,
1158 outValue,
1159 "Encode L3CNTLREG2 Override",
1160 MediaUserSetting::Group::Device,
1161 l3CacheConfig->dwL3CacheCntlReg2_Setting,
1162 true);
1163 l3Overrides->dwCntlReg2 = outValue.Get<uint32_t>();
1164
1165 ReadUserSettingForDebug(
1166 m_userSettingPtr,
1167 outValue,
1168 "Encode L3CNTLREG3 Override",
1169 MediaUserSetting::Group::Device,
1170 l3CacheConfig->dwL3CacheCntlReg3_Setting,
1171 true);
1172 l3Overrides->dwCntlReg3 = outValue.Get<uint32_t>();
1173
1174 ReadUserSettingForDebug(
1175 m_userSettingPtr,
1176 outValue,
1177 "Encode L3SQCREG1 Override",
1178 MediaUserSetting::Group::Device,
1179 l3CacheConfig->dwL3CacheSqcReg1_Setting,
1180 true);
1181 l3Overrides->dwSqcReg1 = outValue.Get<uint32_t>();
1182
1183 ReadUserSettingForDebug(
1184 m_userSettingPtr,
1185 outValue,
1186 "Encode L3SQCREG4 Override",
1187 MediaUserSetting::Group::Device,
1188 l3CacheConfig->dwL3CacheSqcReg4_Setting,
1189 true);
1190 l3Overrides->dwSqcReg4 = outValue.Get<uint32_t>();
1191
1192 ReadUserSettingForDebug(
1193 m_userSettingPtr,
1194 outValue,
1195 "L3LRA1RegOverride",
1196 MediaUserSetting::Group::Device,
1197 l3CacheConfig->dwL3LRA1Reg_Setting,
1198 true);
1199 l3Overrides->dwLra1Reg = outValue.Get<uint32_t>();
1200
1201 return MOS_STATUS_SUCCESS;
1202 }
1203 #endif // _DEBUG || _RELEASE_INTERNAL
1204
SelectVdAndGetMmioReg(MHW_VDBOX_NODE_IND index,PMOS_COMMAND_BUFFER pCmdBuffer)1205 MmioRegistersMfx *CodechalHwInterfaceNext::SelectVdAndGetMmioReg(
1206 MHW_VDBOX_NODE_IND index,
1207 PMOS_COMMAND_BUFFER pCmdBuffer)
1208 {
1209 if (m_getVdboxNodeByUMD)
1210 {
1211 pCmdBuffer->iVdboxNodeIndex = m_osInterface->pfnGetVdboxNodeId(m_osInterface, pCmdBuffer);
1212 switch (pCmdBuffer->iVdboxNodeIndex)
1213 {
1214 case MOS_VDBOX_NODE_1:
1215 index = MHW_VDBOX_NODE_1;
1216 break;
1217 case MOS_VDBOX_NODE_2:
1218 index = MHW_VDBOX_NODE_2;
1219 break;
1220 case MOS_VDBOX_NODE_INVALID:
1221 // That's a legal case meaning that we were not assigned with per-bb index because
1222 // balancing algorithm can't work (forcedly diabled or miss kernel support).
1223 // If that's the case we just proceed with the further static context assignment.
1224 break;
1225 default:
1226 // That's the case when MHW and MOS enumerations mismatch. We again proceed with the
1227 // best effort (static context assignment, but provide debug note).
1228 MHW_ASSERTMESSAGE("MOS and MHW VDBOX enumerations mismatch! Adjust HW description!");
1229 break;
1230 }
1231 }
1232
1233 return m_vdencItf->GetMmioRegisters(index);
1234 }
1235