1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <string.h>
26 #include "util/macros.h"
27 #include "util/ralloc.h"
28 #include "broadcom/common/v3d_device_info.h"
29 #include "broadcom/qpu/qpu_disasm.h"
30 #include "broadcom/qpu/qpu_instr.h"
31
32 static const struct {
33 int ver;
34 uint64_t inst;
35 const char *expected;
36 } tests[] = {
37 { 42, 0x3d003186bb800000ull, "nop ; nop ; ldvary.rf0" },
38 { 42, 0x3c20318105829000ull, "fadd r1, r1, r5 ; nop ; thrsw" },
39 { 42, 0x3c403186bb81d000ull, "vpmsetup -, r5 ; nop ; ldunif" },
40 { 42, 0x3c002380b6edb000ull, "or rf0, r3, r3 ; mov vpm, r3" },
41 { 42, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3 ; fmul.pushz rf43.l, r5, r1.h" },
42 { 42, 0xb0044c56ba326840ull, "flpop rf22, rf33 ; fmul.pushz rf49.l, r4.h, r1.abs" },
43
44 /* vfmul input packing */
45 { 42, 0x101e8b6e8aad4000ull, "fmax.nornn rf46, r4.l, r2.l ; vfmul.ifnb rf45, r3, r5" },
46 { 42, 0x1857d3c219825000ull, "faddnf.norc r2.l, r5.l, r4 ; vfmul.ifb rf15, r0.ll, r4 ; ldunif" },
47 { 42, 0x1c0a0dfde2294000ull, "fcmp.ifna rf61.h, r4.abs, r2.l; vfmul rf55, r2.hh, r1" },
48 { 42, 0x2011c89b402cc000ull, "fsub.norz rf27, r4.abs, r1.abs; vfmul.ifa rf34, r3.swp, r1" },
49
50 { 42, 0xe01b42ab3bb063c0ull, "vfpack.andnc rf43, rf15.l, r0.h; fmul.ifna rf10.h, r4.l, r5.abs" },
51 { 42, 0x600b8b87fb4d1000ull, "fdx.ifnb rf7.h, r1.l ; fmul.pushn rf46, r3.l, r2.abs" },
52
53 /* small immediates */
54 { 42, 0x5de24398bbdc6218ull, "vflb.andnn rf24 ; fmul rf14, -8, rf8.h" },
55 { 42, 0x25ef83d8b166f00full, "vfmin.pushn rf24, 15.ff, r5 ; smul24.ifnb rf15, r1, r3" },
56 { 42, 0xadedcdf70839f990ull, "faddnf.pushc rf55, -16.l, r3.abs; fmul.ifb rf55.l, rf38.l, r1.h" },
57 { 42, 0x7dff89fa6a01f020ull, "fsub.nornc rf58.h, 0x3b800000.l, r3.l; fmul.ifnb rf39, r0.h, r0.h" },
58
59 /* branch conditions */
60 { 42, 0x02000006002034c0ull, "b.anyap rf19" },
61 { 42, 0x02679356b4201000ull, "b.anyap -1268280496" },
62 { 42, 0x02b76a2dd0400000ull, "b.anynaq zero_addr+0xd0b76a28" },
63 { 42, 0x0200000500402000ull, "b.anynaq lri" },
64 { 42, 0x0216fe167301c8c0ull, "bu.anya zero_addr+0x7316fe10, rf35" },
65 { 42, 0x020000050040e000ull, "bu.anynaq lri, r:unif" },
66 { 42, 0x0200000300006000ull, "bu.na0 lri, a:unif" },
67
68 /* Special waddr names */
69 { 42, 0x3c00318735808000ull, "vfpack tlb, r0, r1 ; nop" },
70 { 42, 0xe0571c938e8d5000ull, "fmax.andc recip, r5.h, r2.l ; fmul.ifb rf50.h, r3.l, r4.abs; ldunif" },
71 { 42, 0xc04098d4382c9000ull, "add.pushn rsqrt, r1, r1 ; fmul rf35.h, r3.abs, r1.abs ; ldunif" },
72 { 42, 0x481edcd6b3184500ull, "vfmin.norn log, r4.hh, r0 ; fmul.ifnb rf51, rf20.abs, r0.l" },
73 { 42, 0x041618d57c453000ull, "shl.andn exp, r3, r2 ; add.ifb rf35, r1, r2" },
74 { 42, 0x7048e5da49272800ull, "fsub.ifa rf26, r2.l, rf32 ; fmul.pushc sin, r1.h, r1.abs; ldunif" },
75
76 /* signals */
77 { 42, 0x1f010520cf60a000ull, "fcmp.andz rf32, r2.h, r1.h ; vfmul rf20, r0.hh, r3 ; ldunifa" },
78 { 42, 0x932045e6c16ea000ull, "fcmp rf38, r2.abs, r5 ; fmul rf23.l, r3, r3.abs ; ldunifarf.rf1" },
79 { 42, 0xd72f0434e43ae5c0ull, "fcmp rf52.h, rf23, r5.abs ; fmul rf16.h, rf23, r1 ; ldunifarf.rf60" },
80 { 42, 0xdb3048eb9d533780ull, "fmax rf43.l, r3.h, rf30 ; fmul rf35.h, r4, r2.l ; ldunifarf.r1" },
81 { 42, 0x733620471e6ce700ull, "faddnf rf7.l, rf28.h, r1.l ; fmul r1, r3.h, r3.abs ; ldunifarf.rsqrt2" },
82 { 42, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3 ; fmul.pushz rf43.l, r5, r1.h" },
83
84 /* opcodes */
85 { 42, 0x3de020c7bdfd200dull, "ldvpmg_in rf7, r2, r2 ; mov r3, 13" },
86 { 42, 0x3de02040f8ff7201ull, "stvpmv 1, rf8 ; mov r1, 1" },
87 { 42, 0xd8000e50bb2d3000ull, "sampid rf16 ; fmul rf57.h, r3, r1.l" },
88
89 /* SFU instructions. */
90 { 42, 0xe98d60c1ba2aef80ull, "recip rf1, rf62 ; fmul r3.h, r2.l, r1.l ; ldunifrf.rf53" },
91 { 42, 0x7d87c2debc51c000ull, "rsqrt rf30, r4 ; fmul rf11, r4.h, r2.h ; ldunifrf.rf31" },
92 { 42, 0xb182475abc2bb000ull, "rsqrt2 rf26, r3 ; fmul rf29.l, r2.h, r1.abs ; ldunifrf.rf9" },
93 { 42, 0x79880808bc0b6900ull, "sin rf8, rf36 ; fmul rf32, r2.h, r0.l ; ldunifrf.rf32" },
94 { 42, 0x04092094bc5a28c0ull, "exp.ifb rf20, r2 ; add r2, rf35, r2" },
95 { 42, 0xe00648bfbc32a000ull, "log rf63, r2 ; fmul.andnn rf34.h, r4.l, r1.abs" },
96
97 /* barrierid */
98 { 42, 0x3c203192bb814000ull, "barrierid syncb ; nop ; thrsw" },
99 };
100
101 static void
swap_mux(enum v3d_qpu_mux * a,enum v3d_qpu_mux * b)102 swap_mux(enum v3d_qpu_mux *a, enum v3d_qpu_mux *b)
103 {
104 enum v3d_qpu_mux t = *a;
105 *a = *b;
106 *b = t;
107 }
108
109 static void
swap_pack(enum v3d_qpu_input_unpack * a,enum v3d_qpu_input_unpack * b)110 swap_pack(enum v3d_qpu_input_unpack *a, enum v3d_qpu_input_unpack *b)
111 {
112 enum v3d_qpu_input_unpack t = *a;
113 *a = *b;
114 *b = t;
115 }
116
117 int
main(int argc,char ** argv)118 main(int argc, char **argv)
119 {
120 struct v3d_device_info devinfo = { };
121 int retval = 0;
122
123 for (int i = 0; i < ARRAY_SIZE(tests); i++) {
124 devinfo.ver = tests[i].ver;
125
126 printf("Testing v%d.%d 0x%016llx (\"%s\")... ",
127 devinfo.ver / 10, devinfo.ver % 10,
128 (long long)tests[i].inst,
129 tests[i].expected);
130
131 const char *disasm_output = v3d_qpu_disasm(&devinfo,
132 tests[i].inst);
133
134 printf("%s\n", disasm_output);
135
136 if (strcmp(disasm_output, tests[i].expected) != 0) {
137 printf("FAIL\n");
138 printf(" Expected: \"%s\"\n", tests[i].expected);
139 printf(" Got: \"%s\"\n", disasm_output);
140 retval = 1;
141 continue;
142 }
143 ralloc_free((void *)disasm_output);
144
145 struct v3d_qpu_instr instr;
146 if (!v3d_qpu_instr_unpack(&devinfo, tests[i].inst, &instr)) {
147 printf("FAIL (unpack) %s\n", tests[i].expected);
148 retval = 1;
149 continue;
150 }
151
152 if (instr.type == V3D_QPU_INSTR_TYPE_ALU) {
153 switch (instr.alu.add.op) {
154 case V3D_QPU_A_FADD:
155 case V3D_QPU_A_FADDNF:
156 case V3D_QPU_A_FMIN:
157 case V3D_QPU_A_FMAX:
158 /* Swap the operands to be sure that we test
159 * how the QPUs distinguish between these ops.
160 */
161 swap_mux(&instr.alu.add.a.mux,
162 &instr.alu.add.b.mux);
163 swap_pack(&instr.alu.add.a.unpack,
164 &instr.alu.add.b.unpack);
165 break;
166 default:
167 break;
168 }
169 }
170
171 uint64_t repack;
172 if (!v3d_qpu_instr_pack(&devinfo, &instr, &repack)) {
173 printf("FAIL (pack) %s\n", tests[i].expected);
174 retval = 1;
175 continue;
176 }
177
178 if (repack != tests[i].inst) {
179 printf("FAIL (repack) 0x%016llx\n", (long long)repack);
180 printf(" Expected: \"%s\"\n", tests[i].expected);
181 const char *redisasm = v3d_qpu_disasm(&devinfo, repack);
182 printf(" Got: \"%s\"\n", redisasm);
183 retval = 1;
184 ralloc_free((void *)redisasm);
185 }
186
187 printf("PASS\n");
188 }
189
190 return retval;
191 }
192