1 /* 2 * Copyright (c) 2015-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi.h 24 //! \brief MHW interface for MI and generic flush commands across all engines 25 //! \details Impelements the functionalities common across all platforms for MHW_MI 26 //! 27 28 #ifndef __MHW_MI_H__ 29 #define __MHW_MI_H__ 30 31 #include <memory> 32 #include "mos_defs.h" 33 #include "mos_os.h" 34 #include "mhw_mmio.h" 35 #include "mhw_utilities_next.h" 36 #include "mos_os_specific.h" 37 38 class MhwCpInterface; 39 40 #define MHW_MI_WATCHDOG_ENABLE_COUNTER 0x0 41 #define MHW_MI_WATCHDOG_DISABLE_COUNTER 0x1 42 #define MHW_MI_DEFAULT_WATCHDOG_THRESHOLD_IN_MS 60 43 #define MHW_MI_ENCODER_16K_WATCHDOG_THRESHOLD_IN_MS 2000 44 #define MHW_MI_ENCODER_8K_WATCHDOG_THRESHOLD_IN_MS 500 45 #define MHW_MI_ENCODER_4K_WATCHDOG_THRESHOLD_IN_MS 100 46 #define MHW_MI_ENCODER_FHD_WATCHDOG_THRESHOLD_IN_MS 50 47 #define MHW_MI_DECODER_720P_WATCHDOG_THRESHOLD_IN_MS 10 48 #define MHW_MI_DECODER_4K_WATCHDOG_THRESHOLD_IN_MS 20 49 #define MHW_MI_DECODER_8K_WATCHDOG_THRESHOLD_IN_MS 60 50 #define MHW_MI_DECODER_AV1_WATCHDOG_THRESHOLD_IN_MS 80 51 #define MHW_MI_DECODER_16K_WATCHDOG_THRESHOLD_IN_MS 180 52 #define MHW_MI_DECODER_16Kx16K_WATCHDOG_THRESHOLD_IN_MS 256 53 #define MHW_MI_WATCHDOG_COUNTS_PER_MILLISECOND (19200123 / 1000) // Time stamp counts per millisecond 54 55 typedef enum _MHW_COMMON_MI_ADDRESS_SHIFT 56 { 57 MHW_COMMON_MI_GENERAL_SHIFT = 2, 58 MHW_COMMON_MI_PIPE_CONTROL_SHIFT = 3, 59 MHW_COMMON_MI_FLUSH_DW_SHIFT = 3, 60 MHW_COMMON_MI_STORE_DATA_DW_SHIFT = 2, //when write DW to memory, algin with 4 bytes. 61 MHW_COMMON_MI_STORE_DATA_QW_SHIFT = 3, //when write QW to memory, algin with 8 bytes 62 MHW_COMMON_MI_CONDITIONAL_BATCH_BUFFER_END_SHIFT = 3, 63 } MHW_COMMON_MI_ADDRESS_SHIFT; 64 65 typedef enum _MHW_MI_SET_PREDICATE_ENABLE 66 { 67 MHW_MI_SET_PREDICATE_DISABLE = 0x0, 68 MHW_MI_SET_PREDICATE_ENABLE_ON_CLEAR, 69 MHW_MI_SET_PREDICATE_ENABLE_ON_SET, 70 MHW_MI_SET_PREDICATE_ENABLE_ALWAYS = 0xF, 71 } MHW_MI_SET_PREDICATE_ENABLE; 72 73 typedef enum _MHW_MI_POST_SYNC_OPERATION 74 { 75 MHW_FLUSH_NOWRITE = 0, 76 MHW_FLUSH_WRITE_IMMEDIATE_DATA = 1, 77 MHW_FLUSH_WRITE_TIMESTAMP_REG = 3 78 } MHW_MI_POST_SYNC_OPERATION; 79 80 typedef enum _MHW_COMMON_MI_ATOMIC_OPCODE 81 { 82 MHW_MI_ATOMIC_NONE = 0, 83 MHW_MI_ATOMIC_AND = 1, 84 MHW_MI_ATOMIC_OR = 2, 85 MHW_MI_ATOMIC_XOR = 3, 86 MHW_MI_ATOMIC_MOVE = 4, 87 MHW_MI_ATOMIC_INC = 5, 88 MHW_MI_ATOMIC_DEC = 6, 89 MHW_MI_ATOMIC_ADD = 7, 90 MHW_MI_ATOMIC_SUB = 8, 91 MHW_MI_ATOMIC_RSUB = 9, 92 MHW_MI_ATOMIC_IMAX = 10, 93 MHW_MI_ATOMIC_IMIN = 11, 94 MHW_MI_ATOMIC_UMAX = 12, 95 MHW_MI_ATOMIC_UMIN = 13, 96 MHW_MI_ATOMIC_CMP = 14, 97 MHW_MI_ATOMIC_MAX = 15 98 } MHW_COMMON_MI_ATOMIC_OPCODE; 99 100 typedef enum _MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION 101 { 102 MHW_MI_SAD_GREATER_THAN_SDD = 0, 103 MHW_MI_SAD_GREATER_THAN_OR_EQUAL_SDD = 1, 104 MHW_MI_SAD_LESS_THAN_SDD = 2, 105 MHW_MI_SAD_LESS_THAN_OR_EQUAL_SDD = 3, 106 MHW_MI_SAD_EQUAL_SDD = 4, 107 MHW_MI_SAD_NOT_EQUAL_SDD = 5, 108 } MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION; 109 110 typedef enum _MHW_MI_ALU_OPCODE 111 { 112 MHW_MI_ALU_NOOP = 0x0, 113 MHW_MI_ALU_LOAD = 0x80, 114 MHW_MI_ALU_LOADINV = 0x480, 115 MHW_MI_ALU_LOAD0 = 0x81, 116 MHW_MI_ALU_LOAD1 = 0x481, 117 MHW_MI_ALU_ADD = 0x100, 118 MHW_MI_ALU_SUB = 0x101, 119 MHW_MI_ALU_AND = 0x102, 120 MHW_MI_ALU_OR = 0x103, 121 MHW_MI_ALU_XOR = 0x104, 122 MHW_MI_ALU_SHR = 0x106, 123 MHW_MI_ALU_STORE = 0x180, 124 MHW_MI_ALU_STOREINV = 0x580 125 } MHW_MI_ALU_OPCODE; 126 127 typedef enum _MHW_MI_ALU_REG 128 { 129 MHW_MI_ALU_GPREG0 = 0, 130 MHW_MI_ALU_GPREG1, 131 MHW_MI_ALU_GPREG2, 132 MHW_MI_ALU_GPREG3, 133 MHW_MI_ALU_GPREG4, 134 MHW_MI_ALU_GPREG5, 135 MHW_MI_ALU_GPREG6, 136 MHW_MI_ALU_GPREG7, 137 MHW_MI_ALU_GPREG8, 138 MHW_MI_ALU_GPREG9, 139 MHW_MI_ALU_GPREG10, 140 MHW_MI_ALU_GPREG11, 141 MHW_MI_ALU_GPREG12, 142 MHW_MI_ALU_GPREG13, 143 MHW_MI_ALU_GPREG14, 144 MHW_MI_ALU_GPREG15, 145 MHW_MI_ALU_SRCA = 0x20, 146 MHW_MI_ALU_SRCB = 0x21, 147 MHW_MI_ALU_ACCU = 0x31, 148 MHW_MI_ALU_ZF = 0x32, 149 MHW_MI_ALU_CF = 0x33 150 } MHW_MI_ALU_REG; 151 152 typedef enum _MHW_FLUSH_OPERATION 153 { 154 MHW_FLUSH_NONE = 0, // No flush 155 MHW_FLUSH_WRITE_CACHE, // Flush write cache 156 MHW_FLUSH_READ_CACHE, // Flush read cache 157 MHW_FLUSH_CUSTOM // Flush with custom parameters 158 } MHW_FLUSH_OPERATION; 159 160 typedef enum _MMIO_REMAP_OPERATION 161 { 162 MMIO_REMAP_OPERATION_NONE = 0, // default operation 163 CCS_HW_FRONT_END_MMIO_REMAP // Remap CCS mmio base offset 164 }MMIO_REMAP_OPERATION; 165 166 typedef struct _MHW_PIPE_CONTROL_PARAMS 167 { 168 PMOS_RESOURCE presDest; 169 uint32_t dwResourceOffset; 170 uint32_t dwDataDW1; 171 uint32_t dwDataDW2; 172 uint32_t dwFlushMode; 173 uint32_t dwPostSyncOp; 174 uint32_t bDisableCSStall : 1; 175 uint32_t bInvalidateStateCache : 1; 176 uint32_t bInvalidateConstantCache : 1; 177 uint32_t bInvalidateVFECache : 1; 178 uint32_t bInvalidateInstructionCache : 1; 179 uint32_t bFlushRenderTargetCache : 1; 180 uint32_t bTlbInvalidate : 1; 181 uint32_t bInvalidateTextureCache : 1; 182 uint32_t bGenericMediaStateClear : 1; 183 uint32_t bIndirectStatePointersDisable : 1; 184 uint32_t bUnTypedDataPortCacheFlush : 1; 185 uint32_t bHdcPipelineFlush : 1; 186 uint32_t bKernelFenceEnabled : 1; 187 uint32_t bPPCFlush : 1; 188 } MHW_PIPE_CONTROL_PARAMS, *PMHW_PIPE_CONTROL_PARAMS; 189 190 typedef struct _MHW_MI_COPY_MEM_MEM_PARAMS 191 { 192 PMOS_RESOURCE presSrc; 193 uint32_t dwSrcOffset; 194 PMOS_RESOURCE presDst; 195 uint32_t dwDstOffset; 196 } MHW_MI_COPY_MEM_MEM_PARAMS, *PMHW_MI_COPY_MEM_MEM_PARAMS; 197 198 typedef struct _MHW_MI_STORE_REGISTER_MEM_PARAMS 199 { 200 PMOS_RESOURCE presStoreBuffer; 201 uint32_t dwOffset; 202 uint32_t dwRegister; 203 uint32_t dwOption; 204 } MHW_MI_STORE_REGISTER_MEM_PARAMS, *PMHW_MI_STORE_REGISTER_MEM_PARAMS; 205 206 typedef MHW_MI_STORE_REGISTER_MEM_PARAMS MHW_MI_LOAD_REGISTER_MEM_PARAMS, *PMHW_MI_LOAD_REGISTER_MEM_PARAMS; 207 208 typedef struct _MHW_MI_LOAD_REGISTER_REG_PARAMS 209 { 210 uint32_t dwSrcRegister; 211 uint32_t dwDstRegister; 212 } MHW_MI_LOAD_REGISTER_REG_PARAMS, *PMHW_MI_LOAD_REGISTER_REG_PARAMS; 213 214 typedef struct _MHW_MI_ALU_PARAMS 215 { 216 // DW 0 217 union 218 { 219 struct 220 { 221 uint32_t Operand2 : MOS_BITFIELD_RANGE(0, 9); // Operand-2 222 uint32_t Operand1 : MOS_BITFIELD_RANGE(10, 19); // Operand-1 223 uint32_t AluOpcode : MOS_BITFIELD_RANGE(20, 31); // ALU OPCODE 224 }; 225 uint32_t Value; 226 }; 227 } MHW_MI_ALU_PARAMS, *PMHW_MI_ALU_PARAMS; 228 229 typedef struct _MHW_MI_MATH_PARAMS 230 { 231 PMHW_MI_ALU_PARAMS pAluPayload; 232 uint32_t dwNumAluParams; 233 } MHW_MI_MATH_PARAMS, *PMHW_MI_MATH_PARAMS; 234 235 typedef struct _MHW_MI_LOAD_REGISTER_IMM_PARAMS 236 { 237 uint32_t dwRegister; 238 uint32_t dwData; 239 } MHW_MI_LOAD_REGISTER_IMM_PARAMS, *PMHW_MI_LOAD_REGISTER_IMM_PARAMS; 240 241 typedef struct _MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS 242 { 243 PMOS_RESOURCE presSemaphoreBuffer; 244 uint32_t dwOffset; 245 uint32_t dwValue; 246 bool bDisableCompareMask; 247 uint32_t dwParamsType; //reserved 248 } MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS, *PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS; 249 250 typedef struct _MHW_MI_STORE_DATA_PARAMS 251 { 252 PMOS_RESOURCE pOsResource; // Target OS Resource 253 uint32_t dwResourceOffset; 254 uint32_t dwValue; // Value to Write 255 } MHW_MI_STORE_DATA_PARAMS, *PMHW_MI_STORE_DATA_PARAMS; 256 257 typedef struct _MHW_MI_FLUSH_DW_PARAMS 258 { 259 PMOS_RESOURCE pOsResource; // Target OS Resource 260 uint32_t dwResourceOffset; 261 uint32_t dwDataDW1; // Value to Write 262 uint32_t dwDataDW2; 263 bool bVideoPipelineCacheInvalidate; 264 uint32_t postSyncOperation; 265 uint32_t bQWordEnable; 266 bool bEnablePPCFlush; 267 } MHW_MI_FLUSH_DW_PARAMS, *PMHW_MI_FLUSH_DW_PARAMS; 268 269 typedef struct _MHW_MI_ATOMIC_PARAMS 270 { 271 PMOS_RESOURCE pOsResource; // Target OS Resource 272 uint32_t dwResourceOffset; 273 bool bReturnData; 274 bool bInlineData; 275 uint32_t dwOperand1Data[4]; // Values to Write 276 uint32_t dwOperand2Data[4]; // Values to Write 277 uint32_t dwDataSize; 278 MHW_COMMON_MI_ATOMIC_OPCODE Operation; 279 } MHW_MI_ATOMIC_PARAMS, *PMHW_MI_ATOMIC_PARAMS; 280 281 typedef struct _MHW_MI_SEMAPHORE_WAIT_PARAMS 282 { 283 PMOS_RESOURCE presSemaphoreMem; // Semaphore memory Resource 284 uint32_t dwResourceOffset; 285 bool bRegisterPollMode; 286 bool bPollingWaitMode; 287 uint32_t dwCompareOperation; 288 uint32_t dwSemaphoreData; 289 MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION CompareOperation; 290 }MHW_MI_SEMAPHORE_WAIT_PARAMS, *PMHW_MI_SEMAPHORE_WAIT_PARAMS; 291 292 typedef struct _MHW_MEDIA_STATE_FLUSH_PARAM 293 { 294 bool bFlushToGo; 295 uint8_t ui8InterfaceDescriptorOffset; 296 } MHW_MEDIA_STATE_FLUSH_PARAM, *PMHW_MEDIA_STATE_FLUSH_PARAM; 297 298 typedef struct _MHW_MI_FORCE_WAKEUP_PARAMS 299 { 300 uint32_t bForceMediaSlice0Awake : 1; //!< Force Media-Slice0 Awake 301 uint32_t bForceRenderAwake : 1; //!< Force Render Awake 302 uint32_t bForceMediaSlice1Awake : 1; //!< Force Media-Slice1 Awake 303 uint32_t bForceMediaSlice2Awake : 1; //!< Force Media-Slice2 Awake 304 uint32_t bForceMediaSlice3Awake : 1; //!< Force Media-Slice3 Awake 305 uint32_t Reserved5 : 3; //!< Reserved 306 uint32_t bHEVCPowerWellControl : 1; //!< HEVC Power Well Control 307 uint32_t bMFXPowerWellControl : 1; //!< MFX Power Well Control 308 uint32_t Reserved10 : 6; //!< Reserved 309 uint32_t bForceMediaSlice0AwakeMask : 1; //!< Force Media-Slice0 Awake Mask 310 uint32_t bForceRenderAwakeMask : 1; //!< Force Render Awake Mask 311 uint32_t bForceMediaSlice1AwakeMask : 1; //!< Force Media-Slice1 Awake Mask 312 uint32_t bForceMediaSlice2AwakeMask : 1; //!< Force Media-Slice2 Awake Mask 313 uint32_t bForceMediaSlice3AwakeMask : 1; //!< Force Media-Slice3 Awake Mask 314 uint32_t ReservedMask23_21 : 3; //!< Reserved Mask 315 uint32_t bHEVCPowerWellControlMask : 1; //!< HEVC Power Well Control Mask 316 uint32_t bMFXPowerWellControlMask : 1; //!< MFX Power Well Control Mask 317 uint32_t Reserved31_26 : 6; //!< Reserved Mask 318 } MHW_MI_FORCE_WAKEUP_PARAMS, *PMHW_MI_FORCE_WAKEUP_PARAMS; 319 320 typedef struct _MHW_MI_VD_CONTROL_STATE_PARAMS 321 { 322 bool vdencEnabled; 323 bool avpEnabled; 324 bool initialization; 325 bool vdencInitialization; 326 bool scalableModePipeLock; 327 bool scalableModePipeUnlock; 328 bool memoryImplicitFlush; 329 } MHW_MI_VD_CONTROL_STATE_PARAMS, *PMHW_MI_VD_CONTROL_STATE_PARAMS; 330 331 class MhwMiInterface 332 { 333 public: ~MhwMiInterface()334 virtual ~MhwMiInterface() { MHW_FUNCTION_ENTER; } 335 336 //! 337 //! \brief Adds MI_NOOP_CMD to the buffer provided 338 //! \details Either the command or batch buffer must be valid 339 //! \param [in] cmdBuffer 340 //! If valid, command buffer to which HW command is added 341 //! \param [in] batchBuffer 342 //! If valid, batch buffer to which HW command is added 343 //! \return MOS_STATUS 344 //! MOS_STATUS_SUCCESS if success, else fail reason 345 //! 346 virtual MOS_STATUS AddMiNoop( 347 PMOS_COMMAND_BUFFER cmdBuffer, 348 PMHW_BATCH_BUFFER batchBuffer) = 0; 349 350 //! 351 //! \brief Adds MI_BATCH_BUFFER_END to the buffer provided 352 //! \details Either the command or batch buffer must be valid 353 //! \param [in] cmdBuffer 354 //! If valid, command buffer to which HW command is added 355 //! \param [in] batchBuffer 356 //! If valid, batch buffer to which HW command is added 357 //! \return MOS_STATUS 358 //! MOS_STATUS_SUCCESS if success, else fail reason 359 //! 360 virtual MOS_STATUS AddMiBatchBufferEnd( 361 PMOS_COMMAND_BUFFER cmdBuffer, 362 PMHW_BATCH_BUFFER batchBuffer) = 0; 363 364 //! 365 //! \brief Add batch buffer end insertion flag 366 //! 367 //! \param [in/out] constructedCmdBuf 368 //! Constructed cmd buffer 369 //! 370 //! \return MOS_STATUS 371 //! MOS_STATUS_SUCCESS if success, else fail reason 372 //! 373 virtual MOS_STATUS AddBatchBufferEndInsertionFlag( 374 MOS_COMMAND_BUFFER &constructedCmdBuf) = 0; 375 376 //! 377 //! \brief Adds MI_BATCH_BUFFER_END to the buffer provided without any WA 378 //! \details Either the command or batch buffer must be valid 379 //! \param [in] cmdBuffer 380 //! If valid, command buffer to which HW command is added 381 //! \param [in] batchBuffer 382 //! If valid, batch buffer to which HW command is added 383 //! \return MOS_STATUS 384 //! MOS_STATUS_SUCCESS if success, else fail reason 385 //! 386 virtual MOS_STATUS AddMiBatchBufferEndOnly( 387 PMOS_COMMAND_BUFFER cmdBuffer, 388 PMHW_BATCH_BUFFER batchBuffer) = 0; 389 390 //! 391 //! \brief Adds MI_CONDITIONAL_BATCH_BUFFER_END to the command buffer 392 //! \param [in] cmdBuffer 393 //! Command buffer to which requested command is added 394 //! \param [in] params 395 //! Parameters used to populate the requested command 396 //! \return MOS_STATUS 397 //! MOS_STATUS_SUCCESS if success, else fail reason 398 //! 399 virtual MOS_STATUS AddMiConditionalBatchBufferEndCmd( 400 PMOS_COMMAND_BUFFER cmdBuffer, 401 PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS params) = 0; 402 403 //! 404 //! \brief Adds MI_BATCH_BUFFER_START to the command buffer 405 //! \param [in] cmdBuffer 406 //! Command buffer to which requested command is added 407 //! \param [in] batchBuffer 408 //! Batch buffer to refer to in MI_BATCH_BUFFER_START 409 //! \return MOS_STATUS 410 //! MOS_STATUS_SUCCESS if success, else fail reason 411 //! 412 virtual MOS_STATUS AddMiBatchBufferStartCmd( 413 PMOS_COMMAND_BUFFER cmdBuffer, 414 PMHW_BATCH_BUFFER batchBuffer) = 0; 415 416 //! 417 //! \brief Adds MI_STORE_DATA_IMM to the command buffer 418 //! \param [in] cmdBuffer 419 //! Command buffer to which requested command is added 420 //! \param [in] params 421 //! Parameters used to populate the requested command 422 //! \return MOS_STATUS 423 //! MOS_STATUS_SUCCESS if success, else fail reason 424 //! 425 virtual MOS_STATUS AddMiStoreDataImmCmd( 426 PMOS_COMMAND_BUFFER cmdBuffer, 427 PMHW_MI_STORE_DATA_PARAMS params) = 0; 428 429 //! 430 //! \brief Adds MI_FLUSH_DW to the command buffer 431 //! \param [in] cmdBuffer 432 //! Command buffer to which requested command is added 433 //! \param [in] params 434 //! Parameters used to populate the requested command 435 //! \return MOS_STATUS 436 //! MOS_STATUS_SUCCESS if success, else fail reason 437 //! 438 virtual MOS_STATUS AddMiFlushDwCmd( 439 PMOS_COMMAND_BUFFER cmdBuffer, 440 PMHW_MI_FLUSH_DW_PARAMS params) = 0; 441 442 //! 443 //! \brief Adds MI_FORCE_WAKEUP to the command buffer 444 //! \param [in] cmdBuffer 445 //! Command buffer to which requested command is added 446 //! \param [in] params 447 //! Parameters used to populate the requested command 448 //! \return MOS_STATUS 449 //! MOS_STATUS_SUCCESS if success, else fail reason 450 //! AddMiForceWakeupCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_FORCE_WAKEUP_PARAMS params)451 virtual MOS_STATUS AddMiForceWakeupCmd( 452 PMOS_COMMAND_BUFFER cmdBuffer, 453 PMHW_MI_FORCE_WAKEUP_PARAMS params) 454 { 455 return MOS_STATUS_SUCCESS; 456 }; 457 458 //! 459 //! \brief Adds MI_COPY_MEM_MEM to the command buffer 460 //! \param [in] cmdBuffer 461 //! Command buffer to which requested command is added 462 //! \param [in] params 463 //! Parameters used to populate the requested command 464 //! \return MOS_STATUS 465 //! MOS_STATUS_SUCCESS if success, else fail reason 466 //! 467 virtual MOS_STATUS AddMiCopyMemMemCmd( 468 PMOS_COMMAND_BUFFER cmdBuffer, 469 PMHW_MI_COPY_MEM_MEM_PARAMS params) = 0; 470 471 //! 472 //! \brief Adds MI_STORE_REGISTER_MEM to the command buffer 473 //! \param [in] cmdBuffer 474 //! Command buffer to which requested command is added 475 //! \param [in] params 476 //! Parameters used to populate the requested command 477 //! \return MOS_STATUS 478 //! MOS_STATUS_SUCCESS if success, else fail reason 479 //! 480 virtual MOS_STATUS AddMiStoreRegisterMemCmd( 481 PMOS_COMMAND_BUFFER cmdBuffer, 482 PMHW_MI_STORE_REGISTER_MEM_PARAMS params) = 0; 483 484 //! 485 //! \brief Adds MI_LOAD_REGISTER_MEM to the command buffer 486 //! \param [in] cmdBuffer 487 //! Command buffer to which requested command is added 488 //! \param [in] params 489 //! Parameters used to populate the requested command 490 //! \return MOS_STATUS 491 //! MOS_STATUS_SUCCESS if success, else fail reason 492 //! 493 virtual MOS_STATUS AddMiLoadRegisterMemCmd( 494 PMOS_COMMAND_BUFFER cmdBuffer, 495 PMHW_MI_STORE_REGISTER_MEM_PARAMS params) = 0; 496 497 //! 498 //! \brief Adds MI_LOAD_REGISTER_IMM to the command buffer 499 //! \param [in] cmdBuffer 500 //! Command buffer to which requested command is added 501 //! \param [in] params 502 //! Parameters used to populate the requested command 503 //! \return MOS_STATUS 504 //! MOS_STATUS_SUCCESS if success, else fail reason 505 //! 506 virtual MOS_STATUS AddMiLoadRegisterImmCmd( 507 PMOS_COMMAND_BUFFER cmdBuffer, 508 PMHW_MI_LOAD_REGISTER_IMM_PARAMS params) = 0; 509 510 //! 511 //! \brief Adds MI_LOAD_REGISTER_REG to the command buffer 512 //! \param [in] cmdBuffer 513 //! Command buffer to which requested command is added 514 //! \param [in] params 515 //! Parameters used to populate the requested command 516 //! \return MOS_STATUS 517 //! MOS_STATUS_SUCCESS if success, else fail reason 518 //! 519 virtual MOS_STATUS AddMiLoadRegisterRegCmd( 520 PMOS_COMMAND_BUFFER cmdBuffer, 521 PMHW_MI_LOAD_REGISTER_REG_PARAMS params) = 0; 522 523 //! 524 //! \brief Adds MI_MATH to the command buffer 525 //! \details MI_MATH is a variable length command requiring the ALU payload 526 //! for completion. 527 //! \param [in] cmdBuffer 528 //! Command buffer to which requested command is added 529 //! \param [in] params 530 //! Parameters used to populate the requested command 531 //! \return MOS_STATUS 532 //! MOS_STATUS_SUCCESS if success, else fail reason 533 //! 534 virtual MOS_STATUS AddMiMathCmd( 535 PMOS_COMMAND_BUFFER cmdBuffer, 536 PMHW_MI_MATH_PARAMS params) = 0; 537 538 //! 539 //! \brief Adds MI_SET_PREDICATE to the command buffer 540 //! for completion. 541 //! \param [in] cmdBuffer 542 //! Command buffer to which requested command is added 543 //! \param [in] params 544 //! Parameters used to populate the requested command 545 //! \return MOS_STATUS 546 //! MOS_STATUS_SUCCESS if success, else fail reason 547 //! 548 virtual MOS_STATUS AddMiSetPredicateCmd( 549 PMOS_COMMAND_BUFFER cmdBuffer, 550 MHW_MI_SET_PREDICATE_ENABLE enableFlag) = 0; 551 552 //! 553 //! \brief Adds MI_ATOMIC to the command buffer 554 //! \param [in] cmdBuffer 555 //! Command buffer to which requested command is added 556 //! \param [in] params 557 //! Parameters used to populate the requested command 558 //! \return MOS_STATUS 559 //! MOS_STATUS_SUCCESS if success, else fail reason 560 //! 561 virtual MOS_STATUS AddMiAtomicCmd( 562 PMOS_COMMAND_BUFFER cmdBuffer, 563 PMHW_MI_ATOMIC_PARAMS params) = 0; 564 565 //! 566 //! \brief Adds MI_SEMAPHORE_WAIT to the command buffer 567 //! \param [in] cmdBuffer 568 //! Command buffer to which requested command is added 569 //! \param [in] params 570 //! Parameters used to populate the requested command 571 //! \return MOS_STATUS 572 //! MOS_STATUS_SUCCESS if success, else fail reason 573 //! 574 virtual MOS_STATUS AddMiSemaphoreWaitCmd( 575 PMOS_COMMAND_BUFFER cmdBuffer, 576 PMHW_MI_SEMAPHORE_WAIT_PARAMS params) = 0; 577 578 //! 579 //! \brief Adds MI_ARB_CHECK to the command buffer 580 //! \param [in] cmdBuffer 581 //! Command buffer to which requested command is added 582 //! \return MOS_STATUS 583 //! MOS_STATUS_SUCCESS if success, else fail reason 584 //! 585 virtual MOS_STATUS AddMiArbCheckCmd( 586 PMOS_COMMAND_BUFFER cmdBuffer) = 0; 587 588 //! 589 //! \brief Adds PIPE_CONTROL to the command buffer 590 //! \details Although this function is not an MI function, all flushses are part of 591 //! the common MI interface, either the command or batch buffer must be valid 592 //! \param [in] cmdBuffer 593 //! Command buffer to which HW command is added, if valid batchBuffer should be null 594 //! \param [in] batchBuffer 595 //! Batch buffer to which HW command is added, if valid cmdBuffer should be null 596 //! \param [in] params 597 //! Parameters used to populate the requested command 598 //! \return MOS_STATUS 599 //! MOS_STATUS_SUCCESS if success, else fail reason 600 //! 601 virtual MOS_STATUS AddPipeControl( 602 PMOS_COMMAND_BUFFER cmdBuffer, 603 PMHW_BATCH_BUFFER batchBuffer, 604 PMHW_PIPE_CONTROL_PARAMS params) = 0; 605 606 //! 607 //! \brief Adds MFX_WAIT_CMD to the buffer provided 608 //! \details Either the command or batch buffer must be valid 609 //! \param [in] cmdBuffer 610 //! If valid, command buffer to which command are added 611 //! \param [in] batchBuffer 612 //! If valid, batch buffer to which the command is added 613 //! \param [in] stallVdboxPipeline 614 //! Indicates whether or not the MFX_WAIT will wait on VDBOX pipelines (HuC/HCP/MFX) 615 //! \return MOS_STATUS 616 //! MOS_STATUS_SUCCESS if success, else fail reason 617 //! 618 virtual MOS_STATUS AddMfxWaitCmd( 619 PMOS_COMMAND_BUFFER cmdBuffer, 620 PMHW_BATCH_BUFFER batchBuffer, 621 bool stallVdboxPipeline) = 0; 622 623 //! 624 //! \brief Adds MEDIA_STATE_FLUSH to valid buffer provided 625 //! \details Client facing function to add MEDIA_STATE_FLUSH to either the 626 //! command buffer or batch buffer (whichever is valid) 627 //! \param [in] cmdBuffer 628 //! If valid, command buffer to which HW command is added 629 //! \param [in] batchBuffer 630 //! If valid, Batch buffer to which HW command is added 631 //! \param [in] params 632 //! Parameters used to populate the requested command, may be nullptr if not needed 633 //! \return MOS_STATUS 634 //! MOS_STATUS_SUCCESS if success, else fail reason 635 //! 636 virtual MOS_STATUS AddMediaStateFlush( 637 PMOS_COMMAND_BUFFER cmdBuffer, 638 PMHW_BATCH_BUFFER batchBuffer, 639 PMHW_MEDIA_STATE_FLUSH_PARAM params = nullptr) = 0; 640 641 //! 642 //! \brief Skips batch buffer end command in a batch buffer 643 //! \details Inserts the space equivalent to what would have been inserted during 644 //! AddBatchBufferEnd to the batch buffer provided. 645 //! \param [in] batchBuffer 646 //! Batch buffer which HW command is skipped 647 //! \return MOS_STATUS 648 //! MOS_STATUS_SUCCESS if success, else fail reason 649 //! 650 virtual MOS_STATUS SkipMiBatchBufferEndBb( 651 PMHW_BATCH_BUFFER batchBuffer) = 0; 652 653 //! 654 //! \brief Adds prolog for protected content 655 //! \param [in] cmdBuffer 656 //! Command buffer into which prolog is inserted 657 //! \return MOS_STATUS 658 //! MOS_STATUS_SUCCESS if success, else fail reason 659 //! 660 MOS_STATUS AddProtectedProlog(MOS_COMMAND_BUFFER *cmdBuffer); 661 662 //! 663 //! \brief Get mmio registers address 664 //! \details Get mmio registers address 665 //! \return [out] PMHW_MI_MMIOREGISTERS* 666 //! mmio registers got. 667 //! GetMmioRegisters()668 inline PMHW_MI_MMIOREGISTERS GetMmioRegisters() 669 { 670 return &m_mmioRegisters; 671 } 672 673 //! 674 //! \brief Get Os interface 675 //! \details Get Os interface in codechal hw interface 676 //! 677 //! \return [out] PMOS_INTERFACE 678 //! Interface got. 679 //! GetOsInterface()680 inline PMOS_INTERFACE GetOsInterface() 681 { 682 return m_osInterface; 683 } 684 685 //! 686 //! \brief get the size of hw command 687 //! \details Internal function to get the size of MI_FLUSH_DW_CMD 688 //! \return commandSize 689 //! The command size 690 //! 691 virtual uint32_t GetMiFlushDwCmdSize() = 0; 692 693 //! 694 //! \brief get the size of hw command 695 //! \details Internal function to get the size of MI_BATCH_BUFFER_START_CMD 696 //! \return commandSize 697 //! The command size 698 //! 699 virtual uint32_t GetMiBatchBufferStartCmdSize() = 0; 700 701 //! 702 //! \brief get the size of hw command 703 //! \details Internal function to get the size of MI_BATCH_BUFFER_END_CMD 704 //! \return commandSize 705 //! The command size 706 //! 707 virtual uint32_t GetMiBatchBufferEndCmdSize() = 0; 708 709 //! 710 //! \brief Set Watchdog Timer Threshold 711 //! \details Set Watchdog Timer Threshold 712 //! \return MOS_STATUS 713 //! MOS_STATUS_SUCCESS if success, else fail reason 714 //! 715 virtual MOS_STATUS SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder = true) = 0; 716 717 //! 718 //! \brief Set Watchdog Timer Register Offset 719 //! \details Set Watchdog Timer Register Offset 720 //! \return MOS_STATUS 721 //! MOS_STATUS_SUCCESS if success, else fail reason 722 //! 723 virtual MOS_STATUS SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext) = 0; 724 725 //! 726 //! \brief Add Watchdog Timer Start Cmd 727 //! \details Add Watchdog Timer Start Cmd 728 //! \return MOS_STATUS 729 //! MOS_STATUS_SUCCESS if success, else fail reason 730 //! 731 virtual MOS_STATUS AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 732 733 //! 734 //! \brief Add Watchdog Timer Stop Cmd 735 //! \details Add Watchdog Timer Stop Cmd 736 //! \return MOS_STATUS 737 //! MOS_STATUS_SUCCESS if success, else fail reason 738 //! 739 virtual MOS_STATUS AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 740 741 //! 742 //! \brief Adds Mi Vd control state cmd in command buffer 743 //! 744 //! \param [in] cmdBuffer 745 //! Command buffer to which HW command is added 746 //! \param [in] params 747 //! Params structure used to populate the HW command 748 //! 749 //! \return MOS_STATUS 750 //! MOS_STATUS_SUCCESS if success, else fail reason 751 //! AddMiVdControlStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_VD_CONTROL_STATE_PARAMS params)752 virtual MOS_STATUS AddMiVdControlStateCmd( 753 PMOS_COMMAND_BUFFER cmdBuffer, 754 PMHW_MI_VD_CONTROL_STATE_PARAMS params) 755 { 756 return MOS_STATUS_SUCCESS; 757 }; 758 759 //! 760 //! \brief Get new render interface, temporal solution before switching from 761 //! old interface to new one 762 //! 763 //! \return pointer to new render interface 764 //! GetNewMiInterface()765 virtual std::shared_ptr<void> GetNewMiInterface() { return nullptr; } 766 767 protected: 768 //! 769 //! \brief Initializes the MI interface 770 //! \details Internal MHW function to initialize all function pointers and some parameters 771 //! Assumes that the caller has checked pointer validity and whether or not an 772 //! addressing method has been selected in the OS interface (bUsesGfxAddress or 773 //! bUsesPatchList). 774 //! \param [in] pCpInterface 775 //! CP interface, must be valid 776 //! \param [in] pOsInterface 777 //! OS interface, must be valid 778 //! 779 MhwMiInterface( 780 MhwCpInterface *cpInterface, 781 PMOS_INTERFACE osInterface); 782 783 //! 784 //! \brief Adds a resource to the command buffer or indirect state (SSH) 785 //! \details Internal MHW function to add either a graphics address of a resource or 786 //! add the resource to the patch list for the requested buffer or state 787 //! \param [in] pOsInterface 788 //! OS interface 789 //! \param [in] cmdBuffer 790 //! If adding a resource to the command buffer, the buffer to which the resource 791 //! is added 792 //! \param [in] params 793 //! Parameters necessary to add the graphics address 794 //! \return MOS_STATUS 795 //! MOS_STATUS_SUCCESS if success, else fail reason 796 //! 797 MOS_STATUS (*AddResourceToCmd) ( 798 PMOS_INTERFACE pOsInterface, 799 PMOS_COMMAND_BUFFER cmdBuffer, 800 PMHW_RESOURCE_PARAMS params) = nullptr; 801 802 //! 803 //! \brief Helper function to get GTT type (PGTT or GGTT) 804 //! \return bool 805 //! true for GGTT, false for PPGTT 806 //! 807 bool IsGlobalGttInUse(); 808 809 void GetWatchdogThreshold(PMOS_INTERFACE osInterface); 810 811 MhwCpInterface *m_cpInterface = nullptr; //!< Responsible for CP functionality 812 PMOS_INTERFACE m_osInterface = nullptr; //!< Responsible for interaction with OS 813 814 //! \brief Indicates the global GTT setting on each engine. 815 struct 816 { 817 uint8_t m_cs : 1; //!< GGTT in use for the render engine. 818 uint8_t m_vcs : 1; //!< GGTT in use for VDBOX. 819 uint8_t m_vecs : 1; //!< GGTT in use for VEBOX. 820 } UseGlobalGtt; 821 822 //! \brief Indicates the MediaReset Parameter. 823 struct 824 { 825 uint32_t watchdogCountThreshold; 826 uint32_t watchdogCountCtrlOffset; 827 uint32_t watchdogCountThresholdOffset; 828 } MediaResetParam; 829 830 //! \brief Mmio registers address 831 MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; //!< mfx mmio registers 832 833 std::shared_ptr<void> m_miItfNew = nullptr; 834 }; 835 836 #endif // __MHW_MI_H__ 837