1 /* 2 * Copyright (c) 2024, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_x2_lpm_impl.h 24 //! \brief MHW MI interface common base for Xe_HPM 25 //! \details 26 //! 27 28 #ifndef __MHW_MI_XE2_LPM_BASE_NEXT_IMPL_H__ 29 #define __MHW_MI_XE2_LPM_BASE_NEXT_IMPL_H__ 30 31 #include "mhw_mi_impl.h" 32 #include "mhw_mi_hwcmd_xe2_lpm_base_next.h" 33 #include "mhw_mi_itf.h" 34 #include "mhw_impl.h" 35 #include "mhw_mmio_xe2_lpm_base.h" 36 37 #define MHW_MI_TEE_DEFAULT_WATCHDOG_THRESHOLD_IN_MS 200 38 39 namespace mhw 40 { 41 namespace mi 42 { 43 namespace xe2_lpm_base_next 44 { 45 class Impl : public mi::Impl<Cmd> 46 { 47 protected: 48 using base_t = mi::Impl<Cmd>; 49 50 //! \brief Indicates the MediaReset Parameter. 51 struct 52 { 53 uint32_t watchdogCountThreshold = 0; 54 uint32_t watchdogCountCtrlOffset = 0; 55 uint32_t watchdogCountThresholdOffset = 0; 56 } MediaResetParam; 57 58 public: Impl(PMOS_INTERFACE osItf)59 Impl(PMOS_INTERFACE osItf) : base_t(osItf) 60 { 61 MHW_FUNCTION_ENTER; 62 InitMhwMiInterface(); 63 InitMmioRegisters(); 64 }; 65 SetManualResetThreshold(PMOS_INTERFACE osInterface)66 void SetManualResetThreshold(PMOS_INTERFACE osInterface) 67 { 68 MediaUserSetting::Value outValue; 69 MediaUserSettingSharedPtr userSettingPtr = osInterface->pfnGetUserSettingInstance(osInterface); 70 MHW_CHK_NULL_NO_STATUS_RETURN(userSettingPtr); 71 72 #if (_DEBUG || _RELEASE_INTERNAL) 73 ReadUserSettingForDebug( 74 userSettingPtr, 75 outValue, 76 __MEDIA_USER_FEATURE_VALUE_FORCE_RESET_THRESHOLD, 77 MediaUserSetting::Group::Device); 78 m_useManualThreshold = outValue.Get<bool>(); 79 #endif 80 } 81 GetWatchdogThreshold(PMOS_INTERFACE osInterface)82 void GetWatchdogThreshold(PMOS_INTERFACE osInterface) 83 { 84 uint32_t countThreshold = 0; 85 #if (_DEBUG || _RELEASE_INTERNAL) 86 // User feature config of watchdog timer threshold 87 ReadUserSettingForDebug( 88 m_userSettingPtr, 89 countThreshold, 90 __MEDIA_USER_FEATURE_VALUE_MEDIA_RESET_TH, 91 MediaUserSetting::Group::Device); 92 93 if (countThreshold != 0) 94 { 95 MediaResetParam.watchdogCountThreshold = countThreshold; 96 } 97 #endif 98 } 99 InitMhwMiInterface()100 void InitMhwMiInterface() 101 { 102 MHW_FUNCTION_ENTER; 103 104 UseGlobalGtt = {}; 105 MediaResetParam = {}; 106 107 if (this->m_osItf == nullptr) 108 { 109 MHW_ASSERTMESSAGE("Invalid input pointers provided"); 110 return; 111 } 112 113 if (!this->m_osItf->bUsesGfxAddress && !this->m_osItf->bUsesPatchList) 114 { 115 MHW_ASSERTMESSAGE("No valid addressing mode indicated"); 116 return; 117 } 118 119 UseGlobalGtt.m_cs = 120 UseGlobalGtt.m_vcs = 121 UseGlobalGtt.m_vecs = MEDIA_IS_WA(this->m_osItf->pfnGetWaTable(this->m_osItf), WaForceGlobalGTT) || 122 !MEDIA_IS_SKU(this->m_osItf->pfnGetSkuTable(this->m_osItf), FtrPPGTT); 123 124 MediaResetParam.watchdogCountThreshold = MHW_MI_DEFAULT_WATCHDOG_THRESHOLD_IN_MS; 125 126 GetWatchdogThreshold(this->m_osItf); 127 SetManualResetThreshold(this->m_osItf); 128 129 if (this->m_osItf->bUsesGfxAddress) 130 { 131 AddResourceToCmd = Mhw_AddResourceToCmd_GfxAddress; 132 } 133 else // if (pOsInterface->bUsesPatchList) 134 { 135 AddResourceToCmd = Mhw_AddResourceToCmd_PatchList; 136 } 137 } 138 InitMmioRegisters()139 void InitMmioRegisters() 140 { 141 MHW_FUNCTION_ENTER; 142 MHW_MI_MMIOREGISTERS* mmioRegisters = &m_mmioRegisters; 143 144 mmioRegisters->generalPurposeRegister0LoOffset = GP_REGISTER0_LO_OFFSET; 145 mmioRegisters->generalPurposeRegister0HiOffset = GP_REGISTER0_HI_OFFSET; 146 mmioRegisters->generalPurposeRegister4LoOffset = GP_REGISTER4_LO_OFFSET; 147 mmioRegisters->generalPurposeRegister4HiOffset = GP_REGISTER4_HI_OFFSET; 148 mmioRegisters->generalPurposeRegister11LoOffset = GP_REGISTER11_LO_OFFSET; 149 mmioRegisters->generalPurposeRegister11HiOffset = GP_REGISTER11_HI_OFFSET; 150 mmioRegisters->generalPurposeRegister12LoOffset = GP_REGISTER12_LO_OFFSET; 151 mmioRegisters->generalPurposeRegister12HiOffset = GP_REGISTER12_HI_OFFSET; 152 } 153 154 //! 155 //! \brief Check RCS and CCS remap offset 156 //! \details Check if a RCS register offset is set and remap it to RCS/CCS register offset if so. 157 //! \param [in] reg 158 //! Register to be checked and converted 159 //! \return bool 160 //! Return true if it is RCS register 161 //! IsRemappingMMIO(uint32_t & reg)162 bool IsRemappingMMIO(uint32_t ®) 163 { 164 if (nullptr == this->m_osItf) 165 { 166 MHW_ASSERTMESSAGE("invalid m_osInterface for RemappingMMIO"); 167 return false; 168 } 169 MOS_GPU_CONTEXT gpuContext = this->m_osItf->pfnGetGpuContext(this->m_osItf); 170 171 if (MOS_RCS_ENGINE_USED(gpuContext) && 172 ((M_MMIO_RCS_HW_FE_REMAP_RANGE_BEGIN <= reg && reg <= M_MMIO_RCS_HW_FE_REMAP_RANGE_END) 173 ||(M_MMIO_RCS_AUX_TBL_REMAP_RANGE_BEGIN <= reg && reg <= M_MMIO_RCS_AUX_TBL_REMAP_RANGE_END) 174 ||(M_MMIO_RCS_TRTT_REMAP_RANGE_BEGIN <= reg && reg <= M_MMIO_RCS_TRTT_REMAP_RANGE_END) 175 ||(M_MMIO_CCS0_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS0_HW_FRONT_END_BASE_END) 176 ||(M_MMIO_CCS1_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS1_HW_FRONT_END_BASE_END) 177 ||(M_MMIO_CCS2_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS2_HW_FRONT_END_BASE_END) 178 ||(M_MMIO_CCS3_HW_FRONT_END_BASE_BEGIN <= reg && reg <= M_MMIO_CCS3_HW_FRONT_END_BASE_END))) 179 { 180 return true; 181 } 182 else 183 { 184 return false; 185 } 186 } 187 IsRelativeMMIO(uint32_t & reg)188 bool IsRelativeMMIO(uint32_t ®) 189 { 190 if (nullptr == this->m_osItf) 191 { 192 MHW_ASSERTMESSAGE("invalid m_osInterface for RelativeMMIO"); 193 return false; 194 } 195 MOS_GPU_CONTEXT gpuContext = this->m_osItf->pfnGetGpuContext(this->m_osItf); 196 197 if ((MOS_VCS_ENGINE_USED(gpuContext) || MOS_VECS_ENGINE_USED(gpuContext)) && 198 (reg >= M_MMIO_MEDIA_LOW_OFFSET && reg < M_MMIO_MEDIA_HIGH_OFFSET)) 199 { 200 reg &= M_MMIO_MAX_RELATIVE_OFFSET; 201 return true; 202 } 203 return false; 204 } 205 SetWatchdogTimerThresholdForTee()206 MOS_STATUS SetWatchdogTimerThresholdForTee() 207 { 208 MHW_FUNCTION_ENTER; 209 MHW_MI_CHK_NULL(this->m_osItf); 210 if (this->m_osItf->bMediaReset == false || 211 this->m_osItf->umdMediaResetEnable == false) 212 { 213 return MOS_STATUS_SUCCESS; 214 } 215 216 MediaResetParam.watchdogCountThreshold = MHW_MI_TEE_DEFAULT_WATCHDOG_THRESHOLD_IN_MS; 217 GetWatchdogThreshold(this->m_osItf); 218 219 return MOS_STATUS_SUCCESS; 220 } 221 SetWatchdogTimerThreshold(uint32_t frameWidth,uint32_t frameHeight,bool isEncoder,uint32_t codecMode)222 MOS_STATUS SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder, uint32_t codecMode) override 223 { 224 MHW_FUNCTION_ENTER; 225 MHW_MI_CHK_NULL(this->m_osItf); 226 if (this->m_osItf->bMediaReset == false || 227 this->m_osItf->umdMediaResetEnable == false) 228 { 229 return MOS_STATUS_SUCCESS; 230 } 231 232 if (isEncoder) 233 { 234 if ((frameWidth * frameHeight) >= (7680 * 4320)) 235 { 236 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_16K_WATCHDOG_THRESHOLD_IN_MS; 237 } 238 else if ((frameWidth * frameHeight) >= (3840 * 2160)) 239 { 240 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_8K_WATCHDOG_THRESHOLD_IN_MS; 241 } 242 else if ((frameWidth * frameHeight) >= (1920 * 1080)) 243 { 244 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_4K_WATCHDOG_THRESHOLD_IN_MS; 245 } 246 else 247 { 248 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_FHD_WATCHDOG_THRESHOLD_IN_MS; 249 } 250 } 251 else 252 { 253 if ((frameWidth * frameHeight) >= (7680 * 4320)) 254 { 255 MediaResetParam.watchdogCountThreshold = MHW_MI_DECODER_8K_WATCHDOG_THRESHOLD_IN_MS; 256 } 257 else if ((frameWidth * frameHeight) >= (3840 * 2160)) 258 { 259 MediaResetParam.watchdogCountThreshold = MHW_MI_DECODER_4K_WATCHDOG_THRESHOLD_IN_MS; 260 } 261 else 262 { 263 MediaResetParam.watchdogCountThreshold = MHW_MI_DECODER_720P_WATCHDOG_THRESHOLD_IN_MS; 264 } 265 266 if ((CODECHAL_STANDARD)codecMode == CODECHAL_AV1) 267 { 268 // This is temporary solution to address the inappropriate threshold setting for high bit-rate AV1 decode. 269 // The final solution will incorporate bitstream size, increasing the setting when the bit-rate is high. 270 MediaResetParam.watchdogCountThreshold = MHW_MI_DECODER_AV1_WATCHDOG_THRESHOLD_IN_MS; 271 } 272 } 273 274 GetWatchdogThreshold(this->m_osItf); 275 276 return MOS_STATUS_SUCCESS; 277 } 278 SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext)279 MOS_STATUS SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext) override 280 { 281 MHW_FUNCTION_ENTER; 282 283 switch (gpuContext) 284 { 285 // RCS 286 case MOS_GPU_CONTEXT_RENDER: 287 case MOS_GPU_CONTEXT_RENDER2: 288 case MOS_GPU_CONTEXT_RENDER3: 289 case MOS_GPU_CONTEXT_RENDER4: 290 case MOS_GPU_CONTEXT_COMPUTE: 291 case MOS_GPU_CONTEXT_CM_COMPUTE: 292 case MOS_GPU_CONTEXT_RENDER_RA: 293 case MOS_GPU_CONTEXT_COMPUTE_RA: 294 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_RCS; 295 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_RCS; 296 break; 297 // VCS0 298 case MOS_GPU_CONTEXT_VIDEO: 299 case MOS_GPU_CONTEXT_VIDEO2: 300 case MOS_GPU_CONTEXT_VIDEO3: 301 case MOS_GPU_CONTEXT_VIDEO4: 302 case MOS_GPU_CONTEXT_VIDEO5: 303 case MOS_GPU_CONTEXT_VIDEO6: 304 case MOS_GPU_CONTEXT_VIDEO7: 305 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_VCS0; 306 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS0; 307 break; 308 // VCS1 309 case MOS_GPU_CONTEXT_VDBOX2_VIDEO: 310 case MOS_GPU_CONTEXT_VDBOX2_VIDEO2: 311 case MOS_GPU_CONTEXT_VDBOX2_VIDEO3: 312 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_VCS1; 313 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS1; 314 break; 315 // VECS 316 case MOS_GPU_CONTEXT_VEBOX: 317 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_VECS; 318 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_VECS; 319 break; 320 // TEE 321 case MOS_GPU_CONTEXT_TEE: 322 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_TEECS_XE2_LPM_BASE ; 323 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_TEECS_XE2_LPM_BASE ; 324 break; 325 // Default 326 default: 327 break; 328 } 329 330 return MOS_STATUS_SUCCESS; 331 } 332 AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer)333 MOS_STATUS AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer) override 334 { 335 MOS_GPU_CONTEXT gpuContext; 336 337 MHW_FUNCTION_ENTER; 338 MHW_MI_CHK_NULL(this->m_osItf); 339 if (this->m_osItf->bMediaReset == false || 340 this->m_osItf->umdMediaResetEnable == false) 341 { 342 return MOS_STATUS_SUCCESS; 343 } 344 345 MHW_MI_CHK_NULL(cmdBuffer); 346 347 // Set Watchdog Timer Register Offset 348 gpuContext = this->m_osItf->pfnGetGpuContext(this->m_osItf); 349 MHW_MI_CHK_STATUS(SetWatchdogTimerRegisterOffset(gpuContext)); 350 351 // Send Stop before Start is to help recover from incorrect wdt state if previous submission 352 // cause hang and not have a chance to execute the stop cmd in the end of batch buffer. 353 MHW_MI_CHK_STATUS(AddWatchdogTimerStopCmd(cmdBuffer)); 354 355 //Configure Watchdog timer Threshold 356 auto& par = MHW_GETPAR_F(MI_LOAD_REGISTER_IMM)(); 357 par = {}; 358 if (gpuContext == MOS_GPU_CONTEXT_TEE) 359 { 360 MHW_MI_CHK_STATUS(SetWatchdogTimerThresholdForTee()); 361 } 362 par.dwData = MHW_MI_WATCHDOG_COUNTS_PER_MILLISECOND * MediaResetParam.watchdogCountThreshold * 363 (this->m_osItf->bSimIsActive ? 2 : 1); 364 #if (_DEBUG || _RELEASE_INTERNAL) 365 // For debug usage, use manual threshold value without multiplying watchdog timestamp counts 366 if (m_useManualThreshold) 367 { 368 par.dwData = MediaResetParam.watchdogCountThreshold; 369 } 370 #endif 371 par.dwRegister = MediaResetParam.watchdogCountThresholdOffset; 372 MHW_ADDCMD_F(MI_LOAD_REGISTER_IMM)(cmdBuffer); 373 374 MHW_VERBOSEMESSAGE("MediaReset Threshold is %d", MediaResetParam.watchdogCountThreshold * (this->m_osItf->bSimIsActive ? 2 : 1)); 375 376 //Start Watchdog Timer 377 auto& par1 = MHW_GETPAR_F(MI_LOAD_REGISTER_IMM)(); 378 par1 = {}; 379 par1.dwData = MHW_MI_WATCHDOG_ENABLE_COUNTER; 380 par1.dwRegister = MediaResetParam.watchdogCountCtrlOffset; 381 MHW_ADDCMD_F(MI_LOAD_REGISTER_IMM)(cmdBuffer); 382 383 return MOS_STATUS_SUCCESS; 384 } 385 AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer)386 MOS_STATUS AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer) override 387 { 388 MOS_GPU_CONTEXT gpuContext; 389 390 MHW_FUNCTION_ENTER; 391 MHW_MI_CHK_NULL(this->m_osItf); 392 if (this->m_osItf->bMediaReset == false || 393 this->m_osItf->umdMediaResetEnable == false) 394 { 395 return MOS_STATUS_SUCCESS; 396 } 397 398 MHW_MI_CHK_NULL(cmdBuffer); 399 400 // Set Watchdog Timer Register Offset 401 gpuContext = this->m_osItf->pfnGetGpuContext(this->m_osItf); 402 MHW_MI_CHK_STATUS(SetWatchdogTimerRegisterOffset(gpuContext)); 403 404 //Stop Watchdog Timer 405 auto& par = MHW_GETPAR_F(MI_LOAD_REGISTER_IMM)(); 406 par = {}; 407 par.dwData = MHW_MI_WATCHDOG_DISABLE_COUNTER; 408 par.dwRegister = MediaResetParam.watchdogCountCtrlOffset; 409 MHW_ADDCMD_F(MI_LOAD_REGISTER_IMM)(cmdBuffer); 410 411 return MOS_STATUS_SUCCESS; 412 } 413 GetMmioInterfaces(MHW_MMIO_REGISTER_OPCODE opCode)414 uint32_t GetMmioInterfaces(MHW_MMIO_REGISTER_OPCODE opCode) override 415 { 416 uint32_t mmioRegisters = MHW_MMIO_RCS_AUX_TABLE_NONE; 417 418 switch (opCode) 419 { 420 case MHW_MMIO_RCS_AUX_TABLE_BASE_LOW: 421 mmioRegisters = M_MMIO_RCS_AUX_TABLE_BASE_LOW; 422 break; 423 case MHW_MMIO_RCS_AUX_TABLE_BASE_HIGH: 424 mmioRegisters = M_MMIO_RCS_AUX_TABLE_BASE_HIGH; 425 break; 426 case MHW_MMIO_RCS_AUX_TABLE_INVALIDATE: 427 mmioRegisters = M_MMIO_RCS_AUX_TABLE_INVALIDATE; 428 break; 429 case MHW_MMIO_VD0_AUX_TABLE_BASE_LOW: 430 mmioRegisters = M_MMIO_VD0_AUX_TABLE_BASE_LOW; 431 break; 432 case MHW_MMIO_VD0_AUX_TABLE_BASE_HIGH: 433 mmioRegisters = M_MMIO_VD0_AUX_TABLE_BASE_HIGH; 434 break; 435 case MHW_MMIO_VD0_AUX_TABLE_INVALIDATE: 436 mmioRegisters = M_MMIO_VD0_AUX_TABLE_INVALIDATE; 437 break; 438 case MHW_MMIO_VD1_AUX_TABLE_BASE_LOW: 439 mmioRegisters = M_MMIO_VD1_AUX_TABLE_BASE_LOW; 440 break; 441 case MHW_MMIO_VD1_AUX_TABLE_BASE_HIGH: 442 mmioRegisters = M_MMIO_VD1_AUX_TABLE_BASE_HIGH; 443 break; 444 case MHW_MMIO_VD1_AUX_TABLE_INVALIDATE: 445 mmioRegisters = M_MMIO_VD1_AUX_TABLE_INVALIDATE; 446 break; 447 case MHW_MMIO_VD2_AUX_TABLE_BASE_LOW: 448 mmioRegisters = M_MMIO_VD2_AUX_TABLE_BASE_LOW; 449 break; 450 case MHW_MMIO_VD2_AUX_TABLE_BASE_HIGH: 451 mmioRegisters = M_MMIO_VD2_AUX_TABLE_BASE_HIGH; 452 break; 453 case MHW_MMIO_VD2_AUX_TABLE_INVALIDATE: 454 mmioRegisters = M_MMIO_VD2_AUX_TABLE_INVALIDATE; 455 break; 456 case MHW_MMIO_VD3_AUX_TABLE_BASE_LOW: 457 mmioRegisters = M_MMIO_VD3_AUX_TABLE_BASE_LOW; 458 break; 459 case MHW_MMIO_VD3_AUX_TABLE_BASE_HIGH: 460 mmioRegisters = M_MMIO_VD3_AUX_TABLE_BASE_HIGH; 461 break; 462 case MHW_MMIO_VD3_AUX_TABLE_INVALIDATE: 463 mmioRegisters = M_MMIO_VD3_AUX_TABLE_INVALIDATE; 464 break; 465 case MHW_MMIO_VE0_AUX_TABLE_BASE_LOW: 466 mmioRegisters = M_MMIO_VE0_AUX_TABLE_BASE_LOW; 467 break; 468 case MHW_MMIO_VE0_AUX_TABLE_BASE_HIGH: 469 mmioRegisters = M_MMIO_VE0_AUX_TABLE_BASE_HIGH; 470 break; 471 case MHW_MMIO_VE0_AUX_TABLE_INVALIDATE: 472 mmioRegisters = M_MMIO_VE0_AUX_TABLE_INVALIDATE; 473 break; 474 case MHW_MMIO_VE1_AUX_TABLE_BASE_LOW: 475 mmioRegisters = M_MMIO_VE1_AUX_TABLE_BASE_LOW; 476 break; 477 case MHW_MMIO_VE1_AUX_TABLE_BASE_HIGH: 478 mmioRegisters = M_MMIO_VE1_AUX_TABLE_BASE_HIGH; 479 break; 480 case MHW_MMIO_VE1_AUX_TABLE_INVALIDATE: 481 mmioRegisters = M_MMIO_VE1_AUX_TABLE_INVALIDATE; 482 break; 483 case MHW_MMIO_CCS0_AUX_TABLE_BASE_LOW: 484 mmioRegisters = M_MMIO_CCS0_AUX_TABLE_BASE_LOW; 485 break; 486 case MHW_MMIO_CCS0_AUX_TABLE_BASE_HIGH: 487 mmioRegisters = M_MMIO_CCS0_AUX_TABLE_BASE_HIGH; 488 break; 489 case MHW_MMIO_CCS0_AUX_TABLE_INVALIDATE: 490 mmioRegisters = M_MMIO_CCS0_AUX_TABLE_INVALIDATE; 491 break; 492 default: 493 MHW_ASSERTMESSAGE("Invalid mmio data provided"); 494 ; 495 break; 496 } 497 498 return mmioRegisters; 499 } 500 AddMiBatchBufferEnd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer)501 MOS_STATUS AddMiBatchBufferEnd( 502 PMOS_COMMAND_BUFFER cmdBuffer, 503 PMHW_BATCH_BUFFER batchBuffer) override 504 { 505 MHW_FUNCTION_ENTER; 506 507 if (cmdBuffer == nullptr && batchBuffer == nullptr) 508 { 509 MHW_ASSERTMESSAGE("There was no valid buffer to add the HW command to."); 510 return MOS_STATUS_NULL_POINTER; 511 } 512 513 auto waTable = this->m_osItf->pfnGetWaTable(this->m_osItf); 514 MHW_MI_CHK_NULL(waTable); 515 516 // This WA does not apply for video or other engines, render requirement only 517 bool isRender = 518 MOS_RCS_ENGINE_USED(this->m_osItf->pfnGetGpuContext(this->m_osItf)); 519 520 if (isRender && 521 (MEDIA_IS_WA(waTable, WaMSFWithNoWatermarkTSGHang) || 522 MEDIA_IS_WA(waTable, WaAddMediaStateFlushCmd))) 523 { 524 auto& params = MHW_GETPAR_F(MEDIA_STATE_FLUSH)(); 525 params = {}; 526 MHW_ADDCMD_F(MEDIA_STATE_FLUSH)(cmdBuffer, batchBuffer); 527 } 528 529 // Mhw_CommonMi_AddMiBatchBufferEnd() is designed to handle both 1st level 530 // and 2nd level BB. It inserts MI_BATCH_BUFFER_END in both cases. 531 // However, since the 2nd level BB always returens to the 1st level BB and 532 // no chained BB scenario in Media, Epilog is only needed in the 1st level BB. 533 // Therefre, here only the 1st level BB case needs an Epilog inserted. 534 if (cmdBuffer && cmdBuffer->is1stLvlBB) 535 { 536 MHW_MI_CHK_STATUS(m_cpInterface->AddEpilog(this->m_osItf, cmdBuffer)); 537 } 538 539 auto& params = MHW_GETPAR_F(MI_BATCH_BUFFER_END)(); 540 params = {}; 541 MHW_ADDCMD_F(MI_BATCH_BUFFER_END)(cmdBuffer, batchBuffer); 542 543 if (!cmdBuffer) // Don't need BB not nullptr chk b/c if both are nullptr it won't get this far 544 { 545 #if (_DEBUG || _RELEASE_INTERNAL) 546 batchBuffer->iLastCurrent = batchBuffer->iCurrent; 547 #endif 548 } 549 550 // Send End Marker command 551 if (this->m_osItf->pfnIsSetMarkerEnabled(this->m_osItf) && cmdBuffer && cmdBuffer->is1stLvlBB) 552 { 553 PMOS_RESOURCE resMarker = nullptr; 554 resMarker = this->m_osItf->pfnGetMarkerResource(this->m_osItf); 555 MHW_MI_CHK_NULL(resMarker); 556 557 if (isRender) 558 { 559 // Send pipe_control to get the timestamp 560 auto& params = MHW_GETPAR_F(PIPE_CONTROL)(); 561 params = {}; 562 params.presDest = resMarker; 563 params.dwResourceOffset = sizeof(uint64_t); 564 params.dwPostSyncOp = MHW_FLUSH_WRITE_TIMESTAMP_REG; 565 params.dwFlushMode = MHW_FLUSH_WRITE_CACHE; 566 MHW_ADDCMD_F(PIPE_CONTROL)(cmdBuffer, batchBuffer); 567 } 568 else 569 { 570 // Send flush_dw to get the timestamp 571 auto& params = MHW_GETPAR_F(MI_FLUSH_DW)(); 572 params = {}; 573 params.pOsResource = resMarker; 574 params.dwResourceOffset = sizeof(uint64_t); 575 params.postSyncOperation = MHW_FLUSH_WRITE_TIMESTAMP_REG; 576 params.bQWordEnable = 1; 577 MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer, batchBuffer); 578 } 579 580 if (!this->m_osItf->apoMosEnabled) 581 { 582 MOS_SafeFreeMemory(resMarker); 583 } 584 } 585 MHW_MI_CHK_STATUS(this->m_osItf->osCpInterface->PermeateBBPatchForHM()); 586 587 return MOS_STATUS_SUCCESS; 588 } 589 _MHW_SETCMD_OVERRIDE_DECL(MI_SEMAPHORE_WAIT)590 _MHW_SETCMD_OVERRIDE_DECL(MI_SEMAPHORE_WAIT) 591 { 592 _MHW_SETCMD_CALLBASE(MI_SEMAPHORE_WAIT); 593 594 cmd.DW0.RegisterPollMode = params.bRegisterPollMode; 595 596 return MOS_STATUS_SUCCESS; 597 } 598 _MHW_SETCMD_OVERRIDE_DECL(PIPE_CONTROL)599 _MHW_SETCMD_OVERRIDE_DECL(PIPE_CONTROL) 600 { 601 _MHW_SETCMD_CALLBASE(PIPE_CONTROL); 602 MEDIA_WA_TABLE *pWaTable = this->m_osItf->pfnGetWaTable(this->m_osItf); 603 MHW_MI_CHK_NULL(pWaTable); 604 605 if (this->m_currentCmdBuf == nullptr && this->m_currentBatchBuf == nullptr) 606 { 607 MHW_ASSERTMESSAGE("There was no valid buffer to add the HW command to."); 608 return MOS_STATUS_NULL_POINTER; 609 } 610 611 cmd.DW1.PipeControlFlushEnable = true; 612 cmd.DW1.CommandStreamerStallEnable = !params.bDisableCSStall; 613 cmd.DW4_5.Value[0] = params.dwDataDW1; 614 cmd.DW4_5.Value[1] = params.dwDataDW2; 615 616 if (params.presDest) 617 { 618 cmd.DW1.PostSyncOperation = params.dwPostSyncOp; 619 cmd.DW1.DestinationAddressType = UseGlobalGtt.m_cs; 620 621 MHW_RESOURCE_PARAMS resourceParams = {}; 622 resourceParams.presResource = params.presDest; 623 resourceParams.dwOffset = params.dwResourceOffset; 624 resourceParams.pdwCmd = &(cmd.DW2.Value); 625 resourceParams.dwLocationInCmd = 2; 626 resourceParams.dwLsbNum = MHW_COMMON_MI_PIPE_CONTROL_SHIFT; 627 resourceParams.bIsWritable = true; 628 resourceParams.HwCommandType = MOS_PIPE_CONTROL; 629 630 MHW_MI_CHK_STATUS(AddResourceToCmd( 631 this->m_osItf, 632 this->m_currentCmdBuf, 633 &resourceParams)); 634 } 635 else 636 { 637 if (MEDIA_IS_WA(pWaTable, Wa_14010840176)) 638 { 639 cmd.DW0.DataportFlush = true; 640 cmd.DW1.ConstantCacheInvalidationEnable = false; 641 } 642 else 643 { 644 cmd.DW1.ConstantCacheInvalidationEnable = true; 645 } 646 cmd.DW1.StateCacheInvalidationEnable = true; 647 cmd.DW1.VfCacheInvalidationEnable = true; 648 cmd.DW1.InstructionCacheInvalidateEnable = true; 649 cmd.DW1.RenderTargetCacheFlushEnable = true; 650 cmd.DW1.PostSyncOperation = cmd.POST_SYNC_OPERATION_NOWRITE; 651 } 652 653 // Cache flush mode 654 switch (params.dwFlushMode) 655 { 656 // Flush all Write caches 657 case MHW_FLUSH_WRITE_CACHE: 658 cmd.DW1.RenderTargetCacheFlushEnable = true; 659 cmd.DW1.DcFlushEnable = true; 660 break; 661 662 // Invalidate all Read-only caches 663 case MHW_FLUSH_READ_CACHE: 664 if (MEDIA_IS_WA(pWaTable, Wa_14010840176)) 665 { 666 cmd.DW0.DataportFlush = true; 667 cmd.DW1.ConstantCacheInvalidationEnable = false; 668 } 669 else 670 { 671 cmd.DW1.ConstantCacheInvalidationEnable = true; 672 } 673 cmd.DW1.RenderTargetCacheFlushEnable = false; 674 cmd.DW1.StateCacheInvalidationEnable = true; 675 cmd.DW1.VfCacheInvalidationEnable = true; 676 cmd.DW1.InstructionCacheInvalidateEnable = true; 677 break; 678 679 // Custom flush parameters 680 case MHW_FLUSH_CUSTOM: 681 if (MEDIA_IS_WA(pWaTable, Wa_14010840176) && params.bInvalidateConstantCache) 682 { 683 cmd.DW0.DataportFlush = true; 684 cmd.DW1.StateCacheInvalidationEnable = true; 685 cmd.DW1.ConstantCacheInvalidationEnable = false; 686 } 687 else 688 { 689 cmd.DW1.StateCacheInvalidationEnable = params.bInvalidateStateCache; 690 cmd.DW1.ConstantCacheInvalidationEnable = params.bInvalidateConstantCache; 691 } 692 693 cmd.DW0.DataportFlush = params.bHdcPipelineFlush; 694 cmd.DW0.UnTypedDataPortCacheFlush = params.bUnTypedDataPortCacheFlush; 695 cmd.DW1.RenderTargetCacheFlushEnable = params.bFlushRenderTargetCache; 696 cmd.DW1.DcFlushEnable = params.bFlushRenderTargetCache; // same as above 697 cmd.DW1.VfCacheInvalidationEnable = params.bInvalidateVFECache; 698 cmd.DW1.InstructionCacheInvalidateEnable = params.bInvalidateInstructionCache; 699 cmd.DW1.TlbInvalidate = params.bTlbInvalidate; 700 cmd.DW1.TextureCacheInvalidationEnable = params.bInvalidateTextureCache; 701 break; 702 703 // No-flush operation requested 704 case MHW_FLUSH_NONE: 705 default: 706 cmd.DW1.RenderTargetCacheFlushEnable = false; 707 break; 708 } 709 710 // When PIPE_CONTROL stall bit is set, one of the following must also be set, otherwise set stall bit to 0 711 if (cmd.DW1.CommandStreamerStallEnable && 712 (cmd.DW1.DcFlushEnable == 0 && cmd.DW1.NotifyEnable == 0 && cmd.DW1.PostSyncOperation == 0 && 713 cmd.DW1.DepthStallEnable == 0 && cmd.DW1.StallAtPixelScoreboard == 0 && cmd.DW1.DepthCacheFlushEnable == 0 && 714 cmd.DW1.RenderTargetCacheFlushEnable == 0)) 715 { 716 cmd.DW1.CommandStreamerStallEnable = 0; 717 } 718 719 cmd.DW1.GenericMediaStateClear = params.bGenericMediaStateClear; 720 cmd.DW1.IndirectStatePointersDisable = params.bIndirectStatePointersDisable; 721 722 if (params.bPPCFlush) 723 { 724 cmd.DW0.CompressionControlSurfaceCcsFlush = true; 725 } 726 727 return MOS_STATUS_SUCCESS; 728 } 729 _MHW_SETCMD_OVERRIDE_DECL(MI_BATCH_BUFFER_START)730 _MHW_SETCMD_OVERRIDE_DECL(MI_BATCH_BUFFER_START) 731 { 732 _MHW_SETCMD_CALLBASE(MI_BATCH_BUFFER_START); 733 MHW_MI_CHK_NULL(this->m_currentCmdBuf); 734 MHW_MI_CHK_NULL(this->m_currentBatchBuf); 735 MHW_MI_CHK_NULL(this->m_osItf); 736 bool vcsEngineUsed = 737 MOS_VCS_ENGINE_USED(this->m_osItf->pfnGetGpuContext(this->m_osItf)); 738 739 MHW_RESOURCE_PARAMS resourceParams = {}; 740 resourceParams.presResource = &this->m_currentBatchBuf->OsResource; 741 resourceParams.dwOffset = this->m_currentBatchBuf->dwOffset; 742 resourceParams.pdwCmd = cmd.DW1_2.Value; 743 resourceParams.dwLocationInCmd = 1; 744 resourceParams.dwLsbNum = MHW_COMMON_MI_GENERAL_SHIFT; 745 resourceParams.HwCommandType = vcsEngineUsed ? MOS_MI_BATCH_BUFFER_START : MOS_MI_BATCH_BUFFER_START_RCS; 746 747 MHW_MI_CHK_STATUS(AddResourceToCmd( 748 this->m_osItf, 749 this->m_currentCmdBuf, 750 &resourceParams)); 751 752 // Set BB start 753 cmd.DW0.Obj3.SecondLevelBatchBuffer = true; 754 cmd.DW0.Obj0.AddressSpaceIndicator = !IsGlobalGttInUse(); 755 756 return MOS_STATUS_SUCCESS; 757 } 758 __MHW_ADDCMD_DECL(MI_CONDITIONAL_BATCH_BUFFER_END)759 __MHW_ADDCMD_DECL(MI_CONDITIONAL_BATCH_BUFFER_END) override 760 { 761 // Case 1 - Batch buffer condition matches - If this is not present then conditional 762 // batch buffer will exit to ring with terminating CP. 763 // Case 2 - Batch buffer condition DOES NOT match - Although this will disable CP 764 // but after end of conditional batch buffer CP will be re-enabled. 765 MHW_MI_CHK_STATUS(m_cpInterface->AddEpilog(this->m_osItf, cmdBuf)); 766 767 base_t::MHW_ADDCMD_F(MI_CONDITIONAL_BATCH_BUFFER_END)(cmdBuf, batchBuf); 768 769 MHW_MI_CHK_STATUS(m_cpInterface->AddProlog(this->m_osItf, cmdBuf)); 770 771 return MOS_STATUS_SUCCESS; 772 } 773 _MHW_SETCMD_OVERRIDE_DECL(MI_CONDITIONAL_BATCH_BUFFER_END)774 _MHW_SETCMD_OVERRIDE_DECL(MI_CONDITIONAL_BATCH_BUFFER_END) 775 { 776 _MHW_SETCMD_CALLBASE(MI_CONDITIONAL_BATCH_BUFFER_END); 777 778 MHW_MI_CHK_NULL(params.presSemaphoreBuffer); 779 780 cmd.DW0.UseGlobalGtt = IsGlobalGttInUse(); 781 cmd.DW0.CompareSemaphore = 1; // CompareDataDword is always assumed to be set 782 cmd.DW0.CompareMaskMode = !params.bDisableCompareMask; 783 if (params.dwParamsType == MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS::ENHANCED_PARAMS) 784 { 785 cmd.DW0.EndCurrentBatchBufferLevel = params.enableEndCurrentBatchBuffLevel; 786 cmd.DW0.CompareOperation = params.compareOperation; 787 } 788 cmd.DW1.CompareDataDword = params.dwValue; 789 790 MHW_RESOURCE_PARAMS resourceParams = {}; 791 resourceParams.presResource = params.presSemaphoreBuffer; 792 resourceParams.dwOffset = params.dwOffset; 793 resourceParams.pdwCmd = cmd.DW2_3.Value; 794 resourceParams.dwLocationInCmd = 2; 795 resourceParams.dwLsbNum = MHW_COMMON_MI_CONDITIONAL_BATCH_BUFFER_END_SHIFT; 796 resourceParams.HwCommandType = MOS_MI_CONDITIONAL_BATCH_BUFFER_END; 797 798 MHW_MI_CHK_STATUS(AddResourceToCmd( 799 this->m_osItf, 800 this->m_currentCmdBuf, 801 &resourceParams)); 802 803 return MOS_STATUS_SUCCESS; 804 } 805 _MHW_SETCMD_OVERRIDE_DECL(MI_SET_PREDICATE)806 _MHW_SETCMD_OVERRIDE_DECL(MI_SET_PREDICATE) 807 { 808 _MHW_SETCMD_CALLBASE(MI_SET_PREDICATE); 809 cmd.DW0.PredicateEnable = params.PredicateEnable; 810 811 return MOS_STATUS_SUCCESS; 812 } 813 _MHW_SETCMD_OVERRIDE_DECL(MI_STORE_REGISTER_MEM)814 _MHW_SETCMD_OVERRIDE_DECL(MI_STORE_REGISTER_MEM) 815 { 816 _MHW_SETCMD_CALLBASE(MI_STORE_REGISTER_MEM); 817 uint32_t reg = params.dwRegister; 818 if (IsRelativeMMIO(reg)) 819 { 820 cmd.DW0.AddCsMmioStartOffset = 1; 821 cmd.DW1.RegisterAddress = reg >> 2; 822 } 823 824 if (params.dwOption == CCS_HW_FRONT_END_MMIO_REMAP) 825 { 826 MOS_GPU_CONTEXT gpuContext = m_osItf->pfnGetGpuContext(m_osItf); 827 if (MOS_RCS_ENGINE_USED(gpuContext)) 828 { 829 reg &= M_CCS_HW_FRONT_END_MMIO_MASK; 830 reg += M_MMIO_CCS0_HW_FRONT_END_BASE_BEGIN; 831 } 832 } 833 834 cmd.DW0.MmioRemapEnable = IsRemappingMMIO(reg); 835 836 return MOS_STATUS_SUCCESS; 837 } 838 _MHW_SETCMD_OVERRIDE_DECL(MI_LOAD_REGISTER_MEM)839 _MHW_SETCMD_OVERRIDE_DECL(MI_LOAD_REGISTER_MEM) 840 { 841 _MHW_SETCMD_CALLBASE(MI_LOAD_REGISTER_MEM); 842 uint32_t Reg = params.dwRegister; 843 if (IsRelativeMMIO(Reg)) 844 { 845 cmd.DW0.AddCsMmioStartOffset = 1; 846 cmd.DW1.RegisterAddress = Reg >> 2; 847 } 848 849 cmd.DW0.MmioRemapEnable = IsRemappingMMIO(Reg); 850 851 return MOS_STATUS_SUCCESS; 852 } 853 _MHW_SETCMD_OVERRIDE_DECL(MI_LOAD_REGISTER_IMM)854 _MHW_SETCMD_OVERRIDE_DECL(MI_LOAD_REGISTER_IMM) 855 { 856 _MHW_SETCMD_CALLBASE(MI_LOAD_REGISTER_IMM); 857 uint32_t Reg = params.dwRegister; 858 if (IsRelativeMMIO(Reg)) 859 { 860 cmd.DW0.AddCsMmioStartOffset = 1; 861 cmd.DW1.RegisterOffset = Reg >> 2; 862 } 863 864 cmd.DW0.MmioRemapEnable = IsRemappingMMIO(Reg); 865 866 return MOS_STATUS_SUCCESS; 867 } 868 _MHW_SETCMD_OVERRIDE_DECL(MI_LOAD_REGISTER_REG)869 _MHW_SETCMD_OVERRIDE_DECL(MI_LOAD_REGISTER_REG) 870 { 871 _MHW_SETCMD_CALLBASE(MI_LOAD_REGISTER_REG); 872 uint32_t srcReg = params.dwSrcRegister; 873 if (IsRelativeMMIO(srcReg)) 874 { 875 cmd.DW0.AddCsMmioStartOffsetSource = 1; 876 cmd.DW1.SourceRegisterAddress = srcReg >> 2; 877 } 878 uint32_t dstReg = params.dwDstRegister; 879 if (IsRelativeMMIO(dstReg)) 880 { 881 cmd.DW0.AddCsMmioStartOffsetDestination = 1; 882 cmd.DW2.DestinationRegisterAddress = dstReg >> 2; 883 } 884 885 cmd.DW0.MmioRemapEnableSource = IsRemappingMMIO(srcReg); 886 cmd.DW0.MmioRemapEnableDestination = IsRemappingMMIO(dstReg); 887 888 return MOS_STATUS_SUCCESS; 889 } 890 _MHW_SETCMD_OVERRIDE_DECL(MI_FORCE_WAKEUP)891 _MHW_SETCMD_OVERRIDE_DECL(MI_FORCE_WAKEUP) 892 { 893 _MHW_SETCMD_CALLBASE(MI_FORCE_WAKEUP); 894 895 cmd.DW1.ForceMediaSlice0Awake = params.bForceMediaSlice0Awake; 896 cmd.DW1.ForceRenderAwake = params.bForceRenderAwake; 897 cmd.DW1.ForceMediaSlice1Awake = params.bForceMediaSlice1Awake; 898 cmd.DW1.ForceMediaSlice2Awake = params.bForceMediaSlice2Awake; 899 cmd.DW1.ForceMediaSlice3Awake = params.bForceMediaSlice3Awake; 900 cmd.DW1.HevcPowerWellControl = params.bHEVCPowerWellControl; 901 cmd.DW1.MfxPowerWellControl = params.bMFXPowerWellControl; 902 cmd.DW1.MaskBits = params.bForceMediaSlice0AwakeMask; 903 cmd.DW1.MaskBits += (params.bForceRenderAwakeMask << 1); 904 cmd.DW1.MaskBits += (params.bForceMediaSlice1AwakeMask << 2); 905 cmd.DW1.MaskBits += (params.bForceMediaSlice2AwakeMask << 3); 906 cmd.DW1.MaskBits += (params.bForceMediaSlice3AwakeMask << 4); 907 cmd.DW1.MaskBits += (params.bHEVCPowerWellControlMask << 8); 908 cmd.DW1.MaskBits += (params.bMFXPowerWellControlMask << 9); 909 910 return MOS_STATUS_SUCCESS; 911 } 912 _MHW_SETCMD_OVERRIDE_DECL(VD_CONTROL_STATE)913 _MHW_SETCMD_OVERRIDE_DECL(VD_CONTROL_STATE) 914 { 915 _MHW_SETCMD_CALLBASE(VD_CONTROL_STATE); 916 917 if (params.vdencEnabled) 918 { 919 cmd.DW0.MediaInstructionCommand = 920 mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::MEDIA_INSTRUCTION_COMMAND_VDCONTROLSTATEFORVDENC; 921 cmd.DW0.MediaInstructionOpcode = 922 mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::MEDIA_INSTRUCTION_OPCODE_CODECENGINENAMEFORVDENC; 923 } 924 else 925 { 926 cmd.DW0.MediaInstructionCommand = 927 mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::MEDIA_INSTRUCTION_COMMAND_VDCONTROLSTATEFORHCP; 928 if (params.avpEnabled) 929 { 930 cmd.DW0.MediaInstructionOpcode = 931 mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::MEDIA_INSTRUCTION_OPCODE_CODECENGINENAMEFORAVP; 932 } 933 else 934 { 935 cmd.DW0.MediaInstructionOpcode = 936 mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::MEDIA_INSTRUCTION_OPCODE_CODECENGINENAMEFORHCP; 937 } 938 939 cmd.DW1.PipelineInitialization = params.initialization; 940 cmd.DW2.MemoryImplicitFlush = params.memoryImplicitFlush; 941 cmd.DW2.ScalableModePipeLock = params.scalableModePipeLock; 942 cmd.DW2.ScalableModePipeUnlock = params.scalableModePipeUnlock; 943 } 944 MEDIA_WA_TABLE *pWaTable = this->m_osItf->pfnGetWaTable(this->m_osItf); 945 MHW_MI_CHK_NULL(pWaTable); 946 if (MEDIA_IS_WA(pWaTable, Wa_16021867713)) 947 { 948 cmd.DW1.VdboxPipelineArchitectureClockgateDisable = 1; 949 } 950 951 return MOS_STATUS_SUCCESS; 952 } 953 _MHW_SETCMD_OVERRIDE_DECL(MEDIA_STATE_FLUSH)954 _MHW_SETCMD_OVERRIDE_DECL(MEDIA_STATE_FLUSH) 955 { 956 _MHW_SETCMD_CALLBASE(MEDIA_STATE_FLUSH); 957 958 return MOS_STATUS_SUCCESS; 959 } 960 _MHW_SETCMD_OVERRIDE_DECL(MI_BATCH_BUFFER_END)961 _MHW_SETCMD_OVERRIDE_DECL(MI_BATCH_BUFFER_END) 962 { 963 _MHW_SETCMD_CALLBASE(MI_BATCH_BUFFER_END); 964 965 return MOS_STATUS_SUCCESS; 966 } 967 _MHW_SETCMD_OVERRIDE_DECL(MI_FLUSH_DW)968 _MHW_SETCMD_OVERRIDE_DECL(MI_FLUSH_DW) 969 { 970 _MHW_SETCMD_CALLBASE(MI_FLUSH_DW); 971 972 // set the protection bit based on CP status 973 #if !EMUL 974 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForMiFlushDw(this->m_osItf, &cmd)); 975 #endif 976 cmd.DW0.VideoPipelineCacheInvalidate = params.bVideoPipelineCacheInvalidate; 977 cmd.DW0.PostSyncOperation = cmd.POST_SYNC_OPERATION_NOWRITE; 978 cmd.DW3_4.Value[0] = params.dwDataDW1; 979 980 if (!Mos_ResourceIsNull(params.pOsResource)) 981 { 982 cmd.DW0.PostSyncOperation = cmd.POST_SYNC_OPERATION_WRITEIMMEDIATEDATA; 983 cmd.DW1_2.DestinationAddressType = UseGlobalGtt.m_vcs; 984 985 MHW_RESOURCE_PARAMS resourceParams = {}; 986 resourceParams.presResource = params.pOsResource; 987 resourceParams.dwOffset = params.dwResourceOffset; 988 resourceParams.pdwCmd = cmd.DW1_2.Value; 989 resourceParams.dwLocationInCmd = 1; 990 resourceParams.dwLsbNum = MHW_COMMON_MI_FLUSH_DW_SHIFT; 991 resourceParams.HwCommandType = MOS_MI_FLUSH_DW; 992 resourceParams.bIsWritable = true; 993 994 MHW_MI_CHK_STATUS(AddResourceToCmd( 995 this->m_osItf, 996 this->m_currentCmdBuf, 997 &resourceParams)); 998 } 999 1000 if (params.postSyncOperation) 1001 { 1002 cmd.DW0.PostSyncOperation = params.postSyncOperation; 1003 } 1004 1005 if (params.dwDataDW2 || params.bQWordEnable) 1006 { 1007 cmd.DW3_4.Value[1] = params.dwDataDW2; 1008 } 1009 else 1010 { 1011 cmd.DW0.DwordLength--; 1012 } 1013 1014 if (params.bEnablePPCFlush && !m_osItf->bNullHwIsEnabled) 1015 { 1016 cmd.DW0.FlushCcs = params.bEnablePPCFlush; 1017 } 1018 1019 return MOS_STATUS_SUCCESS; 1020 } 1021 _MHW_SETCMD_OVERRIDE_DECL(MI_NOOP)1022 _MHW_SETCMD_OVERRIDE_DECL(MI_NOOP) 1023 { 1024 _MHW_SETCMD_CALLBASE(MI_NOOP); 1025 1026 return MOS_STATUS_SUCCESS; 1027 } 1028 _MHW_SETCMD_OVERRIDE_DECL(MI_ATOMIC)1029 _MHW_SETCMD_OVERRIDE_DECL(MI_ATOMIC) 1030 { 1031 _MHW_SETCMD_CALLBASE(MI_ATOMIC); 1032 1033 return MOS_STATUS_SUCCESS; 1034 } 1035 _MHW_SETCMD_OVERRIDE_DECL(MI_STORE_DATA_IMM)1036 _MHW_SETCMD_OVERRIDE_DECL(MI_STORE_DATA_IMM) 1037 { 1038 _MHW_SETCMD_CALLBASE(MI_STORE_DATA_IMM); 1039 1040 return MOS_STATUS_SUCCESS; 1041 } 1042 __MHW_ADDCMD_DECL(MI_MATH)1043 __MHW_ADDCMD_DECL(MI_MATH) override 1044 { 1045 MHW_FUNCTION_ENTER; 1046 const auto ¶ms = __MHW_CMDINFO_M(MI_MATH)->first; 1047 1048 if (params.dwNumAluParams == 0 || params.pAluPayload == nullptr) 1049 { 1050 MHW_ASSERTMESSAGE("MI_MATH requires a valid payload"); 1051 return MOS_STATUS_INVALID_PARAMETER; 1052 } 1053 1054 base_t::MHW_ADDCMD_F(MI_MATH)(cmdBuf, batchBuf); 1055 1056 return Mhw_AddCommandCmdOrBB(m_osItf, cmdBuf, nullptr, ¶ms.pAluPayload[0], 1057 sizeof(MHW_MI_ALU_PARAMS)* params.dwNumAluParams); 1058 } 1059 _MHW_SETCMD_OVERRIDE_DECL(MI_MATH)1060 _MHW_SETCMD_OVERRIDE_DECL(MI_MATH) 1061 { 1062 _MHW_SETCMD_CALLBASE(MI_MATH); 1063 1064 cmd.DW0.DwordLength = params.dwNumAluParams - 1; 1065 1066 return MOS_STATUS_SUCCESS; 1067 } 1068 1069 private: 1070 #if (_DEBUG || _RELEASE_INTERNAL) 1071 bool m_useManualThreshold = false; // Flag for denoting if using manual threshold value 1072 #endif 1073 1074 MEDIA_CLASS_DEFINE_END(mhw__mi__xe2_lpm_base_next__Impl) 1075 }; 1076 1077 } // namespace xe2_lpm_base_next 1078 } // namespace mi 1079 } // namespace mhw 1080 1081 #endif // __MHW_MI_XE2_LPM_BASE_NEXT_IMPL_H__ 1082