1 /* 2 * Copyright (c) 2015-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mmio_g12.h 24 //! \brief Define the MMIO registers access of Gen12 25 //! \details 26 //! 27 28 #ifndef __MHW_MMIO_G12_H__ 29 #define __MHW_MMIO_G12_H__ 30 31 #include "mhw_mmio_common.h" 32 33 // CS register offsets 34 #define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G12 0x2600 35 #define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G12 0x2604 36 #define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G12 0x2620 37 #define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G12 0x2624 38 #define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G12 0x2658 39 #define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G12 0x265C 40 #define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G12 0x2660 41 #define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G12 0x2664 42 43 // Vebox register offsets 44 // Used in Commen MI 45 #define GP_REGISTER0_LO_OFFSET_G12 0x1C8600 46 #define GP_REGISTER0_HI_OFFSET_G12 0x1C8604 47 #define GP_REGISTER4_LO_OFFSET_G12 0x1C8620 48 #define GP_REGISTER4_HI_OFFSET_G12 0x1C8624 49 #define GP_REGISTER11_LO_OFFSET_G12 0x1C8658 50 #define GP_REGISTER11_HI_OFFSET_G12 0x1C865C 51 #define GP_REGISTER12_LO_OFFSET_G12 0x1C8660 52 #define GP_REGISTER12_HI_OFFSET_G12 0x1C8664 53 54 //VEBOX 55 #define WATCHDOG_COUNT_CTRL_OFFSET_RCS_G12 0x2178 56 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_RCS_G12 0x217C 57 58 #define WATCHDOG_COUNT_CTRL_OFFSET_VCS0_G12 0x1C0178 59 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS0_G12 0x1C017C 60 61 #define WATCHDOG_COUNT_CTRL_OFFSET_VCS1_G12 0x1C4178 62 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS1_G12 0x1C417C 63 64 #define WATCHDOG_COUNT_CTRL_OFFSET_VECS_G12 0x1C8178 65 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_VECS_G12 0x1C817C 66 67 //VDBOX HCP 68 #define WATCHDOG_COUNT_CTRL_OFFSET_INIT_G12 0x1C0178 69 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_INIT_G12 0x1C017C 70 #define HCP_DEBUG_FE_STREAM_OUT_SIZE_REG_OFFSET_INIT_G12 0x1C2828 71 #define HCP_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G12 0x1C28B8 72 #define HCP_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G12 0x1C28BC 73 #define HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G12 0x1C28A0 74 #define HCP_ENC_BIT_STREAM_SE_BIT_COUNT_FRAME_REG_OFFSET_INIT_G12 0x1C28A8 75 #define HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G12 0x1C28A4 76 #define HCP_ENC_QP_STATUS_COUNT_REG_OFFSET_INIT_G12 0x1C28C0 77 #define HCP_ENC_SLICE_COUNT_REG_OFFSET_INIT_G12 0x1C28C8 78 #define HCP_ENC_VDENC_MODE_TIMER_REG_OFFSET_INIT_G12 0x1C28DC 79 #define HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G12 0x1C28E0 80 #define HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G12 0x1C28E4 81 #define HCP_VP9_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G12 0x1C28F0 82 #define HCP_VP9_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G12 0x1C28F4 83 #define CS_ENGINE_ID_OFFSET_INIT_G12 0x1C008C 84 #define HCP_DEC_STATUS_REG_OFFSET_INIT_G12 0x1C2800 85 #define HCP_CABAC_STATUS_REG_OFFSET_INIT_G12 0x1C2804 86 #define HCP_FRAME_CRC_REG_OFFSET_INIT_G12 0x1C2920 87 88 89 //VDBOX HUC 90 #define HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G12 0x1C2014 91 #define HUC_STATUS_REG_OFFSET_NODE_1_INIT_G12 0x1C2000 92 #define HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G12 0x1C23B0 93 #define HUC_LOAD_INFO_REG_OFFSET_G12 0xC1DC 94 #define HUC_LOAD_INFO_REG_MASK_G12 0x1 95 96 //VDBOX MFX register offsets 97 #define GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_1_INIT_G12 0x1C0600 98 #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G12 0x1C0604 99 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G12 0x1C0620 100 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G12 0x1C0624 101 #define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G12 0x1C0658 102 #define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G12 0x1C065C 103 #define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G12 0x1C0660 104 #define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G12 0x1C0664 105 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G12 0x1C08B4 106 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G12 0x1C08B8 107 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G12 0x1C0954 108 #define MFC_QP_STATUS_COUNT_OFFSET_NODE_1_INIT_G12 0x1C08BC 109 #define MFX_ERROR_FLAG_REG_OFFSET_NODE_1_INIT_G12 0x1C0800 110 #define MFX_FRAME_CRC_REG_OFFSET_NODE_1_INIT_G12 0x1C0850 111 #define MFX_MB_COUNT_REG_OFFSET_NODE_1_INIT_G12 0x1C0868 112 #define MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G12 0x1C08A0 113 #define MFC_BITSTREAM_SE_BITCOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G12 0x1C08A4 114 #define MFC_BITSTREAM_BYTECOUNT_SLICE_REG_OFFSET_NODE_1_INIT_G12 0x1C08D0 115 116 //VDBOX VDENC 117 #define M_VDBOX_VDENC_REG_BASE {0x1C2D00, 0x1C6D00, 0x1D2D00, 0x1D6D00} 118 119 120 //VDBOX MFX register initial value 121 #define MFC_VP8_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G12 0 122 #define MFC_VP8_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G12 0 123 #define MFC_VP8_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G12 0 124 #define MFX_VP8_BRC_DQ_INDEX_REG_OFFSET_NODE_1_INIT_G12 0 125 #define MFX_VP8_BRC_LOOP_FILTER_REG_OFFSET_NODE_1_INIT_G12 0 126 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET_NODE_1_INIT_G12 0 127 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET_NODE_1_INIT_G12 0 128 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER01_REG_OFFSET_NODE_1_INIT_G12 0 129 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER23_REG_OFFSET_NODE_1_INIT_G12 0 130 #define MFX_VP8_BRC_CONVERGENCE_STATUS_REG_OFFSET_NODE_1_INIT_G12 0 131 #define MFX_LRA0_REG_OFFSET_NODE_1_INIT_G12 0 132 #define MFX_LRA1_REG_OFFSET_NODE_1_INIT_G12 0 133 #define MFX_LRA2_REG_OFFSET_NODE_1_INIT_G12 0 134 135 // HAL 136 #define REG_GPR_BASE_G12 CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G12 137 #define REG_TIMESTAMP_BASE_G12 0x2358 138 139 #define M_CCS_HW_FRONT_END_MMIO_MASK 0x7FF 140 141 // Media Engine 142 #define M_MMIO_MAX_RELATIVE_OFFSET 0x3FFF //!< Max reg relative offset in an engine 143 #define M_MMIO_MEDIA_LOW_OFFSET 0x1C0000 //!< Low bound of VDBox and VEBox MMIO offset 144 #define M_MMIO_MEDIA_HIGH_OFFSET 0x200000 //!< High bound of VDBox and VEBox MMIO offset 145 146 //Render 147 #define M_MMIO_RCS_AUX_TABLE_BASE_LOW 0x4200 148 #define M_MMIO_RCS_AUX_TABLE_BASE_HIGH 0x4204 149 #define M_MMIO_RCS_AUX_TABLE_INVALIDATE 0x4208 150 #define M_MMIO_RCS_HW_FE_REMAP_RANGE_BEGIN 0x2000 151 #define M_MMIO_RCS_HW_FE_REMAP_RANGE_END 0x27FF 152 #define M_MMIO_RCS_AUX_TBL_REMAP_RANGE_BEGIN 0x4200 153 #define M_MMIO_RCS_AUX_TBL_REMAP_RANGE_END 0x420F 154 #define M_MMIO_RCS_TRTT_REMAP_RANGE_BEGIN 0x4400 155 #define M_MMIO_RCS_TRTT_REMAP_RANGE_END 0x441F 156 157 #define M_MMIO_MEDIA_REG_BASE 0X380000 //!<Media Engine Base 158 159 //VD 160 #define M_MMIO_VD0_AUX_TABLE_BASE_LOW 0x4210 161 #define M_MMIO_VD0_AUX_TABLE_BASE_HIGH 0x4214 162 #define M_MMIO_VD0_AUX_TABLE_INVALIDATE 0x4218 163 #define M_MMIO_VD1_AUX_TABLE_BASE_LOW 0x4220 164 #define M_MMIO_VD1_AUX_TABLE_BASE_HIGH 0x4224 165 #define M_MMIO_VD1_AUX_TABLE_INVALIDATE 0x4228 166 #define M_MMIO_VD2_AUX_TABLE_BASE_LOW 0x4290 167 #define M_MMIO_VD2_AUX_TABLE_BASE_HIGH 0x4294 168 #define M_MMIO_VD2_AUX_TABLE_INVALIDATE 0x4298 169 #define M_MMIO_VD3_AUX_TABLE_BASE_LOW 0x42A0 170 #define M_MMIO_VD3_AUX_TABLE_BASE_HIGH 0x42A4 171 #define M_MMIO_VD3_AUX_TABLE_INVALIDATE 0x42A8 172 173 //VE 174 #define M_MMIO_VE0_AUX_TABLE_BASE_LOW 0x4230 175 #define M_MMIO_VE0_AUX_TABLE_BASE_HIGH 0x4234 176 #define M_MMIO_VE0_AUX_TABLE_INVALIDATE 0x4238 177 #define M_MMIO_VE1_AUX_TABLE_BASE_LOW 0x42B0 178 #define M_MMIO_VE1_AUX_TABLE_BASE_HIGH 0x42B4 179 #define M_MMIO_VE1_AUX_TABLE_INVALIDATE 0x42B8 180 181 //Compute 182 #define M_MMIO_CCS0_AUX_TABLE_BASE_LOW 0x42C0 183 #define M_MMIO_CCS0_AUX_TABLE_BASE_HIGH 0x42C4 184 #define M_MMIO_CCS0_AUX_TABLE_INVALIDATE 0x42C8 185 #define M_MMIO_CCS0_HW_FRONT_END_BASE_BEGIN 0x1A000 186 #define M_MMIO_CCS0_HW_FRONT_END_BASE_END 0x1A7FF 187 #define M_MMIO_CCS1_HW_FRONT_END_BASE_BEGIN 0x1C000 188 #define M_MMIO_CCS1_HW_FRONT_END_BASE_END 0x1C7FF 189 #define M_MMIO_CCS2_HW_FRONT_END_BASE_BEGIN 0x1E000 190 #define M_MMIO_CCS2_HW_FRONT_END_BASE_END 0x1E7FF 191 #define M_MMIO_CCS3_HW_FRONT_END_BASE_BEGIN 0x26000 192 #define M_MMIO_CCS3_HW_FRONT_END_BASE_END 0x267FF 193 194 //L3 cache configure 195 #define M_MMIO_RCS_L3ALLOCREG 0xB134 196 #define M_MMIO_CCS0_L3ALLOCREG 0xB234 197 #define M_MMIO_RCS_TCCNTLREG 0xB138 198 #define M_MMIO_CCS0_TCCNTLREG 0xB238 199 200 #endif //__MHW_MMIO_G12_H__ 201