1 /* 2 * Copyright (c) 2014-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render.h 24 //! \brief MHW interface for constructing commands for the render engine 25 //! \details Impelements the functionalities common across all platforms for MHW_RENDER 26 //! 27 28 #ifndef __MHW_RENDER_H__ 29 #define __MHW_RENDER_H__ 30 31 #include "mos_os.h" 32 #include "mhw_state_heap.h" 33 #include "mhw_render_itf.h" 34 35 #define MHW_RENDER_ENGINE_SSH_SURFACES_PER_BT_MAX 256 36 #define MHW_RENDER_ENGINE_SAMPLERS_MAX 16 37 #define MHW_RENDER_ENGINE_SAMPLERS_AVS_MAX 8 38 #define MHW_RENDER_ENGINE_MEDIA_PALOAD_SIZE_MAX 512 39 #define MHW_RENDER_ENGINE_URB_SIZE_MAX 2048 40 #define MHW_RENDER_ENGINE_URB_ENTRIES_MAX 128 41 #define MHW_RENDER_ENGINE_INTERFACE_DESCRIPTOR_ENTRIES_MAX 64 42 #define MHW_RENDER_ENGINE_EU_INDEX_MAX 12 43 #define MHW_RENDER_ENGINE_SIZE_REGISTERS_PER_THREAD 0x1800 44 #define MHW_RENDER_ENGINE_NUMBER_OF_THREAD_UNIT 32 45 #define MHW_RENDER_ENGINE_MAX_NUMBER_OF_THREAD (1024 / MHW_RENDER_ENGINE_NUMBER_OF_THREAD_UNIT) 46 47 #define MHW_MAX_DEPENDENCY_COUNT 8 48 49 typedef struct _MHW_RENDER_ENGINE_L3_CACHE_SETTINGS 50 { 51 uint32_t dwCntlReg = 0; 52 uint32_t dwCntlReg2 = 0; 53 uint32_t dwCntlReg3 = 0; 54 uint32_t dwSqcReg1 = 0; 55 uint32_t dwSqcReg4 = 0; 56 uint32_t dwLra1Reg = 0; ~_MHW_RENDER_ENGINE_L3_CACHE_SETTINGS_MHW_RENDER_ENGINE_L3_CACHE_SETTINGS57 virtual ~_MHW_RENDER_ENGINE_L3_CACHE_SETTINGS() {} 58 } MHW_RENDER_ENGINE_L3_CACHE_SETTINGS, *PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS; 59 60 typedef struct _MHW_RENDER_ENGINE_L3_CACHE_CONFIG 61 { 62 uint32_t dwL3CacheCntlReg_Register = 0; 63 uint32_t dwL3CacheCntlReg_Setting = 0; 64 uint32_t dwL3CacheCntlReg2_Register = 0; 65 uint32_t dwL3CacheCntlReg2_Setting = 0; 66 uint32_t dwL3CacheCntlReg3_Register = 0; 67 uint32_t dwL3CacheCntlReg3_Setting = 0; 68 uint32_t dwL3CacheSqcReg1_Register = 0; 69 uint32_t dwL3CacheSqcReg1_Setting = 0; 70 uint32_t dwL3CacheSqcReg4_Register = 0; 71 uint32_t dwL3CacheSqcReg4_Setting = 0; 72 uint32_t dwL3LRA1Reg_Register = 0; 73 uint32_t dwL3LRA1Reg_Setting = 0; 74 bool bL3CachingEnabled = false; 75 bool bL3LRA1Reset = false; 76 } MHW_RENDER_ENGINE_L3_CACHE_CONFIG, *PMHW_RENDER_ENGINE_L3_CACHE_CONFIG; 77 78 typedef enum _MHW_RENDER_ENGINE_ADDRESS_SHIFT 79 { 80 MHW_RENDER_ENGINE_KERNEL_POINTER_SHIFT = 6, 81 MHW_RENDER_ENGINE_STATE_BASE_ADDRESS_SHIFT = 12 82 } MHW_RENDER_ENGINE_ADDRESS_SHIFT; 83 84 typedef enum _MHW_VFE_SLICE_DISABLE 85 { 86 MHW_VFE_SLICE_ALL = 0, 87 MHW_VFE_SLICE0_SUBSLICE_ALL, 88 MHW_VFE_SLICE0_SUBSLICE0 89 } MHW_VFE_SLICE_DISABLE; 90 91 typedef enum _MHW_WALKER_MODE 92 { 93 MHW_WALKER_MODE_NOT_SET = -1, 94 MHW_WALKER_MODE_DISABLED = 0, 95 MHW_WALKER_MODE_SINGLE = 1, // dual = 0, repel = 1 96 MHW_WALKER_MODE_DUAL = 2, // dual = 1, repel = 0) 97 MHW_WALKER_MODE_TRI = 3, // applies in BDW GT2 which has 1 slice and 3 sampler/VME per slice 98 MHW_WALKER_MODE_QUAD = 4, // applies in HSW GT3 which has 2 slices and 2 sampler/VME per slice 99 MHW_WALKER_MODE_HEX = 6, // applies in BDW GT2 which has 2 slices and 3 sampler/VME per slice 100 MHW_WALKER_MODE_OCT = 8 // may apply in future Gen media architectures 101 } MHW_WALKER_MODE; 102 103 typedef enum _MHW_EMIT_LOCAL_MODE 104 { 105 MHW_EMIT_LOCAL_NONE = 0, 106 MHW_EMIT_LOCAL_X = 1, 107 MHW_EMIT_LOCAL_XY = 3, 108 MHW_EMIT_LOCAL_XYZ = 7 109 } MHW_EMIT_LOCAL_MODE; 110 111 //! 112 //! \brief Structure to capture HW capabilities 113 //! 114 typedef struct _MHW_RENDER_ENGINE_CAPS 115 { 116 uint32_t dwMaxUnormSamplers; // Max UNORM Sampler States supported 117 uint32_t dwMaxAVSSamplers; // Max AVS Sampler States supported 118 uint32_t dwMaxBTIndex; // Max Binding Table index per Binding Table 119 uint32_t dwMaxThreads; // Max Threads supported 120 uint32_t dwMaxMediaPayloadSize; // Max Media payload size 121 uint32_t dwMaxURBSize; // Max URB Size 122 uint32_t dwMaxURBEntries; // Max URB Entries 123 uint32_t dwMaxURBEntryAllocationSize; // Max URB Entry Allocation Size 124 uint32_t dwMaxCURBEAllocationSize; 125 uint32_t dwMaxInterfaceDescriptorEntries; // Max Interface Descriptor Entries 126 uint32_t dwMaxSubslice; // Max number of subslice 127 uint32_t dwMaxEUIndex; // Max EU index (sometimes != number of EU) 128 uint32_t dwNumThreadsPerEU; // Num threads per EU 129 uint32_t dwSizeRegistersPerThread; // Size of all registers per thread (for ASM Debug) 130 } MHW_RENDER_ENGINE_CAPS, *PMHW_RENDER_ENGINE_CAPS; 131 132 typedef struct _MHW_STATE_BASE_ADDR_PARAMS 133 { 134 PMOS_RESOURCE presGeneralState; 135 uint32_t dwGeneralStateSize; 136 PMOS_RESOURCE presDynamicState; 137 uint32_t dwDynamicStateSize; 138 bool bDynamicStateRenderTarget; 139 PMOS_RESOURCE presIndirectObjectBuffer; 140 uint32_t dwIndirectObjectBufferSize; 141 PMOS_RESOURCE presInstructionBuffer; 142 uint32_t dwInstructionBufferSize; 143 uint32_t mocs4InstructionCache; 144 uint32_t mocs4GeneralState; 145 uint32_t mocs4DynamicState; 146 uint32_t mocs4SurfaceState; 147 uint32_t mocs4IndirectObjectBuffer; 148 uint32_t mocs4StatelessDataport; 149 uint32_t l1CacheConfig; 150 bool addressDis; 151 } MHW_STATE_BASE_ADDR_PARAMS, *PMHW_STATE_BASE_ADDR_PARAMS; 152 153 typedef struct _MHW_VFE_SCOREBOARD_DELTA 154 { 155 uint8_t x : 4; 156 uint8_t y : 4; 157 } MHW_VFE_SCOREBOARD_DELTA, *PMHW_VFE_SCOREBOARD_DELTA; 158 159 typedef struct _MHW_VFE_SCOREBOARD 160 { 161 struct 162 { 163 uint32_t ScoreboardMask : 8; 164 uint32_t ScoreboardColor : 4; 165 uint32_t : 18; 166 uint32_t ScoreboardType : 1; 167 uint32_t ScoreboardEnable : 1; 168 }; 169 170 union 171 { 172 MHW_VFE_SCOREBOARD_DELTA ScoreboardDelta[MHW_MAX_DEPENDENCY_COUNT]; 173 struct 174 { 175 uint32_t Value[2]; 176 }; 177 }; 178 } MHW_VFE_SCOREBOARD, *PMHW_VFE_SCOREBOARD; 179 180 struct MHW_VFE_PARAMS 181 { 182 uint32_t dwDebugCounterControl = 0; // Debug Counter Control 183 uint32_t dwMaximumNumberofThreads = 0; 184 uint32_t dwNumberofURBEntries = 0; 185 uint32_t dwCURBEAllocationSize = 0; 186 uint32_t dwURBEntryAllocationSize = 0; 187 uint32_t dwPerThreadScratchSpace = 0; 188 uint32_t dwScratchSpaceBasePointer = 0; 189 MHW_VFE_SLICE_DISABLE eVfeSliceDisable = MHW_VFE_SLICE_ALL; 190 MHW_VFE_SCOREBOARD Scoreboard = {}; 191 PMHW_KERNEL_STATE pKernelState = nullptr; ~MHW_VFE_PARAMSMHW_VFE_PARAMS192 virtual ~MHW_VFE_PARAMS() {} 193 }; 194 typedef MHW_VFE_PARAMS *PMHW_VFE_PARAMS; 195 196 typedef struct _MHW_CURBE_LOAD_PARAMS 197 { 198 PMHW_KERNEL_STATE pKernelState; 199 bool bOldInterface; 200 uint32_t dwCURBETotalDataLength; 201 uint32_t dwCURBEDataStartAddress; 202 } MHW_CURBE_LOAD_PARAMS, *PMHW_CURBE_LOAD_PARAMS; 203 204 typedef struct _MHW_ID_LOAD_PARAMS 205 { 206 PMHW_KERNEL_STATE pKernelState; 207 uint32_t dwNumKernelsLoaded; 208 uint32_t dwIdIdx; 209 uint32_t dwInterfaceDescriptorStartOffset; 210 uint32_t dwInterfaceDescriptorLength; 211 } MHW_ID_LOAD_PARAMS, *PMHW_ID_LOAD_PARAMS; 212 213 typedef struct _MHW_SIP_STATE_PARAMS 214 { 215 bool bSipKernel; 216 uint32_t dwSipBase; 217 } MHW_SIP_STATE_PARAMS, *PMHW_SIP_STATE_PARAMS; 218 219 typedef struct _MHW_WALKER_XY 220 { 221 union 222 { 223 struct 224 { 225 uint32_t x : 16; 226 uint32_t y : 16; 227 }; 228 uint32_t value; 229 }; 230 } MHW_WALKER_XY, *PMHW_WALKER_XY; 231 232 typedef struct _MHW_PALETTE_PARAMS 233 { 234 int32_t iPaletteID; //!< Palette ID 235 int32_t iNumEntries; //!< Palette entries in use 236 void* pPaletteData; //!< Palette data 237 } MHW_PALETTE_PARAMS, *PMHW_PALETTE_PARAMS; 238 239 typedef struct _MHW_CHROMAKEY_PARAMS 240 { 241 uint32_t dwIndex; //!< Chroma Key Index 242 uint32_t dwLow; //!< Chroma Key Low 243 uint32_t dwHigh; //!< Chroma Key High 244 } MHW_CHROMAKEY_PARAMS, *PMHW_CHROMAKEY_PARAMS; 245 246 // IMPORTANT - changes in this structure must 247 // be ported to CM_HAL_WALKER_PARAMS in cm_common.h 248 typedef struct _MHW_WALKER_PARAMS 249 { 250 uint32_t InterfaceDescriptorOffset : 5; 251 uint32_t CmWalkerEnable : 1; 252 uint32_t ColorCountMinusOne : 8; 253 uint32_t UseScoreboard : 1; 254 uint32_t ScoreboardMask : 8; 255 uint32_t MidLoopUnitX : 2; 256 uint32_t MidLoopUnitY : 2; 257 uint32_t MiddleLoopExtraSteps : 5; 258 259 uint32_t GroupIdLoopSelect : 24; 260 uint32_t : 8; 261 262 uint32_t InlineDataLength; 263 uint8_t* pInlineData; 264 uint32_t dwLocalLoopExecCount; 265 uint32_t dwGlobalLoopExecCount; 266 267 MHW_WALKER_MODE WalkerMode; 268 MHW_WALKER_XY BlockResolution; 269 MHW_WALKER_XY LocalStart; 270 MHW_WALKER_XY LocalEnd; 271 MHW_WALKER_XY LocalOutLoopStride; 272 MHW_WALKER_XY LocalInnerLoopUnit; 273 MHW_WALKER_XY GlobalResolution; 274 MHW_WALKER_XY GlobalStart; 275 MHW_WALKER_XY GlobalOutlerLoopStride; 276 MHW_WALKER_XY GlobalInnerLoopUnit; 277 278 bool bAddMediaFlush; 279 bool bRequestSingleSlice; 280 281 uint32_t IndirectDataLength; 282 uint32_t IndirectDataStartAddress; 283 } MHW_WALKER_PARAMS, *PMHW_WALKER_PARAMS; 284 285 typedef struct _MHW_GPGPU_WALKER_PARAMS 286 { 287 uint32_t InterfaceDescriptorOffset : 5; 288 uint32_t GpGpuEnable : 1; 289 uint32_t : 26; 290 uint32_t ThreadWidth; 291 uint32_t ThreadHeight; 292 uint32_t ThreadDepth; 293 uint32_t GroupWidth; 294 uint32_t GroupHeight; 295 uint32_t GroupDepth; 296 uint32_t GroupStartingX; 297 uint32_t GroupStartingY; 298 uint32_t GroupStartingZ; 299 uint32_t SLMSize; 300 301 uint32_t IndirectDataLength; 302 uint32_t IndirectDataStartAddress; 303 uint32_t BindingTableID; 304 uint32_t ForcePreferredSLMZero; 305 306 bool isEmitInlineParameter; 307 uint32_t inlineDataLength; 308 uint8_t* inlineData; 309 310 bool isGenerateLocalID; 311 MHW_EMIT_LOCAL_MODE emitLocal; 312 313 bool hasBarrier; 314 PMHW_INLINE_DATA_PARAMS inlineDataParamBase; 315 uint32_t inlineDataParamSize; 316 317 } MHW_GPGPU_WALKER_PARAMS, *PMHW_GPGPU_WALKER_PARAMS; 318 319 typedef struct _MHW_MEDIA_OBJECT_PARAMS 320 { 321 uint32_t dwInterfaceDescriptorOffset; 322 uint32_t dwHalfSliceDestinationSelect; 323 uint32_t dwSliceDestinationSelect; 324 uint32_t dwIndirectLoadLength; 325 uint32_t dwIndirectDataStartAddress; 326 void* pInlineData; 327 uint32_t dwInlineDataSize; 328 bool bForceDestination; 329 MHW_VFE_SCOREBOARD VfeScoreboard; 330 } MHW_MEDIA_OBJECT_PARAMS, *PMHW_MEDIA_OBJECT_PARAMS; 331 332 #endif // __MHW_RENDER_H__