1 /* 2 * Copyright (c) 2015-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_hwcmd_g12_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g12_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_RENDER_HWCMD_G12_X_H__ 29 #define __MHW_RENDER_HWCMD_G12_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_render_g12_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MEDIA_OBJECT 50 //! \details 51 //! 52 //! 53 struct MEDIA_OBJECT_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 61 uint32_t MediaCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< MEDIA_COMMAND_SUB_OPCODE 62 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 63 uint32_t MediaCommandPipeline : __CODEGEN_BITFIELD(27, 28) ; //!< MEDIA_COMMAND_PIPELINE 64 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 65 }; 66 uint32_t Value; 67 } DW0; 68 union 69 { 70 //!< DWORD 1 71 struct 72 { 73 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 74 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 75 }; 76 uint32_t Value; 77 } DW1; 78 union 79 { 80 //!< DWORD 2 81 struct 82 { 83 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 84 uint32_t SubsliceDestinationSelect : __CODEGEN_BITFIELD(17, 18) ; //!< SUBSLICE_DESTINATION_SELECT 85 uint32_t SliceDestinationSelect : __CODEGEN_BITFIELD(19, 20) ; //!< SLICE_DESTINATION_SELECT 86 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 87 uint32_t ForceDestination : __CODEGEN_BITFIELD(22, 22) ; //!< Force Destination 88 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 89 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 90 uint32_t SliceDestinationSelectMsbs : __CODEGEN_BITFIELD(25, 26) ; //!< Slice Destination Select MSBs 91 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 92 }; 93 uint32_t Value; 94 } DW2; 95 union 96 { 97 //!< DWORD 3 98 struct 99 { 100 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 101 }; 102 uint32_t Value; 103 } DW3; 104 union 105 { 106 //!< DWORD 4 107 struct 108 { 109 uint32_t XPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< X Position 110 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 111 uint32_t YPosition : __CODEGEN_BITFIELD(16, 24) ; //!< Y Position 112 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 113 }; 114 uint32_t Value; 115 } DW4; 116 union 117 { 118 //!< DWORD 5 119 struct 120 { 121 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 122 uint32_t BlockColor : __CODEGEN_BITFIELD(16, 23) ; //!< Block Color 123 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 124 }; 125 uint32_t Value; 126 } DW5; 127 128 //! \name Local enumerations 129 130 enum MEDIA_COMMAND_SUB_OPCODE 131 { 132 MEDIA_COMMAND_SUB_OPCODE_MEDIAOBJECTSUBOP = 0, //!< No additional details 133 }; 134 135 enum MEDIA_COMMAND_OPCODE 136 { 137 MEDIA_COMMAND_OPCODE_MEDIAOBJECT = 1, //!< No additional details 138 }; 139 140 enum MEDIA_COMMAND_PIPELINE 141 { 142 MEDIA_COMMAND_PIPELINE_MEDIA = 2, //!< No additional details 143 }; 144 145 enum COMMAND_TYPE 146 { 147 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 148 }; 149 150 //! \brief SUBSLICE_DESTINATION_SELECT 151 //! \details 152 //! This field selects the SubSlice that this thread must be sent to. 153 //! Ignored if <b>Force Destination</b> = 0 154 enum SUBSLICE_DESTINATION_SELECT 155 { 156 SUBSLICE_DESTINATION_SELECT_SUBSLICE0 = 0, //!< No additional details 157 SUBSLICE_DESTINATION_SELECT_SUBSLICE1 = 1, //!< No additional details 158 SUBSLICE_DESTINATION_SELECT_SUBSLICE2 = 2, //!< No additional details 159 SUBSLICE_DESTINATION_SELECT_SUBSLICE3 = 3, //!< No additional details 160 }; 161 162 //! \brief SLICE_DESTINATION_SELECT 163 //! \details 164 //! This bit along with the subslice destination select determines the slice 165 //! that this thread must be sent to. Ignored if <b>Force Destination</b> = 166 //! 0, or if product only has 1 slice. 167 enum SLICE_DESTINATION_SELECT 168 { 169 SLICE_DESTINATION_SELECT_SLICE0 = 0, //!< No additional details 170 SLICE_DESTINATION_SELECT_SLICE1 = 1, //!< Cannot be used in products without a Slice 1. 171 SLICE_DESTINATION_SELECT_SLICE2 = 2, //!< Cannot be used in products without a Slice 2. 172 }; 173 174 //! \brief THREAD_SYNCHRONIZATION 175 //! \details 176 //! This field when set indicates that the dispatch of the thread originated 177 //! from this command is based on the "spawn root thread" message. 178 enum THREAD_SYNCHRONIZATION 179 { 180 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 181 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 182 }; 183 184 //! \name Initializations 185 186 //! \brief Explicit member initialization function 187 MEDIA_OBJECT_CMD(); 188 189 static const size_t dwSize = 6; 190 static const size_t byteSize = 24; 191 }; 192 193 //! 194 //! \brief PIPELINE_SELECT 195 //! \details 196 //! The PIPELINE_SELECT command is used to specify which GPE pipeline is to 197 //! be considered the 'current' active pipeline. Issuing 198 //! 3D-pipeline-specific commands when the Media pipeline is selected, or 199 //! vice versa, is UNDEFINED. 200 //! 201 //! Issuing 3D-pipeline-specific commands when the GPGPU pipeline is 202 //! selected, or vice versa, is UNDEFINED. 203 //! 204 //! Programming common non pipeline commands (e.g., STATE_BASE_ADDRESS) is 205 //! allowed in all pipeline modes. 206 //! 207 //! Software must ensure all the write caches are flushed through a stalling 208 //! PIPE_CONTROL command followed by another PIPE_CONTROL command to 209 //! invalidate read only caches prior to programming MI_PIPELINE_SELECT 210 //! command to change the Pipeline Select Mode. Example: ... Workload-3Dmode 211 //! PIPE_CONTROL (CS Stall, Depth Cache Flush Enable, Render Target Cache 212 //! Flush Enable, DC Flush Enable) PIPE_CONTROL (Constant Cache Invalidate, 213 //! Texture Cache Invalidate, Instruction Cache Invalidate, State Cache 214 //! invalidate) PIPELINE_SELECT ( GPGPU) 215 //! 216 struct PIPELINE_SELECT_CMD 217 { 218 union 219 { 220 //!< DWORD 0 221 struct 222 { 223 uint32_t PipelineSelection : __CODEGEN_BITFIELD( 0, 1) ; //!< PIPELINE_SELECTION 224 uint32_t RenderSliceCommonPowerGateEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< RENDER_SLICE_COMMON_POWER_GATE_ENABLE 225 uint32_t RenderSamplerPowerGateEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< RENDER_SAMPLER_POWER_GATE_ENABLE 226 uint32_t MediaSamplerDopClockGateEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 227 uint32_t ForceMediaAwake : __CODEGEN_BITFIELD( 5, 5) ; //!< FORCE_MEDIA_AWAKE 228 uint32_t MediaSamplerPowerClockGateDisable : __CODEGEN_BITFIELD( 6, 6) ; //!< Media Sampler Power Clock Gate Disable 229 uint32_t Reserved7 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 230 uint32_t MaskBits : __CODEGEN_BITFIELD( 8, 15) ; //!< Mask Bits 231 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 232 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 233 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 234 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 235 }; 236 uint32_t Value; 237 } DW0; 238 239 //! \name Local enumerations 240 241 //! \brief PIPELINE_SELECTION 242 //! \details 243 //! Mask bits [9:8] has to be set for HW to look at this field when 244 //! PIPELINE_SELECT command is parsed. Setting only one of the mask bit [9] 245 //! or [8] is illegal. 246 enum PIPELINE_SELECTION 247 { 248 PIPELINE_SELECTION_3D = 0, //!< 3D pipeline is selected 249 PIPELINE_SELECTION_MEDIA = 1, //!< Media pipeline is selected (Includes HD optical disc playback, HD video playback, and generic media workloads) 250 PIPELINE_SELECTION_GPGPU = 2, //!< GPGPU pipeline is selected 251 }; 252 253 //! \brief RENDER_SLICE_COMMON_POWER_GATE_ENABLE 254 //! \details 255 //! Mask bit [10] has to be set for HW to look at this field when 256 //! PIPELINE_SELECT command is parsed. 257 enum RENDER_SLICE_COMMON_POWER_GATE_ENABLE 258 { 259 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render slice common Power Gating. 260 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render slice common Power Gating. 261 }; 262 263 //! \brief RENDER_SAMPLER_POWER_GATE_ENABLE 264 //! \details 265 //! Mask bit [11] has to be set for HW to look at this field when 266 //! PIPELINE_SELECT command is parsed. 267 enum RENDER_SAMPLER_POWER_GATE_ENABLE 268 { 269 RENDER_SAMPLER_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render sampler Power Gating. 270 RENDER_SAMPLER_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render sampler Power Gating. 271 }; 272 273 //! \brief MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 274 //! \details 275 //! Mask bit [12] has to be set for HW to look at this field when 276 //! PIPELINE_SELECT command is parsed. 277 enum MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 278 { 279 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable sampler DOP Clock Gating. 280 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable media sampler DOP Clock Gating. 281 }; 282 283 //! \brief FORCE_MEDIA_AWAKE 284 //! \details 285 //! Mask bit [13] has to be set for HW to look at this field when 286 //! PIPELINE_SELECT command is parsed. 287 //! 288 //! Example for usage model: 289 //! 290 //! <b>RCS Ring Buffer</b>: 291 //! <b>PIPELINE_SELECT (Force Media Awake set to '1')</b> 292 //! MI_SEMPAHORE_SINGAL (Signal context id 0xABC to Render Command 293 //! Streamer) 294 //! <b>PIPELINE_SELECT (Force Media Awake set to '0')</b> 295 //! <b>MI_BATCH_BUFFER_START</b> 296 //! STATE Commands .. 297 //! ………… 298 //! <b>PIPELINE_SELECT (Force Media Awake set to '1')</b> 299 //! MI_LOAD_REGISTER_IMM (Load register 0x23XX in render command 300 //! streamer with data 0xFFF) 301 //! <b>PIPELINE_SELECT (Force Media Awake set to '0')</b> 302 //! ………… 303 //! <b>MI_BATCH_BUFFER_END</b> 304 enum FORCE_MEDIA_AWAKE 305 { 306 FORCE_MEDIA_AWAKE_DISABLED = 0, //!< Command streamer sends message to PM to disable force awake of media engine (next instructions do not require the media engine to be awake). Command streamer waits for acknowledge from PM before parsing the next command. 307 FORCE_MEDIA_AWAKE_ENABLED = 1, //!< Command streamer sends message to PM to force awake media engine (next instructions require media engine awake). Command streamer waits for acknowledge from PM before parsing the next command. 308 }; 309 310 enum _3D_COMMAND_SUB_OPCODE 311 { 312 _3D_COMMAND_SUB_OPCODE_PIPELINESELECT = 4, //!< No additional details 313 }; 314 315 enum _3D_COMMAND_OPCODE 316 { 317 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 318 }; 319 320 enum COMMAND_SUBTYPE 321 { 322 COMMAND_SUBTYPE_GFXPIPESINGLEDW = 1, //!< No additional details 323 }; 324 325 enum COMMAND_TYPE 326 { 327 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 328 }; 329 330 //! \name Initializations 331 332 //! \brief Explicit member initialization function 333 PIPELINE_SELECT_CMD(); 334 335 static const size_t dwSize = 1; 336 static const size_t byteSize = 4; 337 }; 338 339 //! 340 //! \brief STATE_BASE_ADDRESS 341 //! \details 342 //! The STATE_BASE_ADDRESS command sets the base pointers for subsequent 343 //! state, instruction, and media indirect object accesses by the GPE. 344 //! For more information see the Base Address Utilization table in the 345 //! Memory Access Indirection narrative topic. 346 //! 347 //! The following commands must be reissued following any change to the base 348 //! addresses: 3DSTATE_CC_POINTERS 349 //! 3DSTATE_BINDING_TABLE_POINTERS 350 //! 3DSTATE_SAMPLER_STATE_POINTERS 351 //! 3DSTATE_VIEWPORT_STATE_POINTERS 352 //! MEDIA_STATE_POINTERS 353 //! Execution of this command causes a full pipeline flush, thus its use 354 //! should be minimized for higher performance. 355 //! 356 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 357 //! Cache Flush Enable" set before programming STATE_BASE_ADDRESS command 358 //! for GPGPU workloads i.e when pipeline select is GPGPU via 359 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 360 //! preemption latencies in certain workload programming sequences. If 361 //! programming PIPE_CONTROL has performance implications then preemption 362 //! latencies can be traded off against performance by not implementing this 363 //! programming note. 364 //! 365 struct STATE_BASE_ADDRESS_CMD 366 { 367 union 368 { 369 //!< DWORD 0 370 struct 371 { 372 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 373 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 374 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 375 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 376 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 377 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 378 }; 379 uint32_t Value; 380 } DW0; 381 union 382 { 383 //!< DWORD 1..2 384 struct 385 { 386 uint64_t GeneralStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 387 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 388 uint64_t GeneralStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< General State Memory Object Control State 389 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 390 uint64_t GeneralStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< General State Base Address 391 }; 392 uint32_t Value[2]; 393 } DW1_2; 394 union 395 { 396 //!< DWORD 3 397 struct 398 { 399 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 13) ; //!< Reserved 400 uint32_t DisableSupportforMultiGPUAtomicsforStatelessAccesses : __CODEGEN_BITFIELD(14, 14) ; //!< 401 uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : __CODEGEN_BITFIELD(15, 15) ; //!< 402 uint32_t StatelessDataPortAccessMemoryObjectControlState : __CODEGEN_BITFIELD(16, 22) ; //!< Stateless Data Port Access Memory Object Control State 403 uint32_t Reserved119 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 404 }; 405 uint32_t Value; 406 } DW3; 407 union 408 { 409 //!< DWORD 4..5 410 struct 411 { 412 uint64_t SurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 413 uint64_t Reserved129 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 414 uint64_t SurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Surface State Memory Object Control State 415 uint64_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 416 uint64_t SurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Surface State Base Address 417 }; 418 uint32_t Value[2]; 419 } DW4_5; 420 union 421 { 422 //!< DWORD 6..7 423 struct 424 { 425 uint64_t DynamicStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 426 uint64_t Reserved193 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 427 uint64_t DynamicStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Dynamic State Memory Object Control State 428 uint64_t Reserved203 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 429 uint64_t DynamicStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Dynamic State Base Address 430 }; 431 uint32_t Value[2]; 432 } DW6_7; 433 union 434 { 435 //!< DWORD 8..9 436 struct 437 { 438 uint64_t IndirectObjectBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 439 uint64_t Reserved257 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 440 uint64_t IndirectObjectMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Indirect Object Memory Object Control State 441 uint64_t Reserved267 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 442 uint64_t IndirectObjectBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Indirect Object Base Address 443 }; 444 uint32_t Value[2]; 445 } DW8_9; 446 union 447 { 448 //!< DWORD 10..11 449 struct 450 { 451 uint64_t InstructionBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 452 uint64_t Reserved321 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 453 uint64_t InstructionMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Instruction Memory Object Control State 454 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 455 uint64_t InstructionBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Instruction Base Address 456 }; 457 uint32_t Value[2]; 458 } DW10_11; 459 union 460 { 461 //!< DWORD 12 462 struct 463 { 464 uint32_t GeneralStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 465 uint32_t Reserved385 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 466 uint32_t GeneralStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< General State Buffer Size 467 }; 468 uint32_t Value; 469 } DW12; 470 union 471 { 472 //!< DWORD 13 473 struct 474 { 475 uint32_t DynamicStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 476 uint32_t Reserved417 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 477 uint32_t DynamicStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Dynamic State Buffer Size 478 }; 479 uint32_t Value; 480 } DW13; 481 union 482 { 483 //!< DWORD 14 484 struct 485 { 486 uint32_t IndirectObjectBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 487 uint32_t Reserved449 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 488 uint32_t IndirectObjectBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Indirect Object Buffer Size 489 }; 490 uint32_t Value; 491 } DW14; 492 union 493 { 494 //!< DWORD 15 495 struct 496 { 497 uint32_t InstructionBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 498 uint32_t Reserved481 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 499 uint32_t InstructionBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Instruction Buffer Size 500 }; 501 uint32_t Value; 502 } DW15; 503 union 504 { 505 //!< DWORD 16..17 506 struct 507 { 508 uint64_t BindlessSurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 509 uint64_t Reserved513 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 510 uint64_t BindlessSurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Surface State Memory Object Control State 511 uint64_t Reserved523 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 512 uint64_t BindlessSurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Surface State Base Address 513 }; 514 uint32_t Value[2]; 515 } DW16_17; 516 union 517 { 518 //!< DWORD 18 519 struct 520 { 521 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 522 uint32_t BindlessSurfaceStateSize : __CODEGEN_BITFIELD(12, 31) ; //!< Bindless Surface State Size 523 }; 524 uint32_t Value; 525 } DW18; 526 union 527 { 528 //!< DWORD 19..20 529 struct 530 { 531 uint64_t BindlessSamplerStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 532 uint64_t Reserved609 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 533 uint64_t BindlessSamplerStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Sampler State Memory Object Control State 534 uint64_t Reserved619 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 535 uint64_t BindlessSamplerStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Sampler State Base Address 536 }; 537 uint32_t Value[2]; 538 } DW19_20; 539 union 540 { 541 //!< DWORD 21 542 struct 543 { 544 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 545 uint32_t BindlessSamplerStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Bindless Sampler State Buffer Size 546 }; 547 uint32_t Value; 548 } DW21; 549 550 //! \name Local enumerations 551 552 enum _3D_COMMAND_SUB_OPCODE 553 { 554 _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS = 1, //!< No additional details 555 }; 556 557 enum _3D_COMMAND_OPCODE 558 { 559 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 560 }; 561 562 enum COMMAND_SUBTYPE 563 { 564 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 565 }; 566 567 enum COMMAND_TYPE 568 { 569 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 570 }; 571 572 //! \brief GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 573 //! \details 574 //! <p>The other fields in this DWord and the following DWord are updated 575 //! only when this bit is set.</p> 576 enum GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 577 { 578 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 579 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 580 }; 581 582 //! \brief SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 583 //! \details 584 //! The other fields in this DWord and the following DWord are updated only 585 //! when this bit is set. 586 enum SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 587 { 588 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 589 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 590 }; 591 592 //! \brief DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 593 //! \details 594 //! The other fields in this DWord and the following DWord are updated only 595 //! when this bit is set. 596 enum DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 597 { 598 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 599 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 600 }; 601 602 //! \brief INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 603 //! \details 604 //! <p>The other fields in this DWord and the following DWord are updated 605 //! only when this bit is set.</p> 606 enum INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 607 { 608 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 609 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 610 }; 611 612 //! \brief INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 613 //! \details 614 //! <p>The other fields in this DWord and the following DWord are updated 615 //! only when this bit is set.</p> 616 enum INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 617 { 618 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 619 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 620 }; 621 622 //! \brief GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 623 //! \details 624 //! The bound in this DWord is updated only when this bit is set. 625 enum GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 626 { 627 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 628 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 629 }; 630 631 //! \brief DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 632 //! \details 633 //! FormatDesc 634 enum DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 635 { 636 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 637 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 638 }; 639 640 //! \brief INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 641 //! \details 642 //! FormatDesc 643 enum INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 644 { 645 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 646 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 647 }; 648 649 //! \brief INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 650 //! \details 651 //! FormatDesc 652 enum INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 653 { 654 INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 655 }; 656 657 //! \brief BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 658 //! \details 659 //! <p>The other fields in this DWord are updated only when this bit is 660 //! set.</p> 661 enum BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 662 { 663 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 664 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 665 }; 666 667 //! \brief BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 668 //! \details 669 //! <p>The other fields in this DWord and the following two DWords are 670 //! updated only when this bit is set.</p> 671 enum BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 672 { 673 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 674 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 675 }; 676 677 //! \name Initializations 678 679 //! \brief Explicit member initialization function 680 STATE_BASE_ADDRESS_CMD(); 681 682 static const size_t dwSize = 22; 683 static const size_t byteSize = 88; 684 }; 685 686 //! 687 //! \brief MEDIA_VFE_STATE 688 //! \details 689 //! A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless the 690 //! only bits that are changed are scoreboard related: Scoreboard Enable, 691 //! Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For these 692 //! scoreboard related states, a MEDIA_STATE_FLUSH is sufficient. 693 //! 694 //! MEDIA_STATE_FLUSH (optional, only if barrier dependency is needed) 695 //! 696 //! MEDIA_INTERFACE_DESCRIPTOR_LOAD (optional) 697 //! 698 //! 699 //! 700 struct MEDIA_VFE_STATE_CMD 701 { 702 union 703 { 704 //!< DWORD 0 705 struct 706 { 707 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 708 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 709 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 710 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 711 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 712 }; 713 uint32_t Value; 714 } DW0; 715 union 716 { 717 //!< DWORD 1 718 struct 719 { 720 uint32_t PerThreadScratchSpace : __CODEGEN_BITFIELD( 0, 3) ; //!< Per Thread Scratch Space 721 uint32_t StackSize : __CODEGEN_BITFIELD( 4, 7) ; //!< Stack Size 722 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 9) ; //!< Reserved 723 uint32_t ScratchSpaceBasePointer : __CODEGEN_BITFIELD(10, 31) ; //!< Scratch Space Base Pointer 724 }; 725 uint32_t Value; 726 } DW1; 727 union 728 { 729 //!< DWORD 2 730 struct 731 { 732 uint32_t ScratchSpaceBasePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scratch Space Base Pointer High 733 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 734 }; 735 uint32_t Value; 736 } DW2; 737 union 738 { 739 //!< DWORD 3 740 struct 741 { 742 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 743 uint32_t DispatchLoadBalance : __CODEGEN_BITFIELD( 2, 2) ; //!< DISPATCH_LOAD_BALANCE 744 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 745 uint32_t FusedEuDispatch : __CODEGEN_BITFIELD( 6, 6) ; //!< FUSED_EU_DISPATCH 746 uint32_t Reserved103 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 747 uint32_t NumberOfUrbEntries : __CODEGEN_BITFIELD( 8, 15) ; //!< Number of URB Entries 748 uint32_t MaximumNumberOfThreads : __CODEGEN_BITFIELD(16, 31) ; //!< Maximum Number of Threads 749 }; 750 uint32_t Value; 751 } DW3; 752 union 753 { 754 //!< DWORD 4 755 struct 756 { 757 uint32_t MaximumNumberOfDualSubslices : __CODEGEN_BITFIELD( 0, 7) ; //!< Maximum Number of Dual-Subslices 758 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 759 }; 760 uint32_t Value; 761 } DW4; 762 union 763 { 764 //!< DWORD 5 765 struct 766 { 767 uint32_t CurbeAllocationSize : __CODEGEN_BITFIELD( 0, 15) ; //!< CURBE Allocation Size 768 uint32_t UrbEntryAllocationSize : __CODEGEN_BITFIELD(16, 31) ; //!< URB Entry Allocation Size 769 }; 770 uint32_t Value; 771 } DW5; 772 union 773 { 774 //!< DWORD 6 775 struct 776 { 777 uint32_t Reserved192 ; //!< Reserved 778 }; 779 uint32_t Value; 780 } DW6; 781 union 782 { 783 //!< DWORD 7 784 struct 785 { 786 uint32_t Reserved224 ; //!< Reserved 787 }; 788 uint32_t Value; 789 } DW7; 790 union 791 { 792 //!< DWORD 8 793 struct 794 { 795 uint32_t Reserved256 ; //!< Reserved 796 }; 797 uint32_t Value; 798 } DW8; 799 800 //! \name Local enumerations 801 802 enum SUBOPCODE 803 { 804 SUBOPCODE_MEDIAVFESTATESUBOP = 0, //!< No additional details 805 }; 806 807 enum MEDIA_COMMAND_OPCODE 808 { 809 MEDIA_COMMAND_OPCODE_MEDIAVFESTATE = 0, //!< No additional details 810 }; 811 812 enum PIPELINE 813 { 814 PIPELINE_MEDIA = 2, //!< No additional details 815 }; 816 817 enum COMMAND_TYPE 818 { 819 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 820 }; 821 822 //! \brief DISPATCH_LOAD_BALANCE 823 //! \details 824 //! This bit determines how media threads are dispatched between the various 825 //! dual subslices. GPGPU threads are not impacted by this bit. 826 enum DISPATCH_LOAD_BALANCE 827 { 828 DISPATCH_LOAD_BALANCE_LEASTLOADED = 0, //!< When this value is used the threads are sent to the least loaded dual subslice of all active dual subslices. If media with groups is being used then each group is kept in the same dual subslice. 829 DISPATCH_LOAD_BALANCE_COLORLSB = 1, //!< When this value is used the threads are split into two groups depending on the LSB of the color value for media threads. One group will be sent to even dual subslices and the other to odd dual subslices. The least loaded active dual subslice available will selected for threads in that group. This allows color to be used to separate workloads with different operations to get better cache coherency.If media with groups is being used then each group is kept in the same dual subslices. 830 }; 831 832 //! \brief FUSED_EU_DISPATCH 833 //! \details 834 //! This field determine if threads will be dispatched in sets to fused EUs 835 //! if set or if they will be dispatched individually. Depending of the 836 //! project the set size can be 2 or 4. If dispatched in sets the fused 837 //! threads will all be part of the same thread group for GPGPU threads or 838 //! will be part of the same iteration of the inner local loop if media 839 //! threads. 840 enum FUSED_EU_DISPATCH 841 { 842 FUSED_EU_DISPATCH_FUSEDEUMODE = 0, //!< No additional details 843 FUSED_EU_DISPATCH_LEGACYMODE_THREADSARENOTFUSED = 1, //!< No additional details 844 }; 845 846 //! \name Initializations 847 848 //! \brief Explicit member initialization function 849 MEDIA_VFE_STATE_CMD(); 850 851 static const size_t dwSize = 9; 852 static const size_t byteSize = 36; 853 }; 854 855 //! 856 //! \brief MEDIA_CURBE_LOAD 857 //! \details 858 //! See "GPGPU Command" section for additional 859 //! programming constraints for this command. 860 //! 861 struct MEDIA_CURBE_LOAD_CMD 862 { 863 union 864 { 865 //!< DWORD 0 866 struct 867 { 868 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 869 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 870 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 871 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 872 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 873 }; 874 uint32_t Value; 875 } DW0; 876 union 877 { 878 //!< DWORD 1 879 struct 880 { 881 uint32_t Reserved32 ; //!< Reserved 882 }; 883 uint32_t Value; 884 } DW1; 885 union 886 { 887 //!< DWORD 2 888 struct 889 { 890 uint32_t CurbeTotalDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< CURBE Total Data Length 891 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 892 }; 893 uint32_t Value; 894 } DW2; 895 union 896 { 897 //!< DWORD 3 898 struct 899 { 900 uint32_t CurbeDataStartAddress ; //!< CURBE Data Start Address 901 }; 902 uint32_t Value; 903 } DW3; 904 905 //! \name Local enumerations 906 907 enum SUBOPCODE 908 { 909 SUBOPCODE_MEDIACURBELOADSUBOP = 1, //!< No additional details 910 }; 911 912 enum MEDIA_COMMAND_OPCODE 913 { 914 MEDIA_COMMAND_OPCODE_MEDIACURBELOAD = 0, //!< No additional details 915 }; 916 917 enum PIPELINE 918 { 919 PIPELINE_MEDIA = 2, //!< No additional details 920 }; 921 922 enum COMMAND_TYPE 923 { 924 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 925 }; 926 927 //! \name Initializations 928 929 //! \brief Explicit member initialization function 930 MEDIA_CURBE_LOAD_CMD(); 931 932 static const size_t dwSize = 4; 933 static const size_t byteSize = 16; 934 }; 935 936 //! 937 //! \brief MEDIA_INTERFACE_DESCRIPTOR_LOAD 938 //! \details 939 //! A Media_State_Flush should be used before this command to ensure that 940 //! the temporary Interface Descriptor storage is cleared. 941 //! 942 //! See "GPGPU Command" section for additional 943 //! programming constraints for this command. 944 //! 945 struct MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD 946 { 947 union 948 { 949 //!< DWORD 0 950 struct 951 { 952 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 953 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 954 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 955 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 956 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 957 }; 958 uint32_t Value; 959 } DW0; 960 union 961 { 962 //!< DWORD 1 963 struct 964 { 965 uint32_t Reserved32 ; //!< Reserved 966 }; 967 uint32_t Value; 968 } DW1; 969 union 970 { 971 //!< DWORD 2 972 struct 973 { 974 uint32_t InterfaceDescriptorTotalLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Interface Descriptor Total Length 975 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 976 }; 977 uint32_t Value; 978 } DW2; 979 union 980 { 981 //!< DWORD 3 982 struct 983 { 984 uint32_t InterfaceDescriptorDataStartAddress ; //!< Interface Descriptor Data Start Address 985 }; 986 uint32_t Value; 987 } DW3; 988 989 //! \name Local enumerations 990 991 enum SUBOPCODE 992 { 993 SUBOPCODE_MEDIAINTERFACEDESCRIPTORLOADSUBOP = 2, //!< No additional details 994 }; 995 996 enum MEDIA_COMMAND_OPCODE 997 { 998 MEDIA_COMMAND_OPCODE_MEDIAINTERFACEDESCRIPTORLOAD = 0, //!< No additional details 999 }; 1000 1001 enum PIPELINE 1002 { 1003 PIPELINE_MEDIA = 2, //!< No additional details 1004 }; 1005 1006 enum COMMAND_TYPE 1007 { 1008 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1009 }; 1010 1011 //! \name Initializations 1012 1013 //! \brief Explicit member initialization function 1014 MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD(); 1015 1016 static const size_t dwSize = 4; 1017 static const size_t byteSize = 16; 1018 }; 1019 1020 //! 1021 //! \brief MEDIA_OBJECT_WALKER 1022 //! \details 1023 //! 1024 //! 1025 struct MEDIA_OBJECT_WALKER_CMD 1026 { 1027 union 1028 { 1029 //!< DWORD 0 1030 struct 1031 { 1032 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 1033 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1034 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1035 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1036 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1037 }; 1038 uint32_t Value; 1039 } DW0; 1040 union 1041 { 1042 //!< DWORD 1 1043 struct 1044 { 1045 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1046 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1047 }; 1048 uint32_t Value; 1049 } DW1; 1050 union 1051 { 1052 //!< DWORD 2 1053 struct 1054 { 1055 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1056 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 21) ; //!< Reserved 1057 uint32_t MaskedDispatch : __CODEGEN_BITFIELD(22, 23) ; //!< MASKED_DISPATCH 1058 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 1059 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1060 }; 1061 uint32_t Value; 1062 } DW2; 1063 union 1064 { 1065 //!< DWORD 3 1066 struct 1067 { 1068 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 1069 }; 1070 uint32_t Value; 1071 } DW3; 1072 union 1073 { 1074 //!< DWORD 4 1075 struct 1076 { 1077 uint32_t Reserved128 ; //!< Reserved 1078 }; 1079 uint32_t Value; 1080 } DW4; 1081 union 1082 { 1083 //!< DWORD 5 1084 struct 1085 { 1086 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1087 uint32_t GroupIdLoopSelect : __CODEGEN_BITFIELD( 8, 31) ; //!< GROUP_ID_LOOP_SELECT 1088 }; 1089 uint32_t Value; 1090 } DW5; 1091 union 1092 { 1093 //!< DWORD 6 1094 struct 1095 { 1096 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1097 uint32_t MidLoopUnitX : __CODEGEN_BITFIELD( 8, 9) ; //!< Mid-Loop Unit X 1098 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1099 uint32_t LocalMidLoopUnitY : __CODEGEN_BITFIELD(12, 13) ; //!< Local Mid-Loop Unit Y 1100 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1101 uint32_t MiddleLoopExtraSteps : __CODEGEN_BITFIELD(16, 20) ; //!< Middle Loop Extra Steps 1102 uint32_t Reserved213 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1103 uint32_t ColorCountMinusOne : __CODEGEN_BITFIELD(24, 31) ; //!< Color Count Minus One 1104 }; 1105 uint32_t Value; 1106 } DW6; 1107 union 1108 { 1109 //!< DWORD 7 1110 struct 1111 { 1112 uint32_t LocalLoopExecCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Loop Exec Count 1113 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1114 uint32_t GlobalLoopExecCount : __CODEGEN_BITFIELD(16, 27) ; //!< Global Loop Exec Count 1115 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1116 }; 1117 uint32_t Value; 1118 } DW7; 1119 union 1120 { 1121 //!< DWORD 8 1122 struct 1123 { 1124 uint32_t BlockResolutionX : __CODEGEN_BITFIELD( 0, 10) ; //!< Block Resolution X 1125 uint32_t Reserved267 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1126 uint32_t BlockResolutionY : __CODEGEN_BITFIELD(16, 26) ; //!< Block Resolution Y 1127 uint32_t Reserved283 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1128 }; 1129 uint32_t Value; 1130 } DW8; 1131 union 1132 { 1133 //!< DWORD 9 1134 struct 1135 { 1136 uint32_t LocalStartX : __CODEGEN_BITFIELD( 0, 10) ; //!< Local Start X 1137 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1138 uint32_t LocalStartY : __CODEGEN_BITFIELD(16, 26) ; //!< Local Start Y 1139 uint32_t Reserved315 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1140 }; 1141 uint32_t Value; 1142 } DW9; 1143 union 1144 { 1145 //!< DWORD 10 1146 struct 1147 { 1148 uint32_t Reserved320 ; //!< Reserved 1149 }; 1150 uint32_t Value; 1151 } DW10; 1152 union 1153 { 1154 //!< DWORD 11 1155 struct 1156 { 1157 uint32_t LocalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Outer Loop Stride X 1158 uint32_t Reserved364 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1159 uint32_t LocalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 27) ; //!< Local Outer Loop Stride Y 1160 uint32_t Reserved380 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1161 }; 1162 uint32_t Value; 1163 } DW11; 1164 union 1165 { 1166 //!< DWORD 12 1167 struct 1168 { 1169 uint32_t LocalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Inner Loop Unit X 1170 uint32_t Reserved396 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1171 uint32_t LocalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 27) ; //!< Local Inner Loop Unit Y 1172 uint32_t Reserved412 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1173 }; 1174 uint32_t Value; 1175 } DW12; 1176 union 1177 { 1178 //!< DWORD 13 1179 struct 1180 { 1181 uint32_t GlobalResolutionX : __CODEGEN_BITFIELD( 0, 10) ; //!< Global Resolution X 1182 uint32_t Reserved427 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1183 uint32_t GlobalResolutionY : __CODEGEN_BITFIELD(16, 26) ; //!< Global Resolution Y 1184 uint32_t Reserved443 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1185 }; 1186 uint32_t Value; 1187 } DW13; 1188 union 1189 { 1190 //!< DWORD 14 1191 struct 1192 { 1193 uint32_t GlobalStartX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Start X 1194 uint32_t Reserved460 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1195 uint32_t GlobalStartY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Start Y 1196 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1197 }; 1198 uint32_t Value; 1199 } DW14; 1200 union 1201 { 1202 //!< DWORD 15 1203 struct 1204 { 1205 uint32_t GlobalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Outer Loop Stride X 1206 uint32_t Reserved492 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1207 uint32_t GlobalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Outer Loop Stride Y 1208 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1209 }; 1210 uint32_t Value; 1211 } DW15; 1212 union 1213 { 1214 //!< DWORD 16 1215 struct 1216 { 1217 uint32_t GlobalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Inner Loop Unit X 1218 uint32_t Reserved524 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1219 uint32_t GlobalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Inner Loop Unit Y 1220 uint32_t Reserved540 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1221 }; 1222 uint32_t Value; 1223 } DW16; 1224 1225 //! \name Local enumerations 1226 1227 enum SUBOPCODE 1228 { 1229 SUBOPCODE_MEDIAOBJECTWALKERSUBOP = 3, //!< No additional details 1230 }; 1231 1232 enum MEDIA_COMMAND_OPCODE 1233 { 1234 MEDIA_COMMAND_OPCODE_MEDIAOBJECTWALKER = 1, //!< No additional details 1235 }; 1236 1237 enum PIPELINE 1238 { 1239 PIPELINE_MEDIA = 2, //!< No additional details 1240 }; 1241 1242 enum COMMAND_TYPE 1243 { 1244 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1245 }; 1246 1247 //! \brief MASKED_DISPATCH 1248 //! \details 1249 //! Enable the masking of the dispatch of individual threads based on a 1250 //! bitmask read from CURBE, and specifies the pitch of the CURBE surface. 1251 //! If enabled, CURBE will not be used for thread payload. 1252 enum MASKED_DISPATCH 1253 { 1254 MASKED_DISPATCH_UNNAMED0 = 0, //!< Masked Dispatch Disabled 1255 MASKED_DISPATCH_UNNAMED1 = 1, //!< Masked Dispatch with 128-bit pitch in CURBE 1256 MASKED_DISPATCH_UNNAMED2 = 2, //!< Masked Dispatch with 256-bit pitch in CURBE 1257 MASKED_DISPATCH_UNNAMED3 = 3, //!< Masked Dispatch with 512-bit pitch in CURBE 1258 }; 1259 1260 //! \brief THREAD_SYNCHRONIZATION 1261 //! \details 1262 //! This field when set indicates that the dispatch of the thread originated 1263 //! from this command is based on the "spawn root thread" message. 1264 enum THREAD_SYNCHRONIZATION 1265 { 1266 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 1267 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 1268 }; 1269 1270 //! \brief GROUP_ID_LOOP_SELECT 1271 //! \details 1272 //! This bit field chooses which of the nested loops of the walker are used 1273 //! to identify threads which share a group id and therefore a shared 1274 //! barrier and SLM. The programmer must ensure that each group will fit 1275 //! into a single subslice. When barriers are enabled every group must have 1276 //! the same number of threads matching the number specified in the 1277 //! Interface Descriptor. 1278 enum GROUP_ID_LOOP_SELECT 1279 { 1280 GROUP_ID_LOOP_SELECT_NOGROUPS = 0, //!< Groups are not created, barriers and SLM are not allocated 1281 GROUP_ID_LOOP_SELECT_COLORGROUPS = 1, //!< Each complete iteration of the Color loop defines a group, the group id is the concatenation of the Outer global, Inner global, Outer local, Mid local and Inner local loop execution counts. 1282 GROUP_ID_LOOP_SELECT_INNERLOCALGROUPS = 2, //!< Each complete iteration of the Inner local loop and Color loop defines a group, the group id is the concatenation of the Outer global loop to the Mid local loop execution counts. 1283 GROUP_ID_LOOP_SELECT_MIDLOCALGROUPS = 3, //!< Each complete iteration of the Mid local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop to the Outer local loop execution counts. 1284 GROUP_ID_LOOP_SELECT_OUTERLOCALGROUPS = 4, //!< Each complete iteration of the Outer local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop and the Inner global loop execution counts. 1285 GROUP_ID_LOOP_SELECT_INNERGLOBALGROUPS = 5, //!< Each complete iteration of the Inner global loop and lower loops defines a group, the group id is the Outer global loop execution count. 1286 }; 1287 1288 //! \name Initializations 1289 1290 //! \brief Explicit member initialization function 1291 MEDIA_OBJECT_WALKER_CMD(); 1292 1293 static const size_t dwSize = 17; 1294 static const size_t byteSize = 68; 1295 }; 1296 1297 //! 1298 //! \brief GPGPU_WALKER 1299 //! \details 1300 //! If the threads spawned by this command are required to observe memory 1301 //! writes performed by threads spawned from a previous command, software 1302 //! must precede this command with a command that performs a memory flush 1303 //! (e.g., MI_FLUSH). 1304 //! 1305 struct GPGPU_WALKER_CMD 1306 { 1307 union 1308 { 1309 //!< DWORD 0 1310 struct 1311 { 1312 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1313 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Predicate Enable 1314 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1315 uint32_t IndirectParameterEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Indirect Parameter Enable 1316 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1317 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1318 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1319 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1320 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1321 }; 1322 uint32_t Value; 1323 } DW0; 1324 union 1325 { 1326 //!< DWORD 1 1327 struct 1328 { 1329 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1330 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1331 }; 1332 uint32_t Value; 1333 } DW1; 1334 union 1335 { 1336 //!< DWORD 2 1337 struct 1338 { 1339 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1340 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1341 }; 1342 uint32_t Value; 1343 } DW2; 1344 union 1345 { 1346 //!< DWORD 3 1347 struct 1348 { 1349 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1350 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Indirect Data Start Address 1351 }; 1352 uint32_t Value; 1353 } DW3; 1354 union 1355 { 1356 //!< DWORD 4 1357 struct 1358 { 1359 uint32_t ThreadWidthCounterMaximum : __CODEGEN_BITFIELD( 0, 5) ; //!< Thread Width Counter Maximum 1360 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1361 uint32_t ThreadHeightCounterMaximum : __CODEGEN_BITFIELD( 8, 13) ; //!< Thread Height Counter Maximum 1362 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1363 uint32_t ThreadDepthCounterMaximum : __CODEGEN_BITFIELD(16, 21) ; //!< Thread Depth Counter Maximum 1364 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 29) ; //!< Reserved 1365 uint32_t SimdSize : __CODEGEN_BITFIELD(30, 31) ; //!< SIMD_SIZE 1366 }; 1367 uint32_t Value; 1368 } DW4; 1369 union 1370 { 1371 //!< DWORD 5 1372 struct 1373 { 1374 uint32_t ThreadGroupIdStartingX ; //!< Thread Group ID Starting X 1375 }; 1376 uint32_t Value; 1377 } DW5; 1378 union 1379 { 1380 //!< DWORD 6 1381 struct 1382 { 1383 uint32_t Reserved192 ; //!< Reserved 1384 }; 1385 uint32_t Value; 1386 } DW6; 1387 union 1388 { 1389 //!< DWORD 7 1390 struct 1391 { 1392 uint32_t ThreadGroupIdXDimension ; //!< Thread Group ID X Dimension 1393 }; 1394 uint32_t Value; 1395 } DW7; 1396 union 1397 { 1398 //!< DWORD 8 1399 struct 1400 { 1401 uint32_t ThreadGroupIdStartingY ; //!< Thread Group ID Starting Y 1402 }; 1403 uint32_t Value; 1404 } DW8; 1405 union 1406 { 1407 //!< DWORD 9 1408 struct 1409 { 1410 uint32_t Reserved288 ; //!< Reserved 1411 }; 1412 uint32_t Value; 1413 } DW9; 1414 union 1415 { 1416 //!< DWORD 10 1417 struct 1418 { 1419 uint32_t ThreadGroupIdYDimension ; //!< Thread Group ID Y Dimension 1420 }; 1421 uint32_t Value; 1422 } DW10; 1423 union 1424 { 1425 //!< DWORD 11 1426 struct 1427 { 1428 uint32_t ThreadGroupIdStartingResumeZ ; //!< Thread Group ID Starting/Resume Z 1429 }; 1430 uint32_t Value; 1431 } DW11; 1432 union 1433 { 1434 //!< DWORD 12 1435 struct 1436 { 1437 uint32_t ThreadGroupIdZDimension ; //!< Thread Group ID Z Dimension 1438 }; 1439 uint32_t Value; 1440 } DW12; 1441 union 1442 { 1443 //!< DWORD 13 1444 struct 1445 { 1446 uint32_t RightExecutionMask ; //!< Right Execution Mask 1447 }; 1448 uint32_t Value; 1449 } DW13; 1450 union 1451 { 1452 //!< DWORD 14 1453 struct 1454 { 1455 uint32_t BottomExecutionMask ; //!< Bottom Execution Mask 1456 }; 1457 uint32_t Value; 1458 } DW14; 1459 1460 //! \name Local enumerations 1461 1462 enum SUBOPCODE 1463 { 1464 SUBOPCODE_GPGPUWALKERSUBOP = 5, //!< No additional details 1465 }; 1466 1467 enum MEDIA_COMMAND_OPCODE 1468 { 1469 MEDIA_COMMAND_OPCODE_GPGPUWALKER = 1, //!< No additional details 1470 }; 1471 1472 enum PIPELINE 1473 { 1474 PIPELINE_MEDIA = 2, //!< No additional details 1475 }; 1476 1477 enum COMMAND_TYPE 1478 { 1479 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1480 }; 1481 1482 //! \brief SIMD_SIZE 1483 //! \details 1484 //! This field determines the size of the payload and the number of bits of 1485 //! the execution mask that are expected. The kernel pointed to by the 1486 //! interface descriptor should match the SIMD declared here. 1487 enum SIMD_SIZE 1488 { 1489 SIMD_SIZE_SIMD8 = 0, //!< 8 LSBs of the execution mask are used 1490 SIMD_SIZE_SIMD16 = 1, //!< 16 LSBs used in execution mask 1491 SIMD_SIZE_SIMD32 = 2, //!< 32 bits of execution mask used 1492 }; 1493 1494 //! \name Initializations 1495 1496 //! \brief Explicit member initialization function 1497 GPGPU_WALKER_CMD(); 1498 1499 static const size_t dwSize = 15; 1500 static const size_t byteSize = 60; 1501 }; 1502 1503 //! 1504 //! \brief _3DSTATE_CHROMA_KEY 1505 //! \details 1506 //! The 3DSTATE_CHROMA_KEY instruction is used to program texture 1507 //! color/chroma-key key values. A table containing four set of values is 1508 //! supported. The ChromaKey Index sampler state variable is used to select 1509 //! which table entry is associated with the map. Texture chromakey 1510 //! functions are enabled and controlled via use of the ChromaKey Enable 1511 //! texture sampler state variable.Texture Color Key (keying on a paletted 1512 //! texture index) is not supported. 1513 //! 1514 struct _3DSTATE_CHROMA_KEY_CMD 1515 { 1516 union 1517 { 1518 //!< DWORD 0 1519 struct 1520 { 1521 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1522 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1523 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1524 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1525 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1526 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1527 }; 1528 uint32_t Value; 1529 } DW0; 1530 union 1531 { 1532 //!< DWORD 1 1533 struct 1534 { 1535 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 1536 uint32_t ChromakeyTableIndex : __CODEGEN_BITFIELD(30, 31) ; //!< ChromaKey Table Index 1537 }; 1538 uint32_t Value; 1539 } DW1; 1540 union 1541 { 1542 //!< DWORD 2 1543 struct 1544 { 1545 uint32_t ChromakeyLowValue ; //!< ChromaKey Low Value 1546 }; 1547 uint32_t Value; 1548 } DW2; 1549 union 1550 { 1551 //!< DWORD 3 1552 struct 1553 { 1554 uint32_t ChromakeyHighValue ; //!< ChromaKey High Value 1555 }; 1556 uint32_t Value; 1557 } DW3; 1558 1559 //! \name Local enumerations 1560 1561 enum _3D_COMMAND_SUB_OPCODE 1562 { 1563 _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY = 4, //!< No additional details 1564 }; 1565 1566 enum _3D_COMMAND_OPCODE 1567 { 1568 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1569 }; 1570 1571 enum COMMAND_SUBTYPE 1572 { 1573 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1574 }; 1575 1576 enum COMMAND_TYPE 1577 { 1578 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1579 }; 1580 1581 //! \name Initializations 1582 1583 //! \brief Explicit member initialization function 1584 _3DSTATE_CHROMA_KEY_CMD(); 1585 1586 static const size_t dwSize = 4; 1587 static const size_t byteSize = 16; 1588 }; 1589 1590 //! 1591 //! \brief PALETTE_ENTRY 1592 //! \details 1593 //! 1594 //! 1595 struct PALETTE_ENTRY_CMD 1596 { 1597 union 1598 { 1599 //!< DWORD 0 1600 struct 1601 { 1602 uint32_t Blue : __CODEGEN_BITFIELD( 0, 7) ; //!< Blue 1603 uint32_t Green : __CODEGEN_BITFIELD( 8, 15) ; //!< Green 1604 uint32_t Red : __CODEGEN_BITFIELD(16, 23) ; //!< Red 1605 uint32_t Alpha : __CODEGEN_BITFIELD(24, 31) ; //!< Alpha 1606 }; 1607 uint32_t Value; 1608 } DW0; 1609 1610 //! \name Local enumerations 1611 1612 //! \name Initializations 1613 1614 //! \brief Explicit member initialization function 1615 PALETTE_ENTRY_CMD(); 1616 1617 static const size_t dwSize = 1; 1618 static const size_t byteSize = 4; 1619 }; 1620 1621 //! 1622 //! \brief STATE_SIP 1623 //! \details 1624 //! The STATE_SIP command specifies the starting instruction location of the 1625 //! System Routine that is shared by all threads in execution. 1626 //! 1627 struct STATE_SIP_CMD 1628 { 1629 union 1630 { 1631 //!< DWORD 0 1632 struct 1633 { 1634 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1635 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1636 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1637 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1638 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1639 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1640 }; 1641 uint32_t Value; 1642 } DW0; 1643 union 1644 { 1645 //!< DWORD 1..2 1646 struct 1647 { 1648 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 1649 uint64_t SystemInstructionPointer : __CODEGEN_BITFIELD( 4, 63) ; //!< System Instruction Pointer 1650 }; 1651 uint32_t Value[2]; 1652 } DW1_2; 1653 1654 //! \name Local enumerations 1655 1656 enum _3D_COMMAND_SUB_OPCODE 1657 { 1658 _3D_COMMAND_SUB_OPCODE_STATESIP = 2, //!< No additional details 1659 }; 1660 1661 enum _3D_COMMAND_OPCODE 1662 { 1663 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1664 }; 1665 1666 enum COMMAND_SUBTYPE 1667 { 1668 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1669 }; 1670 1671 enum COMMAND_TYPE 1672 { 1673 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1674 }; 1675 1676 //! \name Initializations 1677 1678 //! \brief Explicit member initialization function 1679 STATE_SIP_CMD(); 1680 1681 static const size_t dwSize = 3; 1682 static const size_t byteSize = 12; 1683 }; 1684 1685 //! 1686 //! \brief GPGPU_CSR_BASE_ADDRESS 1687 //! \details 1688 //! The GPGPU_CSR_BASE_ADDRESS command sets the base pointers for EU and L3 1689 //! to Context Save and Restore EU State and SLM for GPGPU mid-thread 1690 //! preemption. 1691 //! 1692 //! Execution of this command causes a full pipeline flush, thus its use 1693 //! should be minimized for higher performance. State and instruction caches 1694 //! are flushed on completion of the flush. 1695 //! 1696 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 1697 //! Cache Flush Enable" set prior to programming GPGPU_CSR_BASE_ADDRESS 1698 //! command for GPGPU workloads i.e when pipeline select is GPGPU via 1699 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 1700 //! preemption latencies for certain programming sequences. If programming 1701 //! PIPE_CONTROL has performance implications then preemption latencies can 1702 //! be trade off against performance by not implementing this programming 1703 //! note. 1704 //! 1705 struct GPGPU_CSR_BASE_ADDRESS_CMD 1706 { 1707 union 1708 { 1709 //!< DWORD 0 1710 struct 1711 { 1712 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1713 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1714 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1715 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1716 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1717 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1718 }; 1719 uint32_t Value; 1720 } DW0; 1721 union 1722 { 1723 //!< DWORD 1..2 1724 struct 1725 { 1726 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1727 uint64_t GpgpuCsrBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< GPGPU CSR Base Address 1728 }; 1729 uint32_t Value[2]; 1730 } DW1_2; 1731 1732 //! \name Local enumerations 1733 1734 enum _3D_COMMAND_SUB_OPCODE 1735 { 1736 _3D_COMMAND_SUB_OPCODE_GPGPUCSRBASEADDRESS = 4, //!< No additional details 1737 }; 1738 1739 enum _3D_COMMAND_OPCODE 1740 { 1741 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1742 }; 1743 1744 enum COMMAND_SUBTYPE 1745 { 1746 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1747 }; 1748 1749 enum COMMAND_TYPE 1750 { 1751 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1752 }; 1753 1754 //! \name Initializations 1755 1756 //! \brief Explicit member initialization function 1757 GPGPU_CSR_BASE_ADDRESS_CMD(); 1758 1759 static const size_t dwSize = 3; 1760 static const size_t byteSize = 12; 1761 }; 1762 }; 1763 1764 #pragma pack() 1765 1766 #endif // __MHW_RENDER_HWCMD_G12_X_H__ 1767