1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_hwcmd_g9_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g9_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_RENDER_HWCMD_G9_X_H__ 29 #define __MHW_RENDER_HWCMD_G9_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_render_g9_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MEDIA_OBJECT 50 //! \details 51 //! 52 //! 53 struct MEDIA_OBJECT_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 61 uint32_t MediaCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< MEDIA_COMMAND_SUB_OPCODE 62 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 63 uint32_t MediaCommandPipeline : __CODEGEN_BITFIELD(27, 28) ; //!< MEDIA_COMMAND_PIPELINE 64 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 65 }; 66 uint32_t Value; 67 } DW0; 68 union 69 { 70 //!< DWORD 1 71 struct 72 { 73 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 74 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 75 }; 76 uint32_t Value; 77 } DW1; 78 union 79 { 80 //!< DWORD 2 81 struct 82 { 83 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 84 uint32_t SubsliceDestinationSelect : __CODEGEN_BITFIELD(17, 18) ; //!< SUBSLICE_DESTINATION_SELECT 85 uint32_t SliceDestinationSelect : __CODEGEN_BITFIELD(19, 20) ; //!< SLICE_DESTINATION_SELECT 86 uint32_t UseScoreboard : __CODEGEN_BITFIELD(21, 21) ; //!< USE_SCOREBOARD 87 uint32_t ForceDestination : __CODEGEN_BITFIELD(22, 22) ; //!< Force Destination 88 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 89 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 90 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 30) ; //!< Reserved 91 uint32_t ChildrenPresent : __CODEGEN_BITFIELD(31, 31) ; //!< Children Present 92 }; 93 uint32_t Value; 94 } DW2; 95 union 96 { 97 //!< DWORD 3 98 struct 99 { 100 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 101 }; 102 uint32_t Value; 103 } DW3; 104 union 105 { 106 //!< DWORD 4 107 struct 108 { 109 uint32_t ScoreboardX : __CODEGEN_BITFIELD( 0, 8) ; //!< Scoreboard X 110 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 111 uint32_t ScoredboardY : __CODEGEN_BITFIELD(16, 24) ; //!< Scoredboard Y 112 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 113 }; 114 uint32_t Value; 115 } DW4; 116 union 117 { 118 //!< DWORD 5 119 struct 120 { 121 uint32_t ScoreboardMask : __CODEGEN_BITFIELD( 0, 7) ; //!< Scoreboard Mask 122 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 123 uint32_t ScoreboardColor : __CODEGEN_BITFIELD(16, 19) ; //!< Scoreboard Color 124 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 125 }; 126 uint32_t Value; 127 } DW5; 128 129 //! \name Local enumerations 130 131 enum MEDIA_COMMAND_SUB_OPCODE 132 { 133 MEDIA_COMMAND_SUB_OPCODE_MEDIAOBJECTSUBOP = 0, //!< No additional details 134 }; 135 136 enum MEDIA_COMMAND_OPCODE 137 { 138 MEDIA_COMMAND_OPCODE_MEDIAOBJECT = 1, //!< No additional details 139 }; 140 141 enum MEDIA_COMMAND_PIPELINE 142 { 143 MEDIA_COMMAND_PIPELINE_MEDIA = 2, //!< No additional details 144 }; 145 146 enum COMMAND_TYPE 147 { 148 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 149 }; 150 151 //! \brief SUBSLICE_DESTINATION_SELECT 152 //! \details 153 //! This field selects the SubSlice that this thread must be sent to. 154 //! Ignored if <b>Force Destination</b> = 0 155 enum SUBSLICE_DESTINATION_SELECT 156 { 157 SUBSLICE_DESTINATION_SELECT_SUBSLICE0 = 0, //!< No additional details 158 SUBSLICE_DESTINATION_SELECT_SUBSLICE1 = 1, //!< No additional details 159 SUBSLICE_DESTINATION_SELECT_SUBSLICE2 = 2, //!< No additional details 160 SUBSLICE_DESTINATION_SELECT_SUBSLICE3 = 3, //!< No additional details 161 }; 162 163 //! \brief SLICE_DESTINATION_SELECT 164 //! \details 165 //! This bit along with the subslice destination select determines the slice 166 //! that this thread must be sent to. Ignored if <b>Force Destination</b> = 167 //! 0, or if product only has 1 slice. 168 enum SLICE_DESTINATION_SELECT 169 { 170 SLICE_DESTINATION_SELECT_SLICE0 = 0, //!< No additional details 171 SLICE_DESTINATION_SELECT_SLICE1 = 1, //!< Cannot be used in products without a Slice 1. 172 SLICE_DESTINATION_SELECT_SLICE2 = 2, //!< Cannot be used in products without a Slice 2. 173 }; 174 175 //! \brief USE_SCOREBOARD 176 //! \details 177 //! This field specifies whether the thread associated with this command 178 //! uses hardware scoreboard. Only when this field is set, the scoreboard 179 //! control fields in the VFE Dword are valid. If this field is cleared, the 180 //! thread associated with this command bypasses hardware scoreboard. 181 enum USE_SCOREBOARD 182 { 183 USE_SCOREBOARD_NOTUSINGSCOREBOARD = 0, //!< No additional details 184 USE_SCOREBOARD_USINGSCOREBOARD = 1, //!< No additional details 185 }; 186 187 //! \brief THREAD_SYNCHRONIZATION 188 //! \details 189 //! This field when set indicates that the dispatch of the thread originated 190 //! from this command is based on the "spawn root thread" message. 191 enum THREAD_SYNCHRONIZATION 192 { 193 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 194 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 195 }; 196 197 //! \name Initializations 198 199 //! \brief Explicit member initialization function 200 MEDIA_OBJECT_CMD(); 201 202 static const size_t dwSize = 6; 203 static const size_t byteSize = 24; 204 }; 205 206 //! 207 //! \brief PIPELINE_SELECT 208 //! \details 209 //! The PIPELINE_SELECT command is used to specify which GPE pipeline is to 210 //! be considered the 'current' active pipeline. Issuing 211 //! 3D-pipeline-specific commands when the Media pipeline is selected, or 212 //! vice versa, is UNDEFINED. 213 //! 214 //! Issuing 3D-pipeline-specific commands when the GPGPU pipeline is 215 //! selected, or vice versa, is UNDEFINED. 216 //! 217 //! Programming common non pipeline commands (e.g., STATE_BASE_ADDRESS) is 218 //! allowed in all pipeline modes. 219 //! 220 //! Software must ensure all the write caches are flushed through a stalling 221 //! PIPE_CONTROL command followed by another PIPE_CONTROL command to 222 //! invalidate read only caches prior to programming MI_PIPELINE_SELECT 223 //! command to change the Pipeline Select Mode. Example: ... Workload-3Dmode 224 //! PIPE_CONTROL (CS Stall, Depth Cache Flush Enable, Render Target Cache 225 //! Flush Enable, DC Flush Enable) PIPE_CONTROL (Constant Cache Invalidate, 226 //! Texture Cache Invalidate, Instruction Cache Invalidate, State Cache 227 //! invalidate) PIPELINE_SELECT ( GPGPU) 228 //! 229 //! Software must clear the COLOR_CALC_STATE Valid field in 230 //! 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT with 231 //! Pipeline Select set to GPGPU. 232 //! 233 //! Render CS Only: SW must always program PIPE_CONTROL with CS Stall and 234 //! Render Target Cache Flush Enable set prior to programming 235 //! PIPELINE_SELECT command for GPGPU workloads i.e when pipeline mode is 236 //! set to GPGPU. This is required to achieve better GPGPU preemption 237 //! latencies for certain programming sequences. If programming PIPE_CONTROL 238 //! has performance implications then preemption latencies can be trade off 239 //! against performance by not implementing this programming note. 240 //! 241 //! Hardware Binding Tables are only supported for 3D workloads. Resource 242 //! streamer must be enabled only for 3D workloads. Resource streamer must 243 //! be disabled for Media and GPGPU workloads. Batch buffer containing both 244 //! 3D and GPGPU workloads must take care of disabling and enabling Resource 245 //! Streamer appropriately while changing the PIPELINE_SELECT mode from 3D 246 //! to GPGPU and vice versa. Resource streamer must be disabled using 247 //! MI_RS_CONTROL command and Hardware Binding Tables must be disabled by 248 //! programming 3DSTATE_BINDING_TABLE_POOL_ALLOC with "Binding Table Pool 249 //! Enable" set to disable (i.e. value '0'). Example below shows disabling 250 //! and enabling of resource streamer in a batch buffer for 3D and GPGPU 251 //! workloads. MI_BATCH_BUFFER_START (Resource Streamer Enabled) 252 //! PIPELINE_SELECT (3D) 3DSTATE_BINDING_TABLE_POOL_ALLOC (Binding Table 253 //! Pool Enabled) 3D WORKLOAD MI_RS_CONTROL (Disable Resource Streamer) 254 //! 3DSTATE_BINDING_TABLE_POOL_ALLOC (Binding Table Pool Disabled) 255 //! PIPELINE_SELECT (GPGPU) GPGPU Workload 3DSTATE_BINDING_TABLE_POOL_ALLOC 256 //! (Binding Table Pool Enabled) MI_RS_CONTROL (Enable Resource Streamer) 3D 257 //! WORKLOAD MI_BATCH_BUFFER_END 258 //! 259 struct PIPELINE_SELECT_CMD 260 { 261 union 262 { 263 //!< DWORD 0 264 struct 265 { 266 uint32_t PipelineSelection : __CODEGEN_BITFIELD( 0, 1) ; //!< PIPELINE_SELECTION 267 uint32_t RenderSliceCommonPowerGateEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< RENDER_SLICE_COMMON_POWER_GATE_ENABLE 268 uint32_t RenderSamplerPowerGateEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< RENDER_SAMPLER_POWER_GATE_ENABLE 269 uint32_t MediaSamplerDopClockGateEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 270 uint32_t ForceMediaAwake : __CODEGEN_BITFIELD( 5, 5) ; //!< FORCE_MEDIA_AWAKE 271 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 272 uint32_t MaskBits : __CODEGEN_BITFIELD( 8, 15) ; //!< Mask Bits 273 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 274 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 275 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 276 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 277 }; 278 uint32_t Value; 279 } DW0; 280 281 //! \name Local enumerations 282 283 //! \brief PIPELINE_SELECTION 284 //! \details 285 //! Mask bits [9:8] has to be set for HW to look at this field when 286 //! PIPELINE_SELECT command is parsed. Setting only one of the mask bit [9] 287 //! or [8] is illegal. 288 enum PIPELINE_SELECTION 289 { 290 PIPELINE_SELECTION_3D = 0, //!< 3D pipeline is selected 291 PIPELINE_SELECTION_MEDIA = 1, //!< Media pipeline is selected (Includes HD optical disc playback, HD video playback, and generic media workloads) 292 PIPELINE_SELECTION_GPGPU = 2, //!< GPGPU pipeline is selected 293 }; 294 295 //! \brief RENDER_SLICE_COMMON_POWER_GATE_ENABLE 296 //! \details 297 //! Mask bit [10] has to be set for HW to look at this field when 298 //! PIPELINE_SELECT command is parsed. 299 enum RENDER_SLICE_COMMON_POWER_GATE_ENABLE 300 { 301 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render slice common Power Gating. 302 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render slice common Power Gating. 303 }; 304 305 //! \brief RENDER_SAMPLER_POWER_GATE_ENABLE 306 //! \details 307 //! Mask bit [11] has to be set for HW to look at this field when 308 //! PIPELINE_SELECT command is parsed. 309 enum RENDER_SAMPLER_POWER_GATE_ENABLE 310 { 311 RENDER_SAMPLER_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render sampler Power Gating. 312 RENDER_SAMPLER_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render sampler Power Gating. 313 }; 314 315 //! \brief MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 316 //! \details 317 //! Mask bit [12] has to be set for HW to look at this field when 318 //! PIPELINE_SELECT command is parsed. 319 enum MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 320 { 321 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable sampler DOP Clock Gating. 322 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable media sampler DOP Clock Gating. 323 }; 324 325 //! \brief FORCE_MEDIA_AWAKE 326 //! \details 327 //! Mask bit [13] has to be set for HW to look at this field when 328 //! PIPELINE_SELECT command is parsed. 329 //! 330 //! Example for usage model: 331 //! 332 //! <b>RCS Ring Buffer</b>: 333 //! <b>PIPELINE_SELECT (Force Media Awake set to '1')</b> 334 //! MI_SEMPAHORE_SINGAL (Signal context id 0xABC to Render Command 335 //! Streamer) 336 //! <b>PIPELINE_SELECT (Force Media Awake set to '0')</b> 337 //! <b>MI_BATCH_BUFFER_START</b> 338 //! STATE Commands .. 339 //! ………… 340 //! <b>PIPELINE_SELECT (Force Media Awake set to '1')</b> 341 //! MI_LOAD_REGISTER_IMM (Load register 0x23XX in render command 342 //! streamer with data 0xFFF) 343 //! <b>PIPELINE_SELECT (Force Media Awake set to '0')</b> 344 //! ………… 345 //! <b>MI_BATCH_BUFFER_END</b> 346 enum FORCE_MEDIA_AWAKE 347 { 348 FORCE_MEDIA_AWAKE_DISABLED = 0, //!< Command streamer sends message to PM to disable force awake of media engine (next instructions do not require the media engine to be awake). Command streamer waits for acknowledge from PM before parsing the next command. 349 FORCE_MEDIA_AWAKE_ENABLED = 1, //!< Command streamer sends message to PM to force awake media engine (next instructions require media engine awake). Command streamer waits for acknowledge from PM before parsing the next command. 350 }; 351 352 enum _3D_COMMAND_SUB_OPCODE 353 { 354 _3D_COMMAND_SUB_OPCODE_PIPELINESELECT = 4, //!< No additional details 355 }; 356 357 enum _3D_COMMAND_OPCODE 358 { 359 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 360 }; 361 362 enum COMMAND_SUBTYPE 363 { 364 COMMAND_SUBTYPE_GFXPIPESINGLEDW = 1, //!< No additional details 365 }; 366 367 enum COMMAND_TYPE 368 { 369 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 370 }; 371 372 //! \name Initializations 373 374 //! \brief Explicit member initialization function 375 PIPELINE_SELECT_CMD(); 376 377 static const size_t dwSize = 1; 378 static const size_t byteSize = 4; 379 }; 380 381 //! 382 //! \brief STATE_BASE_ADDRESS 383 //! \details 384 //! The STATE_BASE_ADDRESS command sets the base pointers for subsequent 385 //! state, instruction, and media indirect object accesses by the GPE. 386 //! For more information see the Base Address Utilization table in the 387 //! Memory Access Indirection narrative topic. 388 //! 389 //! The following commands must be reissued following any change to the base 390 //! addresses: 3DSTATE_CC_POINTERS 391 //! 3DSTATE_BINDING_TABLE_POINTERS 392 //! 3DSTATE_SAMPLER_STATE_POINTERS 393 //! 3DSTATE_VIEWPORT_STATE_POINTERS 394 //! MEDIA_STATE_POINTERS 395 //! Execution of this command causes a full pipeline flush, thus its use 396 //! should be minimized for higher performance. 397 //! 398 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 399 //! Cache Flush Enable" set before programming STATE_BASE_ADDRESS command 400 //! for GPGPU workloads i.e when pipeline select is GPGPU via 401 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 402 //! preemption latencies in certain workload programming sequences. If 403 //! programming PIPE_CONTROL has performance implications then preemption 404 //! latencies can be traded off against performance by not implementing this 405 //! programming note. 406 //! 407 struct STATE_BASE_ADDRESS_CMD 408 { 409 union 410 { 411 //!< DWORD 0 412 struct 413 { 414 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 415 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 416 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 417 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 418 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 419 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 420 }; 421 uint32_t Value; 422 } DW0; 423 union 424 { 425 //!< DWORD 1..2 426 struct 427 { 428 uint64_t GeneralStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 429 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 430 uint64_t GeneralStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< General State Memory Object Control State 431 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 432 uint64_t GeneralStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< General State Base Address 433 }; 434 uint32_t Value[2]; 435 } DW1_2; 436 union 437 { 438 //!< DWORD 3 439 struct 440 { 441 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 442 uint32_t StatelessDataPortAccessMemoryObjectControlState : __CODEGEN_BITFIELD(16, 22) ; //!< Stateless Data Port Access Memory Object Control State 443 uint32_t Reserved119 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 444 }; 445 uint32_t Value; 446 } DW3; 447 union 448 { 449 //!< DWORD 4..5 450 struct 451 { 452 uint64_t SurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 453 uint64_t Reserved129 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 454 uint64_t SurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Surface State Memory Object Control State 455 uint64_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 456 uint64_t SurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Surface State Base Address 457 }; 458 uint32_t Value[2]; 459 } DW4_5; 460 union 461 { 462 //!< DWORD 6..7 463 struct 464 { 465 uint64_t DynamicStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 466 uint64_t Reserved193 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 467 uint64_t DynamicStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Dynamic State Memory Object Control State 468 uint64_t Reserved203 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 469 uint64_t DynamicStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Dynamic State Base Address 470 }; 471 uint32_t Value[2]; 472 } DW6_7; 473 union 474 { 475 //!< DWORD 8..9 476 struct 477 { 478 uint64_t IndirectObjectBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 479 uint64_t Reserved257 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 480 uint64_t IndirectObjectMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Indirect Object Memory Object Control State 481 uint64_t Reserved267 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 482 uint64_t IndirectObjectBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Indirect Object Base Address 483 }; 484 uint32_t Value[2]; 485 } DW8_9; 486 union 487 { 488 //!< DWORD 10..11 489 struct 490 { 491 uint64_t InstructionBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 492 uint64_t Reserved321 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 493 uint64_t InstructionMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Instruction Memory Object Control State 494 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 495 uint64_t InstructionBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Instruction Base Address 496 }; 497 uint32_t Value[2]; 498 } DW10_11; 499 union 500 { 501 //!< DWORD 12 502 struct 503 { 504 uint32_t GeneralStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 505 uint32_t Reserved385 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 506 uint32_t GeneralStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< General State Buffer Size 507 }; 508 uint32_t Value; 509 } DW12; 510 union 511 { 512 //!< DWORD 13 513 struct 514 { 515 uint32_t DynamicStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 516 uint32_t Reserved417 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 517 uint32_t DynamicStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Dynamic State Buffer Size 518 }; 519 uint32_t Value; 520 } DW13; 521 union 522 { 523 //!< DWORD 14 524 struct 525 { 526 uint32_t IndirectObjectBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 527 uint32_t Reserved449 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 528 uint32_t IndirectObjectBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Indirect Object Buffer Size 529 }; 530 uint32_t Value; 531 } DW14; 532 union 533 { 534 //!< DWORD 15 535 struct 536 { 537 uint32_t InstructionBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 538 uint32_t Reserved481 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 539 uint32_t InstructionBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Instruction Buffer Size 540 }; 541 uint32_t Value; 542 } DW15; 543 union 544 { 545 //!< DWORD 16..17 546 struct 547 { 548 uint64_t BindlessSurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 549 uint64_t Reserved513 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 550 uint64_t BindlessSurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Surface State Memory Object Control State 551 uint64_t Reserved523 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 552 uint64_t BindlessSurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Surface State Base Address 553 }; 554 uint32_t Value[2]; 555 } DW16_17; 556 union 557 { 558 //!< DWORD 18 559 struct 560 { 561 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 562 uint32_t BindlessSurfaceStateSize : __CODEGEN_BITFIELD(12, 31) ; //!< Bindless Surface State Size 563 }; 564 uint32_t Value; 565 } DW18; 566 567 //! \name Local enumerations 568 569 enum _3D_COMMAND_SUB_OPCODE 570 { 571 _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS = 1, //!< No additional details 572 }; 573 574 enum _3D_COMMAND_OPCODE 575 { 576 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 577 }; 578 579 enum COMMAND_SUBTYPE 580 { 581 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 582 }; 583 584 enum COMMAND_TYPE 585 { 586 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 587 }; 588 589 //! \brief GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 590 //! \details 591 //! <p>The other fields in this DWord and the following DWord are updated 592 //! only when this bit is set.</p> 593 enum GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 594 { 595 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 596 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 597 }; 598 599 //! \brief SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 600 //! \details 601 //! The other fields in this DWord and the following DWord are updated only 602 //! when this bit is set. 603 enum SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 604 { 605 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 606 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 607 }; 608 609 //! \brief DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 610 //! \details 611 //! The other fields in this DWord and the following DWord are updated only 612 //! when this bit is set. 613 enum DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 614 { 615 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 616 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 617 }; 618 619 //! \brief INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 620 //! \details 621 //! <p>The other fields in this DWord and the following DWord are updated 622 //! only when this bit is set.</p> 623 enum INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 624 { 625 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 626 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 627 }; 628 629 //! \brief INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 630 //! \details 631 //! <p>The other fields in this DWord and the following DWord are updated 632 //! only when this bit is set.</p> 633 enum INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 634 { 635 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 636 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 637 }; 638 639 //! \brief GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 640 //! \details 641 //! The bound in this DWord is updated only when this bit is set. 642 enum GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 643 { 644 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 645 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 646 }; 647 648 //! \brief DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 649 //! \details 650 //! FormatDesc 651 enum DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 652 { 653 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 654 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 655 }; 656 657 //! \brief INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 658 //! \details 659 //! FormatDesc 660 enum INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 661 { 662 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 663 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 664 }; 665 666 //! \brief INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 667 //! \details 668 //! FormatDesc 669 enum INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 670 { 671 INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 672 }; 673 674 //! \brief BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 675 //! \details 676 //! <p>The other fields in this DWord are updated only when this bit is 677 //! set.</p> 678 enum BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 679 { 680 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 681 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 682 }; 683 684 //! \name Initializations 685 686 //! \brief Explicit member initialization function 687 STATE_BASE_ADDRESS_CMD(); 688 689 static const size_t dwSize = 19; 690 static const size_t byteSize = 76; 691 }; 692 693 //! 694 //! \brief MEDIA_VFE_STATE 695 //! \details 696 //! A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless the 697 //! only bits that are changed are scoreboard related: Scoreboard Enable, 698 //! Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For these 699 //! scoreboard related states, a MEDIA_STATE_FLUSH is sufficient. 700 //! 701 //! MEDIA_STATE_FLUSH (optional, only if barrier dependency is needed) 702 //! 703 //! MEDIA_INTERFACE_DESCRIPTOR_LOAD (optional) 704 //! 705 //! 706 //! 707 struct MEDIA_VFE_STATE_CMD 708 { 709 union 710 { 711 //!< DWORD 0 712 struct 713 { 714 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 715 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 716 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 717 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 718 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 719 }; 720 uint32_t Value; 721 } DW0; 722 union 723 { 724 //!< DWORD 1 725 struct 726 { 727 uint32_t PerThreadScratchSpace : __CODEGEN_BITFIELD( 0, 3) ; //!< Per Thread Scratch Space 728 uint32_t StackSize : __CODEGEN_BITFIELD( 4, 7) ; //!< Stack Size 729 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 9) ; //!< Reserved 730 uint32_t ScratchSpaceBasePointer : __CODEGEN_BITFIELD(10, 31) ; //!< Scratch Space Base Pointer 731 }; 732 uint32_t Value; 733 } DW1; 734 union 735 { 736 //!< DWORD 2 737 struct 738 { 739 uint32_t ScratchSpaceBasePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scratch Space Base Pointer High 740 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 741 }; 742 uint32_t Value; 743 } DW2; 744 union 745 { 746 //!< DWORD 3 747 struct 748 { 749 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 750 uint32_t ResetGatewayTimer : __CODEGEN_BITFIELD( 7, 7) ; //!< RESET_GATEWAY_TIMER 751 uint32_t NumberOfUrbEntries : __CODEGEN_BITFIELD( 8, 15) ; //!< Number of URB Entries 752 uint32_t MaximumNumberOfThreads : __CODEGEN_BITFIELD(16, 31) ; //!< Maximum Number of Threads 753 }; 754 uint32_t Value; 755 } DW3; 756 union 757 { 758 //!< DWORD 4 759 struct 760 { 761 uint32_t SliceDisable : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_DISABLE 762 uint32_t Reserved130 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 763 }; 764 uint32_t Value; 765 } DW4; 766 union 767 { 768 //!< DWORD 5 769 struct 770 { 771 uint32_t CurbeAllocationSize : __CODEGEN_BITFIELD( 0, 15) ; //!< CURBE Allocation Size 772 uint32_t UrbEntryAllocationSize : __CODEGEN_BITFIELD(16, 31) ; //!< URB Entry Allocation Size 773 }; 774 uint32_t Value; 775 } DW5; 776 union 777 { 778 //!< DWORD 6 779 struct 780 { 781 uint32_t ScoreboardMask : __CODEGEN_BITFIELD( 0, 7) ; //!< Scoreboard Mask 782 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 29) ; //!< Reserved 783 uint32_t ScoreboardType : __CODEGEN_BITFIELD(30, 30) ; //!< SCOREBOARD_TYPE 784 uint32_t ScoreboardEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SCOREBOARD_ENABLE 785 }; 786 uint32_t Value; 787 } DW6; 788 union 789 { 790 //!< DWORD 7 791 struct 792 { 793 uint32_t Scoreboard0DeltaX : __CODEGEN_BITFIELD( 0, 3) ; //!< Scoreboard 0 Delta X 794 uint32_t Scoreboard0DeltaY : __CODEGEN_BITFIELD( 4, 7) ; //!< Scoreboard 0 Delta Y 795 uint32_t Scoreboard1DeltaX : __CODEGEN_BITFIELD( 8, 11) ; //!< Scoreboard 1 Delta X 796 uint32_t Scoreboard1DeltaY : __CODEGEN_BITFIELD(12, 15) ; //!< Scoreboard 1 Delta Y 797 uint32_t Scoreboard2DeltaX : __CODEGEN_BITFIELD(16, 19) ; //!< Scoreboard 2 Delta X 798 uint32_t Scoreboard2DeltaY : __CODEGEN_BITFIELD(20, 23) ; //!< Scoreboard 2 Delta Y 799 uint32_t Scoreboard3DeltaX : __CODEGEN_BITFIELD(24, 27) ; //!< Scoreboard 3 Delta X 800 uint32_t Scoreboard3DeltaY : __CODEGEN_BITFIELD(28, 31) ; //!< Scoreboard 3 Delta Y 801 }; 802 uint32_t Value; 803 } DW7; 804 union 805 { 806 //!< DWORD 8 807 struct 808 { 809 uint32_t Scoreboard4DeltaX : __CODEGEN_BITFIELD( 0, 3) ; //!< Scoreboard 4 Delta X 810 uint32_t Scoreboard4DeltaY : __CODEGEN_BITFIELD( 4, 7) ; //!< Scoreboard 4 Delta Y 811 uint32_t Scoreboard5DeltaX : __CODEGEN_BITFIELD( 8, 11) ; //!< Scoreboard 5 Delta X 812 uint32_t Scoreboard5DeltaY : __CODEGEN_BITFIELD(12, 15) ; //!< Scoreboard 5 Delta Y 813 uint32_t Scoreboard6DeltaX : __CODEGEN_BITFIELD(16, 19) ; //!< Scoreboard 6 Delta X 814 uint32_t Scoreboard6DeltaY : __CODEGEN_BITFIELD(20, 23) ; //!< Scoreboard 6 Delta Y 815 uint32_t Scoreboard7DeltaX : __CODEGEN_BITFIELD(24, 27) ; //!< Scoreboard 7 Delta X 816 uint32_t Scoreboard7DeltaY : __CODEGEN_BITFIELD(28, 31) ; //!< Scoreboard 7 Delta Y 817 }; 818 uint32_t Value; 819 } DW8; 820 821 //! \name Local enumerations 822 823 enum SUBOPCODE 824 { 825 SUBOPCODE_MEDIAVFESTATESUBOP = 0, //!< No additional details 826 }; 827 828 enum MEDIA_COMMAND_OPCODE 829 { 830 MEDIA_COMMAND_OPCODE_MEDIAVFESTATE = 0, //!< No additional details 831 }; 832 833 enum PIPELINE 834 { 835 PIPELINE_MEDIA = 2, //!< No additional details 836 }; 837 838 enum COMMAND_TYPE 839 { 840 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 841 }; 842 843 //! \brief RESET_GATEWAY_TIMER 844 //! \details 845 //! This field controls the reset of the timestamp counter maintained in 846 //! Message Gateway. 847 enum RESET_GATEWAY_TIMER 848 { 849 RESET_GATEWAY_TIMER_MAINTAININGTHEEXISTINGTIMESTAMPSTATE = 0, //!< No additional details 850 RESET_GATEWAY_TIMER_RESETTINGRELATIVETIMERANDLATCHINGTHEGLOBALTIMESTAMP = 1, //!< No additional details 851 }; 852 853 //! \brief SLICE_DISABLE 854 //! \details 855 //! This field disables dispatch to slices and subslices for Media and GPGPU 856 //! applications. It is used to limit the amount of scratch space that needs 857 //! to be allocated for a context. If a particular configuration doesn't 858 //! have slice or subslice then there is no impact to disabling it. 859 enum SLICE_DISABLE 860 { 861 SLICE_DISABLE_ALLSUBSLICESENABLED = 0, //!< All subslices are enabled. 862 SLICE_DISABLE_ONLYSLICE0ENABLED = 1, //!< Slice 2 and 1 are disabled, only Slice 0 with all subslices is enabled. 863 SLICE_DISABLE_ONLYSLICE0SUBSLICE0ENABLED = 3, //!< Slice 2 and 1 are disabled, only Slice 0 with only subslice 0 enabled. 864 }; 865 866 //! \brief SCOREBOARD_TYPE 867 //! \details 868 //! This field selects the type of scoreboard in use. 869 enum SCOREBOARD_TYPE 870 { 871 SCOREBOARD_TYPE_STALLINGSCOREBOARD = 0, //!< No additional details 872 SCOREBOARD_TYPE_NON_STALLINGSCOREBOARD = 1, //!< No additional details 873 }; 874 875 //! \brief SCOREBOARD_ENABLE 876 //! \details 877 //! This field enables and disables the hardware scoreboard in the Media 878 //! Pipeline. If this field is cleared, hardware ignores the following 879 //! scoreboard state fields. 880 enum SCOREBOARD_ENABLE 881 { 882 SCOREBOARD_ENABLE_SCOREBOARDDISABLED = 0, //!< No additional details 883 SCOREBOARD_ENABLE_SCOREBOARDENABLED = 1, //!< No additional details 884 }; 885 886 //! \name Initializations 887 888 //! \brief Explicit member initialization function 889 MEDIA_VFE_STATE_CMD(); 890 891 static const size_t dwSize = 9; 892 static const size_t byteSize = 36; 893 }; 894 895 //! 896 //! \brief MEDIA_CURBE_LOAD 897 //! 898 struct MEDIA_CURBE_LOAD_CMD 899 { 900 union 901 { 902 //!< DWORD 0 903 struct 904 { 905 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 906 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 907 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 908 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 909 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 910 }; 911 uint32_t Value; 912 } DW0; 913 union 914 { 915 //!< DWORD 1 916 struct 917 { 918 uint32_t Reserved32 ; //!< Reserved 919 }; 920 uint32_t Value; 921 } DW1; 922 union 923 { 924 //!< DWORD 2 925 struct 926 { 927 uint32_t CurbeTotalDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< CURBE Total Data Length 928 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 929 }; 930 uint32_t Value; 931 } DW2; 932 union 933 { 934 //!< DWORD 3 935 struct 936 { 937 uint32_t CurbeDataStartAddress ; //!< CURBE Data Start Address 938 }; 939 uint32_t Value; 940 } DW3; 941 942 //! \name Local enumerations 943 944 enum SUBOPCODE 945 { 946 SUBOPCODE_MEDIACURBELOADSUBOP = 1, //!< No additional details 947 }; 948 949 enum MEDIA_COMMAND_OPCODE 950 { 951 MEDIA_COMMAND_OPCODE_MEDIACURBELOAD = 0, //!< No additional details 952 }; 953 954 enum PIPELINE 955 { 956 PIPELINE_MEDIA = 2, //!< No additional details 957 }; 958 959 enum COMMAND_TYPE 960 { 961 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 962 }; 963 964 //! \name Initializations 965 966 //! \brief Explicit member initialization function 967 MEDIA_CURBE_LOAD_CMD(); 968 969 static const size_t dwSize = 4; 970 static const size_t byteSize = 16; 971 }; 972 973 //! 974 //! \brief MEDIA_INTERFACE_DESCRIPTOR_LOAD 975 //! \details 976 //! A Media_State_Flush should be used before this command to ensure that 977 //! the temporary Interface Descriptor storage is cleared. 978 //! 979 struct MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD 980 { 981 union 982 { 983 //!< DWORD 0 984 struct 985 { 986 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 987 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 988 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 989 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 990 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 991 }; 992 uint32_t Value; 993 } DW0; 994 union 995 { 996 //!< DWORD 1 997 struct 998 { 999 uint32_t Reserved32 ; //!< Reserved 1000 }; 1001 uint32_t Value; 1002 } DW1; 1003 union 1004 { 1005 //!< DWORD 2 1006 struct 1007 { 1008 uint32_t InterfaceDescriptorTotalLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Interface Descriptor Total Length 1009 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1010 }; 1011 uint32_t Value; 1012 } DW2; 1013 union 1014 { 1015 //!< DWORD 3 1016 struct 1017 { 1018 uint32_t InterfaceDescriptorDataStartAddress ; //!< Interface Descriptor Data Start Address 1019 }; 1020 uint32_t Value; 1021 } DW3; 1022 1023 //! \name Local enumerations 1024 1025 enum SUBOPCODE 1026 { 1027 SUBOPCODE_MEDIAINTERFACEDESCRIPTORLOADSUBOP = 2, //!< No additional details 1028 }; 1029 1030 enum MEDIA_COMMAND_OPCODE 1031 { 1032 MEDIA_COMMAND_OPCODE_MEDIAINTERFACEDESCRIPTORLOAD = 0, //!< No additional details 1033 }; 1034 1035 enum PIPELINE 1036 { 1037 PIPELINE_MEDIA = 2, //!< No additional details 1038 }; 1039 1040 enum COMMAND_TYPE 1041 { 1042 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1043 }; 1044 1045 //! \name Initializations 1046 1047 //! \brief Explicit member initialization function 1048 MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD(); 1049 1050 static const size_t dwSize = 4; 1051 static const size_t byteSize = 16; 1052 }; 1053 1054 //! 1055 //! \brief MEDIA_OBJECT_WALKER 1056 //! \details 1057 //! 1058 //! 1059 struct MEDIA_OBJECT_WALKER_CMD 1060 { 1061 union 1062 { 1063 //!< DWORD 0 1064 struct 1065 { 1066 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 1067 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1068 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1069 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1070 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1071 }; 1072 uint32_t Value; 1073 } DW0; 1074 union 1075 { 1076 //!< DWORD 1 1077 struct 1078 { 1079 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1080 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1081 }; 1082 uint32_t Value; 1083 } DW1; 1084 union 1085 { 1086 //!< DWORD 2 1087 struct 1088 { 1089 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1090 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 20) ; //!< Reserved 1091 uint32_t UseScoreboard : __CODEGEN_BITFIELD(21, 21) ; //!< USE_SCOREBOARD 1092 uint32_t MaskedDispatch : __CODEGEN_BITFIELD(22, 23) ; //!< MASKED_DISPATCH 1093 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 1094 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1095 }; 1096 uint32_t Value; 1097 } DW2; 1098 union 1099 { 1100 //!< DWORD 3 1101 struct 1102 { 1103 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 1104 }; 1105 uint32_t Value; 1106 } DW3; 1107 union 1108 { 1109 //!< DWORD 4 1110 struct 1111 { 1112 uint32_t Reserved128 ; //!< Reserved 1113 }; 1114 uint32_t Value; 1115 } DW4; 1116 union 1117 { 1118 //!< DWORD 5 1119 struct 1120 { 1121 uint32_t ScoreboardMask : __CODEGEN_BITFIELD( 0, 7) ; //!< Scoreboard Mask 1122 uint32_t GroupIdLoopSelect : __CODEGEN_BITFIELD( 8, 31) ; //!< GROUP_ID_LOOP_SELECT 1123 }; 1124 uint32_t Value; 1125 } DW5; 1126 union 1127 { 1128 //!< DWORD 6 1129 struct 1130 { 1131 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1132 uint32_t MidLoopUnitX : __CODEGEN_BITFIELD( 8, 9) ; //!< Mid-Loop Unit X 1133 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1134 uint32_t LocalMidLoopUnitY : __CODEGEN_BITFIELD(12, 13) ; //!< Local Mid-Loop Unit Y 1135 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1136 uint32_t MiddleLoopExtraSteps : __CODEGEN_BITFIELD(16, 20) ; //!< Middle Loop Extra Steps 1137 uint32_t Reserved213 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1138 uint32_t ColorCountMinusOne : __CODEGEN_BITFIELD(24, 27) ; //!< Color Count Minus One 1139 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1140 }; 1141 uint32_t Value; 1142 } DW6; 1143 union 1144 { 1145 //!< DWORD 7 1146 struct 1147 { 1148 uint32_t LocalLoopExecCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Loop Exec Count 1149 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1150 uint32_t GlobalLoopExecCount : __CODEGEN_BITFIELD(16, 27) ; //!< Global Loop Exec Count 1151 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1152 }; 1153 uint32_t Value; 1154 } DW7; 1155 union 1156 { 1157 //!< DWORD 8 1158 struct 1159 { 1160 uint32_t BlockResolutionX : __CODEGEN_BITFIELD( 0, 10) ; //!< Block Resolution X 1161 uint32_t Reserved267 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1162 uint32_t BlockResolutionY : __CODEGEN_BITFIELD(16, 26) ; //!< Block Resolution Y 1163 uint32_t Reserved283 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1164 }; 1165 uint32_t Value; 1166 } DW8; 1167 union 1168 { 1169 //!< DWORD 9 1170 struct 1171 { 1172 uint32_t LocalStartX : __CODEGEN_BITFIELD( 0, 10) ; //!< Local Start X 1173 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1174 uint32_t LocalStartY : __CODEGEN_BITFIELD(16, 26) ; //!< Local Start Y 1175 uint32_t Reserved315 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1176 }; 1177 uint32_t Value; 1178 } DW9; 1179 union 1180 { 1181 //!< DWORD 10 1182 struct 1183 { 1184 uint32_t Reserved320 ; //!< Reserved 1185 }; 1186 uint32_t Value; 1187 } DW10; 1188 union 1189 { 1190 //!< DWORD 11 1191 struct 1192 { 1193 uint32_t LocalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Outer Loop Stride X 1194 uint32_t Reserved364 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1195 uint32_t LocalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 27) ; //!< Local Outer Loop Stride Y 1196 uint32_t Reserved380 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1197 }; 1198 uint32_t Value; 1199 } DW11; 1200 union 1201 { 1202 //!< DWORD 12 1203 struct 1204 { 1205 uint32_t LocalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Inner Loop Unit X 1206 uint32_t Reserved396 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1207 uint32_t LocalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 27) ; //!< Local Inner Loop Unit Y 1208 uint32_t Reserved412 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1209 }; 1210 uint32_t Value; 1211 } DW12; 1212 union 1213 { 1214 //!< DWORD 13 1215 struct 1216 { 1217 uint32_t GlobalResolutionX : __CODEGEN_BITFIELD( 0, 10) ; //!< Global Resolution X 1218 uint32_t Reserved427 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1219 uint32_t GlobalResolutionY : __CODEGEN_BITFIELD(16, 26) ; //!< Global Resolution Y 1220 uint32_t Reserved443 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1221 }; 1222 uint32_t Value; 1223 } DW13; 1224 union 1225 { 1226 //!< DWORD 14 1227 struct 1228 { 1229 uint32_t GlobalStartX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Start X 1230 uint32_t Reserved460 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1231 uint32_t GlobalStartY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Start Y 1232 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1233 }; 1234 uint32_t Value; 1235 } DW14; 1236 union 1237 { 1238 //!< DWORD 15 1239 struct 1240 { 1241 uint32_t GlobalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Outer Loop Stride X 1242 uint32_t Reserved492 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1243 uint32_t GlobalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Outer Loop Stride Y 1244 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1245 }; 1246 uint32_t Value; 1247 } DW15; 1248 union 1249 { 1250 //!< DWORD 16 1251 struct 1252 { 1253 uint32_t GlobalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Inner Loop Unit X 1254 uint32_t Reserved524 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1255 uint32_t GlobalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Inner Loop Unit Y 1256 uint32_t Reserved540 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1257 }; 1258 uint32_t Value; 1259 } DW16; 1260 1261 //! \name Local enumerations 1262 1263 enum SUBOPCODE 1264 { 1265 SUBOPCODE_MEDIAOBJECTWALKERSUBOP = 3, //!< No additional details 1266 }; 1267 1268 enum MEDIA_COMMAND_OPCODE 1269 { 1270 MEDIA_COMMAND_OPCODE_MEDIAOBJECTWALKER = 1, //!< No additional details 1271 }; 1272 1273 enum PIPELINE 1274 { 1275 PIPELINE_MEDIA = 2, //!< No additional details 1276 }; 1277 1278 enum COMMAND_TYPE 1279 { 1280 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1281 }; 1282 1283 //! \brief USE_SCOREBOARD 1284 //! \details 1285 //! This field specifies whether the thread associated with this command 1286 //! uses hardware scoreboard. Only when this field is set, the scoreboard 1287 //! control fields in the VFE Dword are valid. If this field is cleared, the 1288 //! thread associated with this command bypasses hardware scoreboard. 1289 enum USE_SCOREBOARD 1290 { 1291 USE_SCOREBOARD_NOTUSINGSCOREBOARD = 0, //!< No additional details 1292 USE_SCOREBOARD_USINGSCOREBOARD = 1, //!< No additional details 1293 }; 1294 1295 //! \brief MASKED_DISPATCH 1296 //! \details 1297 //! Enable the masking of the dispatch of individual threads based on a 1298 //! bitmask read from CURBE, and specifies the pitch of the CURBE surface. 1299 //! If enabled, CURBE will not be used for thread payload. 1300 enum MASKED_DISPATCH 1301 { 1302 MASKED_DISPATCH_UNNAMED0 = 0, //!< Masked Dispatch Disabled 1303 MASKED_DISPATCH_UNNAMED1 = 1, //!< Masked Dispatch with 128-bit pitch in CURBE 1304 MASKED_DISPATCH_UNNAMED2 = 2, //!< Masked Dispatch with 256-bit pitch in CURBE 1305 MASKED_DISPATCH_UNNAMED3 = 3, //!< Masked Dispatch with 512-bit pitch in CURBE 1306 }; 1307 1308 //! \brief THREAD_SYNCHRONIZATION 1309 //! \details 1310 //! This field when set indicates that the dispatch of the thread originated 1311 //! from this command is based on the "spawn root thread" message. 1312 enum THREAD_SYNCHRONIZATION 1313 { 1314 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 1315 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 1316 }; 1317 1318 //! \brief GROUP_ID_LOOP_SELECT 1319 //! \details 1320 //! This bit field chooses which of the nested loops of the walker are used 1321 //! to identify threads which share a group id and therefore a shared 1322 //! barrier and SLM. The programmer must ensure that each group will fit 1323 //! into a single subslice. When barriers are enabled every group must have 1324 //! the same number of threads matching the number specified in the 1325 //! Interface Descriptor. 1326 enum GROUP_ID_LOOP_SELECT 1327 { 1328 GROUP_ID_LOOP_SELECT_NOGROUPS = 0, //!< Groups are not created, barriers and SLM are not allocated 1329 GROUP_ID_LOOP_SELECT_COLORGROUPS = 1, //!< Each complete iteration of the Color loop defines a group, the group id is the concatenation of the Outer global, Inner global, Outer local, Mid local and Inner local loop execution counts. 1330 GROUP_ID_LOOP_SELECT_INNERLOCALGROUPS = 2, //!< Each complete iteration of the Inner local loop and Color loop defines a group, the group id is the concatenation of the Outer global loop to the Mid local loop execution counts. 1331 GROUP_ID_LOOP_SELECT_MIDLOCALGROUPS = 3, //!< Each complete iteration of the Mid local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop to the Outer local loop execution counts. 1332 GROUP_ID_LOOP_SELECT_OUTERLOCALGROUPS = 4, //!< Each complete iteration of the Outer local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop and the Inner global loop execution counts. 1333 GROUP_ID_LOOP_SELECT_INNERGLOBALGROUPS = 5, //!< Each complete iteration of the Inner global loop and lower loops defines a group, the group id is the Outer global loop execution count. 1334 }; 1335 1336 //! \name Initializations 1337 1338 //! \brief Explicit member initialization function 1339 MEDIA_OBJECT_WALKER_CMD(); 1340 1341 static const size_t dwSize = 17; 1342 static const size_t byteSize = 68; 1343 }; 1344 1345 //! 1346 //! \brief GPGPU_WALKER 1347 //! \details 1348 //! If the threads spawned by this command are required to observe memory 1349 //! writes performed by threads spawned from a previous command, software 1350 //! must precede this command with a command that performs a memory flush 1351 //! (e.g., MI_FLUSH). 1352 //! 1353 struct GPGPU_WALKER_CMD 1354 { 1355 union 1356 { 1357 //!< DWORD 0 1358 struct 1359 { 1360 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1361 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Predicate Enable 1362 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1363 uint32_t IndirectParameterEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Indirect Parameter Enable 1364 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1365 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1366 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1367 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1368 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1369 }; 1370 uint32_t Value; 1371 } DW0; 1372 union 1373 { 1374 //!< DWORD 1 1375 struct 1376 { 1377 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1378 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1379 }; 1380 uint32_t Value; 1381 } DW1; 1382 union 1383 { 1384 //!< DWORD 2 1385 struct 1386 { 1387 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1388 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1389 }; 1390 uint32_t Value; 1391 } DW2; 1392 union 1393 { 1394 //!< DWORD 3 1395 struct 1396 { 1397 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1398 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Indirect Data Start Address 1399 }; 1400 uint32_t Value; 1401 } DW3; 1402 union 1403 { 1404 //!< DWORD 4 1405 struct 1406 { 1407 uint32_t ThreadWidthCounterMaximum : __CODEGEN_BITFIELD( 0, 5) ; //!< Thread Width Counter Maximum 1408 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1409 uint32_t ThreadHeightCounterMaximum : __CODEGEN_BITFIELD( 8, 13) ; //!< Thread Height Counter Maximum 1410 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1411 uint32_t ThreadDepthCounterMaximum : __CODEGEN_BITFIELD(16, 21) ; //!< Thread Depth Counter Maximum 1412 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 29) ; //!< Reserved 1413 uint32_t SimdSize : __CODEGEN_BITFIELD(30, 31) ; //!< SIMD_SIZE 1414 }; 1415 uint32_t Value; 1416 } DW4; 1417 union 1418 { 1419 //!< DWORD 5 1420 struct 1421 { 1422 uint32_t ThreadGroupIdStartingX ; //!< Thread Group ID Starting X 1423 }; 1424 uint32_t Value; 1425 } DW5; 1426 union 1427 { 1428 //!< DWORD 6 1429 struct 1430 { 1431 uint32_t Reserved192 ; //!< Reserved 1432 }; 1433 uint32_t Value; 1434 } DW6; 1435 union 1436 { 1437 //!< DWORD 7 1438 struct 1439 { 1440 uint32_t ThreadGroupIdXDimension ; //!< Thread Group ID X Dimension 1441 }; 1442 uint32_t Value; 1443 } DW7; 1444 union 1445 { 1446 //!< DWORD 8 1447 struct 1448 { 1449 uint32_t ThreadGroupIdStartingY ; //!< Thread Group ID Starting Y 1450 }; 1451 uint32_t Value; 1452 } DW8; 1453 union 1454 { 1455 //!< DWORD 9 1456 struct 1457 { 1458 uint32_t Reserved288 ; //!< Reserved 1459 }; 1460 uint32_t Value; 1461 } DW9; 1462 union 1463 { 1464 //!< DWORD 10 1465 struct 1466 { 1467 uint32_t ThreadGroupIdYDimension ; //!< Thread Group ID Y Dimension 1468 }; 1469 uint32_t Value; 1470 } DW10; 1471 union 1472 { 1473 //!< DWORD 11 1474 struct 1475 { 1476 uint32_t ThreadGroupIdStartingResumeZ ; //!< Thread Group ID Starting/Resume Z 1477 }; 1478 uint32_t Value; 1479 } DW11; 1480 union 1481 { 1482 //!< DWORD 12 1483 struct 1484 { 1485 uint32_t ThreadGroupIdZDimension ; //!< Thread Group ID Z Dimension 1486 }; 1487 uint32_t Value; 1488 } DW12; 1489 union 1490 { 1491 //!< DWORD 13 1492 struct 1493 { 1494 uint32_t RightExecutionMask ; //!< Right Execution Mask 1495 }; 1496 uint32_t Value; 1497 } DW13; 1498 union 1499 { 1500 //!< DWORD 14 1501 struct 1502 { 1503 uint32_t BottomExecutionMask ; //!< Bottom Execution Mask 1504 }; 1505 uint32_t Value; 1506 } DW14; 1507 1508 //! \name Local enumerations 1509 1510 enum SUBOPCODE 1511 { 1512 SUBOPCODE_GPGPUWALKERSUBOP = 5, //!< No additional details 1513 }; 1514 1515 enum MEDIA_COMMAND_OPCODE 1516 { 1517 MEDIA_COMMAND_OPCODE_GPGPUWALKER = 1, //!< No additional details 1518 }; 1519 1520 enum PIPELINE 1521 { 1522 PIPELINE_MEDIA = 2, //!< No additional details 1523 }; 1524 1525 enum COMMAND_TYPE 1526 { 1527 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1528 }; 1529 1530 //! \brief SIMD_SIZE 1531 //! \details 1532 //! This field determines the size of the payload and the number of bits of 1533 //! the execution mask that are expected. The kernel pointed to by the 1534 //! interface descriptor should match the SIMD declared here. 1535 enum SIMD_SIZE 1536 { 1537 SIMD_SIZE_SIMD8 = 0, //!< 8 LSBs of the execution mask are used 1538 SIMD_SIZE_SIMD16 = 1, //!< 16 LSBs used in execution mask 1539 SIMD_SIZE_SIMD32 = 2, //!< 32 bits of execution mask used 1540 }; 1541 1542 //! \name Initializations 1543 1544 //! \brief Explicit member initialization function 1545 GPGPU_WALKER_CMD(); 1546 1547 static const size_t dwSize = 15; 1548 static const size_t byteSize = 60; 1549 }; 1550 1551 //! 1552 //! \brief _3DSTATE_CHROMA_KEY 1553 //! \details 1554 //! The 3DSTATE_CHROMA_KEY instruction is used to program texture 1555 //! color/chroma-key key values. A table containing four set of values is 1556 //! supported. The ChromaKey Index sampler state variable is used to select 1557 //! which table entry is associated with the map. Texture chromakey 1558 //! functions are enabled and controlled via use of the ChromaKey Enable 1559 //! texture sampler state variable.Texture Color Key (keying on a paletted 1560 //! texture index) is not supported. 1561 //! 1562 struct _3DSTATE_CHROMA_KEY_CMD 1563 { 1564 union 1565 { 1566 //!< DWORD 0 1567 struct 1568 { 1569 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1570 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1571 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1572 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1573 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1574 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1575 }; 1576 uint32_t Value; 1577 } DW0; 1578 union 1579 { 1580 //!< DWORD 1 1581 struct 1582 { 1583 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 1584 uint32_t ChromakeyTableIndex : __CODEGEN_BITFIELD(30, 31) ; //!< ChromaKey Table Index 1585 }; 1586 uint32_t Value; 1587 } DW1; 1588 union 1589 { 1590 //!< DWORD 2 1591 struct 1592 { 1593 uint32_t ChromakeyLowValue ; //!< ChromaKey Low Value 1594 }; 1595 uint32_t Value; 1596 } DW2; 1597 union 1598 { 1599 //!< DWORD 3 1600 struct 1601 { 1602 uint32_t ChromakeyHighValue ; //!< ChromaKey High Value 1603 }; 1604 uint32_t Value; 1605 } DW3; 1606 1607 //! \name Local enumerations 1608 1609 enum _3D_COMMAND_SUB_OPCODE 1610 { 1611 _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY = 4, //!< No additional details 1612 }; 1613 1614 enum _3D_COMMAND_OPCODE 1615 { 1616 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1617 }; 1618 1619 enum COMMAND_SUBTYPE 1620 { 1621 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1622 }; 1623 1624 enum COMMAND_TYPE 1625 { 1626 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1627 }; 1628 1629 //! \name Initializations 1630 1631 //! \brief Explicit member initialization function 1632 _3DSTATE_CHROMA_KEY_CMD(); 1633 1634 static const size_t dwSize = 4; 1635 static const size_t byteSize = 16; 1636 }; 1637 1638 //! 1639 //! \brief _3DSTATE_SAMPLER_PALETTE_LOAD0 1640 //! \details 1641 //! The 3DSTATE_SAMPLER_PALETTE_LOAD0 instruction is used to load 32-bit 1642 //! values into the first texture palette. The texture palette is used 1643 //! whenever a texture with a paletted format (containing "Px [palette0]") 1644 //! is referenced by the sampler. 1645 //! 1646 //! This instruction is used to load all or a subset of the 256 entries of 1647 //! the first palette. Partial loads always start from the first (index 0) 1648 //! entry. 1649 //! 1650 struct _3DSTATE_SAMPLER_PALETTE_LOAD0_CMD 1651 { 1652 union 1653 { 1654 //!< DWORD 0 1655 struct 1656 { 1657 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWord Length 1658 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1659 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1660 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1661 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1662 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1663 }; 1664 uint32_t Value; 1665 } DW0; 1666 1667 //! \name Local enumerations 1668 1669 enum _3D_COMMAND_SUB_OPCODE 1670 { 1671 _3D_COMMAND_SUB_OPCODE_3DSTATESAMPLERPALETTELOAD0 = 2, //!< No additional details 1672 }; 1673 1674 enum _3D_COMMAND_OPCODE 1675 { 1676 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1677 }; 1678 1679 enum COMMAND_SUBTYPE 1680 { 1681 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1682 }; 1683 1684 enum COMMAND_TYPE 1685 { 1686 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1687 }; 1688 1689 //! \name Initializations 1690 1691 //! \brief Explicit member initialization function 1692 _3DSTATE_SAMPLER_PALETTE_LOAD0_CMD(); 1693 1694 static const size_t dwSize = 1; 1695 static const size_t byteSize = 4; 1696 }; 1697 1698 //! 1699 //! \brief _3DSTATE_SAMPLER_PALETTE_LOAD1 1700 //! \details 1701 //! The 3DSTATE_SAMPLER_PALETTE_LOAD1 instruction is used to load 32-bit 1702 //! values into the second texture palette. The second texture palette is 1703 //! used whenever a texture with a paletted format (containing 1704 //! "Px...[palette1]") is referenced by the sampler.This instruction is used 1705 //! to load all or a subset of the 256 entries of the second palette. 1706 //! Partial loads always start from the first (index 0) entry. 1707 //! 1708 struct _3DSTATE_SAMPLER_PALETTE_LOAD1_CMD 1709 { 1710 union 1711 { 1712 //!< DWORD 0 1713 struct 1714 { 1715 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1716 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1717 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1718 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1719 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1720 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1721 }; 1722 uint32_t Value; 1723 } DW0; 1724 1725 //! \name Local enumerations 1726 1727 enum _3D_COMMAND_SUB_OPCODE 1728 { 1729 _3D_COMMAND_SUB_OPCODE_3DSTATESAMPLERPALETTELOAD1 = 12, //!< No additional details 1730 }; 1731 1732 enum _3D_COMMAND_OPCODE 1733 { 1734 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1735 }; 1736 1737 enum COMMAND_SUBTYPE 1738 { 1739 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1740 }; 1741 1742 enum COMMAND_TYPE 1743 { 1744 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1745 }; 1746 1747 //! \name Initializations 1748 1749 //! \brief Explicit member initialization function 1750 _3DSTATE_SAMPLER_PALETTE_LOAD1_CMD(); 1751 1752 static const size_t dwSize = 1; 1753 static const size_t byteSize = 4; 1754 }; 1755 1756 //! 1757 //! \brief PALETTE_ENTRY 1758 //! \details 1759 //! 1760 //! 1761 struct PALETTE_ENTRY_CMD 1762 { 1763 union 1764 { 1765 //!< DWORD 0 1766 struct 1767 { 1768 uint32_t Blue : __CODEGEN_BITFIELD( 0, 7) ; //!< Blue 1769 uint32_t Green : __CODEGEN_BITFIELD( 8, 15) ; //!< Green 1770 uint32_t Red : __CODEGEN_BITFIELD(16, 23) ; //!< Red 1771 uint32_t Alpha : __CODEGEN_BITFIELD(24, 31) ; //!< Alpha 1772 }; 1773 uint32_t Value; 1774 } DW0; 1775 1776 //! \name Local enumerations 1777 1778 //! \name Initializations 1779 1780 //! \brief Explicit member initialization function 1781 PALETTE_ENTRY_CMD(); 1782 1783 static const size_t dwSize = 1; 1784 static const size_t byteSize = 4; 1785 }; 1786 1787 //! 1788 //! \brief STATE_SIP 1789 //! \details 1790 //! The STATE_SIP command specifies the starting instruction location of the 1791 //! System Routine that is shared by all threads in execution. 1792 //! 1793 struct STATE_SIP_CMD 1794 { 1795 union 1796 { 1797 //!< DWORD 0 1798 struct 1799 { 1800 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1801 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1802 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1803 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1804 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1805 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1806 }; 1807 uint32_t Value; 1808 } DW0; 1809 union 1810 { 1811 //!< DWORD 1..2 1812 struct 1813 { 1814 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 1815 uint64_t SystemInstructionPointer : __CODEGEN_BITFIELD( 4, 63) ; //!< System Instruction Pointer 1816 }; 1817 uint32_t Value[2]; 1818 } DW1_2; 1819 1820 //! \name Local enumerations 1821 1822 enum _3D_COMMAND_SUB_OPCODE 1823 { 1824 _3D_COMMAND_SUB_OPCODE_STATESIP = 2, //!< No additional details 1825 }; 1826 1827 enum _3D_COMMAND_OPCODE 1828 { 1829 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1830 }; 1831 1832 enum COMMAND_SUBTYPE 1833 { 1834 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1835 }; 1836 1837 enum COMMAND_TYPE 1838 { 1839 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1840 }; 1841 1842 //! \name Initializations 1843 1844 //! \brief Explicit member initialization function 1845 STATE_SIP_CMD(); 1846 1847 static const size_t dwSize = 3; 1848 static const size_t byteSize = 12; 1849 }; 1850 1851 //! 1852 //! \brief GPGPU_CSR_BASE_ADDRESS 1853 //! \details 1854 //! The GPGPU_CSR_BASE_ADDRESS command sets the base pointers for EU and L3 1855 //! to Context Save and Restore EU State and SLM for GPGPU mid-thread 1856 //! preemption. 1857 //! 1858 //! Execution of this command causes a full pipeline flush, thus its use 1859 //! should be minimized for higher performance. State and instruction caches 1860 //! are flushed on completion of the flush. 1861 //! 1862 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 1863 //! Cache Flush Enable" set prior to programming GPGPU_CSR_BASE_ADDRESS 1864 //! command for GPGPU workloads i.e when pipeline select is GPGPU via 1865 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 1866 //! preemption latencies for certain programming sequences. If programming 1867 //! PIPE_CONTROL has performance implications then preemption latencies can 1868 //! be trade off against performance by not implementing this programming 1869 //! note. 1870 //! 1871 struct GPGPU_CSR_BASE_ADDRESS_CMD 1872 { 1873 union 1874 { 1875 //!< DWORD 0 1876 struct 1877 { 1878 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1879 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1880 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1881 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1882 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1883 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1884 }; 1885 uint32_t Value; 1886 } DW0; 1887 union 1888 { 1889 //!< DWORD 1..2 1890 struct 1891 { 1892 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1893 uint64_t GpgpuCsrBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< GPGPU CSR Base Address 1894 }; 1895 uint32_t Value[2]; 1896 } DW1_2; 1897 1898 //! \name Local enumerations 1899 1900 enum _3D_COMMAND_SUB_OPCODE 1901 { 1902 _3D_COMMAND_SUB_OPCODE_GPGPUCSRBASEADDRESS = 4, //!< No additional details 1903 }; 1904 1905 enum _3D_COMMAND_OPCODE 1906 { 1907 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1908 }; 1909 1910 enum COMMAND_SUBTYPE 1911 { 1912 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1913 }; 1914 1915 enum COMMAND_TYPE 1916 { 1917 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1918 }; 1919 1920 //! \name Initializations 1921 1922 //! \brief Explicit member initialization function 1923 GPGPU_CSR_BASE_ADDRESS_CMD(); 1924 1925 static const size_t dwSize = 3; 1926 static const size_t byteSize = 12; 1927 }; 1928 1929 }; 1930 1931 #pragma pack() 1932 1933 #endif // __MHW_RENDER_HWCMD_G9_X_H__ 1934