1 /*===================== begin_copyright_notice ================================== 2 3 * Copyright (c) 2021, Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 25 //! 26 //! \file mhw_render_hwcmd_xe_hp_base.h 27 //! \brief Auto-generated constructors for MHW and states. 28 //! \details This file may not be included outside of g12_X as other components 29 //! should use MHW interface to interact with MHW commands and states. 30 //! 31 32 // DO NOT EDIT 33 34 #ifndef __MHW_RENDER_HWCMD_XE_HP_BASE_H__ 35 #define __MHW_RENDER_HWCMD_XE_HP_BASE_H__ 36 37 #pragma once 38 #pragma pack(1) 39 40 #include <cstdint> 41 #include <cstddef> 42 43 class mhw_render_xe_xpm_base 44 { 45 public: 46 // Internal Macros 47 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 48 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 49 #define __CODEGEN_OP_LENGTH_BIAS 2 50 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 51 GetOpLength(uint32_t uiLength)52 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 53 54 //! 55 //! \brief PIPELINE_SELECT 56 //! \details 57 //! The PIPELINE_SELECT command is used to specify which GPE pipeline is to 58 //! be considered the 'current' active pipeline. Issuing 59 //! 3D-pipeline-specific commands when the Media pipeline is selected, or 60 //! vice versa, is UNDEFINED. 61 //! 62 //! Issuing 3D-pipeline-specific commands when the GPGPU pipeline is 63 //! selected, or vice versa, is UNDEFINED. 64 //! 65 //! Programming common non pipeline commands (e.g., STATE_BASE_ADDRESS) is 66 //! allowed in all pipeline modes. 67 //! 68 //! Software must ensure all the write caches are flushed through a stalling 69 //! PIPE_CONTROL command followed by another PIPE_CONTROL command to 70 //! invalidate read only caches prior to programming MI_PIPELINE_SELECT 71 //! command to change the Pipeline Select Mode. Example: ... Workload-3Dmode 72 //! PIPE_CONTROL (CS Stall, Depth Cache Flush Enable, Render Target Cache 73 //! Flush Enable, DC Flush Enable) PIPE_CONTROL (Constant Cache Invalidate, 74 //! Texture Cache Invalidate, Instruction Cache Invalidate, State Cache 75 //! invalidate) PIPELINE_SELECT ( GPGPU) 76 //! 77 //! "Pipe Selection" must be never set to "3D" in PIPELINE_SELECT command 78 //! programmed for workloads submitted to ComputeCS. 79 //! 80 //! style="margin:0in 0in 0.0001pt">While GPU is operating in GPGPU mode of 81 //! operation and when a Mid Thread Preemption (if enabled) occurs on a 82 //! PIPELINE_SELECT command with "Media Sampler DOP CG Enable" reset along 83 //! with "Pipeline Select Mode" set to 3D and on resubmission of this 84 //! context on context restore "Sampler DOP CG Enable" will be reset. This 85 //! would mean the GPGPU mid thread preempted threads restored will get 86 //! executed with media sampler DOP clock not gated consuming media sampler 87 //! DOP power until all GPGPU threads have retired. 88 //! style="margin:0in 0in 0.0001pt"> 89 //! style="margin:0in 0in 0.0001pt">Programming of the PIPELINE_SELECT can 90 //! be modified to avoid the above inefficiency. This can be done by 91 //! programming "Pipeline Selection" and "Media Sampler DOP CG Enable" 92 //! fields in two different PIPELINE_SELECT commands instead of on single 93 //! PIPELINE_SELECTcommand. 94 //! style="margin:0in 0in 0.0001pt"> 95 //! style="margin:0in 0in 0.0001pt">Example: 96 //! style="margin:0in 0in 0.0001pt">PIPELINE_SELECT ( Pipeline Selection = 97 //! 3D, Media Sampler DOP CG Enable = False) 98 //! style="margin:0in 0in 0.0001pt"> 99 //! style="margin:0in 0in 0.0001pt">To 100 //! style="margin:0in 0in 0.0001pt">PIPELINE_SELECT ( Pipeline Selection = 101 //! 3D) 102 //! style="margin:0in 0in 0.0001pt">PIPELINE_SELECT (Media Sampler DOP CG 103 //! Enable = False) 104 //! 105 struct PIPELINE_SELECT_CMD 106 { 107 union 108 { 109 struct 110 { 111 uint32_t PipelineSelection : __CODEGEN_BITFIELD( 0, 1) ; //!< PIPELINE_SELECTION 112 uint32_t RenderSliceCommonPowerGateEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< RENDER_SLICE_COMMON_POWER_GATE_ENABLE 113 uint32_t RenderSamplerPowerGateEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< RENDER_SAMPLER_POWER_GATE_ENABLE 114 uint32_t MediaSamplerDopClockGateEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 115 uint32_t Reserved5 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 116 uint32_t MediaSamplerPowerClockGateDisable : __CODEGEN_BITFIELD( 6, 6) ; //!< Media Sampler Power Clock Gate Disable 117 uint32_t SystolicModeEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SYSTOLIC_MODE_ENABLE 118 uint32_t MaskBits : __CODEGEN_BITFIELD( 8, 15) ; //!< Mask Bits 119 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 120 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 121 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 122 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 123 }; 124 uint32_t Value; 125 } DW0; 126 127 //! \name Local enumerations 128 129 //! \brief PIPELINE_SELECTION 130 //! \details 131 //! Mask bits [9:8] has to be set for HW to look at this field when 132 //! PIPELINE_SELECT command is parsed. Setting only one of the mask bit [9] 133 //! or [8] is illegal. 134 enum PIPELINE_SELECTION 135 { 136 PIPELINE_SELECTION_3D = 0, //!< 3D pipeline is selected 137 PIPELINE_SELECTION_MEDIA = 1, //!< Media pipeline is selected (Includes HD optical disc playback, HD video playback, and generic media workloads) 138 PIPELINE_SELECTION_GPGPU = 2, //!< GPGPU pipeline is selected 139 }; 140 141 //! \brief RENDER_SLICE_COMMON_POWER_GATE_ENABLE 142 //! \details 143 //! Mask bit [10] has to be set for HW to look at this field when 144 //! PIPELINE_SELECT command is parsed. 145 enum RENDER_SLICE_COMMON_POWER_GATE_ENABLE 146 { 147 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render slice common Power Gating. 148 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render slice common Power Gating. 149 }; 150 151 //! \brief RENDER_SAMPLER_POWER_GATE_ENABLE 152 //! \details 153 //! Mask bit [11] has to be set for HW to look at this field when 154 //! PIPELINE_SELECT command is parsed. 155 enum RENDER_SAMPLER_POWER_GATE_ENABLE 156 { 157 RENDER_SAMPLER_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render sampler Power Gating. 158 RENDER_SAMPLER_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render sampler Power Gating. 159 }; 160 161 //! \brief MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 162 //! \details 163 //! Mask bit [12] has to be set for HW to look at this field when 164 //! PIPELINE_SELECT command is parsed. 165 enum MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 166 { 167 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable sampler DOP Clock Gating. 168 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable media sampler DOP Clock Gating. 169 }; 170 171 //! \brief SYSTOLIC_MODE_ENABLE 172 //! \details 173 //! When set, this will enable systolic mode for the following 174 //! COMPUTE_WALKER commands. This will lower the Fmax to avoid ICC current 175 //! issues when executing systolic array commands in the execution units. If 176 //! this is not set prior to executing systolic array operations, the 177 //! context will be halted to avoid any ICC issues. 178 enum SYSTOLIC_MODE_ENABLE 179 { 180 SYSTOLIC_MODE_ENABLE_SYSTOLICMODEDISABLED = 0, //!< No additional details 181 SYSTOLIC_MODE_ENABLE_SYSTOLICMODEENABLED = 1, //!< No additional details 182 }; 183 184 enum _3D_COMMAND_SUB_OPCODE 185 { 186 _3D_COMMAND_SUB_OPCODE_PIPELINESELECT = 4, //!< No additional details 187 }; 188 189 enum _3D_COMMAND_OPCODE 190 { 191 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 192 }; 193 194 enum COMMAND_SUBTYPE 195 { 196 COMMAND_SUBTYPE_GFXPIPESINGLEDW = 1, //!< No additional details 197 }; 198 199 enum COMMAND_TYPE 200 { 201 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 202 }; 203 204 //! \name Initializations 205 206 //! \brief Explicit member initialization function 207 PIPELINE_SELECT_CMD(); 208 209 static const size_t dwSize = 1; 210 static const size_t byteSize = 4; 211 }; 212 213 //! 214 //! \brief STATE_BASE_ADDRESS 215 //! \details 216 //! The STATE_BASE_ADDRESS command sets the base pointers for subsequent 217 //! state, instruction, and media indirect object accesses by the GPE. 218 //! For more information see the Base Address Utilization table in the 219 //! Memory Access Indirection narrative topic. 220 //! 221 //! The following commands must be reissued following any change to the base 222 //! addresses: 223 //! 224 //! 3DSTATE_CC_POINTERS 225 //! 226 //! 3DSTATE_BINDING_TABLE_POINTERS 227 //! 228 //! 3DSTATE_SAMPLER_STATE_POINTERS 229 //! 230 //! 3DSTATE_VIEWPORT_STATE_POINTERS 231 //! 232 //! 233 //! 234 //! 235 //! 236 //! Execution of this command causes a full pipeline flush, thus its use 237 //! should be minimized for higher performance. 238 //! 239 //! If 3DSTATE_PS_EXTRA::Pixel Shader Is Per Coarse Pixel == 1, the 240 //! 3DSTATE_CPS_POINTERS command must be reissued following any change to 241 //! the dynamic state base address. 242 //! 243 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 244 //! Cache Flush Enable" set before programming STATE_BASE_ADDRESS command 245 //! for GPGPU workloads i.e when pipeline select is GPGPU via 246 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 247 //! preemption latencies in certain workload programming sequences. If 248 //! programming PIPE_CONTROL has performance implications then preemption 249 //! latencies can be traded off against performance by not implementing this 250 //! programming note. 251 //! 252 //! SW must always program PIPE_CONTROL command with "HDC Pipleine FLush" 253 //! set prior to programming of STATE_BASE_ADDRESS command for GPGPU/Media 254 //! workloads i.e when pipeline select is GPGPU or Media via PIPELINE_SELECT 255 //! command. This is required to ensure thewrite data out of the prior 256 //! thread group are flushed out prior to the state changes due to the 257 //! programming of STATE_BASE_ADDRESS command take place. 258 //! 259 struct STATE_BASE_ADDRESS_CMD 260 { 261 union 262 { 263 struct 264 { 265 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 266 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 267 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 268 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 269 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 270 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 271 }; 272 uint32_t Value; 273 } DW0; 274 union 275 { 276 struct 277 { 278 uint64_t GeneralStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 279 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 280 uint64_t GeneralStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< General State Memory Object Control State 281 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 282 uint64_t GeneralStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< General State Base Address 283 }; 284 uint32_t Value[2]; 285 } DW1_2; 286 union 287 { 288 struct 289 { 290 uint32_t CoherencySettingModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< COHERENCY_SETTING_MODIFY_ENABLE 291 uint32_t Reserved97 : __CODEGEN_BITFIELD( 1, 12) ; //!< Reserved 292 uint32_t EnableMemoryCompressionForAllStatelessAccesses : __CODEGEN_BITFIELD(13, 13) ; //!< ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES 293 uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : __CODEGEN_BITFIELD(14, 14) ; //!< DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES 294 uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : __CODEGEN_BITFIELD(15, 15) ; //!< DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES 295 uint32_t StatelessDataPortAccessMemoryObjectControlState : __CODEGEN_BITFIELD(16, 22) ; //!< Stateless Data Port Access Memory Object Control State 296 uint32_t L1CachePolicy : __CODEGEN_BITFIELD(23, 25) ; //!< L1 Cache Policy for stateless accesses 297 uint32_t Reserved119 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 298 }; 299 uint32_t Value; 300 } DW3; 301 union 302 { 303 struct 304 { 305 uint64_t SurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 306 uint64_t Reserved129 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 307 uint64_t SurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Surface State Memory Object Control State 308 uint64_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 309 uint64_t SurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Surface State Base Address 310 }; 311 uint32_t Value[2]; 312 } DW4_5; 313 union 314 { 315 struct 316 { 317 uint64_t DynamicStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 318 uint64_t Reserved193 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 319 uint64_t DynamicStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Dynamic State Memory Object Control State 320 uint64_t Reserved203 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 321 uint64_t DynamicStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Dynamic State Base Address 322 }; 323 uint32_t Value[2]; 324 } DW6_7; 325 union 326 { 327 struct 328 { 329 uint64_t IndirectObjectBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 330 uint64_t Reserved257 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 331 uint64_t IndirectObjectMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Indirect Object Memory Object Control State 332 uint64_t Reserved267 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 333 uint64_t IndirectObjectBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Indirect Object Base Address 334 }; 335 uint32_t Value[2]; 336 } DW8_9; 337 union 338 { 339 struct 340 { 341 uint64_t InstructionBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 342 uint64_t Reserved321 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 343 uint64_t InstructionMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Instruction Memory Object Control State 344 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 345 uint64_t InstructionBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Instruction Base Address 346 }; 347 uint32_t Value[2]; 348 } DW10_11; 349 union 350 { 351 struct 352 { 353 uint32_t GeneralStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 354 uint32_t Reserved385 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 355 uint32_t GeneralStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< General State Buffer Size 356 }; 357 uint32_t Value; 358 } DW12; 359 union 360 { 361 struct 362 { 363 uint32_t DynamicStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 364 uint32_t Reserved417 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 365 uint32_t DynamicStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Dynamic State Buffer Size 366 }; 367 uint32_t Value; 368 } DW13; 369 union 370 { 371 struct 372 { 373 uint32_t IndirectObjectBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 374 uint32_t Reserved449 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 375 uint32_t IndirectObjectBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Indirect Object Buffer Size 376 }; 377 uint32_t Value; 378 } DW14; 379 union 380 { 381 struct 382 { 383 uint32_t InstructionBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 384 uint32_t Reserved481 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 385 uint32_t InstructionBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Instruction Buffer Size 386 }; 387 uint32_t Value; 388 } DW15; 389 union 390 { 391 struct 392 { 393 uint64_t BindlessSurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 394 uint64_t Reserved513 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 395 uint64_t BindlessSurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Surface State Memory Object Control State 396 uint64_t Reserved523 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 397 uint64_t BindlessSurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Surface State Base Address 398 }; 399 uint32_t Value[2]; 400 } DW16_17; 401 union 402 { 403 struct 404 { 405 uint32_t BindlessSurfaceStateSize ; //!< Bindless Surface State Size 406 }; 407 uint32_t Value; 408 } DW18; 409 union 410 { 411 struct 412 { 413 uint64_t BindlessSamplerStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 414 uint64_t Reserved609 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 415 uint64_t BindlessSamplerStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Sampler State Memory Object Control State 416 uint64_t Reserved619 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 417 uint64_t BindlessSamplerStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Sampler State Base Address 418 }; 419 uint32_t Value[2]; 420 } DW19_20; 421 union 422 { 423 struct 424 { 425 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 426 uint32_t BindlessSamplerStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Bindless Sampler State Buffer Size 427 }; 428 uint32_t Value; 429 } DW21; 430 431 //! \name Local enumerations 432 433 enum _3D_COMMAND_SUB_OPCODE 434 { 435 _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS = 1, //!< No additional details 436 }; 437 438 enum _3D_COMMAND_OPCODE 439 { 440 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 441 }; 442 443 enum COMMAND_SUBTYPE 444 { 445 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 446 }; 447 448 enum COMMAND_TYPE 449 { 450 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 451 }; 452 453 //! \brief GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 454 //! \details 455 //! The other fields in this DWord and the following DWord are updated 456 //! only when this bit is set. 457 enum GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 458 { 459 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 460 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 461 }; 462 463 //! \brief COHERENCY_SETTING_MODIFY_ENABLE 464 //! \details 465 //! All the fields in this DW is only updated when this bit is set. 466 enum COHERENCY_SETTING_MODIFY_ENABLE 467 { 468 COHERENCY_SETTING_MODIFY_ENABLE_DISABLEWRITETOTHISDW = 0, //!< No additional details 469 COHERENCY_SETTING_MODIFY_ENABLE_ENABLEWRITETOTHISDW = 1, //!< No additional details 470 }; 471 472 //! \brief ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES 473 //! \details 474 //! Enable compression for stateless memory accesses. 475 enum ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES 476 { 477 ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED = 0, //!< No additional details 478 ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_ENABLED = 1, //!< No additional details 479 }; 480 481 //! \brief DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES 482 //! \details 483 //! Specifies whether sequential consistency of atomic memory operations are 484 //! supported across multiple GPUs. 485 enum DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES 486 { 487 DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES_ENABLE = 0, //!< Atomic memory operations from all GPUs to the same address is sequentially consistent. 488 DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES_DISABLE = 1, //!< Disable multi-GPU Atomic consistency. Atomic memory operations to the same address is sequentially consistent only if the operations are from the same GPU. 489 }; 490 491 //! \brief DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES 492 //! \details 493 //! Specifies whether data-consistency on partial memory write operations 494 //! are supported across multiple GPUs. 495 enum DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES 496 { 497 DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES_ENABLED = 0, //!< Enable data consistency on multi-GPU partial memory writes. 498 DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES_DISABLED = 1, //!< Disable data consistency on multi-GPU partial memory writes. If multiple GPUs write different bytes of the same cacheline, the data may be corrupted. 499 }; 500 501 //! \brief SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 502 //! \details 503 //! The other fields in this DWord and the following DWord are updated only 504 //! when this bit is set. 505 enum SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 506 { 507 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 508 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 509 }; 510 511 //! \brief DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 512 //! \details 513 //! The other fields in this DWord and the following DWord are updated only 514 //! when this bit is set. 515 enum DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 516 { 517 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 518 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 519 }; 520 521 //! \brief INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 522 //! \details 523 //! The other fields in this DWord and the following DWord are updated 524 //! only when this bit is set. 525 enum INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 526 { 527 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 528 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 529 }; 530 531 //! \brief INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 532 //! \details 533 //! The other fields in this DWord and the following DWord are updated 534 //! only when this bit is set. 535 enum INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 536 { 537 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 538 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 539 }; 540 541 //! \brief GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 542 //! \details 543 //! The bound in this DWord is updated only when this bit is set. 544 enum GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 545 { 546 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 547 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 548 }; 549 550 //! \brief DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 551 //! \details 552 //! FormatDesc 553 enum DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 554 { 555 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 556 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 557 }; 558 559 //! \brief INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 560 //! \details 561 //! FormatDesc 562 enum INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 563 { 564 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 565 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 566 }; 567 568 //! \brief INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 569 //! \details 570 //! FormatDesc 571 enum INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 572 { 573 INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 574 }; 575 576 //! \brief BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 577 //! \details 578 //! The other fields in this DWord and the following two DWords are 579 //! updated only when this bit is set. 580 enum BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 581 { 582 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 583 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 584 }; 585 586 //! \brief BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 587 //! \details 588 //! The other fields in this DWord and the following two DWords are 589 //! updated only when this bit is set. 590 enum BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 591 { 592 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 593 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 594 }; 595 596 //! \name Initializations 597 598 //! \brief Explicit member initialization function 599 STATE_BASE_ADDRESS_CMD(); 600 601 static const size_t dwSize = 22; 602 static const size_t byteSize = 88; 603 }; 604 605 //! 606 //! \brief _3DSTATE_CHROMA_KEY 607 //! \details 608 //! The 3DSTATE_CHROMA_KEY instruction is used to program texture 609 //! color/chroma-key key values. A table containing four set of values is 610 //! supported. The ChromaKey Index sampler state variable is used to select 611 //! which table entry is associated with the map. Texture chromakey 612 //! functions are enabled and controlled via use of the ChromaKey Enable 613 //! texture sampler state variable.Texture Color Key (keying on a paletted 614 //! texture index) is not supported. 615 //! 616 struct _3DSTATE_CHROMA_KEY_CMD 617 { 618 union 619 { 620 struct 621 { 622 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 623 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 624 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 625 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 626 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 627 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 628 }; 629 uint32_t Value; 630 } DW0; 631 union 632 { 633 struct 634 { 635 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 636 uint32_t ChromakeyTableIndex : __CODEGEN_BITFIELD(30, 31) ; //!< ChromaKey Table Index 637 }; 638 uint32_t Value; 639 } DW1; 640 union 641 { 642 struct 643 { 644 uint32_t ChromakeyLowValue ; //!< ChromaKey Low Value 645 }; 646 uint32_t Value; 647 } DW2; 648 union 649 { 650 struct 651 { 652 uint32_t ChromakeyHighValue ; //!< ChromaKey High Value 653 }; 654 uint32_t Value; 655 } DW3; 656 657 //! \name Local enumerations 658 659 enum _3D_COMMAND_SUB_OPCODE 660 { 661 _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY = 4, //!< No additional details 662 }; 663 664 enum _3D_COMMAND_OPCODE 665 { 666 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 667 }; 668 669 enum COMMAND_SUBTYPE 670 { 671 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 672 }; 673 674 enum COMMAND_TYPE 675 { 676 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 677 }; 678 679 //! \name Initializations 680 681 //! \brief Explicit member initialization function 682 _3DSTATE_CHROMA_KEY_CMD(); 683 684 static const size_t dwSize = 4; 685 static const size_t byteSize = 16; 686 }; 687 688 //! 689 //! \brief PALETTE_ENTRY 690 //! \details 691 //! 692 //! 693 struct PALETTE_ENTRY_CMD 694 { 695 union 696 { 697 struct 698 { 699 uint32_t Blue : __CODEGEN_BITFIELD( 0, 7) ; //!< Blue 700 uint32_t Green : __CODEGEN_BITFIELD( 8, 15) ; //!< Green 701 uint32_t Red : __CODEGEN_BITFIELD(16, 23) ; //!< Red 702 uint32_t Alpha : __CODEGEN_BITFIELD(24, 31) ; //!< Alpha 703 }; 704 uint32_t Value; 705 } DW0; 706 707 //! \name Local enumerations 708 709 //! \name Initializations 710 711 //! \brief Explicit member initialization function 712 PALETTE_ENTRY_CMD(); 713 714 static const size_t dwSize = 1; 715 static const size_t byteSize = 4; 716 }; 717 718 //! 719 //! \brief STATE_SIP 720 //! \details 721 //! The STATE_SIP command specifies the starting instruction location of the 722 //! System Routine that is shared by all threads in execution. 723 //! 724 struct STATE_SIP_CMD 725 { 726 union 727 { 728 struct 729 { 730 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 731 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 732 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 733 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 734 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 735 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 736 }; 737 uint32_t Value; 738 } DW0; 739 union 740 { 741 struct 742 { 743 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 744 uint64_t SystemInstructionPointer : __CODEGEN_BITFIELD( 4, 63) ; //!< System Instruction Pointer 745 }; 746 uint32_t Value[2]; 747 } DW1_2; 748 749 //! \name Local enumerations 750 751 enum _3D_COMMAND_SUB_OPCODE 752 { 753 _3D_COMMAND_SUB_OPCODE_STATESIP = 2, //!< No additional details 754 }; 755 756 enum _3D_COMMAND_OPCODE 757 { 758 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 759 }; 760 761 enum COMMAND_SUBTYPE 762 { 763 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 764 }; 765 766 enum COMMAND_TYPE 767 { 768 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 769 }; 770 771 //! \name Initializations 772 773 //! \brief Explicit member initialization function 774 STATE_SIP_CMD(); 775 776 static const size_t dwSize = 3; 777 static const size_t byteSize = 12; 778 }; 779 780 //! 781 //! \brief GPGPU_CSR_BASE_ADDRESS 782 //! \details 783 //! The GPGPU_CSR_BASE_ADDRESS command sets the base pointers for EU and L3 784 //! to Context Save and Restore EU State and SLM for GPGPU mid-thread 785 //! preemption. 786 //! 787 //! Execution of this command causes a full pipeline flush, thus its use 788 //! should be minimized for higher performance. State and instruction caches 789 //! are flushed on completion of the flush. 790 //! 791 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 792 //! Cache Flush Enable" set prior to programming GPGPU_CSR_BASE_ADDRESS 793 //! command for GPGPU workloads i.e when pipeline select is GPGPU via 794 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 795 //! preemption latencies for certain programming sequences. If programming 796 //! PIPE_CONTROL has performance implications then preemption latencies can 797 //! be trade off against performance by not implementing this programming 798 //! note. 799 //! 800 struct GPGPU_CSR_BASE_ADDRESS_CMD 801 { 802 union 803 { 804 struct 805 { 806 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 807 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 808 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 809 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 810 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 811 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 812 }; 813 uint32_t Value; 814 } DW0; 815 union 816 { 817 struct 818 { 819 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 820 uint64_t GpgpuCsrBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< GPGPU CSR Base Address 821 }; 822 uint32_t Value[2]; 823 } DW1_2; 824 825 //! \name Local enumerations 826 827 enum _3D_COMMAND_SUB_OPCODE 828 { 829 _3D_COMMAND_SUB_OPCODE_GPGPUCSRBASEADDRESS = 4, //!< No additional details 830 }; 831 832 enum _3D_COMMAND_OPCODE 833 { 834 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 835 }; 836 837 enum COMMAND_SUBTYPE 838 { 839 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 840 }; 841 842 enum COMMAND_TYPE 843 { 844 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 845 }; 846 847 //! \name Initializations 848 849 //! \brief Explicit member initialization function 850 GPGPU_CSR_BASE_ADDRESS_CMD(); 851 852 static const size_t dwSize = 3; 853 static const size_t byteSize = 12; 854 }; 855 856 //! 857 //! \brief _3DSTATE_BINDING_TABLE_POOL_ALLOC 858 //! \details 859 //! This command is to program the base address and size of the binding 860 //! table pool. The address to fetch the binding table is based on the 861 //! Binding Table Pool Base Address and the binding table pointer if the 862 //! Binding Table Pool is enabled. Otherwise the binding table pointer is an 863 //! offset from the Surface Base Address. 864 //! 865 struct _3DSTATE_BINDING_TABLE_POOL_ALLOC_CMD 866 { 867 union 868 { 869 struct 870 { 871 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 872 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 873 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 874 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 875 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 876 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 877 }; 878 uint32_t Value; 879 } DW0; 880 union 881 { 882 struct 883 { 884 uint64_t SurfaceObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Surface Object Control State 885 uint64_t Reserved39 : __CODEGEN_BITFIELD( 7, 11) ; //!< Reserved 886 uint64_t BindingTablePoolBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Binding Table Pool Base Address 887 }; 888 uint32_t Value[2]; 889 } DW1_2; 890 union 891 { 892 struct 893 { 894 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 895 uint32_t BindingTablePoolBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< BINDING_TABLE_POOL_BUFFER_SIZE 896 }; 897 uint32_t Value; 898 } DW3; 899 900 //! \name Local enumerations 901 902 enum _3D_COMMAND_SUB_OPCODE 903 { 904 _3D_COMMAND_SUB_OPCODE_3DSTATEBINDINGTABLEPOOLALLOC = 25, //!< No additional details 905 }; 906 907 enum _3D_COMMAND_OPCODE 908 { 909 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 910 }; 911 912 enum COMMAND_SUBTYPE 913 { 914 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 915 }; 916 917 enum COMMAND_TYPE 918 { 919 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 920 }; 921 922 //! \brief BINDING_TABLE_POOL_BUFFER_SIZE 923 //! \details 924 //! This field specifies the size of the buffer in 4K pages. Any access 925 //! which straddle or go past the end of the buffer will return 0. 926 enum BINDING_TABLE_POOL_BUFFER_SIZE 927 { 928 BINDING_TABLE_POOL_BUFFER_SIZE_NOVALIDDATA = 0, //!< There is no valid data in the buffer 929 }; 930 931 //! \name Initializations 932 933 //! \brief Explicit member initialization function 934 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CMD(); 935 936 static const size_t dwSize = 4; 937 static const size_t byteSize = 16; 938 }; 939 940 //! 941 //! \brief CFE_STATE 942 //! \details 943 //! 944 //! 945 struct CFE_STATE_CMD 946 { 947 union 948 { 949 //!< DWORD 0 950 struct 951 { 952 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7) ; //!< DWord Length 953 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15) ; //!< Reserved 954 uint32_t CFESubOpcodeVariant : __CODEGEN_BITFIELD(16, 17) ; //!< CFE SubOpcode Variant 955 uint32_t CFESubOpcode : __CODEGEN_BITFIELD(18, 23) ; //!< CFE SubOpcode 956 uint32_t ComputeCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< Compute Command Opcode 957 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< Pipeline 958 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< Command Type 959 }; 960 uint32_t Value = 0; 961 } DW0; 962 union 963 { 964 //!< DWORD 1_2 965 struct 966 { 967 uint64_t Reserved32 : __CODEGEN_BITFIELD(0, 9) ; //!< Reserved 968 uint64_t ScratchSpaceBuffer : __CODEGEN_BITFIELD(10, 31) ; //!< Scratch Space Base Pointer 969 uint64_t Reserved64 : __CODEGEN_BITFIELD(32, 63) ; //!< Reserved 970 }; 971 uint64_t Value = 0; 972 } DW1_2; 973 union 974 { 975 //!< DWORD 3 976 struct 977 { 978 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 979 uint32_t NumberOfWalkers : __CODEGEN_BITFIELD( 3, 5) ; //!< Number Of Walkers 980 uint32_t FusedEuDispatch : __CODEGEN_BITFIELD( 6, 6) ; //!< Fused EU Dispatch 981 uint32_t Reserved103 : __CODEGEN_BITFIELD( 7, 12) ; //!< Reserved 982 uint32_t SingleSliceDispatchCcsMode : __CODEGEN_BITFIELD(13, 13) ; //!< Single Slice Dispatch CCS Mode 983 uint32_t OverDispatchControl : __CODEGEN_BITFIELD(14, 15) ; //!< Over Dispatch Control 984 uint32_t MaximumNumberOfThreads : __CODEGEN_BITFIELD(16, 31) ; //!< Maximum Number of Threads 985 }; 986 uint32_t Value = 0; 987 } DW3; 988 union 989 { 990 //!< DWORD 4 991 struct 992 { 993 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 994 uint32_t StopAndDrainTimer : __CODEGEN_BITFIELD(24, 30) ; //!< Stop And Drain Timer 995 uint32_t StopAndDrainTimerEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Stop And Drain Timer Enable 996 }; 997 uint32_t Value = 0; 998 } DW4; 999 union 1000 { 1001 //!< DWORD 5 1002 struct 1003 { 1004 uint32_t DebugCounterControl : __CODEGEN_BITFIELD( 0, 1) ; //!< Debug Counter Control 1005 uint32_t Reserved162 : __CODEGEN_BITFIELD( 2, 7) ; //!< Reserved 1006 uint32_t DebugObjectID : __CODEGEN_BITFIELD( 8, 31) ; //!< Debug Object ID 1007 }; 1008 uint32_t Value = 0; 1009 } DW5; 1010 1011 //! \name Local enumerations 1012 enum PIPELINE 1013 { 1014 PIPELINE_COMPUTE = 2, //!< No additional details 1015 }; 1016 1017 enum COMMAND_TYPE 1018 { 1019 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1020 }; 1021 1022 enum COMPUTE_COMMAND_OPCODE 1023 { 1024 COMPUTE_COMMAND_OPCODE_CFE_COMMAND = 2, //!< No additional details 1025 }; 1026 1027 enum OVER_DISPATCH_CONTROL 1028 { 1029 VER_DISPATCH_CONTROL_NONE = 0, //!< 0% overdispatch 1030 VER_DISPATCH_CONTROL_LOW = 1, //!< 25% overdispatch 1031 VER_DISPATCH_CONTROL_NORMAL = 2, //!< 50% overdispatch 1032 VER_DISPATCH_CONTROL_HIGH = 3, //!< 75% overdispatch 1033 }; 1034 1035 enum SINGLE_SLICE_DISPATCH_CCS_MODE 1036 { 1037 SINGLE_SLICE_DISPATCH_CCS_MODE_DISABLE = 0, //!< No additional details 1038 SINGLE_SLICE_DISPATCH_CCS_MODE_ENABLE = 1, //!< No additional details 1039 }; 1040 1041 enum FUSED_EU_DISPATCH 1042 { 1043 FUSED_EU_DISPATCH_LEGACY_MODE = 1, //!< Legacy Mode, threads are not fused 1044 FUSED_EU_DISPATCH_FUSED_EU_MODE = 0, //!< Fused EU Mode 1045 }; 1046 1047 //! \name Initializations 1048 1049 //! \brief Explicit member initialization function 1050 CFE_STATE_CMD(); 1051 1052 static const size_t dwSize = 6; 1053 static const size_t byteSize = 24; 1054 1055 }; 1056 1057 //! 1058 //! \brief COMPUTE_WALKER for GEN12 HP 1059 //! \details COMPUTE_WALKER spawns threadgroups in 1, 2, or 3 dimensions (X, Y, Z). 1060 //! Each threadgroup is described by Interface Descriptor in this command. 1061 //! Each dispatched thread has a standard payload delivered in R0 and R1, 1062 //! including the Indirect Address to fetch the thread's parameters. 1063 //! After the Walker completes dispatching its threads and those threads have 1064 //! completed running, a PostSync operation can write a completion code or a 1065 //! timestamp. 1066 //! 1067 struct COMPUTE_WALKER_CMD 1068 { 1069 union 1070 { 1071 //!< DWORD 0 1072 struct 1073 { 1074 uint32_t DWordLength : __CODEGEN_BITFIELD(0, 7) ; //!< DWord Length 1075 uint32_t PredicateEnable : __CODEGEN_BITFIELD(8, 8) ; //!< Predicate Enable 1076 uint32_t WorkloadPartitionEnable : __CODEGEN_BITFIELD(9, 9) ; //!< Workload Partition Enable 1077 uint32_t IndirectParameterEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Indirect Parameter Enable 1078 uint32_t UAVWaitToProduce : __CODEGEN_BITFIELD(11, 11) ; //!< UAV Wait to Produce 1079 uint32_t UAVProducer : __CODEGEN_BITFIELD(12, 12) ; //!< UAV Producer 1080 uint32_t UAVConsumer : __CODEGEN_BITFIELD(13, 13) ; //!< UAV Consumer 1081 uint32_t SystolicModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< Systolic Mode Enable 1082 uint32_t Reserved : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1083 uint32_t CFESubOpcodeVariant : __CODEGEN_BITFIELD(16, 17) ; //!< CFE SubOpcode Variant 1084 uint32_t CFESubOpcode : __CODEGEN_BITFIELD(18, 23) ; //!< CFE SubOpcode 1085 uint32_t ComputeCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< Compute Command Opcode 1086 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< Pipeline 1087 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< Command Type 1088 }; 1089 uint32_t Value = 0; 1090 } DW0; 1091 union 1092 { 1093 //!< DWORD 1 1094 struct 1095 { 1096 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 7) ; //!< Reserved 1097 uint32_t DebugObjectID : __CODEGEN_BITFIELD(8, 31) ; //!< Debug Object ID 1098 }; 1099 uint32_t Value = 0; 1100 } DW1; 1101 union 1102 { 1103 //!< DWORD 2 1104 struct 1105 { 1106 uint32_t IndirectDataLength : __CODEGEN_BITFIELD(0, 16) ; //!< Indirect Data Length 1107 uint32_t L3PrefetchDisable : __CODEGEN_BITFIELD(17, 17) ; //!< L3 prefetch disable 1108 uint32_t PartitionDispatchParameter : __CODEGEN_BITFIELD(18, 29) ; //!< Partition Dispatch Parameter 1109 uint32_t PartitionType : __CODEGEN_BITFIELD(30, 31) ; //!< PartitionType 1110 }; 1111 uint32_t Value = 0; 1112 } DW2; 1113 union 1114 { 1115 //!< DWORD 3 1116 struct 1117 { 1118 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 5) ; //!< Reserved 1119 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(6, 31) ; //!< Indirect Data Start Address 1120 }; 1121 uint32_t Value = 0; 1122 } DW3; 1123 union 1124 { 1125 //!< DWORD 4 1126 struct 1127 { 1128 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 16) ; //!< Reserved 1129 uint32_t MessageSIMD : __CODEGEN_BITFIELD(17, 18) ; //!< Message SIMD 1130 uint32_t TileLayout : __CODEGEN_BITFIELD(19, 21) ; //!< Tile Layout 1131 uint32_t WalkOrder : __CODEGEN_BITFIELD(22, 24) ; //!< Walk Order 1132 uint32_t EmitInlineParameter : __CODEGEN_BITFIELD(25, 25) ; //!< Emit Inline Parameter 1133 uint32_t EmitLocal : __CODEGEN_BITFIELD(26, 28) ; //!< Emit Local 1134 uint32_t GenerateLocalID : __CODEGEN_BITFIELD(29, 29) ; //!< Generate Local ID 1135 uint32_t SIMDSize : __CODEGEN_BITFIELD(30, 31) ; //!< SIMD Size 1136 }; 1137 uint32_t Value = 0; 1138 } DW4; 1139 union 1140 { 1141 //!< DWORD 5 1142 struct 1143 { 1144 uint32_t ExecutionMask : __CODEGEN_BITFIELD(0, 31) ; //!< Execution Mask 1145 }; 1146 uint32_t Value = 0; 1147 } DW5; 1148 union 1149 { 1150 //!< DWORD 6 1151 struct 1152 { 1153 uint32_t LocalXMaximum : __CODEGEN_BITFIELD(0, 9) ; //!< Local X Maximum 1154 uint32_t LocalYMaximum : __CODEGEN_BITFIELD(10, 19) ; //!< Local Y Maximum 1155 uint32_t LocalZMaximum : __CODEGEN_BITFIELD(20, 29) ; //!< Local Z Maximum 1156 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1157 }; 1158 uint32_t Value = 0; 1159 } DW6; 1160 union 1161 { 1162 //!< DWORD 7 1163 struct 1164 { 1165 uint32_t ThreadGroupIDXDimension : __CODEGEN_BITFIELD(0, 31) ; //!< Thread Group ID X Dimension 1166 }; 1167 uint32_t Value = 0; 1168 } DW7; 1169 union 1170 { 1171 //!< DWORD 8 1172 struct 1173 { 1174 uint32_t ThreadGroupIDYDimension : __CODEGEN_BITFIELD(0, 31) ; //!< Thread Group ID Y Dimension 1175 }; 1176 uint32_t Value = 0; 1177 } DW8; 1178 union 1179 { 1180 //!< DWORD 9 1181 struct 1182 { 1183 uint32_t ThreadGroupIDZDimension : __CODEGEN_BITFIELD(0, 31) ; //!< Thread Group ID Z Dimension 1184 }; 1185 uint32_t Value = 0; 1186 } DW9; 1187 union 1188 { 1189 //!< DWORD 10 1190 struct 1191 { 1192 uint32_t ThreadGroupIDStartingX : __CODEGEN_BITFIELD(0, 31) ; //!< Thread Group ID Starting X 1193 }; 1194 uint32_t Value = 0; 1195 } DW10; 1196 union 1197 { 1198 //!< DWORD 11 1199 struct 1200 { 1201 uint32_t ThreadGroupIDStartingY : __CODEGEN_BITFIELD(0, 31) ; //!< Thread Group ID Starting Y 1202 }; 1203 uint32_t Value = 0; 1204 } DW11; 1205 union 1206 { 1207 //!< DWORD 12 1208 struct 1209 { 1210 uint32_t ThreadGroupIDStartingZ : __CODEGEN_BITFIELD(0, 31) ; //!< Thread Group ID Starting Z 1211 }; 1212 uint32_t Value = 0; 1213 } DW12; 1214 union 1215 { 1216 //!< DWORD 13_14 1217 struct 1218 { 1219 uint64_t PartitionID : __CODEGEN_BITFIELD(0, 31) ; //!< Partition ID 1220 uint64_t PartitionSize : __CODEGEN_BITFIELD(32, 63) ; //!< Partition Size 1221 }; 1222 uint64_t Value = 0; 1223 } DW13_14; 1224 1225 union 1226 { 1227 struct 1228 { 1229 uint32_t PreemptX; 1230 }; 1231 uint32_t Value = 0; 1232 } DW15; 1233 1234 union 1235 { 1236 struct 1237 { 1238 uint32_t PreemptY; 1239 }; 1240 uint32_t Value = 0; 1241 } DW16; 1242 1243 union 1244 { 1245 struct 1246 { 1247 uint32_t PreemptZ; 1248 }; 1249 uint32_t Value = 0; 1250 } DW17; 1251 1252 //! 1253 //! \brief INTERFACE_DESCRIPTOR_DATA for Gen12 HP 1254 //! \details The Interface Descriptor describes the thread state common for all threads 1255 //! in the dispatch, including the Kernel base address, the binding tables, 1256 //! threadgroup size, and SLM size. 1257 //! 1258 struct INTERFACE_DESCRIPTOR_DATA_G12HP_CMD 1259 { 1260 union 1261 { 1262 //!< DWORD 0_1 1263 struct 1264 { 1265 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 5) ; //!< Reserved 1266 uint64_t KernelStartPointer : __CODEGEN_BITFIELD(6, 31) ; //!< Kernel Start Pointer 1267 uint64_t Reserved32 : __CODEGEN_BITFIELD(32, 63) ; //!< Reserved 1268 }; 1269 uint32_t Value[2] = { 0 }; 1270 } DW0_1; 1271 union 1272 { 1273 //!< DWORD 2 1274 struct 1275 { 1276 uint32_t Reserved64 : __CODEGEN_BITFIELD(0, 6) ; //!< Reserved 1277 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD(7, 7) ; //!< Software Exception Enable 1278 uint32_t Reserved72 : __CODEGEN_BITFIELD(8, 10) ; //!< Reserved 1279 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 1280 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 1281 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 1282 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1283 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< Floating Point Mode 1284 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 17) ; //!< Reserved 1285 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< Single Program Flow 1286 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< Denorm Mode 1287 uint32_t ThreadPreemptionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< Thread Preemption Disable 1288 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 1289 }; 1290 uint32_t Value = 0; 1291 } DW2; 1292 union 1293 { 1294 //!< DWORD 3 1295 struct 1296 { 1297 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 1) ; //!< Reserved 1298 uint32_t SamplerCount : __CODEGEN_BITFIELD(2, 4) ; //!< Sampler Count 1299 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD(5, 31) ; //!< Sampler State Pointer 1300 }; 1301 uint32_t Value = 0; 1302 } DW3; 1303 union 1304 { 1305 //!< DWORD 4 1306 struct 1307 { 1308 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD(0, 4) ; //!< Binding Table Entry Count 1309 uint32_t BindingTablePointer : __CODEGEN_BITFIELD(5, 20) ; //!< Binding Table Pointer 1310 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 1311 }; 1312 uint32_t Value = 0; 1313 } DW4; 1314 union 1315 { 1316 //!< DWORD 5 1317 struct 1318 { 1319 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD(0, 9) ; //!< Number of Threads in GPGPU Thread Group 1320 uint32_t Reserved170 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1321 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< Shared Local Memory Size 1322 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Barrier Enable 1323 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< Rounding Mode 1324 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 1325 uint32_t ThreadGroupDispatchSize : __CODEGEN_BITFIELD(26, 27) ; //!< Thread group dispatch size 1326 uint32_t Reserved188 : __CODEGEN_BITFIELD(28, 30) ; //!< Reserved 1327 uint32_t BTDMode : __CODEGEN_BITFIELD(31, 31) ; //!< BTD mode 1328 }; 1329 uint32_t Value = 0; 1330 } DW5; 1331 union 1332 { 1333 //!< DWORD 6_7 1334 struct 1335 { 1336 uint64_t Reserved192 : __CODEGEN_BITFIELD(0, 63) ; //!< Reserved 1337 }; 1338 uint64_t Value = 0; 1339 } DW6_7; 1340 1341 //! \name Initializations 1342 1343 //! \brief Explicit member initialization function 1344 INTERFACE_DESCRIPTOR_DATA_G12HP_CMD(); 1345 1346 static const size_t dwSize = 8; 1347 static const size_t byteSize = 32; 1348 } interface_descriptor_data; 1349 1350 //! 1351 //! \brief POSTSYNC_DATA_CMD 1352 //! \detail Post Sync command payload includes the operation, the address, a MOCS field, and an Immediate Data Value. 1353 //! 1354 struct POSTSYNC_DATA_CMD 1355 { 1356 union 1357 { 1358 //!< DWORD 0 1359 struct 1360 { 1361 uint32_t Operation : __CODEGEN_BITFIELD(0, 1) ; //!< Operation 1362 uint32_t HDCPipelineFlush : __CODEGEN_BITFIELD(2, 2) ; //!< HDC Pipeline Flush 1363 uint32_t L3Flush : __CODEGEN_BITFIELD(3, 3) ; //!< Reserved 1364 uint32_t MOCS : __CODEGEN_BITFIELD(4, 10) ; //!< MOCS 1365 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 1366 }; 1367 uint32_t Value = 0; 1368 } DW0; 1369 union 1370 { 1371 //!< DWORD 1_2 1372 struct 1373 { 1374 uint64_t DestinationAddress : __CODEGEN_BITFIELD(0, 63) ; //!< Destination Address 1375 }; 1376 uint32_t Value[2] = { 0 }; 1377 } DW1_2; 1378 union 1379 { 1380 //!< DWORD 3_4 1381 struct 1382 { 1383 uint64_t ImmediateData : __CODEGEN_BITFIELD(0, 63) ; //!< Immediate Data 1384 }; 1385 uint64_t Value = 0; 1386 } DW3_4; 1387 1388 //! \name local enumerations. 1389 enum POSTSYNC_OPERATION 1390 { 1391 POSTSYNC_OPERATION_NO_WRITE = 0, //!< The destination address and immediate data fields are ignored. 1392 POSTSYNC_OPERATION_WRITE_IMMEDIATE_DATA = 1, //!< Writes 8 bytes (64 bits) of immediate data to the destination address. 1393 POSTSYNC_OPERATION_WRITE_TIMESTAMP = 3, //!< Writes 16 bytes (128 bits) of timestamp data to the destination address. 1394 }; 1395 1396 //! \brief Explicit member initialization function 1397 POSTSYNC_DATA_CMD(); 1398 1399 static const size_t dwSize = 5; 1400 static const size_t byteSize = 20; 1401 } postsync_data; 1402 1403 struct INLINE_DATA_CMD 1404 { 1405 uint32_t Value[8] = {0}; 1406 1407 //! \brief Explicit member initialization function INLINE_DATA_CMDCOMPUTE_WALKER_CMD::INLINE_DATA_CMD1408 INLINE_DATA_CMD() {} 1409 static const size_t dwSize = 8; 1410 static const size_t byteSize = 32; 1411 } inline_data; 1412 1413 //! \name Local enumerations 1414 enum PIPELINE 1415 { 1416 PIPELINE_COMPUTE = 2, //!< No additional details 1417 }; 1418 1419 enum COMMAND_TYPE 1420 { 1421 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1422 }; 1423 1424 enum CFE_SUBOPCODE 1425 { 1426 CFE_SUBOPCODE_COMPUTE_WALKER = 2, //!< No additional details 1427 }; 1428 1429 enum COMPUTE_COMMAND_OPCODE 1430 { 1431 COMPUTE_COMMAND_OPCODE_CFE_COMMAND = 2, //!< No additional details 1432 }; 1433 1434 enum CFE_SUBOPCODE_VARIANT 1435 { 1436 CFE_SUBOPCODE_VARIANT_STANDARD = 0, //!< No additional details 1437 CFE_SUBOPCODE_VARIANT_RESUME = 1, //!< Resumption of GPGPU_WALKER command, recorded in context image to continue execution after preemption. 1438 }; 1439 1440 //! \brief SIMD_SIZE 1441 //! \details This field determines the size of the payload and the number of bits of 1442 //! the execution mask that are expected. The kernel pointed to by the 1443 //! interface descriptor should match the SIMD declared here. 1444 enum SIMD_SIZE 1445 { 1446 SIMD_SIZE_SIMD8 = 0, //!< 8 LSBs of the execution mask are used 1447 SIMD_SIZE_SIMD16 = 1, //!< 16 LSBs used in execution mask 1448 SIMD_SIZE_SIMD32 = 2, //!< 32 bits of execution mask used 1449 }; 1450 1451 enum WALKER_ORDER 1452 { 1453 WALKER_ORDER_WALK012 = 0, //!< Normal Linear walk order 1454 WALKER_ORDER_WALK021 = 1, //!< No additional details 1455 WALKER_ORDER_WALK102 = 2, //!< Normal TileY walk order 1456 WALKER_ORDER_WALK120 = 3, //!< No additional details 1457 WALKER_ORDER_WALK201 = 4, //!< No additional details 1458 WALKER_ORDER_WALK210 = 5, //!< No additional details 1459 }; 1460 1461 //! \name Initializations 1462 1463 //! \brief Explicit member initialization function 1464 COMPUTE_WALKER_CMD(); 1465 1466 static const size_t dwSize = 39; 1467 static const size_t byteSize = 156; 1468 }; 1469 1470 //! 1471 //! \brief STATE_COMPUTE_MODE command, a general compute programming state shared in the 1472 //! pipeline. 1473 //! 1474 struct STATE_COMPUTE_MODE_CMD 1475 { 1476 union 1477 { 1478 struct 1479 { 1480 uint32_t DwordLength: __CODEGEN_BITFIELD(0, 7); 1481 uint32_t Reserved8: __CODEGEN_BITFIELD(8, 15); 1482 uint32_t CommandSubOpcode: __CODEGEN_BITFIELD(16, 23); 1483 uint32_t CommandOpcode: __CODEGEN_BITFIELD(24, 26); 1484 uint32_t CommandSubType: __CODEGEN_BITFIELD(27, 28); 1485 uint32_t CommandType: __CODEGEN_BITFIELD(29, 31); 1486 }; 1487 uint32_t Value = 0; 1488 } DW0; 1489 1490 union 1491 { 1492 struct 1493 { 1494 uint32_t DisableSupportForMultiGpuFence: __CODEGEN_BITFIELD(0, 0); 1495 uint32_t DisableSupportForMultiGpuAtomics: 1496 __CODEGEN_BITFIELD(1, 1); 1497 1498 uint32_t DisableSupportMultiGpuPartialWrites: 1499 __CODEGEN_BITFIELD(2, 2); 1500 1501 uint32_t ForceNonCoherent: __CODEGEN_BITFIELD(3, 4); 1502 uint32_t FastClearDisabledOnCompressedSurface: 1503 __CODEGEN_BITFIELD(5, 5); 1504 1505 uint32_t DisableSlmReadMergeOptimization: 1506 __CODEGEN_BITFIELD(6, 6); 1507 1508 uint32_t AsyncComputeThreadLimit: __CODEGEN_BITFIELD(7, 9); 1509 uint32_t BindingTableAlignment: __CODEGEN_BITFIELD(10, 10); 1510 uint32_t DisableAtomicOnClearData: __CODEGEN_BITFIELD(11, 11); 1511 uint32_t CoherentAccessL1CacheDisable: 1512 __CODEGEN_BITFIELD(12, 12); 1513 1514 uint32_t DisableL1InvalidateForNonL1CacheableWrites: 1515 __CODEGEN_BITFIELD(13, 13); 1516 1517 uint32_t Reserved46: __CODEGEN_BITFIELD(14, 14); 1518 uint32_t LargeGrfMode: __CODEGEN_BITFIELD(15, 15); 1519 uint32_t MaskBits: __CODEGEN_BITFIELD(16, 31); 1520 }; 1521 uint32_t Value = 0; 1522 } DW1; 1523 1524 STATE_COMPUTE_MODE_CMD(); 1525 1526 static const size_t dwSize = 2; 1527 static const size_t byteSize = 8; 1528 static const uint32_t GFXPIPE = 3; 1529 static const uint32_t GFXPIPE_COMMON = 0; 1530 static const uint32_t GFXPIPE_NONPIPELINED = 1; 1531 static const uint32_t STATE_COMPUTE_MODE = 5; 1532 }; 1533 }; 1534 1535 #pragma pack() 1536 1537 #endif // __MHW_RENDER_HWCMD_XE_HP_BASE_H__ 1538