1 /* 2 * Copyright (c) 2015-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_state_heap_hwcmd_g12_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g12_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 29 // DO NOT EDIT 30 31 #ifndef __MHW_STATE_HEAP_HWCMD_G12_X_H__ 32 #define __MHW_STATE_HEAP_HWCMD_G12_X_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include <cstdint> 38 #include <cstddef> 39 40 class mhw_state_heap_g12_X 41 { 42 public: 43 // Internal Macros 44 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 45 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 46 #define __CODEGEN_OP_LENGTH_BIAS 2 47 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 48 GetOpLength(uint32_t uiLength)49 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 50 51 //! 52 //! \brief INTERFACE_DESCRIPTOR_DATA 53 //! \details 54 //! 55 //! 56 struct INTERFACE_DESCRIPTOR_DATA_CMD 57 { 58 union 59 { 60 struct 61 { 62 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 63 uint32_t KernelStartPointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Kernel Start Pointer 64 }; 65 uint32_t Value; 66 } DW0; 67 union 68 { 69 struct 70 { 71 uint32_t KernelStartPointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Kernel Start Pointer High 72 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 73 }; 74 uint32_t Value; 75 } DW1; 76 union 77 { 78 struct 79 { 80 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 81 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Software Exception Enable 82 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 10) ; //!< Reserved 83 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 84 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 85 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 86 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 87 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< FLOATING_POINT_MODE 88 uint32_t ThreadPriority : __CODEGEN_BITFIELD(17, 17) ; //!< THREAD_PRIORITY 89 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< SINGLE_PROGRAM_FLOW 90 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< DENORM_MODE 91 uint32_t ThreadPreemptionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< THREAD_PREEMPTION_DISABLE 92 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW2; 96 union 97 { 98 struct 99 { 100 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 101 uint32_t SamplerCount : __CODEGEN_BITFIELD( 2, 4) ; //!< SAMPLER_COUNT 102 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD( 5, 31) ; //!< Sampler State Pointer 103 }; 104 uint32_t Value; 105 } DW3; 106 union 107 { 108 struct 109 { 110 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD( 0, 4) ; //!< Binding Table Entry Count 111 uint32_t BindingTablePointer : __CODEGEN_BITFIELD( 5, 20) ; //!< Binding Table Pointer 112 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 113 }; 114 uint32_t Value; 115 } DW4; 116 union 117 { 118 struct 119 { 120 uint32_t ConstantUrbEntryReadOffset : __CODEGEN_BITFIELD( 0, 15) ; //!< Constant URB Entry Read Offset 121 uint32_t ConstantIndirectUrbEntryReadLength : __CODEGEN_BITFIELD(16, 31) ; //!< Constant/Indirect URB Entry Read Length 122 }; 123 uint32_t Value; 124 } DW5; 125 union 126 { 127 struct 128 { 129 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD( 0, 9) ; //!< Number of Threads in GPGPU Thread Group 130 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 12) ; //!< Reserved 131 uint32_t OverDispatchControl : __CODEGEN_BITFIELD(13, 14) ; //!< OVER_DISPATCH_CONTROL 132 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 133 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< SHARED_LOCAL_MEMORY_SIZE 134 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Barrier Enable 135 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< ROUNDING_MODE 136 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 137 }; 138 uint32_t Value; 139 } DW6; 140 union 141 { 142 struct 143 { 144 uint32_t CrossThreadConstantDataReadLength : __CODEGEN_BITFIELD( 0, 7) ; //!< Cross-Thread Constant Data Read Length 145 uint32_t Reserved232 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 146 }; 147 uint32_t Value; 148 } DW7; 149 150 //! \name Local enumerations 151 152 //! \brief FLOATING_POINT_MODE 153 //! \details 154 //! Specifies the floating point mode used by the dispatched thread. 155 enum FLOATING_POINT_MODE 156 { 157 FLOATING_POINT_MODE_IEEE_754 = 0, //!< No additional details 158 FLOATING_POINT_MODE_ALTERNATE = 1, //!< No additional details 159 }; 160 161 //! \brief THREAD_PRIORITY 162 //! \details 163 //! Specifies the priority of the thread for dispatch. 164 enum THREAD_PRIORITY 165 { 166 THREAD_PRIORITY_NORMALPRIORITY = 0, //!< No additional details 167 THREAD_PRIORITY_HIGHPRIORITY = 1, //!< No additional details 168 }; 169 170 //! \brief SINGLE_PROGRAM_FLOW 171 //! \details 172 //! Specifies whether the kernel program has a single program flow (SIMDnxm 173 //! with m = 1) or multiple program flows (SIMDnxm with m > 1). 174 enum SINGLE_PROGRAM_FLOW 175 { 176 SINGLE_PROGRAM_FLOW_MULTIPLE = 0, //!< No additional details 177 SINGLE_PROGRAM_FLOW_SINGLE = 1, //!< No additional details 178 }; 179 180 //! \brief DENORM_MODE 181 //! \details 182 //! This field specifies how Float denormalized numbers are handles in the 183 //! dispatched thread. 184 enum DENORM_MODE 185 { 186 DENORM_MODE_FTZ = 0, //!< Float denorms will be flushed to zero when appearing as inputs; denorms will never come out of instructions. Double precision float and half precision float numbers are not flushed to zero. 187 DENORM_MODE_SETBYKERNEL = 1, //!< Denorms will be handled in by kernel. 188 }; 189 190 //! \brief THREAD_PREEMPTION_DISABLE 191 //! \details 192 //! This field specifies whether, when dispatched, the thread is allowed to 193 //! stop in middle on receiving mid-thread pre-emption request. 194 enum THREAD_PREEMPTION_DISABLE 195 { 196 THREAD_PREEMPTION_DISABLE_DISABLE = 0, //!< Thread is pre-empted on receiving pre-emption indication. 197 THREAD_PREEMPTION_DISABLE_ENABLE = 1, //!< Thread is preempted only in case of page-fault. 198 }; 199 200 //! \brief SAMPLER_COUNT 201 //! \details 202 //! Specifies how many samplers (in multiples of 4) the kernel uses. Used 203 //! only for prefetching the associated sampler state entries. 204 //! This field is ignored for child threads. 205 //! If this field is not zero, sampler state is prefetched for the 206 //! first instance of a root thread upon the startup of the media 207 //! pipeline. 208 enum SAMPLER_COUNT 209 { 210 SAMPLER_COUNT_NOSAMPLERSUSED = 0, //!< No additional details 211 SAMPLER_COUNT_BETWEEN1AND4SAMPLERSUSED = 1, //!< No additional details 212 SAMPLER_COUNT_BETWEEN5AND8SAMPLERSUSED = 2, //!< No additional details 213 SAMPLER_COUNT_BETWEEN9AND12SAMPLERSUSED = 3, //!< No additional details 214 SAMPLER_COUNT_BETWEEN13AND16SAMPLERSUSED = 4, //!< No additional details 215 }; 216 217 //! \brief OVER_DISPATCH_CONTROL 218 //! \details 219 //! Over Dispatch Control that enables and controls the amount of GPGPU 220 //! thread over dispatch. 221 enum OVER_DISPATCH_CONTROL 222 { 223 OVER_DISPATCH_CONTROL_NONE = 0, //!< No additional details 224 OVER_DISPATCH_CONTROL_LOW = 1, //!< No additional details 225 OVER_DISPATCH_CONTROL_HIGH = 2, //!< No additional details 226 OVER_DISPATCH_CONTROL_NORMAL = 3, //!< No additional details 227 }; 228 229 //! \brief SHARED_LOCAL_MEMORY_SIZE 230 //! \details 231 //! This field indicates how much Shared Local Memory the thread group 232 //! requires. The amount is specified in 4k blocks, but only powers of 2 are 233 //! allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice. 234 enum SHARED_LOCAL_MEMORY_SIZE 235 { 236 SHARED_LOCAL_MEMORY_SIZE_ENCODES0K = 0, //!< No SLM used 237 SHARED_LOCAL_MEMORY_SIZE_ENCODES1K = 1, //!< No additional details 238 SHARED_LOCAL_MEMORY_SIZE_ENCODES2K = 2, //!< No additional details 239 SHARED_LOCAL_MEMORY_SIZE_ENCODES4K = 3, //!< No additional details 240 SHARED_LOCAL_MEMORY_SIZE_ENCODES8K = 4, //!< No additional details 241 SHARED_LOCAL_MEMORY_SIZE_ENCODES16K = 5, //!< No additional details 242 SHARED_LOCAL_MEMORY_SIZE_ENCODES32K = 6, //!< No additional details 243 SHARED_LOCAL_MEMORY_SIZE_ENCODES64K = 7, //!< No additional details 244 }; 245 246 enum ROUNDING_MODE 247 { 248 ROUNDING_MODE_RTNE = 0, //!< Round to Nearest Even 249 ROUNDING_MODE_RU = 1, //!< Round toward +Infinity 250 ROUNDING_MODE_RD = 2, //!< Round toward -Infinity 251 ROUNDING_MODE_RTZ = 3, //!< Round toward Zero 252 }; 253 254 //! \name Initializations 255 256 //! \brief Explicit member initialization function 257 INTERFACE_DESCRIPTOR_DATA_CMD(); 258 259 static const size_t dwSize = 8; 260 static const size_t byteSize = 32; 261 }; 262 263 //! 264 //! \brief BINDING_TABLE_STATE 265 //! \details 266 //! The binding table binds surfaces to logical resource indices used by 267 //! shaders and other compute engine kernels. It is stored as an array of up 268 //! to 256 elements, each of which contains one dword as defined here. The 269 //! start of each element is spaced one dword apart. The first element of 270 //! the binding table is aligned to a 64-byte boundary. Binding table 271 //! indexes beyond 256 will automatically be mapped to entry 0 by the HW, w/ 272 //! the exception of any messages which support the special indexes 240 273 //! through 255, inclusive. 274 //! 275 struct BINDING_TABLE_STATE_CMD 276 { 277 union 278 { 279 //!< DWORD 0 280 struct 281 { 282 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 283 uint32_t SurfaceStatePointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Surface State Pointer 284 }; 285 uint32_t Value; 286 } DW0; 287 288 //! \name Local enumerations 289 290 //! \name Initializations 291 292 //! \brief Explicit member initialization function 293 BINDING_TABLE_STATE_CMD(); 294 295 static const size_t dwSize = 1; 296 static const size_t byteSize = 4; 297 }; 298 299 //! 300 //! \brief RENDER_SURFACE_STATE 301 //! \details 302 //! This is the normal surface state used by all messages that use 303 //! SURFACE_STATE except those that use MEDIA_SURFACE_STATE. 304 //! 305 struct RENDER_SURFACE_STATE_CMD 306 { 307 union 308 { 309 struct 310 { 311 uint32_t CubeFaceEnablePositiveZ : __CODEGEN_BITFIELD( 0, 0) ; //!< Cube Face Enable - Positive Z 312 uint32_t CubeFaceEnableNegativeZ : __CODEGEN_BITFIELD( 1, 1) ; //!< Cube Face Enable - Negative Z 313 uint32_t CubeFaceEnablePositiveY : __CODEGEN_BITFIELD( 2, 2) ; //!< Cube Face Enable - Positive Y 314 uint32_t CubeFaceEnableNegativeY : __CODEGEN_BITFIELD( 3, 3) ; //!< Cube Face Enable - Negative Y 315 uint32_t CubeFaceEnablePositiveX : __CODEGEN_BITFIELD( 4, 4) ; //!< Cube Face Enable - Positive X 316 uint32_t CubeFaceEnableNegativeX : __CODEGEN_BITFIELD( 5, 5) ; //!< Cube Face Enable - Negative X 317 uint32_t MediaBoundaryPixelMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MEDIA_BOUNDARY_PIXEL_MODE 318 uint32_t RenderCacheReadWriteMode : __CODEGEN_BITFIELD( 8, 8) ; //!< RENDER_CACHE_READ_WRITE_MODE 319 uint32_t SamplerL2OutOfOrderModeDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Sampler L2 Out of Order Mode Disable 320 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(10, 10) ; //!< Vertical Line Stride Offset 321 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(11, 11) ; //!< Vertical Line Stride 322 uint32_t TileMode : __CODEGEN_BITFIELD(12, 13) ; //!< TILE_MODE 323 uint32_t SurfaceHorizontalAlignment : __CODEGEN_BITFIELD(14, 15) ; //!< SURFACE_HORIZONTAL_ALIGNMENT 324 uint32_t SurfaceVerticalAlignment : __CODEGEN_BITFIELD(16, 17) ; //!< SURFACE_VERTICAL_ALIGNMENT 325 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(18, 26) ; //!< SURFACE_FORMAT 326 uint32_t AstcEnable : __CODEGEN_BITFIELD(27, 27) ; //!< ASTC_Enable 327 uint32_t SurfaceArray : __CODEGEN_BITFIELD(28, 28) ; //!< Surface Array 328 uint32_t SurfaceType : __CODEGEN_BITFIELD(29, 31) ; //!< SURFACE_TYPE 329 }; 330 uint32_t Value; 331 } DW0; 332 union 333 { 334 struct 335 { 336 uint32_t SurfaceQpitch : __CODEGEN_BITFIELD( 0, 14) ; //!< Surface QPitch 337 uint32_t SampleTapDiscardDisable : __CODEGEN_BITFIELD(15, 15) ; //!< SAMPLE_TAP_DISCARD_DISABLE 338 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 16) ; //!< Reserved 339 uint32_t DoubleFetchDisable : __CODEGEN_BITFIELD(17, 17) ; //!< DOUBLE_FETCH_DISABLE 340 uint32_t CornerTexelMode : __CODEGEN_BITFIELD(18, 18) ; //!< CORNER_TEXEL_MODE 341 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(19, 23) ; //!< Base Mip Level 342 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(24, 30) ; //!< Memory Object Control State 343 uint32_t EnableUnormPathInColorPipe : __CODEGEN_BITFIELD(31, 31) ; //!< ENABLE_UNORM_PATH_IN_COLOR_PIPE 344 }; 345 uint32_t Value; 346 } DW1; 347 union 348 { 349 struct 350 { 351 uint32_t Width : __CODEGEN_BITFIELD( 0, 13) ; //!< Width 352 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 353 uint32_t Height : __CODEGEN_BITFIELD(16, 29) ; //!< Height 354 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 355 uint32_t DepthStencilResource : __CODEGEN_BITFIELD(31, 31) ; //!< Depth/Stencil Resource 356 }; 357 uint32_t Value; 358 } DW2; 359 union 360 { 361 struct 362 { 363 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 0, 17) ; //!< Surface Pitch 364 uint32_t NullProbingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< NULL_PROBING_ENABLE 365 uint32_t StandardTilingModeExtensions : __CODEGEN_BITFIELD(19, 19) ; //!< STANDARD_TILING_MODE_EXTENSIONS 366 uint32_t TileAddressMappingMode : __CODEGEN_BITFIELD(20, 20) ; //!< TILE_ADDRESS_MAPPING_MODE 367 uint32_t Depth : __CODEGEN_BITFIELD(21, 31) ; //!< Depth 368 }; 369 uint32_t Value; 370 } DW3; 371 union 372 { 373 struct 374 { 375 uint32_t MultisamplePositionPaletteIndex : __CODEGEN_BITFIELD( 0, 2) ; //!< Multisample Position Palette Index 376 uint32_t NumberOfMultisamples : __CODEGEN_BITFIELD( 3, 5) ; //!< NUMBER_OF_MULTISAMPLES 377 uint32_t MultisampledSurfaceStorageFormat : __CODEGEN_BITFIELD( 6, 6) ; //!< MULTISAMPLED_SURFACE_STORAGE_FORMAT 378 uint32_t RenderTargetViewExtent : __CODEGEN_BITFIELD( 7, 17) ; //!< Render Target View Extent 379 uint32_t MinimumArrayElement : __CODEGEN_BITFIELD(18, 28) ; //!< Minimum Array Element 380 uint32_t RenderTargetAndSampleUnormRotation : __CODEGEN_BITFIELD(29, 30) ; //!< RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 381 uint32_t DecompressInL3 : __CODEGEN_BITFIELD(31, 31) ; //!< DECOMPRESS_IN_L3 382 }; 383 uint32_t Value; 384 } DW4; 385 union 386 { 387 struct 388 { 389 uint32_t MipCountLod : __CODEGEN_BITFIELD( 0, 3) ; //!< MIP Count / LOD 390 uint32_t SurfaceMinLod : __CODEGEN_BITFIELD( 4, 7) ; //!< Surface Min LOD 391 uint32_t MipTailStartLod : __CODEGEN_BITFIELD( 8, 11) ; //!< Mip Tail Start LOD 392 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 13) ; //!< Reserved 393 uint32_t CoherencyType : __CODEGEN_BITFIELD(14, 14) ; //!< COHERENCY_TYPE 394 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 17) ; //!< Reserved 395 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 396 uint32_t EwaDisableForCube : __CODEGEN_BITFIELD(20, 20) ; //!< EWA_DISABLE_FOR_CUBE 397 uint32_t YOffset : __CODEGEN_BITFIELD(21, 23) ; //!< Y Offset 398 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 399 uint32_t XOffset : __CODEGEN_BITFIELD(25, 31) ; //!< X Offset 400 }; 401 uint32_t Value; 402 } DW5; 403 union 404 { 405 struct 406 { 407 uint32_t AuxiliarySurfaceMode : __CODEGEN_BITFIELD( 0, 2) ; //!< AUXILIARY_SURFACE_MODE, ([Surface Format] != 'PLANAR') 408 uint32_t Reserved195 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 409 } Obj0; 410 struct 411 { 412 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved, ([Surface Format] != 'PLANAR') 413 uint32_t AuxiliarySurfacePitch : __CODEGEN_BITFIELD( 3, 12) ; //!< Auxiliary Surface Pitch, ([Surface Format] != 'PLANAR') 414 uint32_t Reserved205 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, ([Surface Format] != 'PLANAR') 415 uint32_t AuxiliarySurfaceQpitch : __CODEGEN_BITFIELD(16, 30) ; //!< Auxiliary Surface QPitch, ([Surface Format] != 'PLANAR') 416 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 417 } Obj1; 418 struct 419 { 420 uint32_t YOffsetForUOrUvPlane : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 421 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, ([Surface Format] == 'PLANAR') 422 uint32_t XOffsetForUOrUvPlane : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 423 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(30, 30) ; //!< HALF_PITCH_FOR_CHROMA, ([Surface Format] == 'PLANAR') 424 uint32_t SeparateUvPlaneEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Separate UV Plane Enable, ([Surface Format] == 'PLANAR') 425 } Obj2; 426 struct 427 { 428 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 14) ; //!< Reserved, ([Surface Format] == 'PLANAR') 429 uint32_t YuvInterpolationEnable : __CODEGEN_BITFIELD(15, 15) ; //!< YUV_INTERPOLATION_ENABLE, 430 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, 431 } Obj3; 432 uint32_t Value; 433 } DW6; 434 union 435 { 436 struct 437 { 438 uint32_t ResourceMinLod : __CODEGEN_BITFIELD( 0, 11) ; //!< Resource Min LOD 439 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 440 uint32_t ShaderChannelSelectAlpha : __CODEGEN_BITFIELD(16, 18) ; //!< SHADER_CHANNEL_SELECT_ALPHA 441 uint32_t ShaderChannelSelectBlue : __CODEGEN_BITFIELD(19, 21) ; //!< SHADER_CHANNEL_SELECT_BLUE 442 uint32_t ShaderChannelSelectGreen : __CODEGEN_BITFIELD(22, 24) ; //!< SHADER_CHANNEL_SELECT_GREEN 443 uint32_t ShaderChannelSelectRed : __CODEGEN_BITFIELD(25, 27) ; //!< SHADER_CHANNEL_SELECT_RED 444 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 445 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< Memory Compression Enable 446 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< MEMORY_COMPRESSION_MODE 447 }; 448 uint32_t Value; 449 } DW7; 450 union 451 { 452 struct 453 { 454 uint64_t SurfaceBaseAddress ; //!< Surface Base Address 455 }; 456 uint32_t Value[2]; 457 } DW8_9; 458 union 459 { 460 struct 461 { 462 uint64_t QuiltWidth : __CODEGEN_BITFIELD( 0, 4) ; //!< Quilt Width, 463 uint64_t QuiltHeight : __CODEGEN_BITFIELD( 5, 9) ; //!< Quilt Height, 464 uint64_t ClearValueAddressEnable : __CODEGEN_BITFIELD(10, 10) ; //!< CLEAR_VALUE_ADDRESS_ENABLE, 465 uint64_t ProceduralTexture : __CODEGEN_BITFIELD(11, 11) ; //!< Procedural Texture, 466 uint64_t Reserved332 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved, 467 uint64_t YOffsetForVPlane : __CODEGEN_BITFIELD(32, 45) ; //!< Y Offset for V Plane, ([Surface Format] == 'PLANAR') 468 uint64_t Reserved366 : __CODEGEN_BITFIELD(46, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 469 } Obj0; 470 struct 471 { 472 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 47) ; //!< Reserved, ([Surface Format] == 'PLANAR') 473 uint64_t XOffsetForVPlane : __CODEGEN_BITFIELD(48, 61) ; //!< X Offset for V Plane, ([Surface Format] == 'PLANAR') 474 uint64_t Reserved382 : __CODEGEN_BITFIELD(62, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 475 } Obj1; 476 struct 477 { 478 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved, ([Surface Format] == 'PLANAR') 479 uint64_t AuxiliarySurfaceBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Auxiliary Surface Base Address, ([Surface Format] != 'PLANAR') AND [Memory Compression Enable] == 0 480 } Obj2; 481 uint32_t Value[2]; 482 } DW10_11; 483 union 484 { 485 struct 486 { 487 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 488 uint32_t ClearAddressLow : __CODEGEN_BITFIELD( 6, 31) ; //!< Clear Address Low 489 }; 490 uint32_t Value; 491 } DW12; 492 union 493 { 494 struct 495 { 496 uint32_t ClearAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Clear Address High 497 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 498 }; 499 uint32_t Value; 500 } DW13; 501 union 502 { 503 struct 504 { 505 uint32_t Reserved448 ; //!< Reserved 506 }; 507 uint32_t Value; 508 } DW14; 509 union 510 { 511 struct 512 { 513 uint32_t Reserved480 ; //!< Reserved 514 }; 515 uint32_t Value; 516 } DW15; 517 518 //! \name Local enumerations 519 520 //! \brief MEDIA_BOUNDARY_PIXEL_MODE 521 //! \details 522 //! 523 //! For 2D Non-Array Surfaces accessed via the Data Port Media Block 524 //! Read Message or Data Port Transpose Read message: 525 //! This field enables control of which rows are returned on vertical 526 //! out-of-bounds reads using the Data Port Media Block Read Message or Data 527 //! Port Transpose Read message. In the description below, frame mode refers 528 //! to Vertical Line Stride = 0, field mode is Vertical Line 529 //! Stride = 1 in which only the even or odd rows are addressable. The 530 //! frame refers to the entire surface, while the field refers only to the 531 //! even or odd rows within the surface. 532 //! For Other Surfaces: 533 //! Reserved : MBZ 534 enum MEDIA_BOUNDARY_PIXEL_MODE 535 { 536 MEDIA_BOUNDARY_PIXEL_MODE_NORMALMODE = 0, //!< The row returned on an out-of-bound access is the closest row in the frame or field. Rows from the opposite field are never returned. 537 MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVEFRAME = 2, //!< The row returned on an out-of-bound access is the closest row in the frame, even if in field mode. 538 MEDIA_BOUNDARY_PIXEL_MODE_INTERLACEDFRAME = 3, //!< In field mode, the row returned on an out-of-bound access is the closest row in the field. In frame mode, even out-of-bound rows return the nearest even row while odd out-of-bound rows return the nearest odd row. 539 }; 540 541 //! \brief RENDER_CACHE_READ_WRITE_MODE 542 //! \details 543 //! For Surfaces accessed via the Data Port to Render Cache: 544 //! This field specifies the way Render Cache treats a write request. If 545 //! unset, Render Cache allocates a write-only cache line for a write miss. 546 //! If set, Render Cache allocates a read-write cache line for a write 547 //! miss. 548 //! For Surfaces accessed via the Sampling Engine or Data Port to 549 //! Texture Cache or Data Cache: 550 //! This field is reserved : MBZ 551 enum RENDER_CACHE_READ_WRITE_MODE 552 { 553 RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLYCACHE = 0, //!< Allocating write-only cache for a write miss 554 RENDER_CACHE_READ_WRITE_MODE_READ_WRITECACHE = 1, //!< Allocating read-write cache for a write miss 555 }; 556 557 //! \brief TILE_MODE 558 //! \details 559 //! This field specifies the type of memory tiling (Linear, XMajor, or 560 //! YMajor) employed to tile this surface. See Memory Interface 561 //! Functions for details on memory tiling and restrictions. 562 enum TILE_MODE 563 { 564 TILE_MODE_LINEAR = 0, //!< Linear mode (no tiling) 565 TILE_MODE_XMAJOR = 2, //!< X major tiling 566 TILE_MODE_YMAJOR = 3, //!< Y major tiling 567 }; 568 569 //! \brief SURFACE_HORIZONTAL_ALIGNMENT 570 //! \details 571 //! For Sampling Engine and Render Target Surfaces: This field specifies the 572 //! horizontal alignment requirement for the surface. 573 enum SURFACE_HORIZONTAL_ALIGNMENT 574 { 575 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN4 = 1, //!< Horizontal alignment factor j = 4 576 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN8 = 2, //!< Horizontal alignment factor j = 8 577 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN16 = 3, //!< Horizontal alignment factor j = 16 578 }; 579 580 //! \brief SURFACE_VERTICAL_ALIGNMENT 581 //! \details 582 //! For Sampling Engine and Render Target Surfaces: This field 583 //! specifies the vertical alignment requirement in elements for the 584 //! surface. Refer to the "Memory Data Formats" chapter for details on how 585 //! this field changes the layout of the surface in memory. An 586 //! element is defined as a pixel in uncompresed surface formats, and 587 //! as a compression block in compressed surface formats. For 588 //! MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample. 589 enum SURFACE_VERTICAL_ALIGNMENT 590 { 591 SURFACE_VERTICAL_ALIGNMENT_VALIGN4 = 1, //!< Vertical alignment factor j = 4 592 SURFACE_VERTICAL_ALIGNMENT_VALIGN8 = 2, //!< Vertical alignment factor j = 8 593 SURFACE_VERTICAL_ALIGNMENT_VALIGN16 = 3, //!< Vertical alignment factor j = 16 594 }; 595 596 //! \brief SURFACE_FORMAT 597 //! \details 598 //! This field specifies the format of the surface or element within this 599 //! surface. This field is ignored for all data port messages other than the 600 //! render target message and streamed vertex buffer write message. Some 601 //! forms of the media block messages use the surface format. 602 enum SURFACE_FORMAT 603 { 604 SURFACE_FORMAT_R32G32B32A32FLOAT = 0, //!< No additional details 605 SURFACE_FORMAT_R32G32B32A32SINT = 1, //!< No additional details 606 SURFACE_FORMAT_R32G32B32A32UINT = 2, //!< No additional details 607 SURFACE_FORMAT_R32G32B32A32UNORM = 3, //!< No additional details 608 SURFACE_FORMAT_R32G32B32A32SNORM = 4, //!< No additional details 609 SURFACE_FORMAT_R64G64FLOAT = 5, //!< No additional details 610 SURFACE_FORMAT_R32G32B32X32FLOAT = 6, //!< No additional details 611 SURFACE_FORMAT_R32G32B32A32SSCALED = 7, //!< No additional details 612 SURFACE_FORMAT_R32G32B32A32USCALED = 8, //!< No additional details 613 SURFACE_FORMAT_R32G32B32A32SFIXED = 32, //!< No additional details 614 SURFACE_FORMAT_R64G64PASSTHRU = 33, //!< No additional details 615 SURFACE_FORMAT_R32G32B32FLOAT = 64, //!< No additional details 616 SURFACE_FORMAT_R32G32B32SINT = 65, //!< No additional details 617 SURFACE_FORMAT_R32G32B32UINT = 66, //!< No additional details 618 SURFACE_FORMAT_R32G32B32UNORM = 67, //!< No additional details 619 SURFACE_FORMAT_R32G32B32SNORM = 68, //!< No additional details 620 SURFACE_FORMAT_R32G32B32SSCALED = 69, //!< No additional details 621 SURFACE_FORMAT_R32G32B32USCALED = 70, //!< No additional details 622 SURFACE_FORMAT_R32G32B32SFIXED = 80, //!< No additional details 623 SURFACE_FORMAT_R16G16B16A16UNORM = 128, //!< No additional details 624 SURFACE_FORMAT_R16G16B16A16SNORM = 129, //!< No additional details 625 SURFACE_FORMAT_R16G16B16A16SINT = 130, //!< No additional details 626 SURFACE_FORMAT_R16G16B16A16UINT = 131, //!< No additional details 627 SURFACE_FORMAT_R16G16B16A16FLOAT = 132, //!< No additional details 628 SURFACE_FORMAT_R32G32FLOAT = 133, //!< No additional details 629 SURFACE_FORMAT_R32G32SINT = 134, //!< No additional details 630 SURFACE_FORMAT_R32G32UINT = 135, //!< No additional details 631 SURFACE_FORMAT_R32FLOATX8X24TYPELESS = 136, //!< No additional details 632 SURFACE_FORMAT_X32TYPELESSG8X24UINT = 137, //!< No additional details 633 SURFACE_FORMAT_L32A32FLOAT = 138, //!< No additional details 634 SURFACE_FORMAT_R32G32UNORM = 139, //!< No additional details 635 SURFACE_FORMAT_R32G32SNORM = 140, //!< No additional details 636 SURFACE_FORMAT_R64FLOAT = 141, //!< No additional details 637 SURFACE_FORMAT_R16G16B16X16UNORM = 142, //!< No additional details 638 SURFACE_FORMAT_R16G16B16X16FLOAT = 143, //!< No additional details 639 SURFACE_FORMAT_A32X32FLOAT = 144, //!< No additional details 640 SURFACE_FORMAT_L32X32FLOAT = 145, //!< No additional details 641 SURFACE_FORMAT_I32X32FLOAT = 146, //!< No additional details 642 SURFACE_FORMAT_R16G16B16A16SSCALED = 147, //!< No additional details 643 SURFACE_FORMAT_R16G16B16A16USCALED = 148, //!< No additional details 644 SURFACE_FORMAT_R32G32SSCALED = 149, //!< No additional details 645 SURFACE_FORMAT_R32G32USCALED = 150, //!< No additional details 646 SURFACE_FORMAT_R32G32SFIXED = 160, //!< No additional details 647 SURFACE_FORMAT_R64PASSTHRU = 161, //!< No additional details 648 SURFACE_FORMAT_B8G8R8A8UNORM = 192, //!< No additional details 649 SURFACE_FORMAT_B8G8R8A8UNORMSRGB = 193, //!< No additional details 650 SURFACE_FORMAT_R10G10B10A2UNORM = 194, //!< No additional details 651 SURFACE_FORMAT_R10G10B10A2UNORMSRGB = 195, //!< No additional details 652 SURFACE_FORMAT_R10G10B10A2UINT = 196, //!< No additional details 653 SURFACE_FORMAT_R10G10B10SNORMA2UNORM = 197, //!< No additional details 654 SURFACE_FORMAT_R8G8B8A8UNORM = 199, //!< No additional details 655 SURFACE_FORMAT_R8G8B8A8UNORMSRGB = 200, //!< No additional details 656 SURFACE_FORMAT_R8G8B8A8SNORM = 201, //!< No additional details 657 SURFACE_FORMAT_R8G8B8A8SINT = 202, //!< No additional details 658 SURFACE_FORMAT_R8G8B8A8UINT = 203, //!< No additional details 659 SURFACE_FORMAT_R16G16UNORM = 204, //!< No additional details 660 SURFACE_FORMAT_R16G16SNORM = 205, //!< No additional details 661 SURFACE_FORMAT_R16G16SINT = 206, //!< No additional details 662 SURFACE_FORMAT_R16G16UINT = 207, //!< No additional details 663 SURFACE_FORMAT_R16G16FLOAT = 208, //!< No additional details 664 SURFACE_FORMAT_B10G10R10A2UNORM = 209, //!< No additional details 665 SURFACE_FORMAT_B10G10R10A2UNORMSRGB = 210, //!< No additional details 666 SURFACE_FORMAT_R11G11B10FLOAT = 211, //!< No additional details 667 SURFACE_FORMAT_R10G10B10FLOATA2UNORM = 213, //!< No additional details 668 SURFACE_FORMAT_R32SINT = 214, //!< No additional details 669 SURFACE_FORMAT_R32UINT = 215, //!< No additional details 670 SURFACE_FORMAT_R32FLOAT = 216, //!< No additional details 671 SURFACE_FORMAT_R24UNORMX8TYPELESS = 217, //!< No additional details 672 SURFACE_FORMAT_X24TYPELESSG8UINT = 218, //!< No additional details 673 SURFACE_FORMAT_L32UNORM = 221, //!< No additional details 674 SURFACE_FORMAT_A32UNORM = 222, //!< No additional details 675 SURFACE_FORMAT_L16A16UNORM = 223, //!< No additional details 676 SURFACE_FORMAT_I24X8UNORM = 224, //!< No additional details 677 SURFACE_FORMAT_L24X8UNORM = 225, //!< No additional details 678 SURFACE_FORMAT_A24X8UNORM = 226, //!< No additional details 679 SURFACE_FORMAT_I32FLOAT = 227, //!< No additional details 680 SURFACE_FORMAT_L32FLOAT = 228, //!< No additional details 681 SURFACE_FORMAT_A32FLOAT = 229, //!< No additional details 682 SURFACE_FORMAT_X8B8UNORMG8R8SNORM = 230, //!< No additional details 683 SURFACE_FORMAT_A8X8UNORMG8R8SNORM = 231, //!< No additional details 684 SURFACE_FORMAT_B8X8UNORMG8R8SNORM = 232, //!< No additional details 685 SURFACE_FORMAT_B8G8R8X8UNORM = 233, //!< No additional details 686 SURFACE_FORMAT_B8G8R8X8UNORMSRGB = 234, //!< No additional details 687 SURFACE_FORMAT_R8G8B8X8UNORM = 235, //!< No additional details 688 SURFACE_FORMAT_R8G8B8X8UNORMSRGB = 236, //!< No additional details 689 SURFACE_FORMAT_R9G9B9E5SHAREDEXP = 237, //!< No additional details 690 SURFACE_FORMAT_B10G10R10X2UNORM = 238, //!< No additional details 691 SURFACE_FORMAT_L16A16FLOAT = 240, //!< No additional details 692 SURFACE_FORMAT_R32UNORM = 241, //!< No additional details 693 SURFACE_FORMAT_R32SNORM = 242, //!< No additional details 694 SURFACE_FORMAT_R10G10B10X2USCALED = 243, //!< No additional details 695 SURFACE_FORMAT_R8G8B8A8SSCALED = 244, //!< No additional details 696 SURFACE_FORMAT_R8G8B8A8USCALED = 245, //!< No additional details 697 SURFACE_FORMAT_R16G16SSCALED = 246, //!< No additional details 698 SURFACE_FORMAT_R16G16USCALED = 247, //!< No additional details 699 SURFACE_FORMAT_R32SSCALED = 248, //!< No additional details 700 SURFACE_FORMAT_R32USCALED = 249, //!< No additional details 701 SURFACE_FORMAT_B5G6R5UNORM = 256, //!< No additional details 702 SURFACE_FORMAT_B5G6R5UNORMSRGB = 257, //!< No additional details 703 SURFACE_FORMAT_B5G5R5A1UNORM = 258, //!< No additional details 704 SURFACE_FORMAT_B5G5R5A1UNORMSRGB = 259, //!< No additional details 705 SURFACE_FORMAT_B4G4R4A4UNORM = 260, //!< No additional details 706 SURFACE_FORMAT_B4G4R4A4UNORMSRGB = 261, //!< No additional details 707 SURFACE_FORMAT_R8G8UNORM = 262, //!< No additional details 708 SURFACE_FORMAT_R8G8SNORM = 263, //!< No additional details 709 SURFACE_FORMAT_R8G8SINT = 264, //!< No additional details 710 SURFACE_FORMAT_R8G8UINT = 265, //!< No additional details 711 SURFACE_FORMAT_R16UNORM = 266, //!< No additional details 712 SURFACE_FORMAT_R16SNORM = 267, //!< No additional details 713 SURFACE_FORMAT_R16SINT = 268, //!< No additional details 714 SURFACE_FORMAT_R16UINT = 269, //!< No additional details 715 SURFACE_FORMAT_R16FLOAT = 270, //!< No additional details 716 SURFACE_FORMAT_A8P8UNORMPALETTE0 = 271, //!< No additional details 717 SURFACE_FORMAT_A8P8UNORMPALETTE1 = 272, //!< No additional details 718 SURFACE_FORMAT_I16UNORM = 273, //!< No additional details 719 SURFACE_FORMAT_L16UNORM = 274, //!< No additional details 720 SURFACE_FORMAT_A16UNORM = 275, //!< No additional details 721 SURFACE_FORMAT_L8A8UNORM = 276, //!< No additional details 722 SURFACE_FORMAT_I16FLOAT = 277, //!< No additional details 723 SURFACE_FORMAT_L16FLOAT = 278, //!< No additional details 724 SURFACE_FORMAT_A16FLOAT = 279, //!< No additional details 725 SURFACE_FORMAT_L8A8UNORMSRGB = 280, //!< No additional details 726 SURFACE_FORMAT_R5G5SNORMB6UNORM = 281, //!< No additional details 727 SURFACE_FORMAT_B5G5R5X1UNORM = 282, //!< No additional details 728 SURFACE_FORMAT_B5G5R5X1UNORMSRGB = 283, //!< No additional details 729 SURFACE_FORMAT_R8G8SSCALED = 284, //!< No additional details 730 SURFACE_FORMAT_R8G8USCALED = 285, //!< No additional details 731 SURFACE_FORMAT_R16SSCALED = 286, //!< No additional details 732 SURFACE_FORMAT_R16USCALED = 287, //!< No additional details 733 SURFACE_FORMAT_P8A8UNORMPALETTE0 = 290, //!< No additional details 734 SURFACE_FORMAT_P8A8UNORMPALETTE1 = 291, //!< No additional details 735 SURFACE_FORMAT_A1B5G5R5UNORM = 292, //!< No additional details 736 SURFACE_FORMAT_A4B4G4R4UNORM = 293, //!< No additional details 737 SURFACE_FORMAT_L8A8UINT = 294, //!< No additional details 738 SURFACE_FORMAT_L8A8SINT = 295, //!< No additional details 739 SURFACE_FORMAT_R8UNORM = 320, //!< No additional details 740 SURFACE_FORMAT_R8SNORM = 321, //!< No additional details 741 SURFACE_FORMAT_R8SINT = 322, //!< No additional details 742 SURFACE_FORMAT_R8UINT = 323, //!< No additional details 743 SURFACE_FORMAT_A8UNORM = 324, //!< No additional details 744 SURFACE_FORMAT_I8UNORM = 325, //!< No additional details 745 SURFACE_FORMAT_L8UNORM = 326, //!< No additional details 746 SURFACE_FORMAT_P4A4UNORMPALETTE0 = 327, //!< No additional details 747 SURFACE_FORMAT_A4P4UNORMPALETTE0 = 328, //!< No additional details 748 SURFACE_FORMAT_R8SSCALED = 329, //!< No additional details 749 SURFACE_FORMAT_R8USCALED = 330, //!< No additional details 750 SURFACE_FORMAT_P8UNORMPALETTE0 = 331, //!< No additional details 751 SURFACE_FORMAT_L8UNORMSRGB = 332, //!< No additional details 752 SURFACE_FORMAT_P8UNORMPALETTE1 = 333, //!< No additional details 753 SURFACE_FORMAT_P4A4UNORMPALETTE1 = 334, //!< No additional details 754 SURFACE_FORMAT_A4P4UNORMPALETTE1 = 335, //!< No additional details 755 SURFACE_FORMAT_Y8UNORM = 336, //!< No additional details 756 SURFACE_FORMAT_L8UINT = 338, //!< No additional details 757 SURFACE_FORMAT_L8SINT = 339, //!< No additional details 758 SURFACE_FORMAT_I8UINT = 340, //!< No additional details 759 SURFACE_FORMAT_I8SINT = 341, //!< No additional details 760 SURFACE_FORMAT_DXT1RGBSRGB = 384, //!< No additional details 761 SURFACE_FORMAT_R1UNORM = 385, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 762 SURFACE_FORMAT_YCRCBNORMAL = 386, //!< No additional details 763 SURFACE_FORMAT_YCRCBSWAPUVY = 387, //!< No additional details 764 SURFACE_FORMAT_P2UNORMPALETTE0 = 388, //!< No additional details 765 SURFACE_FORMAT_P2UNORMPALETTE1 = 389, //!< No additional details 766 SURFACE_FORMAT_BC1UNORM = 390, //!< (DXT1) 767 SURFACE_FORMAT_BC2UNORM = 391, //!< (DXT2/3) 768 SURFACE_FORMAT_BC3UNORM = 392, //!< (DXT4/5) 769 SURFACE_FORMAT_BC4UNORM = 393, //!< No additional details 770 SURFACE_FORMAT_BC5UNORM = 394, //!< No additional details 771 SURFACE_FORMAT_BC1UNORMSRGB = 395, //!< (DXT1_SRGB) 772 SURFACE_FORMAT_BC2UNORMSRGB = 396, //!< (DXT2/3_SRGB) 773 SURFACE_FORMAT_BC3UNORMSRGB = 397, //!< (DXT4/5_SRGB) 774 SURFACE_FORMAT_MONO8 = 398, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 775 SURFACE_FORMAT_YCRCBSWAPUV = 399, //!< No additional details 776 SURFACE_FORMAT_YCRCBSWAPY = 400, //!< No additional details 777 SURFACE_FORMAT_DXT1RGB = 401, //!< No additional details 778 SURFACE_FORMAT_FXT1 = 402, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 779 SURFACE_FORMAT_R8G8B8UNORM = 403, //!< No additional details 780 SURFACE_FORMAT_R8G8B8SNORM = 404, //!< No additional details 781 SURFACE_FORMAT_R8G8B8SSCALED = 405, //!< No additional details 782 SURFACE_FORMAT_R8G8B8USCALED = 406, //!< No additional details 783 SURFACE_FORMAT_R64G64B64A64FLOAT = 407, //!< No additional details 784 SURFACE_FORMAT_R64G64B64FLOAT = 408, //!< No additional details 785 SURFACE_FORMAT_BC4SNORM = 409, //!< No additional details 786 SURFACE_FORMAT_BC5SNORM = 410, //!< No additional details 787 SURFACE_FORMAT_R16G16B16FLOAT = 411, //!< No additional details 788 SURFACE_FORMAT_R16G16B16UNORM = 412, //!< No additional details 789 SURFACE_FORMAT_R16G16B16SNORM = 413, //!< No additional details 790 SURFACE_FORMAT_R16G16B16SSCALED = 414, //!< No additional details 791 SURFACE_FORMAT_R16G16B16USCALED = 415, //!< No additional details 792 SURFACE_FORMAT_BC6HSF16 = 417, //!< No additional details 793 SURFACE_FORMAT_BC7UNORM = 418, //!< No additional details 794 SURFACE_FORMAT_BC7UNORMSRGB = 419, //!< No additional details 795 SURFACE_FORMAT_BC6HUF16 = 420, //!< No additional details 796 SURFACE_FORMAT_PLANAR4208 = 421, //!< No additional details 797 SURFACE_FORMAT_PLANAR42016 = 422, //!< No additional details 798 SURFACE_FORMAT_R8G8B8UNORMSRGB = 424, //!< No additional details 799 SURFACE_FORMAT_ETC1RGB8 = 425, //!< No additional details 800 SURFACE_FORMAT_ETC2RGB8 = 426, //!< No additional details 801 SURFACE_FORMAT_EACR11 = 427, //!< No additional details 802 SURFACE_FORMAT_EACRG11 = 428, //!< No additional details 803 SURFACE_FORMAT_EACSIGNEDR11 = 429, //!< No additional details 804 SURFACE_FORMAT_EACSIGNEDRG11 = 430, //!< No additional details 805 SURFACE_FORMAT_ETC2SRGB8 = 431, //!< No additional details 806 SURFACE_FORMAT_R16G16B16UINT = 432, //!< No additional details 807 SURFACE_FORMAT_R16G16B16SINT = 433, //!< No additional details 808 SURFACE_FORMAT_R32SFIXED = 434, //!< No additional details 809 SURFACE_FORMAT_R10G10B10A2SNORM = 435, //!< No additional details 810 SURFACE_FORMAT_R10G10B10A2USCALED = 436, //!< No additional details 811 SURFACE_FORMAT_R10G10B10A2SSCALED = 437, //!< No additional details 812 SURFACE_FORMAT_R10G10B10A2SINT = 438, //!< No additional details 813 SURFACE_FORMAT_B10G10R10A2SNORM = 439, //!< No additional details 814 SURFACE_FORMAT_B10G10R10A2USCALED = 440, //!< No additional details 815 SURFACE_FORMAT_B10G10R10A2SSCALED = 441, //!< No additional details 816 SURFACE_FORMAT_B10G10R10A2UINT = 442, //!< No additional details 817 SURFACE_FORMAT_B10G10R10A2SINT = 443, //!< No additional details 818 SURFACE_FORMAT_R64G64B64A64PASSTHRU = 444, //!< No additional details 819 SURFACE_FORMAT_R64G64B64PASSTHRU = 445, //!< No additional details 820 SURFACE_FORMAT_ETC2RGB8PTA = 448, //!< No additional details 821 SURFACE_FORMAT_ETC2SRGB8PTA = 449, //!< No additional details 822 SURFACE_FORMAT_ETC2EACRGBA8 = 450, //!< No additional details 823 SURFACE_FORMAT_ETC2EACSRGB8A8 = 451, //!< No additional details 824 SURFACE_FORMAT_R8G8B8UINT = 456, //!< No additional details 825 SURFACE_FORMAT_R8G8B8SINT = 457, //!< No additional details 826 SURFACE_FORMAT_RAW = 511, //!< No additional details 827 }; 828 829 //! \brief SURFACE_TYPE 830 //! \details 831 //! This field defines the type of the surface. 832 enum SURFACE_TYPE 833 { 834 SURFACE_TYPE_SURFTYPE1D = 0, //!< Defines a 1-dimensional map or array of maps 835 SURFACE_TYPE_SURFTYPE2D = 1, //!< Defines a 2-dimensional map or array of maps 836 SURFACE_TYPE_SURFTYPE3D = 2, //!< Defines a 3-dimensional (volumetric) map 837 SURFACE_TYPE_SURFTYPECUBE = 3, //!< Defines a cube map or array of cube maps 838 SURFACE_TYPE_SURFTYPEBUFFER = 4, //!< Defines an element in a buffer 839 SURFACE_TYPE_SURFTYPESTRBUF = 5, //!< Defines a structured buffer surface 840 SURFACE_TYPE_SURFTYPENULL = 7, //!< Defines a null surface 841 }; 842 843 //! \brief SAMPLE_TAP_DISCARD_DISABLE 844 //! \details 845 //! This bit forces sample tap discard filter mode to be disabled for this 846 //! surface state. This bit must be set for surfaces which are no Alpha 847 //! Channel such as R8G8B8_UNORM. 848 enum SAMPLE_TAP_DISCARD_DISABLE 849 { 850 SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0, //!< When programmed to 0h, Sample Tap Discard filter mode is allowed and is not disabled by this bit. This bit is ignored if Sample Tap Discard is not enabled in the Sampler State. 851 SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 1, //!< When programmed to 1h, Sample Tap Discard filter mode will be disabled even if enabled through Sampler State 852 }; 853 854 //! \brief DOUBLE_FETCH_DISABLE 855 //! \details 856 //! This bit is intended to disable the "double fetch" of adjacent 857 //! cache-lines in most all cases. Double fetch is a performance mode, but 858 //! for some surface types for formats it may be lower performance due to 859 //! fetching unused cache-lines. 860 enum DOUBLE_FETCH_DISABLE 861 { 862 DOUBLE_FETCH_DISABLE_ENABLE = 0, //!< When programmed to 0h, double fetches are allowed. 863 DOUBLE_FETCH_DISABLE_DISABLE = 1, //!< When programmed to 1h, double fetches are disabled. 864 }; 865 866 //! \brief CORNER_TEXEL_MODE 867 //! \details 868 //! This field, when ENABLED, indicates when a surface is using corner 869 //! texel-mode for sampling. 870 //! Corner Texel Mode is ignored for Planar YUV/YCrCb surface 871 //! formats. 872 //! Corner Texel Mode is ignored for sample_8X8 and sample_unorm messasge 873 //! types. 874 //! <!--StartFragment-->Does not support legacy sampler features set0 See 875 //! legacy sampler page for more details<!--EndFragment--> 876 enum CORNER_TEXEL_MODE 877 { 878 CORNER_TEXEL_MODE_DISABLE = 0, //!< When programmed to 0h, Corner Texel Mode is disabled. This means texel references are shifted a half-texel from the upper-right corner of the texture map which is the standard texel referencemode. 879 CORNER_TEXEL_MODE_ENABLE = 1, //!< When programmed to 1h, Corner Texel Mode is enabled. The location of a sampled texel on a texture map is shifted a half-texel to the upper-left, meaning texel (0,0) isin the exact upper-left corner of the surface. 880 }; 881 882 //! \brief ENABLE_UNORM_PATH_IN_COLOR_PIPE 883 //! \details 884 //! Enables Unorm Path (fixed Point Conversion of floating point for fill 885 //! and blend in DAPRSS) in color Pipe. 886 enum ENABLE_UNORM_PATH_IN_COLOR_PIPE 887 { 888 ENABLE_UNORM_PATH_IN_COLOR_PIPE_DISABLE = 0, //!< Disables Unorm path in Color Pipe. 889 ENABLE_UNORM_PATH_IN_COLOR_PIPE_ENABLE = 1, //!< Enables Unorm Path in Color Pipe. 890 }; 891 892 //! \brief NULL_PROBING_ENABLE 893 //! \details 894 //! This field is applicable for Render Targets only. It is used for 895 //! enabling NULL tile probing as defined under Tiled Resources. This 896 //! probing guarantees consistent read data return after previous write 897 //! including fast clears. SW must enable this bit for render target only if 898 //! surface contains NULL tiles and read after write consistency is 899 //! required. 900 enum NULL_PROBING_ENABLE 901 { 902 NULL_PROBING_ENABLE_DISABLE = 0, //!< No additional details 903 NULL_PROBING_ENABLE_ENABLE = 1, //!< No additional details 904 }; 905 906 //! \brief STANDARD_TILING_MODE_EXTENSIONS 907 //! \details 908 //! It changes in the MIP Tail Packing. When enabled (programmed to 1h), 909 //! MIP Tail packing for Volumetric and 1D are changed as defined in the 910 //! Surface Layout and Tiling section. 911 //! 912 enum STANDARD_TILING_MODE_EXTENSIONS 913 { 914 STANDARD_TILING_MODE_EXTENSIONS_DISABLE = 0, //!< When programmed to 0h, the Gen11 extensions to support Standard Tiling are disabled. Behvaior reverts to Gen10 and Gen9 Miptail packing. 915 STANDARD_TILING_MODE_EXTENSIONS_ENABLE = 1, //!< When programmed to 1h, the Gen11 changes to support Standard Tiling Extensions are enabled. See the Surface Layout and Tiling section for details. 916 }; 917 918 //! \brief TILE_ADDRESS_MAPPING_MODE 919 //! \details 920 //! This field is used to select between Gen9 Tile Address Mapping mode and 921 //! Gen10 for TileYs and TileYf. 922 enum TILE_ADDRESS_MAPPING_MODE 923 { 924 TILE_ADDRESS_MAPPING_MODE_GEN9 = 0, //!< Gen9 Tile Address Mapping ModeThis field should always be programmed to 0h. Gen9 Tiling mode is the standard tile layout for 3D. 925 TILE_ADDRESS_MAPPING_MODE_GEN10 = 1, //!< Gen10+ Tile Address Mapping Mode (for Standard Tiling).This field should NOT be programmed to 1h as the Gen10 Tiling Address Mapping mode is not supported by SW. 926 }; 927 928 //! \brief NUMBER_OF_MULTISAMPLES 929 //! \details 930 //! This field indicates the number of multisamples on the surface. 931 enum NUMBER_OF_MULTISAMPLES 932 { 933 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT1 = 0, //!< No additional details 934 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT2 = 1, //!< No additional details 935 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT4 = 2, //!< No additional details 936 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT8 = 3, //!< No additional details 937 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT16 = 4, //!< No additional details 938 }; 939 940 //! \brief MULTISAMPLED_SURFACE_STORAGE_FORMAT 941 //! \details 942 //! This field indicates the storage format of the multisampled surface. 943 enum MULTISAMPLED_SURFACE_STORAGE_FORMAT 944 { 945 MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0, //!< Multsampled surface was/is rendered as a render target 946 MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTHSTENCIL = 1, //!< Multisampled surface was rendered as a depth or stencil buffer 947 }; 948 949 //! \brief RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 950 //! \details 951 //! For Render Target Surfaces: 952 //! This field specifies the rotation of this render target surface 953 //! when being written to memory. 954 enum RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 955 { 956 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0, //!< No rotation (0 degrees) 957 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 1, //!< Rotate by 90 degrees 958 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 2, //!< Rotate by 180 degrees [for sample_unorm message] 959 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 3, //!< Rotate by 270 degrees 960 }; 961 962 enum DECOMPRESS_IN_L3 963 { 964 DECOMPRESS_IN_L3_DISABLE = 0, //!< When this field is set to 0h, the associated compressible surface, when accessed by sampler, can be compressed in L3. If the surface is not compressible, this bit field is ignored. 965 DECOMPRESS_IN_L3_ENABLE = 1, //!< When this field is set to 1h, the associated compressible surface, when accessed by sampler, will be uncompressed in L3. If the surface is not compressible, this bit field is ignored. 966 }; 967 968 //! \brief COHERENCY_TYPE 969 //! \details 970 //! Specifies the type of coherency maintained for this surface. 971 enum COHERENCY_TYPE 972 { 973 COHERENCY_TYPE_GPUCOHERENT = 0, //!< Surface memory is kept coherent with GPU threads using GPU read/write ordering rules. Surface memory is backed by system memory but is not kept coherent with CPU (LLC). 974 COHERENCY_TYPE_IACOHERENT = 1, //!< Surface memory is kept coherent with CPU (LLC). 975 }; 976 977 //! \brief TILED_RESOURCE_MODE 978 //! \details 979 //! For Sampling Engine, Render Target, and Typed/Untyped Surfaces: 980 //! This field specifies the tiled resource mode. 981 //! 982 //! For other surfaces: 983 //! This field is ignored. 984 enum TILED_RESOURCE_MODE 985 { 986 TILED_RESOURCE_MODE_NONE = 0, //!< No tiled resource 987 TILED_RESOURCE_MODE_4KB = 1, //!< 4KB tiled resources 988 TILED_RESOURCE_MODE_TILEYF = 1, //!< 4KB tiled resources 989 TILED_RESOURCE_MODE_64KB = 2, //!< 64KB tiled resources 990 TILED_RESOURCE_MODE_TILEYS = 2, //!< 64KB tiled resources 991 }; 992 993 //! \brief EWA_DISABLE_FOR_CUBE 994 //! \details 995 //! Specifies if EWA mode for LOD quality improvement needs to be disabled 996 //! for cube maps. 997 enum EWA_DISABLE_FOR_CUBE 998 { 999 EWA_DISABLE_FOR_CUBE_ENABLE = 0, //!< EWA is enabled for cube maps 1000 EWA_DISABLE_FOR_CUBE_DISABLE = 1, //!< EWA is disabled for cube maps 1001 }; 1002 1003 //! \brief AUXILIARY_SURFACE_MODE 1004 //! \details 1005 //! Specifies what type of surface the Auxiliary surface is. The Auxiliary 1006 //! surface has its own base address and pitch, but otherwise shares or 1007 //! overrides other fields set for the primary surface, detailed in the 1008 //! programming notes below. 1009 enum AUXILIARY_SURFACE_MODE 1010 { 1011 AUXILIARY_SURFACE_MODE_AUXNONE = 0, //!< No Auxiliary surface is used 1012 AUXILIARY_SURFACE_MODE_AUXCCSD = 1, //!< The Auxiliary surface is a CCS (Color Control Surface) with color compression disabled. The Auxiliary surface is a MCS (Multisample Control Surface) with MSAA compression disabled. MCS is tiled y 1013 AUXILIARY_SURFACE_MODE_AUXAPPEND = 2, //!< The Auxiliary surface is an append buffer 1014 AUXILIARY_SURFACE_MODE_AUXMCSLCE = 4, //!< Enables lossless compresion on the top of MSAA compression for RTs with Number of Multisamples not equal to MULTISAMPLECOUNT_1.CCS is tiling format is linear.MCS tiling format is always tiledY. 1015 AUXILIARY_SURFACE_MODE_AUXCCSE = 5, //!< If Number of multisamples = 1, programming this value means lossless compression is enabled for that surface.Auxiliary surface is a CCS with linear tiling. If Number of multisamples > 1, programming this value means MSAA compression is enabled for that surface. Auxillary surafce is MSC with tile y. 1016 }; 1017 1018 //! \brief YUV_INTERPOLATION_ENABLE 1019 //! \details 1020 //! This bit controls whether a Non-Planar YUV4:2:2 and Planar YUV4:2:0 1021 //! surface use interpolated or replicated U and V channels for input to the 1022 //! Sampler filter. Programming to 1h causes interpolation of U and V 1023 //! channels. In this case the chrominance for odd pixels is computed by an 1024 //! interpolation between adjacent even pixels. Programming to 0h causes the 1025 //! chrominance to be copied from the pixel to the left. 1026 enum YUV_INTERPOLATION_ENABLE 1027 { 1028 YUV_INTERPOLATION_ENABLE_DISABLE = 0, //!< Programming to 0h causes the sampler to replicate U and V channels. This will lead to lower quality in certain cases where the YUV surface is being filtered (e.g. linear). 1029 YUV_INTERPOLATION_ENABLE_ENABLE = 1, //!< Programming to 1h causes the sampler to interpolate the U and V channels between the horizonally neighboring pixels. This will improvie image quality if the surface is being filtered. 1030 }; 1031 1032 //! \brief HALF_PITCH_FOR_CHROMA 1033 //! \details 1034 //! style="font-family: "Arial","sans-serif"; 1035 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1036 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1037 //! mso-bidi-language: AR-SA;"><font color="#000000">This bit enables 1038 //! support for half-pitch chroma planes for Planar YUV surfaces. It is 1039 //! ignored for Non-Planar surfaces. For planar surfaces it allows the 1040 //! chroma planes to be one-half the width of a the Y (Luma) 1041 //! plane.</font> 1042 //! style="font-family: "Arial","sans-serif"; 1043 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1044 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1045 //! mso-bidi-language: AR-SA;"><font color="#000000">For example, should be 1046 //! set to 0h for NV12 surfaces.</font> 1047 //! style="font-family: "Arial","sans-serif"; 1048 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1049 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1050 //! mso-bidi-language: AR-SA;"><font color="#000000">Must be set to 1h for 1051 //! YV12 surfaces.</font> 1052 enum HALF_PITCH_FOR_CHROMA 1053 { 1054 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< <font color="#000000">Setting this bit to 0h (default) causes Chroma planes to be treated as full width (same as Y plane).</font> 1055 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< <font color="#000000">Setting this bit to 1h causes Chroma planes (U and V) to be treated as half the width of the Luma (Y) plane.</font> 1056 }; 1057 1058 //! \brief SHADER_CHANNEL_SELECT_ALPHA 1059 //! \details 1060 //! See Shader Channel Select Red for details. 1061 enum SHADER_CHANNEL_SELECT_ALPHA 1062 { 1063 SHADER_CHANNEL_SELECT_ALPHA_ZERO = 0, //!< No additional details 1064 SHADER_CHANNEL_SELECT_ALPHA_ONE = 1, //!< No additional details 1065 SHADER_CHANNEL_SELECT_ALPHA_RED = 4, //!< Shader channel is set to surface red channel 1066 SHADER_CHANNEL_SELECT_ALPHA_GREEN = 5, //!< Shader channel is set to surface green channel 1067 SHADER_CHANNEL_SELECT_ALPHA_BLUE = 6, //!< Shader channel is set to surface blue channel 1068 SHADER_CHANNEL_SELECT_ALPHA_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1069 }; 1070 1071 //! \brief SHADER_CHANNEL_SELECT_BLUE 1072 //! \details 1073 //! See Shader Channel Select Red for details. 1074 enum SHADER_CHANNEL_SELECT_BLUE 1075 { 1076 SHADER_CHANNEL_SELECT_BLUE_ZERO = 0, //!< No additional details 1077 SHADER_CHANNEL_SELECT_BLUE_ONE = 1, //!< No additional details 1078 SHADER_CHANNEL_SELECT_BLUE_RED = 4, //!< Shader channel is set to surface red channel 1079 SHADER_CHANNEL_SELECT_BLUE_GREEN = 5, //!< Shader channel is set to surface green channel 1080 SHADER_CHANNEL_SELECT_BLUE_BLUE = 6, //!< Shader channel is set to surface blue channel 1081 SHADER_CHANNEL_SELECT_BLUE_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1082 }; 1083 1084 //! \brief SHADER_CHANNEL_SELECT_GREEN 1085 //! \details 1086 //! See Shader Channel Select Red for details. 1087 enum SHADER_CHANNEL_SELECT_GREEN 1088 { 1089 SHADER_CHANNEL_SELECT_GREEN_ZERO = 0, //!< No additional details 1090 SHADER_CHANNEL_SELECT_GREEN_ONE = 1, //!< No additional details 1091 SHADER_CHANNEL_SELECT_GREEN_RED = 4, //!< Shader channel is set to surface red channel 1092 SHADER_CHANNEL_SELECT_GREEN_GREEN = 5, //!< Shader channel is set to surface green channel 1093 SHADER_CHANNEL_SELECT_GREEN_BLUE = 6, //!< Shader channel is set to surface blue channel 1094 SHADER_CHANNEL_SELECT_GREEN_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1095 }; 1096 1097 //! \brief SHADER_CHANNEL_SELECT_RED 1098 //! \details 1099 //! Specifies which surface channel is read or written in the Red shader 1100 //! channel. 1101 enum SHADER_CHANNEL_SELECT_RED 1102 { 1103 SHADER_CHANNEL_SELECT_RED_ZERO = 0, //!< No additional details 1104 SHADER_CHANNEL_SELECT_RED_ONE = 1, //!< No additional details 1105 SHADER_CHANNEL_SELECT_RED_RED = 4, //!< Shader channel is set to surface red channel 1106 SHADER_CHANNEL_SELECT_RED_GREEN = 5, //!< Shader channel is set to surface green channel 1107 SHADER_CHANNEL_SELECT_RED_BLUE = 6, //!< Shader channel is set to surface blue channel 1108 SHADER_CHANNEL_SELECT_RED_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1109 }; 1110 1111 //! \brief MEMORY_COMPRESSION_MODE 1112 //! \details 1113 //! MBZ: Only Horizontal mode is supported. 1114 enum MEMORY_COMPRESSION_MODE 1115 { 1116 MEMORY_COMPRESSION_MODE_HORIZONTAL = 0, //!< No additional details 1117 }; 1118 1119 //! \brief CLEAR_VALUE_ADDRESS_ENABLE 1120 //! \details 1121 //! This field enables HW Managed Clear Value Layout for the Surface State. 1122 //! If this bit is enabled, Clear Value Address is present instead of 1123 //! explicit clear values. 1124 enum CLEAR_VALUE_ADDRESS_ENABLE 1125 { 1126 CLEAR_VALUE_ADDRESS_ENABLE_DISABLE = 0, //!< Clear values are present in the surface state explicitly. 1127 CLEAR_VALUE_ADDRESS_ENABLE_ENABLE = 1, //!< Clear value Address is present instead of explicit clear values. 1128 }; 1129 1130 //! \name Initializations 1131 1132 //! \brief Explicit member initialization function 1133 RENDER_SURFACE_STATE_CMD(); 1134 1135 static const size_t dwSize = 16; 1136 static const size_t byteSize = 64; 1137 }; 1138 1139 //! 1140 //! \brief MEDIA_SURFACE_STATE 1141 //! \details 1142 //! This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME 1143 //! messages. 1144 //! 1145 struct MEDIA_SURFACE_STATE_CMD 1146 { 1147 union 1148 { 1149 struct 1150 { 1151 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1152 uint32_t YOffset : __CODEGEN_BITFIELD(16, 19) ; //!< Y Offset 1153 uint32_t XOffset : __CODEGEN_BITFIELD(20, 26) ; //!< X Offset 1154 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 29) ; //!< Reserved 1155 uint32_t Rotation : __CODEGEN_BITFIELD(30, 31) ; //!< ROTATION 1156 }; 1157 uint32_t Value; 1158 } DW0; 1159 union 1160 { 1161 struct 1162 { 1163 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION 1164 uint32_t PictureStructure : __CODEGEN_BITFIELD( 2, 3) ; //!< PICTURE_STRUCTURE 1165 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1166 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1167 }; 1168 uint32_t Value; 1169 } DW1; 1170 union 1171 { 1172 struct 1173 { 1174 uint32_t TileMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILE_MODE 1175 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 1176 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 20) ; //!< Surface Pitch 1177 uint32_t AddressControl : __CODEGEN_BITFIELD(21, 21) ; //!< ADDRESS_CONTROL 1178 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< Memory Compression Enable 1179 uint32_t MemoryCompressionType : __CODEGEN_BITFIELD(23, 23) ; //!< MEMORY_COMPRESSION_TYPE 1180 uint32_t CrVCbUPixelOffsetVDirectionMsb : __CODEGEN_BITFIELD(24, 24) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1181 uint32_t CrVCbUPixelOffsetUDirection : __CODEGEN_BITFIELD(25, 25) ; //!< CRVCBU_PIXEL_OFFSET_U_DIRECTION 1182 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(26, 26) ; //!< Interleave Chroma 1183 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1184 }; 1185 uint32_t Value; 1186 } DW2; 1187 union 1188 { 1189 struct 1190 { 1191 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U(Cb) 1192 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1193 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U(Cb) 1194 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1195 }; 1196 uint32_t Value; 1197 } DW3; 1198 union 1199 { 1200 struct 1201 { 1202 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V(Cr) 1203 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1204 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for V(Cr) 1205 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1206 }; 1207 uint32_t Value; 1208 } DW4; 1209 union 1210 { 1211 struct 1212 { 1213 uint32_t SurfaceMemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< SURFACE_MEMORY_OBJECT_CONTROL_STATE 1214 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 17) ; //!< Reserved 1215 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 1216 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 29) ; //!< Reserved 1217 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(30, 30) ; //!< Vertical Line Stride Offset 1218 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(31, 31) ; //!< Vertical Line Stride 1219 }; 1220 uint32_t Value; 1221 } DW5; 1222 union 1223 { 1224 struct 1225 { 1226 uint32_t SurfaceBaseAddress ; //!< Surface Base Address 1227 }; 1228 uint32_t Value; 1229 } DW6; 1230 union 1231 { 1232 struct 1233 { 1234 uint32_t SurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Surface Base Address High 1235 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1236 }; 1237 uint32_t Value; 1238 } DW7; 1239 1240 //! \name Local enumerations 1241 1242 //! \brief ROTATION 1243 //! \details 1244 //! Rotation is only supported only with AVS function messages and not with 1245 //! HDC direct write and 16x8 AVS messages. 1246 enum ROTATION 1247 { 1248 ROTATION_NOROTATIONOR0DEGREE = 0, //!< No additional details 1249 ROTATION_90DEGREEROTATION = 1, //!< No additional details 1250 ROTATION_180DEGREEROTATION = 2, //!< No additional details 1251 ROTATION_270DEGREEROTATION = 3, //!< No additional details 1252 }; 1253 1254 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION 1255 //! \details 1256 //! Specifies the distance to the U/V values with respect to the even 1257 //! numbered Y channels in the V direction 1258 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION 1259 { 1260 CRVCBU_PIXEL_OFFSET_V_DIRECTION_UNNAMED0 = 0, //!< No additional details 1261 }; 1262 1263 //! \brief PICTURE_STRUCTURE 1264 //! \details 1265 //! Specifies the encoding of the current picture. 1266 enum PICTURE_STRUCTURE 1267 { 1268 PICTURE_STRUCTURE_FRAMEPICTURE = 0, //!< No additional details 1269 PICTURE_STRUCTURE_TOPFIELDPICTURE = 1, //!< No additional details 1270 PICTURE_STRUCTURE_BOTTOMFIELDPICTURE = 2, //!< No additional details 1271 PICTURE_STRUCTURE_INVALID_NOTALLOWED = 3, //!< No additional details 1272 }; 1273 1274 //! \brief TILE_MODE 1275 //! \details 1276 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 1277 //! or YMajor) employed to tile this surface. See Memory Interface Functions 1278 //! for details on memory tiling and restrictions. 1279 enum TILE_MODE 1280 { 1281 TILE_MODE_TILEMODELINEAR = 0, //!< Linear mode (no tiling) 1282 TILE_MODE_TILEMODEXMAJOR = 2, //!< X major tiling 1283 TILE_MODE_TILEMODEYMAJOR = 3, //!< Y major tiling 1284 }; 1285 1286 enum ADDRESS_CONTROL 1287 { 1288 ADDRESS_CONTROL_CLAMP = 0, //!< Clamp 1289 ADDRESS_CONTROL_MIRROR = 1, //!< Mirror 1290 }; 1291 1292 //! \brief MEMORY_COMPRESSION_TYPE 1293 //! \details 1294 //! Specifies the type of memory compression used. 1295 enum MEMORY_COMPRESSION_TYPE 1296 { 1297 MEMORY_COMPRESSION_TYPE_MEDIACOMPRESSION = 0, //!< No additional details 1298 MEMORY_COMPRESSION_TYPE_RENDERCOMPRESSION = 1, //!< No additional details 1299 }; 1300 1301 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1302 //! \details 1303 //! Specifies the distance to the U/V values with respect to the even 1304 //! numbered Y channels in the V direction 1305 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1306 { 1307 CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB_UNNAMED0 = 0, //!< No additional details 1308 }; 1309 1310 //! \brief CRVCBU_PIXEL_OFFSET_U_DIRECTION 1311 //! \details 1312 //! Specifies the distance to the U/V values with respect to the even 1313 //! numbered Y channels in the U direction 1314 enum CRVCBU_PIXEL_OFFSET_U_DIRECTION 1315 { 1316 CRVCBU_PIXEL_OFFSET_U_DIRECTION_UNNAMED0 = 0, //!< No additional details 1317 }; 1318 1319 //! \brief SURFACE_FORMAT 1320 //! \details 1321 //! Specifies the format of the surface. All of the Y and G channels will 1322 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 1323 enum SURFACE_FORMAT 1324 { 1325 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1326 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1327 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1328 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1329 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 1330 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 only 1331 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 AVS only 1332 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 AVS only 1333 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 AVS only 1334 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 AVS only 1335 SURFACE_FORMAT_A8Y8U8V8UNORM = 13, //!< Sample_8x8 AVS only 1336 SURFACE_FORMAT_B8G8R8A8UNORM = 14, //!< Sample_8x8 AVS only 1337 SURFACE_FORMAT_R16G16B16A16 = 15, //!< Sample_8x8 AVS only 1338 SURFACE_FORMAT_PLANAR4228 = 18, //!< Sample_8x8 AVS only 1339 SURFACE_FORMAT_PLANAR42016 = 23, //!< Sample_8x8 AVS only 1340 SURFACE_FORMAT_R16B16UNORM_CRCB = 24, //!< Sample_8x8 AVS only 1341 SURFACE_FORMAT_R16UNORM_CRCB = 25, //!< Sample_8x8 AVS only 1342 SURFACE_FORMAT_Y16UNORM = 26, //!< Sample_8x8 AVS only 1343 }; 1344 1345 //! \brief SURFACE_MEMORY_OBJECT_CONTROL_STATE 1346 //! \details 1347 //! This 7-bit field is used in various state commands and indirect state 1348 //! objects to define cacheability and other attributes related to memory 1349 //! objects. 1350 enum SURFACE_MEMORY_OBJECT_CONTROL_STATE 1351 { 1352 SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0, //!< No additional details 1353 }; 1354 1355 //! \brief TILED_RESOURCE_MODE 1356 //! \details 1357 //! For Sampling Engine, Render Target, and Typed/Untyped Surfaces: 1358 //! This field specifies the tiled resource mode. 1359 //! For other surfaces: 1360 //! This field is ignored. 1361 enum TILED_RESOURCE_MODE 1362 { 1363 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1364 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1365 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1366 }; 1367 1368 //! \name Initializations 1369 1370 //! \brief Explicit member initialization function 1371 MEDIA_SURFACE_STATE_CMD(); 1372 1373 static const size_t dwSize = 8; 1374 static const size_t byteSize = 32; 1375 }; 1376 1377 //! 1378 //! \brief SAMPLER_STATE 1379 //! \details 1380 //! This is the normal sampler state used by all messages that use 1381 //! SAMPLER_STATE except sample_8x8 and deinterlace. The sampler state is 1382 //! stored as an array of up to 16 elements, each of which contains the 1383 //! dwords described here. The start of each element is spaced 4 dwords 1384 //! apart. The first element of the sampler state array is aligned to a 1385 //! 32-byte boundary. 1386 //! 1387 struct SAMPLER_STATE_CMD 1388 { 1389 union 1390 { 1391 struct 1392 { 1393 uint32_t LodAlgorithm : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_ALGORITHM 1394 uint32_t TextureLodBias : __CODEGEN_BITFIELD( 1, 13) ; //!< Texture LOD Bias 1395 uint32_t MinModeFilter : __CODEGEN_BITFIELD(14, 16) ; //!< MIN_MODE_FILTER 1396 uint32_t MagModeFilter : __CODEGEN_BITFIELD(17, 19) ; //!< MAG_MODE_FILTER 1397 uint32_t MipModeFilter : __CODEGEN_BITFIELD(20, 21) ; //!< MIP_MODE_FILTER 1398 uint32_t CoarseLodQualityMode : __CODEGEN_BITFIELD(22, 26) ; //!< COARSE_LOD_QUALITY_MODE 1399 uint32_t LodPreclampMode : __CODEGEN_BITFIELD(27, 28) ; //!< LOD_PRECLAMP_MODE 1400 uint32_t TextureBorderColorMode : __CODEGEN_BITFIELD(29, 29) ; //!< TEXTURE_BORDER_COLOR_MODE 1401 uint32_t CpsLodCompensationEnable : __CODEGEN_BITFIELD(30, 30) ; //!< CPS LOD Compensation Enable 1402 uint32_t SamplerDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Sampler Disable 1403 }; 1404 uint32_t Value; 1405 } DW0; 1406 union 1407 { 1408 struct 1409 { 1410 uint32_t CubeSurfaceControlMode : __CODEGEN_BITFIELD( 0, 0) ; //!< CUBE_SURFACE_CONTROL_MODE 1411 uint32_t ShadowFunction : __CODEGEN_BITFIELD( 1, 3) ; //!< SHADOW_FUNCTION 1412 uint32_t ChromakeyMode : __CODEGEN_BITFIELD( 4, 4) ; //!< CHROMAKEY_MODE 1413 uint32_t ChromakeyIndex : __CODEGEN_BITFIELD( 5, 6) ; //!< ChromaKey Index 1414 uint32_t ChromakeyEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< ChromaKey Enable 1415 uint32_t MaxLod : __CODEGEN_BITFIELD( 8, 19) ; //!< Max LOD 1416 uint32_t MinLod : __CODEGEN_BITFIELD(20, 31) ; //!< Min LOD 1417 }; 1418 uint32_t Value; 1419 } DW1; 1420 union 1421 { 1422 struct 1423 { 1424 uint32_t LodClampMagnificationMode : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_CLAMP_MAGNIFICATION_MODE 1425 uint32_t SrgbDecode : __CODEGEN_BITFIELD( 1, 1) ; //!< SRGB_DECODE 1426 uint32_t ReturnFilterWeightForNullTexels : __CODEGEN_BITFIELD( 2, 2) ; //!< RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1427 uint32_t ReturnFilterWeightForBorderTexels : __CODEGEN_BITFIELD( 3, 3) ; //!< RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1428 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 1429 uint32_t IndirectStatePointer : __CODEGEN_BITFIELD( 6, 23) ; //!< Indirect State Pointer 1430 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1431 }; 1432 uint32_t Value; 1433 } DW2; 1434 union 1435 { 1436 struct 1437 { 1438 uint32_t TczAddressControlMode : __CODEGEN_BITFIELD( 0, 2) ; //!< TCZ_ADDRESS_CONTROL_MODE 1439 uint32_t TcyAddressControlMode : __CODEGEN_BITFIELD( 3, 5) ; //!< TCY_ADDRESS_CONTROL_MODE 1440 uint32_t TcxAddressControlMode : __CODEGEN_BITFIELD( 6, 8) ; //!< TCX_ADDRESS_CONTROL_MODE 1441 uint32_t ReductionTypeEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Reduction Type Enable 1442 uint32_t NonNormalizedCoordinateEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Non-normalized Coordinate Enable 1443 uint32_t TrilinearFilterQuality : __CODEGEN_BITFIELD(11, 12) ; //!< TRILINEAR_FILTER_QUALITY 1444 uint32_t RAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(13, 13) ; //!< R Address Min Filter Rounding Enable 1445 uint32_t RAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(14, 14) ; //!< R Address Mag Filter Rounding Enable 1446 uint32_t VAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(15, 15) ; //!< V Address Min Filter Rounding Enable 1447 uint32_t VAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(16, 16) ; //!< V Address Mag Filter Rounding Enable 1448 uint32_t UAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< U Address Min Filter Rounding Enable 1449 uint32_t UAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< U Address Mag Filter Rounding Enable 1450 uint32_t MaximumAnisotropy : __CODEGEN_BITFIELD(19, 21) ; //!< MAXIMUM_ANISOTROPY 1451 uint32_t ReductionType : __CODEGEN_BITFIELD(22, 23) ; //!< REDUCTION_TYPE 1452 uint32_t AllowLowQualityLodCalculation : __CODEGEN_BITFIELD(24, 24) ; //!< Allow low quality LOD calculation 1453 uint32_t Reserved121 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1454 }; 1455 uint32_t Value; 1456 } DW3; 1457 1458 //! \name Local enumerations 1459 1460 //! \brief LOD_ALGORITHM 1461 //! \details 1462 //! Controls which algorithm is used for LOD calculation. Generally, the EWA 1463 //! approximation algorithm results in higher image quality than the legacy 1464 //! algorithm. 1465 enum LOD_ALGORITHM 1466 { 1467 LOD_ALGORITHM_LEGACY = 0, //!< Use the legacy algorithm for non-anisotropic filtering 1468 LOD_ALGORITHM_EWAAPPROXIMATION = 1, //!< Use the new EWA approximation algorithm for anisotropic filtering 1469 }; 1470 1471 //! \brief MIN_MODE_FILTER 1472 //! \details 1473 //! This field determines how texels are sampled/filtered when a texture is 1474 //! being "minified" (shrunk). For volume maps, this filter mode selection 1475 //! also applies to the 3rd (inter-layer) dimension.See Mag Mode Filter 1476 enum MIN_MODE_FILTER 1477 { 1478 MIN_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1479 MIN_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1480 MIN_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1481 }; 1482 1483 //! \brief MAG_MODE_FILTER 1484 //! \details 1485 //! This field determines how texels are sampled/filtered when a texture is 1486 //! being "magnified" (enlarged). For volume maps, this filter mode 1487 //! selection also applies to the 3rd (inter-layer) dimension. 1488 enum MAG_MODE_FILTER 1489 { 1490 MAG_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1491 MAG_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1492 MAG_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1493 }; 1494 1495 //! \brief MIP_MODE_FILTER 1496 //! \details 1497 //! This field determines if and how mip map levels are chosen and/or 1498 //! combined when texture filtering. 1499 enum MIP_MODE_FILTER 1500 { 1501 MIP_MODE_FILTER_NONE = 0, //!< Disable mip mapping - force use of the mipmap level corresponding to Min LOD. 1502 MIP_MODE_FILTER_NEAREST = 1, //!< Nearest, Select the nearest mip map 1503 MIP_MODE_FILTER_LINEAR = 3, //!< Linearly interpolate between nearest mip maps (combined with linear min/mag filters this is analogous to "Trilinear" filtering). 1504 }; 1505 1506 //! \brief COARSE_LOD_QUALITY_MODE 1507 //! \details 1508 //! This field configures the coarse LOD image quality mode for the 1509 //! sample_d, sample_l, and sample_b messages in the sampling engine. In 1510 //! general, performance will increase and power consumption will decrease 1511 //! with each step of reduced quality (performance gain for sample_l and 1512 //! sample_b will be minimal). 1513 enum COARSE_LOD_QUALITY_MODE 1514 { 1515 COARSE_LOD_QUALITY_MODE_DISABLED = 0, //!< Full quality is enabled, matching prior products 1516 }; 1517 1518 //! \brief LOD_PRECLAMP_MODE 1519 //! \details 1520 //! This field determines whether the computed LOD is clamped to 1521 //! [max,min] mip level 1522 //! before the mag-vs-min determination is performed. 1523 enum LOD_PRECLAMP_MODE 1524 { 1525 LOD_PRECLAMP_MODE_NONE = 0, //!< LOD PreClamp disabled 1526 LOD_PRECLAMP_MODE_OGL = 2, //!< LOD PreClamp enabled (OGL mode) 1527 }; 1528 1529 //! \brief TEXTURE_BORDER_COLOR_MODE 1530 //! \details 1531 //! For some surface formats, the 32 bit border color is decoded differently 1532 //! based on the border color mode. In addition, the default value of 1533 //! channels not included in the surface may be affected by this field. 1534 //! Refer to the "Sampler Output Channel Mapping" table for the values of 1535 //! these channels, and for surface formats that may only support one of 1536 //! these modes. Also refer to the definition of SAMPLER_BORDER_COLOR_STATE 1537 //! for more details on the behavior of the two modes defined by this field. 1538 enum TEXTURE_BORDER_COLOR_MODE 1539 { 1540 TEXTURE_BORDER_COLOR_MODE_OGL = 0, //!< New mode for interpreting the border color 1541 TEXTURE_BORDER_COLOR_MODE_8BIT = 1, //!< Earlier mode for interpreting the border color 1542 }; 1543 1544 //! \brief CUBE_SURFACE_CONTROL_MODE 1545 //! \details 1546 //! When sampling from a SURFTYPE_CUBE surface, this field controls whether 1547 //! the TC* Address Control Mode fields are interpreted as programmed or 1548 //! overridden to TEXCOORDMODE_CUBE. 1549 enum CUBE_SURFACE_CONTROL_MODE 1550 { 1551 CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0, //!< No additional details 1552 CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 1, //!< No additional details 1553 }; 1554 1555 //! \brief SHADOW_FUNCTION 1556 //! \details 1557 //! This field is used for shadow mapping support via the sample_c message 1558 //! type, and specifies the specific comparison operation to be used. The 1559 //! comparison is between the texture sample red channel (except for 1560 //! alpha-only formats which use the alpha channel), and the "ref" value 1561 //! provided in the input message. 1562 enum SHADOW_FUNCTION 1563 { 1564 SHADOW_FUNCTION_PREFILTEROPALWAYS = 0, //!< No additional details 1565 SHADOW_FUNCTION_PREFILTEROPNEVER = 1, //!< No additional details 1566 SHADOW_FUNCTION_PREFILTEROPLESS = 2, //!< No additional details 1567 SHADOW_FUNCTION_PREFILTEROPEQUAL = 3, //!< No additional details 1568 SHADOW_FUNCTION_PREFILTEROPLEQUAL = 4, //!< No additional details 1569 SHADOW_FUNCTION_PREFILTEROPGREATER = 5, //!< No additional details 1570 SHADOW_FUNCTION_PREFILTEROPNOTEQUAL = 6, //!< No additional details 1571 SHADOW_FUNCTION_PREFILTEROPGEQUAL = 7, //!< No additional details 1572 }; 1573 1574 //! \brief CHROMAKEY_MODE 1575 //! \details 1576 //! This field specifies the behavior of the device in the event of a 1577 //! ChromaKey match. This field is ignored if ChromaKey is disabled. 1578 enum CHROMAKEY_MODE 1579 { 1580 CHROMAKEY_MODE_KEYFILTERKILLONANYMATCH = 0, //!< In this mode, if any contributing texel matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this operation is observable only if the Killed Pixel Mask Return flag is set on the input message. 1581 CHROMAKEY_MODE_KEYFILTERREPLACEBLACK = 1, //!< In this mode, each texel that matches the chroma key is replaced with (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha test, etc. 1582 }; 1583 1584 //! \brief LOD_CLAMP_MAGNIFICATION_MODE 1585 //! \details 1586 //! This field allows the flexibility to control how LOD clamping is handled 1587 //! when in magnification mode. 1588 enum LOD_CLAMP_MAGNIFICATION_MODE 1589 { 1590 LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0, //!< When in magnification mode, Sampler will clamp LOD as if the Mip Mode Filteris MIPFILTER_NONE. This is how OpenGL defines magnification, and therefore it isexpected that those drivers would not set this bit. 1591 LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 1, //!< When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter. 1592 }; 1593 1594 //! \brief SRGB_DECODE 1595 //! \details 1596 //! This bit controls whether the 3D sampler will decode an sRGB 1597 //! formatted surface into RGB prior to any filtering operation. 1598 //! When set, it does not convert to linear RGB (via a reverse gamma 1599 //! conversion). This bit is ignored for ASTC formats, which are always 1600 //! converted to linear RGB prior to filtering. 1601 enum SRGB_DECODE 1602 { 1603 SRGB_DECODE_DECODEEXT = 0, //!< When set to 0h, the 3D sampler will convert texels from an sRGB surface to linear RGB prior to filtering and/or returning the value. 1604 SRGB_DECODE_SKIPDECODEEXT = 1, //!< When set to 1h, the 3D sampler will not convert texels to linear RGB before filtering and returning results. 1605 }; 1606 1607 //! \brief RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1608 //! \details 1609 //! This bit, when set, causes samples to return filter_weight of all 1610 //! non-NULL texels in the Alpha channel; Red, Green, and Blue channels are 1611 //! contain the filter result with NULL texels excluded; A non-NULL texel is 1612 //! a texel which does not reference a Null Tile. 1613 //! For cases where Tiled_Resource_Mode is TR_NONE, the result will 1614 //! always be 1.0 since no texels would be NULL. 1615 //! For cases where the surface format contains an Alpha channel, the 1616 //! result returned will be overridden to return the filter weight. 1617 //! For cases where the surface format does not contain Alpha, the result 1618 //! will still be returned in the Alpha Channel. 1619 enum RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1620 { 1621 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE = 0, //!< When programmed to 0h, filter weight will not be returned, and normal data will be returned on the Alpha channel. 1622 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_ENABLE = 1, //!< When programmed to 1h, filter weight will be returned on the Alpha channel rather than the normal data expected on the Alpha channel. 1623 }; 1624 1625 //! \brief RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1626 //! \details 1627 //! This bit, when set, returns the filter_weight in the Alpha channel of 1628 //! all non-border texels. Red, Green, and Blue channels will contain the 1629 //! sample result with border texels excluded. 1630 //! For cases where the surface format contains an Alpha channel, the 1631 //! result returned will be ovewritten to return the filter weight. 1632 //! For cases where the surface format does not contain Alpha, the result 1633 //! will still be returned in the Alpha Channel. 1634 enum RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1635 { 1636 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE = 0, //!< When programmed to 0h, normal data will be returned on RGBA channels, including contribution from border color texels. 1637 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_ENABLE = 1, //!< When programmed to 1h, RGB channels return filter data contributed from non-border color texels, and A channel returns filter weight of contributing texels. 1638 }; 1639 1640 //! \brief TCZ_ADDRESS_CONTROL_MODE 1641 //! \details 1642 //! Controls how the 3rd (TCZ) component of input texture coordinates are 1643 //! mapped to texture map addresses - specifically, how coordinates 1644 //! "outside" the texture are handled (wrap/clamp/mirror).See Address TCX 1645 //! Control Mode above for details 1646 enum TCZ_ADDRESS_CONTROL_MODE 1647 { 1648 TCZ_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1649 TCZ_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1650 TCZ_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1651 TCZ_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1652 TCZ_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1653 TCZ_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1654 TCZ_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1655 TCZ_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces. 1656 }; 1657 1658 //! \brief TCY_ADDRESS_CONTROL_MODE 1659 //! \details 1660 //! Controls how the 2nd (TCY, aka V) component of input texture coordinates 1661 //! are mapped to texture map addresses - specifically, how coordinates 1662 //! "outside" the texture are handled (wrap/clamp/mirror). See Address TCX 1663 //! Control Mode above for details 1664 enum TCY_ADDRESS_CONTROL_MODE 1665 { 1666 TCY_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1667 TCY_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1668 TCY_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1669 TCY_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1670 TCY_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1671 TCY_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1672 TCY_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1673 TCY_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces. 1674 }; 1675 1676 //! \brief TCX_ADDRESS_CONTROL_MODE 1677 //! \details 1678 //! Controls how the 1st (TCX, aka U) component of input texture coordinates 1679 //! are mapped to texture map addresses - specifically, how coordinates 1680 //! "outside" the texture are handled (wrap/clamp/mirror). The setting of 1681 //! this field is subject to being overridden by the Cube Surface Control 1682 //! Mode field when sampling from a SURFTYPE_CUBE surface. 1683 enum TCX_ADDRESS_CONTROL_MODE 1684 { 1685 TCX_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1686 TCX_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1687 TCX_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1688 TCX_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1689 TCX_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1690 TCX_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1691 TCX_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1692 TCX_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces. 1693 }; 1694 1695 //! \brief TRILINEAR_FILTER_QUALITY 1696 //! \details 1697 //! Selects the quality level for the trilinear filter. 1698 enum TRILINEAR_FILTER_QUALITY 1699 { 1700 TRILINEAR_FILTER_QUALITY_FULL = 0, //!< Full Quality. Both mip maps are sampled under all circumstances. 1701 TRILINEAR_FILTER_QUALITY_TRIQUALHIGHMAGCLAMPMIPFILTER = 1, //!< High Quality. 1702 TRILINEAR_FILTER_QUALITY_MED = 2, //!< Medium Quality. 1703 TRILINEAR_FILTER_QUALITY_LOW = 3, //!< Low Quality. 1704 }; 1705 1706 //! \brief MAXIMUM_ANISOTROPY 1707 //! \details 1708 //! This field clamps the maximum value of the anisotropy ratio used by the 1709 //! MAPFILTER_ANISOTROPIC filter (Min or Mag Mode Filter). 1710 enum MAXIMUM_ANISOTROPY 1711 { 1712 MAXIMUM_ANISOTROPY_RATIO21 = 0, //!< At most a 2:1 aspect ratio filter is used 1713 MAXIMUM_ANISOTROPY_RATIO41 = 1, //!< At most a 4:1 aspect ratio filter is used 1714 MAXIMUM_ANISOTROPY_RATIO61 = 2, //!< At most a 6:1 aspect ratio filter is used 1715 MAXIMUM_ANISOTROPY_RATIO81 = 3, //!< At most a 8:1 aspect ratio filter is used 1716 MAXIMUM_ANISOTROPY_RATIO101 = 4, //!< At most a 10:1 aspect ratio filter is used 1717 MAXIMUM_ANISOTROPY_RATIO121 = 5, //!< At most a 12:1 aspect ratio filter is used 1718 MAXIMUM_ANISOTROPY_RATIO141 = 6, //!< At most a 14:1 aspect ratio filter is used 1719 MAXIMUM_ANISOTROPY_RATIO161 = 7, //!< At most a 16:1 aspect ratio filter is used 1720 }; 1721 1722 //! \brief REDUCTION_TYPE 1723 //! \details 1724 //! This field defines the type of reduction that will be performed on the 1725 //! texels in the footprint defined by the Min/Mag/Mip Filter Mode 1726 //! fields. This field is ignored if Reduction Type Enable is 1727 //! disabled. 1728 enum REDUCTION_TYPE 1729 { 1730 REDUCTION_TYPE_STDFILTER = 0, //!< standard filter 1731 REDUCTION_TYPE_COMPARISON = 1, //!< comparison followed by standard filter 1732 REDUCTION_TYPE_MINIMUM = 2, //!< minimum of footprint 1733 REDUCTION_TYPE_MAXIMUM = 3, //!< maximum of footprint 1734 }; 1735 1736 //! \name Initializations 1737 1738 //! \brief Explicit member initialization function 1739 SAMPLER_STATE_CMD(); 1740 1741 static const size_t dwSize = 4; 1742 static const size_t byteSize = 16; 1743 }; 1744 1745 //! 1746 //! \brief SAMPLER_STATE_8x8_AVS_COEFFICIENTS 1747 //! \details 1748 //! ExistsIf = AVS && (Function_mode = 0) 1749 //! 1750 struct SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD 1751 { 1752 union 1753 { 1754 struct 1755 { 1756 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,0] 1757 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,0] 1758 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,1] 1759 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,1] 1760 }; 1761 uint32_t Value; 1762 } DW0; 1763 union 1764 { 1765 struct 1766 { 1767 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,2] 1768 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,2] 1769 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,3] 1770 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,3] 1771 }; 1772 uint32_t Value; 1773 } DW1; 1774 union 1775 { 1776 struct 1777 { 1778 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,4] 1779 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,4] 1780 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,5] 1781 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,5] 1782 }; 1783 uint32_t Value; 1784 } DW2; 1785 union 1786 { 1787 struct 1788 { 1789 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,6] 1790 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,6] 1791 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,7] 1792 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,7] 1793 }; 1794 uint32_t Value; 1795 } DW3; 1796 union 1797 { 1798 struct 1799 { 1800 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1801 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[n,2] 1802 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1X Filter Coefficient[n,3] 1803 }; 1804 uint32_t Value; 1805 } DW4; 1806 union 1807 { 1808 struct 1809 { 1810 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[n,4] 1811 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1X Filter Coefficient[n,5] 1812 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1813 }; 1814 uint32_t Value; 1815 } DW5; 1816 union 1817 { 1818 struct 1819 { 1820 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1821 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1Y Filter Coefficient[n,2] 1822 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[n,3] 1823 }; 1824 uint32_t Value; 1825 } DW6; 1826 union 1827 { 1828 struct 1829 { 1830 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1Y Filter Coefficient[n,4] 1831 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[n,5] 1832 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1833 }; 1834 uint32_t Value; 1835 } DW7; 1836 1837 //! \name Local enumerations 1838 1839 //! \name Initializations 1840 1841 //! \brief Explicit member initialization function 1842 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD(); 1843 1844 static const size_t dwSize = 8; 1845 static const size_t byteSize = 32; 1846 }; 1847 1848 //! 1849 //! \brief SAMPLER_STATE_8x8_AVS 1850 //! \details 1851 //! ExistsIf = AVS 1852 //! 1853 struct SAMPLER_STATE_8x8_AVS_CMD 1854 { 1855 uint32_t Reserved0[3]; //!< Reserved 1856 union 1857 { 1858 struct 1859 { 1860 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 27) ; //!< Reserved 1861 uint32_t Enable8TapFilter : __CODEGEN_BITFIELD(28, 29) ; //!< ENABLE_8_TAP_FILTER 1862 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1863 }; 1864 uint32_t Value; 1865 } DW3; 1866 union 1867 { 1868 struct 1869 { 1870 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 10) ; //!< Reserved 1871 uint32_t ShuffleOutputwritebackForSample8X8 : __CODEGEN_BITFIELD(11, 11) ; //!< SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1872 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 1873 }; 1874 uint32_t Value; 1875 } DW4; 1876 uint32_t Reserved160[11]; //!< Reserved 1877 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient016[17]; //!< DW16..151, Filter Coefficient[0..16] 1878 union 1879 { 1880 struct 1881 { 1882 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 1883 uint32_t Reserved4867 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 1884 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 1885 uint32_t Reserved4871 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 1886 uint32_t MaxDerivative8Pixels : __CODEGEN_BITFIELD( 8, 15) ; //!< Max Derivative 8 Pixels 1887 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 1888 uint32_t DefaultSharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< DEFAULT_SHARPNESS_LEVEL 1889 }; 1890 uint32_t Value; 1891 } DW152; 1892 union 1893 { 1894 struct 1895 { 1896 uint32_t RgbAdaptive : __CODEGEN_BITFIELD( 0, 0) ; //!< RGB_ADAPTIVE 1897 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1898 uint32_t Reserved4898 : __CODEGEN_BITFIELD( 2, 20) ; //!< Reserved 1899 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD(21, 21) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1900 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD(22, 22) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1901 uint32_t Reserved4919 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1902 }; 1903 uint32_t Value; 1904 } DW153; 1905 uint32_t Reserved4928[6]; //!< Reserved 1906 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient1731[15]; //!< DW160..279, Filter Coefficient[17..31] 1907 1908 //! \name Local enumerations 1909 1910 //! \brief ENABLE_8_TAP_FILTER 1911 //! \details 1912 //! Adaptive Filtering (Mode = 11) ExistsIf: 1913 //! R10G10B10A2_UNORM R8G8B8A8_UNORM (AYUV also) R8B8G8A8_UNORM 1914 //! B8G8R8A8_UNORM R16G16B16A16 1915 enum ENABLE_8_TAP_FILTER 1916 { 1917 ENABLE_8_TAP_FILTER_UNNAMED0 = 0, //!< 4-tap filter is only done on all channels. 1918 ENABLE_8_TAP_FILTER_UNNAMED1 = 1, //!< Enable 8-tap Adaptive filter on G-channel. 4-tap filter on other channels. 1919 ENABLE_8_TAP_FILTER_UNNAMED2 = 2, //!< 8-tap filter is done on all channels (UV-ch uses the Y-coefficients) 1920 ENABLE_8_TAP_FILTER_UNNAMED3 = 3, //!< Enable 8-tap Adaptive filter all channels (UV-ch uses the Y-coefficients). 1921 }; 1922 1923 enum SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1924 { 1925 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED0 = 0, //!< Writeback same as Original Sample_8x8 1926 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED1 = 1, //!< Writeback of Sample_8x8 Is Modified to Suite Sample_Unorm 1927 }; 1928 1929 //! \brief DEFAULT_SHARPNESS_LEVEL 1930 //! \details 1931 //! When adaptive scaling is off, determines the balance between sharp and 1932 //! smooth scalers. 1933 enum DEFAULT_SHARPNESS_LEVEL 1934 { 1935 DEFAULT_SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 1936 DEFAULT_SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 1937 }; 1938 1939 //! \brief RGB_ADAPTIVE 1940 //! \details 1941 //! This should be always set to 0 for YUV input and can be enabled/disabled 1942 //! for RGB input. 1943 //! This should be enabled only if we enable 8-tap adaptive filter for 1944 //! RGB input. 1945 enum RGB_ADAPTIVE 1946 { 1947 RGB_ADAPTIVE_DISBLE = 0, //!< Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter 1948 RGB_ADAPTIVE_ENABLE = 1, //!< Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) 1949 }; 1950 1951 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1952 //! \details 1953 //! Only to be enabled if 8-tap Adaptive filter mode is on, eElse it should 1954 //! be disabled. 1955 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1956 { 1957 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISBLE = 0, //!< Disable Adaptive Filter on UV/RB Channels 1958 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLE = 1, //!< Enable Adaptive Filter on UV/RB Channels 1959 }; 1960 1961 //! \brief BYPASS_Y_ADAPTIVE_FILTERING 1962 //! \details 1963 //! When disabled, the Y direction will use Default Sharpness Level 1964 //! to blend between the smooth and sharp filters rather than the calculated 1965 //! value. 1966 enum BYPASS_Y_ADAPTIVE_FILTERING 1967 { 1968 BYPASS_Y_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable Y Adaptive Filtering 1969 BYPASS_Y_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable Y Adaptive Filtering 1970 }; 1971 1972 //! \brief BYPASS_X_ADAPTIVE_FILTERING 1973 //! \details 1974 //! When disabled, the X direction will use Default Sharpness Level 1975 //! to blend between the smooth and sharp filters rather than the calculated 1976 //! value. 1977 enum BYPASS_X_ADAPTIVE_FILTERING 1978 { 1979 BYPASS_X_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable X Adaptive Filtering 1980 BYPASS_X_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable X Adaptive Filtering 1981 }; 1982 1983 //! \name Initializations 1984 1985 //! \brief Explicit member initialization function 1986 SAMPLER_STATE_8x8_AVS_CMD(); 1987 1988 static const size_t dwSize = 280; 1989 static const size_t byteSize = 1120; 1990 }; 1991 1992 //! 1993 //! \brief SAMPLER_INDIRECT_STATE 1994 //! \details 1995 //! Note: There are three variations of this structure, defined separately 1996 //! because their payloads have different lengths. Currently only 1997 //! SAMPLER_INDIRECT_STATE_BORDER_COLOR is fully defined. 1998 //! This structure is pointed to by Indirect State Pointer (SAMPLER_STATE). 1999 //! The interpretation of the border color depends on the Texture Border 2000 //! Color Mode field in SAMPLER_STATE as follows: 2001 //! 2002 //! In 8BIT mode, the border color is 8-bit UNORM format, regardless of the 2003 //! surface format chosen. For surface formats with one or more channels 2004 //! missing (i.e. R5G6R5_UNORM is missing the alpha channel), the value from 2005 //! the border color, if selected, will be used even for the missing 2006 //! channels. 2007 //! 2008 //! In OGL mode, the format of the border color is R32G32B32A32_FLOAT, 2009 //! R32G32B32A32_SINT, or R32G32B32A32_UINT, depending on the surface format 2010 //! chosen. For surface formats with one or more channels missing, the value 2011 //! from the border color is not used for the missing channels, resulting in 2012 //! these channels resulting in the overall default value (0 for colors and 2013 //! 1 for alpha) regardless of whether border color is chosen. The surface 2014 //! formats with "L" and "I" have special behavior with respect to the 2015 //! border color. The border color value used for the replicated channels 2016 //! (RGB for "L" formats and RGBA for "I" formats) comes from the red 2017 //! channel of border color. In these cases, the green and blue channels, 2018 //! and also alpha for "I", of the border color are ignored. 2019 //! 2020 //! 2021 //! 2022 //! 2023 //! 2024 //! The format of this state depends on the Texture Border Color Mode field. 2025 //! 2026 //! 8BIT mode is not supported for surfaces with more than 16 bits in any 2027 //! channel, other than 32-bit float formats which are supported. 2028 //! The conditions under which this color is used depend on the Surface 2029 //! Type - 1D/2D/3D surfaces use the border color when the coordinates 2030 //! extend beyond the surface extent; cube surfaces use the border color for 2031 //! "empty" (disabled) faces. 2032 //! The border color itself is accessed through the texture cache hierarchy 2033 //! rather than the state cache hierarchy. Thus, if the border color is 2034 //! changed in memory, the texture cache must be invalidated and the state 2035 //! cache does not need to be invalidated. 2036 //! MAPFILTER_MONO: The border color is ignored. Border color is fixed at 2037 //! a value of 0 by hardware. 2038 //! 2039 //! 2040 struct SAMPLER_INDIRECT_STATE_CMD 2041 { 2042 union 2043 { 2044 struct 2045 { 2046 uint32_t BorderColorRed : __CODEGEN_BITFIELD( 0, 7) ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2047 uint32_t BorderColorGreen : __CODEGEN_BITFIELD( 8, 15) ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2048 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2049 } Obj0; 2050 struct 2051 { 2052 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2053 uint32_t BorderColorBlue : __CODEGEN_BITFIELD(16, 23) ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2054 uint32_t BorderColorAlpha : __CODEGEN_BITFIELD(24, 31) ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2055 } Obj1; 2056 struct 2057 { 2058 uint32_t BorderColorRed ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2059 } Obj2; 2060 uint32_t Value; 2061 } DW0; 2062 union 2063 { 2064 struct 2065 { 2066 uint32_t BorderColorGreen ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2067 }; 2068 uint32_t Value; 2069 } DW1; 2070 union 2071 { 2072 struct 2073 { 2074 uint32_t BorderColorBlue ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2075 }; 2076 uint32_t Value; 2077 } DW2; 2078 union 2079 { 2080 struct 2081 { 2082 uint32_t BorderColorAlpha ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2083 }; 2084 uint32_t Value; 2085 } DW3; 2086 uint32_t Reserved128[12]; //!< Reserved 2087 2088 //! \name Local enumerations 2089 2090 //! \name Initializations 2091 2092 //! \brief Explicit member initialization function 2093 SAMPLER_INDIRECT_STATE_CMD(); 2094 2095 static const size_t dwSize = 16; 2096 static const size_t byteSize = 64; 2097 }; 2098 2099 }; 2100 2101 #pragma pack() 2102 2103 #endif // __MHW_STATE_HEAP_HWCMD_G12_X_H__