1 2 /*===================== begin_copyright_notice ================================== 3 4 # Copyright (c) 2020-2021, Intel Corporation 5 6 # Permission is hereby granted, free of charge, to any person obtaining a 7 # copy of this software and associated documentation files (the "Software"), 8 # to deal in the Software without restriction, including without limitation 9 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 # and/or sell copies of the Software, and to permit persons to whom the 11 # Software is furnished to do so, subject to the following conditions: 12 13 # The above copyright notice and this permission notice shall be included 14 # in all copies or substantial portions of the Software. 15 16 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 # OTHER DEALINGS IN THE SOFTWARE. 23 24 ======================= end_copyright_notice ==================================*/ 25 //! 26 //! \file mhw_state_heap_hwcmd_xe_xpm.h 27 //! \brief Auto-generated constructors for MHW and states. 28 //! \details This file may not be included outside of g12_X as other components 29 //! should use MHW interface to interact with MHW commands and states. 30 //! 31 32 // DO NOT EDIT 33 34 #ifndef __MHW_STATE_HEAP_HWCMD_XE_XPM_H__ 35 #define __MHW_STATE_HEAP_HWCMD_XE_XPM_H__ 36 37 #pragma once 38 #pragma pack(1) 39 40 #include <cstdint> 41 #include <cstddef> 42 43 class mhw_state_heap_xe_xpm 44 { 45 public: 46 // Internal Macros 47 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 48 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 49 #define __CODEGEN_OP_LENGTH_BIAS 2 50 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 51 GetOpLength(uint32_t uiLength)52 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 53 54 //! 55 //! \brief INTERFACE_DESCRIPTOR_DATA 56 //! \details 57 //! 58 //! 59 struct INTERFACE_DESCRIPTOR_DATA_CMD 60 { 61 union 62 { 63 struct 64 { 65 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 66 uint32_t KernelStartPointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Kernel Start Pointer 67 }; 68 uint32_t Value; 69 } DW0; 70 union 71 { 72 struct 73 { 74 uint32_t KernelStartPointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Kernel Start Pointer High 75 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 76 }; 77 uint32_t Value; 78 } DW1; 79 union 80 { 81 struct 82 { 83 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 84 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Software Exception Enable 85 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 10) ; //!< Reserved 86 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 87 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 88 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 89 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 90 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< FLOATING_POINT_MODE 91 uint32_t ThreadPriority : __CODEGEN_BITFIELD(17, 17) ; //!< THREAD_PRIORITY 92 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< SINGLE_PROGRAM_FLOW 93 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< DENORM_MODE 94 uint32_t ThreadPreemptionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< THREAD_PREEMPTION_DISABLE 95 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 96 }; 97 uint32_t Value; 98 } DW2; 99 union 100 { 101 struct 102 { 103 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 104 uint32_t SamplerCount : __CODEGEN_BITFIELD( 2, 4) ; //!< SAMPLER_COUNT 105 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD( 5, 31) ; //!< Sampler State Pointer 106 }; 107 uint32_t Value; 108 } DW3; 109 union 110 { 111 struct 112 { 113 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD( 0, 4) ; //!< Binding Table Entry Count 114 uint32_t BindingTablePointer : __CODEGEN_BITFIELD( 5, 20) ; //!< Binding Table Pointer 115 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 116 }; 117 uint32_t Value; 118 } DW4; 119 union 120 { 121 struct 122 { 123 uint32_t ConstantUrbEntryReadOffset : __CODEGEN_BITFIELD( 0, 15) ; //!< Constant URB Entry Read Offset 124 uint32_t ConstantIndirectUrbEntryReadLength : __CODEGEN_BITFIELD(16, 31) ; //!< Constant/Indirect URB Entry Read Length 125 }; 126 uint32_t Value; 127 } DW5; 128 union 129 { 130 struct 131 { 132 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD( 0, 9) ; //!< Number of Threads in GPGPU Thread Group 133 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 12) ; //!< Reserved 134 uint32_t OverDispatchControl : __CODEGEN_BITFIELD(13, 14) ; //!< OVER_DISPATCH_CONTROL 135 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 136 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< SHARED_LOCAL_MEMORY_SIZE 137 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Barrier Enable 138 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< ROUNDING_MODE 139 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 140 }; 141 uint32_t Value; 142 } DW6; 143 union 144 { 145 struct 146 { 147 uint32_t CrossThreadConstantDataReadLength : __CODEGEN_BITFIELD( 0, 7) ; //!< Cross-Thread Constant Data Read Length 148 uint32_t Reserved232 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 149 }; 150 uint32_t Value; 151 } DW7; 152 153 //! \name Local enumerations 154 155 //! \brief FLOATING_POINT_MODE 156 //! \details 157 //! Specifies the floating point mode used by the dispatched thread. 158 enum FLOATING_POINT_MODE 159 { 160 FLOATING_POINT_MODE_IEEE_754 = 0, //!< No additional details 161 FLOATING_POINT_MODE_ALTERNATE = 1, //!< No additional details 162 }; 163 164 //! \brief THREAD_PRIORITY 165 //! \details 166 //! Specifies the priority of the thread for dispatch. 167 enum THREAD_PRIORITY 168 { 169 THREAD_PRIORITY_NORMALPRIORITY = 0, //!< No additional details 170 THREAD_PRIORITY_HIGHPRIORITY = 1, //!< No additional details 171 }; 172 173 //! \brief SINGLE_PROGRAM_FLOW 174 //! \details 175 //! Specifies whether the kernel program has a single program flow (SIMDnxm 176 //! with m = 1) or multiple program flows (SIMDnxm with m > 1). 177 enum SINGLE_PROGRAM_FLOW 178 { 179 SINGLE_PROGRAM_FLOW_MULTIPLE = 0, //!< No additional details 180 SINGLE_PROGRAM_FLOW_SINGLE = 1, //!< No additional details 181 }; 182 183 //! \brief DENORM_MODE 184 //! \details 185 //! This field specifies how Float denormalized numbers are handles in the 186 //! dispatched thread. 187 enum DENORM_MODE 188 { 189 DENORM_MODE_FTZ = 0, //!< Float denorms will be flushed to zero when appearing as inputs; denorms will never come out of instructions. Double precision float and half precision float numbers are not flushed to zero. 190 DENORM_MODE_SETBYKERNEL = 1, //!< Denorms will be handled in by kernel. 191 }; 192 193 //! \brief THREAD_PREEMPTION_DISABLE 194 //! \details 195 //! This field specifies whether, when dispatched, the thread is allowed to 196 //! stop in middle on receiving mid-thread pre-emption request. 197 enum THREAD_PREEMPTION_DISABLE 198 { 199 THREAD_PREEMPTION_DISABLE_DISABLE = 0, //!< Thread is pre-empted on receiving pre-emption indication. 200 THREAD_PREEMPTION_DISABLE_ENABLE = 1, //!< Thread is preempted only in case of page-fault. 201 }; 202 203 //! \brief SAMPLER_COUNT 204 //! \details 205 //! Specifies how many samplers (in multiples of 4) the kernel uses. Used 206 //! only for prefetching the associated sampler state entries. 207 //! This field is ignored for child threads. 208 //! If this field is not zero, sampler state is prefetched for the 209 //! first instance of a root thread upon the startup of the media 210 //! pipeline. 211 enum SAMPLER_COUNT 212 { 213 SAMPLER_COUNT_NOSAMPLERSUSED = 0, //!< No additional details 214 SAMPLER_COUNT_BETWEEN1AND4SAMPLERSUSED = 1, //!< No additional details 215 SAMPLER_COUNT_BETWEEN5AND8SAMPLERSUSED = 2, //!< No additional details 216 SAMPLER_COUNT_BETWEEN9AND12SAMPLERSUSED = 3, //!< No additional details 217 SAMPLER_COUNT_BETWEEN13AND16SAMPLERSUSED = 4, //!< No additional details 218 }; 219 220 //! \brief OVER_DISPATCH_CONTROL 221 //! \details 222 //! Over Dispatch Control that enables and controls the amount of GPGPU 223 //! thread over dispatch. 224 enum OVER_DISPATCH_CONTROL 225 { 226 OVER_DISPATCH_CONTROL_NONE = 0, //!< No additional details 227 OVER_DISPATCH_CONTROL_LOW = 1, //!< No additional details 228 OVER_DISPATCH_CONTROL_HIGH = 2, //!< No additional details 229 OVER_DISPATCH_CONTROL_NORMAL = 3, //!< No additional details 230 }; 231 232 //! \brief SHARED_LOCAL_MEMORY_SIZE 233 //! \details 234 //! This field indicates how much Shared Local Memory the thread group 235 //! requires. The amount is specified in 4k blocks, but only powers of 2 are 236 //! allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice. 237 enum SHARED_LOCAL_MEMORY_SIZE 238 { 239 SHARED_LOCAL_MEMORY_SIZE_ENCODES0K = 0, //!< No SLM used 240 SHARED_LOCAL_MEMORY_SIZE_ENCODES1K = 1, //!< No additional details 241 SHARED_LOCAL_MEMORY_SIZE_ENCODES2K = 2, //!< No additional details 242 SHARED_LOCAL_MEMORY_SIZE_ENCODES4K = 3, //!< No additional details 243 SHARED_LOCAL_MEMORY_SIZE_ENCODES8K = 4, //!< No additional details 244 SHARED_LOCAL_MEMORY_SIZE_ENCODES16K = 5, //!< No additional details 245 SHARED_LOCAL_MEMORY_SIZE_ENCODES32K = 6, //!< No additional details 246 SHARED_LOCAL_MEMORY_SIZE_ENCODES64K = 7, //!< No additional details 247 }; 248 249 enum ROUNDING_MODE 250 { 251 ROUNDING_MODE_RTNE = 0, //!< Round to Nearest Even 252 ROUNDING_MODE_RU = 1, //!< Round toward +Infinity 253 ROUNDING_MODE_RD = 2, //!< Round toward -Infinity 254 ROUNDING_MODE_RTZ = 3, //!< Round toward Zero 255 }; 256 257 //! \name Initializations 258 259 //! \brief Explicit member initialization function 260 INTERFACE_DESCRIPTOR_DATA_CMD(); 261 262 static const size_t dwSize = 8; 263 static const size_t byteSize = 32; 264 }; 265 266 //! 267 //! \brief BINDING_TABLE_STATE 268 //! \details 269 //! The binding table binds surfaces to logical resource indices used by 270 //! shaders and other compute engine kernels. It is stored as an array of up 271 //! to 256 elements, each of which contains one dword as defined here. The 272 //! start of each element is spaced one dword apart. The first element of 273 //! the binding table is aligned to a 64-byte boundary. Binding table 274 //! indexes beyond 256 will automatically be mapped to entry 0 by the HW, w/ 275 //! the exception of any messages which support the special indexes 240 276 //! through 255, inclusive. 277 //! 278 struct BINDING_TABLE_STATE_CMD 279 { 280 union 281 { 282 //!< DWORD 0 283 struct 284 { 285 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 286 uint32_t SurfaceStatePointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Surface State Pointer 287 }; 288 uint32_t Value; 289 } DW0; 290 291 //! \name Local enumerations 292 293 //! \name Initializations 294 295 //! \brief Explicit member initialization function 296 BINDING_TABLE_STATE_CMD(); 297 298 static const size_t dwSize = 1; 299 static const size_t byteSize = 4; 300 }; 301 302 //! 303 //! \brief RENDER_SURFACE_STATE 304 //! \details 305 //! This is the normal surface state used by all messages that use 306 //! SURFACE_STATE except those that use MEDIA_SURFACE_STATE. 307 //! 308 struct RENDER_SURFACE_STATE_CMD 309 { 310 union 311 { 312 struct 313 { 314 uint32_t CubeFaceEnablePositiveZ : __CODEGEN_BITFIELD( 0, 0) ; //!< Cube Face Enable - Positive Z 315 uint32_t CubeFaceEnableNegativeZ : __CODEGEN_BITFIELD( 1, 1) ; //!< Cube Face Enable - Negative Z 316 uint32_t CubeFaceEnablePositiveY : __CODEGEN_BITFIELD( 2, 2) ; //!< Cube Face Enable - Positive Y 317 uint32_t CubeFaceEnableNegativeY : __CODEGEN_BITFIELD( 3, 3) ; //!< Cube Face Enable - Negative Y 318 uint32_t CubeFaceEnablePositiveX : __CODEGEN_BITFIELD( 4, 4) ; //!< Cube Face Enable - Positive X 319 uint32_t CubeFaceEnableNegativeX : __CODEGEN_BITFIELD( 5, 5) ; //!< Cube Face Enable - Negative X 320 uint32_t MediaBoundaryPixelMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MEDIA_BOUNDARY_PIXEL_MODE 321 uint32_t RenderCacheReadWriteMode : __CODEGEN_BITFIELD( 8, 8) ; //!< RENDER_CACHE_READ_WRITE_MODE 322 uint32_t SamplerL2OutOfOrderModeDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Sampler L2 Out of Order Mode Disable 323 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(10, 10) ; //!< Vertical Line Stride Offset 324 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(11, 11) ; //!< Vertical Line Stride 325 uint32_t TileMode : __CODEGEN_BITFIELD(12, 13) ; //!< TILE_MODE 326 uint32_t SurfaceHorizontalAlignment : __CODEGEN_BITFIELD(14, 15) ; //!< SURFACE_HORIZONTAL_ALIGNMENT 327 uint32_t SurfaceVerticalAlignment : __CODEGEN_BITFIELD(16, 17) ; //!< SURFACE_VERTICAL_ALIGNMENT 328 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(18, 26) ; //!< SURFACE_FORMAT 329 uint32_t AstcEnable : __CODEGEN_BITFIELD(27, 27) ; //!< ASTC_Enable 330 uint32_t SurfaceArray : __CODEGEN_BITFIELD(28, 28) ; //!< Surface Array 331 uint32_t SurfaceType : __CODEGEN_BITFIELD(29, 31) ; //!< SURFACE_TYPE 332 }; 333 uint32_t Value; 334 } DW0; 335 union 336 { 337 struct 338 { 339 uint32_t SurfaceQpitch : __CODEGEN_BITFIELD( 0, 14) ; //!< Surface QPitch 340 uint32_t SampleTapDiscardDisable : __CODEGEN_BITFIELD(15, 15) ; //!< SAMPLE_TAP_DISCARD_DISABLE 341 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 16) ; //!< Reserved 342 uint32_t DoubleFetchDisable : __CODEGEN_BITFIELD(17, 17) ; //!< DOUBLE_FETCH_DISABLE 343 uint32_t CornerTexelMode : __CODEGEN_BITFIELD(18, 18) ; //!< CORNER_TEXEL_MODE 344 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(19, 23) ; //!< Base Mip Level 345 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(24, 30) ; //!< Memory Object Control State 346 uint32_t EnableUnormPathInColorPipe : __CODEGEN_BITFIELD(31, 31) ; //!< ENABLE_UNORM_PATH_IN_COLOR_PIPE 347 }; 348 uint32_t Value; 349 } DW1; 350 union 351 { 352 struct 353 { 354 uint32_t Width : __CODEGEN_BITFIELD( 0, 13) ; //!< Width 355 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 356 uint32_t Height : __CODEGEN_BITFIELD(16, 29) ; //!< Height 357 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 358 uint32_t DepthStencilResource : __CODEGEN_BITFIELD(31, 31) ; //!< Depth/Stencil Resource 359 }; 360 uint32_t Value; 361 } DW2; 362 union 363 { 364 struct 365 { 366 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 0, 17) ; //!< Surface Pitch 367 uint32_t NullProbingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< NULL_PROBING_ENABLE 368 uint32_t StandardTilingModeExtensions : __CODEGEN_BITFIELD(19, 19) ; //!< STANDARD_TILING_MODE_EXTENSIONS 369 uint32_t TileAddressMappingMode : __CODEGEN_BITFIELD(20, 20) ; //!< TILE_ADDRESS_MAPPING_MODE 370 uint32_t Depth : __CODEGEN_BITFIELD(21, 31) ; //!< Depth 371 }; 372 uint32_t Value; 373 } DW3; 374 union 375 { 376 struct 377 { 378 uint32_t MultisamplePositionPaletteIndex : __CODEGEN_BITFIELD( 0, 2) ; //!< Multisample Position Palette Index 379 uint32_t NumberOfMultisamples : __CODEGEN_BITFIELD( 3, 5) ; //!< NUMBER_OF_MULTISAMPLES 380 uint32_t MultisampledSurfaceStorageFormat : __CODEGEN_BITFIELD( 6, 6) ; //!< MULTISAMPLED_SURFACE_STORAGE_FORMAT 381 uint32_t RenderTargetViewExtent : __CODEGEN_BITFIELD( 7, 17) ; //!< Render Target View Extent 382 uint32_t MinimumArrayElement : __CODEGEN_BITFIELD(18, 28) ; //!< Minimum Array Element 383 uint32_t RenderTargetAndSampleUnormRotation : __CODEGEN_BITFIELD(29, 30) ; //!< RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 384 uint32_t DecompressInL3 : __CODEGEN_BITFIELD(31, 31) ; //!< DECOMPRESS_IN_L3 385 }; 386 uint32_t Value; 387 } DW4; 388 union 389 { 390 struct 391 { 392 uint32_t MipCountLod : __CODEGEN_BITFIELD( 0, 3) ; //!< MIP Count / LOD 393 uint32_t SurfaceMinLod : __CODEGEN_BITFIELD( 4, 7) ; //!< Surface Min LOD 394 uint32_t MipTailStartLod : __CODEGEN_BITFIELD( 8, 11) ; //!< Mip Tail Start LOD 395 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 13) ; //!< Reserved 396 uint32_t CoherencyType : __CODEGEN_BITFIELD(14, 15) ; //!< COHERENCY_TYPE 397 uint32_t L1CachePolicy : __CODEGEN_BITFIELD(16, 18) ; //!< L1_CACHE_POLICY 398 uint32_t Reserved175 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 399 uint32_t EwaDisableForCube : __CODEGEN_BITFIELD(20, 20) ; //!< EWA_DISABLE_FOR_CUBE 400 uint32_t YOffset : __CODEGEN_BITFIELD(21, 23) ; //!< Y Offset 401 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 402 uint32_t XOffset : __CODEGEN_BITFIELD(25, 31) ; //!< X Offset 403 }; 404 uint32_t Value; 405 } DW5; 406 union 407 { 408 struct 409 { 410 uint32_t AuxiliarySurfaceMode : __CODEGEN_BITFIELD( 0, 2) ; //!< AUXILIARY_SURFACE_MODE, ([Surface Format] != 'PLANAR') 411 uint32_t Reserved195 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 412 } Obj0; 413 struct 414 { 415 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved, ([Surface Format] != 'PLANAR') 416 uint32_t AuxiliarySurfacePitch : __CODEGEN_BITFIELD( 3, 12) ; //!< Auxiliary Surface Pitch, ([Surface Format] != 'PLANAR') 417 uint32_t Reserved205 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, ([Surface Format] != 'PLANAR') 418 uint32_t AuxiliarySurfaceQpitch : __CODEGEN_BITFIELD(16, 30) ; //!< Auxiliary Surface QPitch, ([Surface Format] != 'PLANAR') 419 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 420 } Obj1; 421 struct 422 { 423 uint32_t YOffsetForUOrUvPlane : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 424 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, ([Surface Format] == 'PLANAR') 425 uint32_t XOffsetForUOrUvPlane : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 426 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(30, 30) ; //!< HALF_PITCH_FOR_CHROMA, ([Surface Format] == 'PLANAR') 427 uint32_t SeparateUvPlaneEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Separate UV Plane Enable, ([Surface Format] == 'PLANAR') 428 } Obj2; 429 struct 430 { 431 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 14) ; //!< Reserved, ([Surface Format] == 'PLANAR') 432 uint32_t YuvInterpolationEnable : __CODEGEN_BITFIELD(15, 15) ; //!< YUV_INTERPOLATION_ENABLE, 433 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, 434 } Obj3; 435 uint32_t Value; 436 } DW6; 437 union 438 { 439 struct 440 { 441 uint32_t ResourceMinLod : __CODEGEN_BITFIELD( 0, 11) ; //!< Resource Min LOD 442 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 13) ; //!< Reserved 443 uint32_t DisableSupportForMultiGpuAtomics : __CODEGEN_BITFIELD(14, 14) ; //!Disable Support For Multi Gpu Atomics 444 uint32_t DisableSupportMultiGpuPartialWrites : __CODEGEN_BITFIELD(15, 15) ; //!Disable Support Multi Gpu Partial Writes 445 uint32_t ShaderChannelSelectAlpha : __CODEGEN_BITFIELD(16, 18) ; //!< SHADER_CHANNEL_SELECT_ALPHA 446 uint32_t ShaderChannelSelectBlue : __CODEGEN_BITFIELD(19, 21) ; //!< SHADER_CHANNEL_SELECT_BLUE 447 uint32_t ShaderChannelSelectGreen : __CODEGEN_BITFIELD(22, 24) ; //!< SHADER_CHANNEL_SELECT_GREEN 448 uint32_t ShaderChannelSelectRed : __CODEGEN_BITFIELD(25, 27) ; //!< SHADER_CHANNEL_SELECT_RED 449 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 450 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< Memory Compression Enable 451 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< MEMORY_COMPRESSION_MODE 452 }; 453 uint32_t Value; 454 } DW7; 455 union 456 { 457 struct 458 { 459 uint64_t SurfaceBaseAddress ; //!< Surface Base Address 460 }; 461 uint32_t Value[2]; 462 } DW8_9; 463 union 464 { 465 struct 466 { 467 uint64_t QuiltWidth : __CODEGEN_BITFIELD( 0, 4) ; //!< Quilt Width, 468 uint64_t QuiltHeight : __CODEGEN_BITFIELD( 5, 9) ; //!< Quilt Height, 469 uint64_t ClearValueAddressEnable : __CODEGEN_BITFIELD(10, 10) ; //!< CLEAR_VALUE_ADDRESS_ENABLE, 470 uint64_t ProceduralTexture : __CODEGEN_BITFIELD(11, 11) ; //!< Procedural Texture, 471 uint64_t Reserved332 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved, 472 uint64_t YOffsetForVPlane : __CODEGEN_BITFIELD(32, 45) ; //!< Y Offset for V Plane, ([Surface Format] == 'PLANAR') 473 uint64_t Reserved366 : __CODEGEN_BITFIELD(46, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 474 } Obj0; 475 struct 476 { 477 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 47) ; //!< Reserved, ([Surface Format] == 'PLANAR') 478 uint64_t XOffsetForVPlane : __CODEGEN_BITFIELD(48, 61) ; //!< X Offset for V Plane, ([Surface Format] == 'PLANAR') 479 uint64_t Reserved382 : __CODEGEN_BITFIELD(62, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 480 } Obj1; 481 struct 482 { 483 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved, ([Surface Format] == 'PLANAR') 484 uint64_t AuxiliarySurfaceBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Auxiliary Surface Base Address, ([Surface Format] != 'PLANAR') AND [Memory Compression Enable] == 0 485 } Obj2; 486 uint32_t Value[2]; 487 } DW10_11; 488 union 489 { 490 struct 491 { 492 uint32_t CompressionFormat : __CODEGEN_BITFIELD( 0, 4) ; //!< Compression Format 493 uint32_t Reserved_389 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 494 uint32_t ClearAddressLow : __CODEGEN_BITFIELD( 6, 31) ; //!< Clear Address Low 495 }; 496 uint32_t Value; 497 } DW12; 498 union 499 { 500 struct 501 { 502 uint32_t ClearAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Clear Address High 503 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 504 }; 505 uint32_t Value; 506 } DW13; 507 union 508 { 509 struct 510 { 511 uint32_t Reserved448 ; //!< Reserved 512 }; 513 uint32_t Value; 514 } DW14; 515 union 516 { 517 struct 518 { 519 uint32_t Reserved480 ; //!< Reserved 520 }; 521 uint32_t Value; 522 } DW15; 523 524 //! \name Local enumerations 525 526 //! \brief MEDIA_BOUNDARY_PIXEL_MODE 527 //! \details 528 //! 529 //! For 2D Non-Array Surfaces accessed via the Data Port Media Block 530 //! Read Message or Data Port Transpose Read message: 531 //! This field enables control of which rows are returned on vertical 532 //! out-of-bounds reads using the Data Port Media Block Read Message or Data 533 //! Port Transpose Read message. In the description below, frame mode refers 534 //! to Vertical Line Stride = 0, field mode is Vertical Line 535 //! Stride = 1 in which only the even or odd rows are addressable. The 536 //! frame refers to the entire surface, while the field refers only to the 537 //! even or odd rows within the surface. 538 //! For Other Surfaces: 539 //! Reserved : MBZ 540 enum MEDIA_BOUNDARY_PIXEL_MODE 541 { 542 MEDIA_BOUNDARY_PIXEL_MODE_NORMALMODE = 0, //!< The row returned on an out-of-bound access is the closest row in the frame or field. Rows from the opposite field are never returned. 543 MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVEFRAME = 2, //!< The row returned on an out-of-bound access is the closest row in the frame, even if in field mode. 544 MEDIA_BOUNDARY_PIXEL_MODE_INTERLACEDFRAME = 3, //!< In field mode, the row returned on an out-of-bound access is the closest row in the field. In frame mode, even out-of-bound rows return the nearest even row while odd out-of-bound rows return the nearest odd row. 545 }; 546 547 //! \brief RENDER_CACHE_READ_WRITE_MODE 548 //! \details 549 //! For Surfaces accessed via the Data Port to Render Cache: 550 //! This field specifies the way Render Cache treats a write request. If 551 //! unset, Render Cache allocates a write-only cache line for a write miss. 552 //! If set, Render Cache allocates a read-write cache line for a write 553 //! miss. 554 //! For Surfaces accessed via the Sampling Engine or Data Port to 555 //! Texture Cache or Data Cache: 556 //! This field is reserved : MBZ 557 enum RENDER_CACHE_READ_WRITE_MODE 558 { 559 RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLYCACHE = 0, //!< Allocating write-only cache for a write miss 560 RENDER_CACHE_READ_WRITE_MODE_READ_WRITECACHE = 1, //!< Allocating read-write cache for a write miss 561 }; 562 563 //! \brief TILE_MODE 564 //! \details 565 //! This field specifies the type of memory tiling (Linear, XMajor, or 566 //! YMajor) employed to tile this surface. See Memory Interface 567 //! Functions for details on memory tiling and restrictions. 568 enum TILE_MODE 569 { 570 TILE_MODE_LINEAR = 0, //!< Linear mode (no tiling) 571 TILE_MODE_XMAJOR = 2, //!< X major tiling 572 TILE_MODE_YMAJOR = 3, //!< Y major tiling 573 }; 574 575 //! \brief SURFACE_HORIZONTAL_ALIGNMENT 576 //! \details 577 //! For Sampling Engine and Render Target Surfaces: This field specifies the 578 //! horizontal alignment requirement for the surface. 579 enum SURFACE_HORIZONTAL_ALIGNMENT 580 { 581 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN4 = 1, //!< Horizontal alignment factor j = 4 582 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN8 = 2, //!< Horizontal alignment factor j = 8 583 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN16 = 3, //!< Horizontal alignment factor j = 16 584 }; 585 586 //! \brief SURFACE_VERTICAL_ALIGNMENT 587 //! \details 588 //! For Sampling Engine and Render Target Surfaces: This field 589 //! specifies the vertical alignment requirement in elements for the 590 //! surface. Refer to the "Memory Data Formats" chapter for details on how 591 //! this field changes the layout of the surface in memory. An 592 //! element is defined as a pixel in uncompresed surface formats, and 593 //! as a compression block in compressed surface formats. For 594 //! MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample. 595 enum SURFACE_VERTICAL_ALIGNMENT 596 { 597 SURFACE_VERTICAL_ALIGNMENT_VALIGN4 = 1, //!< Vertical alignment factor j = 4 598 SURFACE_VERTICAL_ALIGNMENT_VALIGN8 = 2, //!< Vertical alignment factor j = 8 599 SURFACE_VERTICAL_ALIGNMENT_VALIGN16 = 3, //!< Vertical alignment factor j = 16 600 }; 601 602 //! \brief SURFACE_FORMAT 603 //! \details 604 //! This field specifies the format of the surface or element within this 605 //! surface. This field is ignored for all data port messages other than the 606 //! render target message and streamed vertex buffer write message. Some 607 //! forms of the media block messages use the surface format. 608 enum SURFACE_FORMAT 609 { 610 SURFACE_FORMAT_R32G32B32A32FLOAT = 0, //!< No additional details 611 SURFACE_FORMAT_R32G32B32A32SINT = 1, //!< No additional details 612 SURFACE_FORMAT_R32G32B32A32UINT = 2, //!< No additional details 613 SURFACE_FORMAT_R32G32B32A32UNORM = 3, //!< No additional details 614 SURFACE_FORMAT_R32G32B32A32SNORM = 4, //!< No additional details 615 SURFACE_FORMAT_R64G64FLOAT = 5, //!< No additional details 616 SURFACE_FORMAT_R32G32B32X32FLOAT = 6, //!< No additional details 617 SURFACE_FORMAT_R32G32B32A32SSCALED = 7, //!< No additional details 618 SURFACE_FORMAT_R32G32B32A32USCALED = 8, //!< No additional details 619 SURFACE_FORMAT_R32G32B32A32SFIXED = 32, //!< No additional details 620 SURFACE_FORMAT_R64G64PASSTHRU = 33, //!< No additional details 621 SURFACE_FORMAT_R32G32B32FLOAT = 64, //!< No additional details 622 SURFACE_FORMAT_R32G32B32SINT = 65, //!< No additional details 623 SURFACE_FORMAT_R32G32B32UINT = 66, //!< No additional details 624 SURFACE_FORMAT_R32G32B32UNORM = 67, //!< No additional details 625 SURFACE_FORMAT_R32G32B32SNORM = 68, //!< No additional details 626 SURFACE_FORMAT_R32G32B32SSCALED = 69, //!< No additional details 627 SURFACE_FORMAT_R32G32B32USCALED = 70, //!< No additional details 628 SURFACE_FORMAT_R32G32B32SFIXED = 80, //!< No additional details 629 SURFACE_FORMAT_R16G16B16A16UNORM = 128, //!< No additional details 630 SURFACE_FORMAT_R16G16B16A16SNORM = 129, //!< No additional details 631 SURFACE_FORMAT_R16G16B16A16SINT = 130, //!< No additional details 632 SURFACE_FORMAT_R16G16B16A16UINT = 131, //!< No additional details 633 SURFACE_FORMAT_R16G16B16A16FLOAT = 132, //!< No additional details 634 SURFACE_FORMAT_R32G32FLOAT = 133, //!< No additional details 635 SURFACE_FORMAT_R32G32SINT = 134, //!< No additional details 636 SURFACE_FORMAT_R32G32UINT = 135, //!< No additional details 637 SURFACE_FORMAT_R32FLOATX8X24TYPELESS = 136, //!< No additional details 638 SURFACE_FORMAT_X32TYPELESSG8X24UINT = 137, //!< No additional details 639 SURFACE_FORMAT_L32A32FLOAT = 138, //!< No additional details 640 SURFACE_FORMAT_R32G32UNORM = 139, //!< No additional details 641 SURFACE_FORMAT_R32G32SNORM = 140, //!< No additional details 642 SURFACE_FORMAT_R64FLOAT = 141, //!< No additional details 643 SURFACE_FORMAT_R16G16B16X16UNORM = 142, //!< No additional details 644 SURFACE_FORMAT_R16G16B16X16FLOAT = 143, //!< No additional details 645 SURFACE_FORMAT_A32X32FLOAT = 144, //!< No additional details 646 SURFACE_FORMAT_L32X32FLOAT = 145, //!< No additional details 647 SURFACE_FORMAT_I32X32FLOAT = 146, //!< No additional details 648 SURFACE_FORMAT_R16G16B16A16SSCALED = 147, //!< No additional details 649 SURFACE_FORMAT_R16G16B16A16USCALED = 148, //!< No additional details 650 SURFACE_FORMAT_R32G32SSCALED = 149, //!< No additional details 651 SURFACE_FORMAT_R32G32USCALED = 150, //!< No additional details 652 SURFACE_FORMAT_R32G32SFIXED = 160, //!< No additional details 653 SURFACE_FORMAT_R64PASSTHRU = 161, //!< No additional details 654 SURFACE_FORMAT_B8G8R8A8UNORM = 192, //!< No additional details 655 SURFACE_FORMAT_B8G8R8A8UNORMSRGB = 193, //!< No additional details 656 SURFACE_FORMAT_R10G10B10A2UNORM = 194, //!< No additional details 657 SURFACE_FORMAT_R10G10B10A2UNORMSRGB = 195, //!< No additional details 658 SURFACE_FORMAT_R10G10B10A2UINT = 196, //!< No additional details 659 SURFACE_FORMAT_R10G10B10SNORMA2UNORM = 197, //!< No additional details 660 SURFACE_FORMAT_R8G8B8A8UNORM = 199, //!< No additional details 661 SURFACE_FORMAT_R8G8B8A8UNORMSRGB = 200, //!< No additional details 662 SURFACE_FORMAT_R8G8B8A8SNORM = 201, //!< No additional details 663 SURFACE_FORMAT_R8G8B8A8SINT = 202, //!< No additional details 664 SURFACE_FORMAT_R8G8B8A8UINT = 203, //!< No additional details 665 SURFACE_FORMAT_R16G16UNORM = 204, //!< No additional details 666 SURFACE_FORMAT_R16G16SNORM = 205, //!< No additional details 667 SURFACE_FORMAT_R16G16SINT = 206, //!< No additional details 668 SURFACE_FORMAT_R16G16UINT = 207, //!< No additional details 669 SURFACE_FORMAT_R16G16FLOAT = 208, //!< No additional details 670 SURFACE_FORMAT_B10G10R10A2UNORM = 209, //!< No additional details 671 SURFACE_FORMAT_B10G10R10A2UNORMSRGB = 210, //!< No additional details 672 SURFACE_FORMAT_R11G11B10FLOAT = 211, //!< No additional details 673 SURFACE_FORMAT_R10G10B10FLOATA2UNORM = 213, //!< No additional details 674 SURFACE_FORMAT_R32SINT = 214, //!< No additional details 675 SURFACE_FORMAT_R32UINT = 215, //!< No additional details 676 SURFACE_FORMAT_R32FLOAT = 216, //!< No additional details 677 SURFACE_FORMAT_R24UNORMX8TYPELESS = 217, //!< No additional details 678 SURFACE_FORMAT_X24TYPELESSG8UINT = 218, //!< No additional details 679 SURFACE_FORMAT_L32UNORM = 221, //!< No additional details 680 SURFACE_FORMAT_A32UNORM = 222, //!< No additional details 681 SURFACE_FORMAT_L16A16UNORM = 223, //!< No additional details 682 SURFACE_FORMAT_I24X8UNORM = 224, //!< No additional details 683 SURFACE_FORMAT_L24X8UNORM = 225, //!< No additional details 684 SURFACE_FORMAT_A24X8UNORM = 226, //!< No additional details 685 SURFACE_FORMAT_I32FLOAT = 227, //!< No additional details 686 SURFACE_FORMAT_L32FLOAT = 228, //!< No additional details 687 SURFACE_FORMAT_A32FLOAT = 229, //!< No additional details 688 SURFACE_FORMAT_X8B8UNORMG8R8SNORM = 230, //!< No additional details 689 SURFACE_FORMAT_A8X8UNORMG8R8SNORM = 231, //!< No additional details 690 SURFACE_FORMAT_B8X8UNORMG8R8SNORM = 232, //!< No additional details 691 SURFACE_FORMAT_B8G8R8X8UNORM = 233, //!< No additional details 692 SURFACE_FORMAT_B8G8R8X8UNORMSRGB = 234, //!< No additional details 693 SURFACE_FORMAT_R8G8B8X8UNORM = 235, //!< No additional details 694 SURFACE_FORMAT_R8G8B8X8UNORMSRGB = 236, //!< No additional details 695 SURFACE_FORMAT_R9G9B9E5SHAREDEXP = 237, //!< No additional details 696 SURFACE_FORMAT_B10G10R10X2UNORM = 238, //!< No additional details 697 SURFACE_FORMAT_L16A16FLOAT = 240, //!< No additional details 698 SURFACE_FORMAT_R32UNORM = 241, //!< No additional details 699 SURFACE_FORMAT_R32SNORM = 242, //!< No additional details 700 SURFACE_FORMAT_R10G10B10X2USCALED = 243, //!< No additional details 701 SURFACE_FORMAT_R8G8B8A8SSCALED = 244, //!< No additional details 702 SURFACE_FORMAT_R8G8B8A8USCALED = 245, //!< No additional details 703 SURFACE_FORMAT_R16G16SSCALED = 246, //!< No additional details 704 SURFACE_FORMAT_R16G16USCALED = 247, //!< No additional details 705 SURFACE_FORMAT_R32SSCALED = 248, //!< No additional details 706 SURFACE_FORMAT_R32USCALED = 249, //!< No additional details 707 SURFACE_FORMAT_B5G6R5UNORM = 256, //!< No additional details 708 SURFACE_FORMAT_B5G6R5UNORMSRGB = 257, //!< No additional details 709 SURFACE_FORMAT_B5G5R5A1UNORM = 258, //!< No additional details 710 SURFACE_FORMAT_B5G5R5A1UNORMSRGB = 259, //!< No additional details 711 SURFACE_FORMAT_B4G4R4A4UNORM = 260, //!< No additional details 712 SURFACE_FORMAT_B4G4R4A4UNORMSRGB = 261, //!< No additional details 713 SURFACE_FORMAT_R8G8UNORM = 262, //!< No additional details 714 SURFACE_FORMAT_R8G8SNORM = 263, //!< No additional details 715 SURFACE_FORMAT_R8G8SINT = 264, //!< No additional details 716 SURFACE_FORMAT_R8G8UINT = 265, //!< No additional details 717 SURFACE_FORMAT_R16UNORM = 266, //!< No additional details 718 SURFACE_FORMAT_R16SNORM = 267, //!< No additional details 719 SURFACE_FORMAT_R16SINT = 268, //!< No additional details 720 SURFACE_FORMAT_R16UINT = 269, //!< No additional details 721 SURFACE_FORMAT_R16FLOAT = 270, //!< No additional details 722 SURFACE_FORMAT_A8P8UNORMPALETTE0 = 271, //!< No additional details 723 SURFACE_FORMAT_A8P8UNORMPALETTE1 = 272, //!< No additional details 724 SURFACE_FORMAT_I16UNORM = 273, //!< No additional details 725 SURFACE_FORMAT_L16UNORM = 274, //!< No additional details 726 SURFACE_FORMAT_A16UNORM = 275, //!< No additional details 727 SURFACE_FORMAT_L8A8UNORM = 276, //!< No additional details 728 SURFACE_FORMAT_I16FLOAT = 277, //!< No additional details 729 SURFACE_FORMAT_L16FLOAT = 278, //!< No additional details 730 SURFACE_FORMAT_A16FLOAT = 279, //!< No additional details 731 SURFACE_FORMAT_L8A8UNORMSRGB = 280, //!< No additional details 732 SURFACE_FORMAT_R5G5SNORMB6UNORM = 281, //!< No additional details 733 SURFACE_FORMAT_B5G5R5X1UNORM = 282, //!< No additional details 734 SURFACE_FORMAT_B5G5R5X1UNORMSRGB = 283, //!< No additional details 735 SURFACE_FORMAT_R8G8SSCALED = 284, //!< No additional details 736 SURFACE_FORMAT_R8G8USCALED = 285, //!< No additional details 737 SURFACE_FORMAT_R16SSCALED = 286, //!< No additional details 738 SURFACE_FORMAT_R16USCALED = 287, //!< No additional details 739 SURFACE_FORMAT_P8A8UNORMPALETTE0 = 290, //!< No additional details 740 SURFACE_FORMAT_P8A8UNORMPALETTE1 = 291, //!< No additional details 741 SURFACE_FORMAT_A1B5G5R5UNORM = 292, //!< No additional details 742 SURFACE_FORMAT_A4B4G4R4UNORM = 293, //!< No additional details 743 SURFACE_FORMAT_L8A8UINT = 294, //!< No additional details 744 SURFACE_FORMAT_L8A8SINT = 295, //!< No additional details 745 SURFACE_FORMAT_R8UNORM = 320, //!< No additional details 746 SURFACE_FORMAT_R8SNORM = 321, //!< No additional details 747 SURFACE_FORMAT_R8SINT = 322, //!< No additional details 748 SURFACE_FORMAT_R8UINT = 323, //!< No additional details 749 SURFACE_FORMAT_A8UNORM = 324, //!< No additional details 750 SURFACE_FORMAT_I8UNORM = 325, //!< No additional details 751 SURFACE_FORMAT_L8UNORM = 326, //!< No additional details 752 SURFACE_FORMAT_P4A4UNORMPALETTE0 = 327, //!< No additional details 753 SURFACE_FORMAT_A4P4UNORMPALETTE0 = 328, //!< No additional details 754 SURFACE_FORMAT_R8SSCALED = 329, //!< No additional details 755 SURFACE_FORMAT_R8USCALED = 330, //!< No additional details 756 SURFACE_FORMAT_P8UNORMPALETTE0 = 331, //!< No additional details 757 SURFACE_FORMAT_L8UNORMSRGB = 332, //!< No additional details 758 SURFACE_FORMAT_P8UNORMPALETTE1 = 333, //!< No additional details 759 SURFACE_FORMAT_P4A4UNORMPALETTE1 = 334, //!< No additional details 760 SURFACE_FORMAT_A4P4UNORMPALETTE1 = 335, //!< No additional details 761 SURFACE_FORMAT_Y8UNORM = 336, //!< No additional details 762 SURFACE_FORMAT_L8UINT = 338, //!< No additional details 763 SURFACE_FORMAT_L8SINT = 339, //!< No additional details 764 SURFACE_FORMAT_I8UINT = 340, //!< No additional details 765 SURFACE_FORMAT_I8SINT = 341, //!< No additional details 766 SURFACE_FORMAT_DXT1RGBSRGB = 384, //!< No additional details 767 SURFACE_FORMAT_R1UNORM = 385, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 768 SURFACE_FORMAT_YCRCBNORMAL = 386, //!< No additional details 769 SURFACE_FORMAT_YCRCBSWAPUVY = 387, //!< No additional details 770 SURFACE_FORMAT_P2UNORMPALETTE0 = 388, //!< No additional details 771 SURFACE_FORMAT_P2UNORMPALETTE1 = 389, //!< No additional details 772 SURFACE_FORMAT_BC1UNORM = 390, //!< (DXT1) 773 SURFACE_FORMAT_BC2UNORM = 391, //!< (DXT2/3) 774 SURFACE_FORMAT_BC3UNORM = 392, //!< (DXT4/5) 775 SURFACE_FORMAT_BC4UNORM = 393, //!< No additional details 776 SURFACE_FORMAT_BC5UNORM = 394, //!< No additional details 777 SURFACE_FORMAT_BC1UNORMSRGB = 395, //!< (DXT1_SRGB) 778 SURFACE_FORMAT_BC2UNORMSRGB = 396, //!< (DXT2/3_SRGB) 779 SURFACE_FORMAT_BC3UNORMSRGB = 397, //!< (DXT4/5_SRGB) 780 SURFACE_FORMAT_MONO8 = 398, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 781 SURFACE_FORMAT_YCRCBSWAPUV = 399, //!< No additional details 782 SURFACE_FORMAT_YCRCBSWAPY = 400, //!< No additional details 783 SURFACE_FORMAT_DXT1RGB = 401, //!< No additional details 784 SURFACE_FORMAT_FXT1 = 402, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 785 SURFACE_FORMAT_R8G8B8UNORM = 403, //!< No additional details 786 SURFACE_FORMAT_R8G8B8SNORM = 404, //!< No additional details 787 SURFACE_FORMAT_R8G8B8SSCALED = 405, //!< No additional details 788 SURFACE_FORMAT_R8G8B8USCALED = 406, //!< No additional details 789 SURFACE_FORMAT_R64G64B64A64FLOAT = 407, //!< No additional details 790 SURFACE_FORMAT_R64G64B64FLOAT = 408, //!< No additional details 791 SURFACE_FORMAT_BC4SNORM = 409, //!< No additional details 792 SURFACE_FORMAT_BC5SNORM = 410, //!< No additional details 793 SURFACE_FORMAT_R16G16B16FLOAT = 411, //!< No additional details 794 SURFACE_FORMAT_R16G16B16UNORM = 412, //!< No additional details 795 SURFACE_FORMAT_R16G16B16SNORM = 413, //!< No additional details 796 SURFACE_FORMAT_R16G16B16SSCALED = 414, //!< No additional details 797 SURFACE_FORMAT_R16G16B16USCALED = 415, //!< No additional details 798 SURFACE_FORMAT_BC6HSF16 = 417, //!< No additional details 799 SURFACE_FORMAT_BC7UNORM = 418, //!< No additional details 800 SURFACE_FORMAT_BC7UNORMSRGB = 419, //!< No additional details 801 SURFACE_FORMAT_BC6HUF16 = 420, //!< No additional details 802 SURFACE_FORMAT_PLANAR4208 = 421, //!< No additional details 803 SURFACE_FORMAT_PLANAR42016 = 422, //!< No additional details 804 SURFACE_FORMAT_R8G8B8UNORMSRGB = 424, //!< No additional details 805 SURFACE_FORMAT_ETC1RGB8 = 425, //!< No additional details 806 SURFACE_FORMAT_ETC2RGB8 = 426, //!< No additional details 807 SURFACE_FORMAT_EACR11 = 427, //!< No additional details 808 SURFACE_FORMAT_EACRG11 = 428, //!< No additional details 809 SURFACE_FORMAT_EACSIGNEDR11 = 429, //!< No additional details 810 SURFACE_FORMAT_EACSIGNEDRG11 = 430, //!< No additional details 811 SURFACE_FORMAT_ETC2SRGB8 = 431, //!< No additional details 812 SURFACE_FORMAT_R16G16B16UINT = 432, //!< No additional details 813 SURFACE_FORMAT_R16G16B16SINT = 433, //!< No additional details 814 SURFACE_FORMAT_R32SFIXED = 434, //!< No additional details 815 SURFACE_FORMAT_R10G10B10A2SNORM = 435, //!< No additional details 816 SURFACE_FORMAT_R10G10B10A2USCALED = 436, //!< No additional details 817 SURFACE_FORMAT_R10G10B10A2SSCALED = 437, //!< No additional details 818 SURFACE_FORMAT_R10G10B10A2SINT = 438, //!< No additional details 819 SURFACE_FORMAT_B10G10R10A2SNORM = 439, //!< No additional details 820 SURFACE_FORMAT_B10G10R10A2USCALED = 440, //!< No additional details 821 SURFACE_FORMAT_B10G10R10A2SSCALED = 441, //!< No additional details 822 SURFACE_FORMAT_B10G10R10A2UINT = 442, //!< No additional details 823 SURFACE_FORMAT_B10G10R10A2SINT = 443, //!< No additional details 824 SURFACE_FORMAT_R64G64B64A64PASSTHRU = 444, //!< No additional details 825 SURFACE_FORMAT_R64G64B64PASSTHRU = 445, //!< No additional details 826 SURFACE_FORMAT_ETC2RGB8PTA = 448, //!< No additional details 827 SURFACE_FORMAT_ETC2SRGB8PTA = 449, //!< No additional details 828 SURFACE_FORMAT_ETC2EACRGBA8 = 450, //!< No additional details 829 SURFACE_FORMAT_ETC2EACSRGB8A8 = 451, //!< No additional details 830 SURFACE_FORMAT_R8G8B8UINT = 456, //!< No additional details 831 SURFACE_FORMAT_R8G8B8SINT = 457, //!< No additional details 832 SURFACE_FORMAT_RAW = 511, //!< No additional details 833 }; 834 835 //! \brief SURFACE_TYPE 836 //! \details 837 //! This field defines the type of the surface. 838 enum SURFACE_TYPE 839 { 840 SURFACE_TYPE_SURFTYPE1D = 0, //!< Defines a 1-dimensional map or array of maps 841 SURFACE_TYPE_SURFTYPE2D = 1, //!< Defines a 2-dimensional map or array of maps 842 SURFACE_TYPE_SURFTYPE3D = 2, //!< Defines a 3-dimensional (volumetric) map 843 SURFACE_TYPE_SURFTYPECUBE = 3, //!< Defines a cube map or array of cube maps 844 SURFACE_TYPE_SURFTYPEBUFFER = 4, //!< Defines an element in a buffer 845 SURFACE_TYPE_SURFTYPESTRBUF = 5, //!< Defines a structured buffer surface 846 SURFACE_TYPE_SURFTYPENULL = 7, //!< Defines a null surface 847 }; 848 849 //! \brief SAMPLE_TAP_DISCARD_DISABLE 850 //! \details 851 //! This bit forces sample tap discard filter mode to be disabled for this 852 //! surface state. This bit must be set for surfaces which are no Alpha 853 //! Channel such as R8G8B8_UNORM. 854 enum SAMPLE_TAP_DISCARD_DISABLE 855 { 856 SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0, //!< When programmed to 0h, Sample Tap Discard filter mode is allowed and is not disabled by this bit. This bit is ignored if Sample Tap Discard is not enabled in the Sampler State. 857 SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 1, //!< When programmed to 1h, Sample Tap Discard filter mode will be disabled even if enabled through Sampler State 858 }; 859 860 //! \brief DOUBLE_FETCH_DISABLE 861 //! \details 862 //! This bit is intended to disable the "double fetch" of adjacent 863 //! cache-lines in most all cases. Double fetch is a performance mode, but 864 //! for some surface types for formats it may be lower performance due to 865 //! fetching unused cache-lines. 866 enum DOUBLE_FETCH_DISABLE 867 { 868 DOUBLE_FETCH_DISABLE_ENABLE = 0, //!< When programmed to 0h, double fetches are allowed. 869 DOUBLE_FETCH_DISABLE_DISABLE = 1, //!< When programmed to 1h, double fetches are disabled. 870 }; 871 872 //! \brief CORNER_TEXEL_MODE 873 //! \details 874 //! This field, when ENABLED, indicates when a surface is using corner 875 //! texel-mode for sampling. 876 //! Corner Texel Mode is ignored for Planar YUV/YCrCb surface 877 //! formats. 878 //! Corner Texel Mode is ignored for sample_8X8 and sample_unorm messasge 879 //! types. 880 //! <!--StartFragment-->Does not support legacy sampler features set0 See 881 //! legacy sampler page for more details<!--EndFragment--> 882 enum CORNER_TEXEL_MODE 883 { 884 CORNER_TEXEL_MODE_DISABLE = 0, //!< When programmed to 0h, Corner Texel Mode is disabled. This means texel references are shifted a half-texel from the upper-right corner of the texture map which is the standard texel referencemode. 885 CORNER_TEXEL_MODE_ENABLE = 1, //!< When programmed to 1h, Corner Texel Mode is enabled. The location of a sampled texel on a texture map is shifted a half-texel to the upper-left, meaning texel (0,0) isin the exact upper-left corner of the surface. 886 }; 887 888 //! \brief ENABLE_UNORM_PATH_IN_COLOR_PIPE 889 //! \details 890 //! Enables Unorm Path (fixed Point Conversion of floating point for fill 891 //! and blend in DAPRSS) in color Pipe. 892 enum ENABLE_UNORM_PATH_IN_COLOR_PIPE 893 { 894 ENABLE_UNORM_PATH_IN_COLOR_PIPE_DISABLE = 0, //!< Disables Unorm path in Color Pipe. 895 ENABLE_UNORM_PATH_IN_COLOR_PIPE_ENABLE = 1, //!< Enables Unorm Path in Color Pipe. 896 }; 897 898 //! \brief NULL_PROBING_ENABLE 899 //! \details 900 //! This field is applicable for Render Targets only. It is used for 901 //! enabling NULL tile probing as defined under Tiled Resources. This 902 //! probing guarantees consistent read data return after previous write 903 //! including fast clears. SW must enable this bit for render target only if 904 //! surface contains NULL tiles and read after write consistency is 905 //! required. 906 enum NULL_PROBING_ENABLE 907 { 908 NULL_PROBING_ENABLE_DISABLE = 0, //!< No additional details 909 NULL_PROBING_ENABLE_ENABLE = 1, //!< No additional details 910 }; 911 912 //! \brief STANDARD_TILING_MODE_EXTENSIONS 913 //! \details 914 //! It changes in the MIP Tail Packing. When enabled (programmed to 1h), 915 //! MIP Tail packing for Volumetric and 1D are changed as defined in the 916 //! Surface Layout and Tiling section of the doc. 917 //! 918 enum STANDARD_TILING_MODE_EXTENSIONS 919 { 920 STANDARD_TILING_MODE_EXTENSIONS_DISABLE = 0, //!< When programmed to 0h, the Gen11 extensions to support Standard Tiling are disabled. Behvaior reverts to Gen10 and Gen9 Miptail packing. 921 STANDARD_TILING_MODE_EXTENSIONS_ENABLE = 1, //!< When programmed to 1h, the Gen11 changes to support Standard Tiling Extensions are enabled. See the Surface Layout and Tiling section for details. 922 }; 923 924 //! \brief TILE_ADDRESS_MAPPING_MODE 925 //! \details 926 //! This field is used to select between Gen9 Tile Address Mapping mode and 927 //! Gen10 for TileYs and TileYf. 928 enum TILE_ADDRESS_MAPPING_MODE 929 { 930 TILE_ADDRESS_MAPPING_MODE_GEN9 = 0, //!< Gen9 Tile Address Mapping ModeThis field should always be programmed to 0h. Gen9 Tiling mode is the standard tile layout for 3D. 931 TILE_ADDRESS_MAPPING_MODE_GEN10 = 1, //!< Gen10+ Tile Address Mapping Mode (for Standard Tiling).This field should NOT be programmed to 1h as the Gen10 Tiling Address Mapping mode is not supported by SW. 932 }; 933 934 //! \brief NUMBER_OF_MULTISAMPLES 935 //! \details 936 //! This field indicates the number of multisamples on the surface. 937 enum NUMBER_OF_MULTISAMPLES 938 { 939 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT1 = 0, //!< No additional details 940 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT2 = 1, //!< No additional details 941 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT4 = 2, //!< No additional details 942 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT8 = 3, //!< No additional details 943 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT16 = 4, //!< No additional details 944 }; 945 946 //! \brief MULTISAMPLED_SURFACE_STORAGE_FORMAT 947 //! \details 948 //! This field indicates the storage format of the multisampled surface. 949 enum MULTISAMPLED_SURFACE_STORAGE_FORMAT 950 { 951 MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0, //!< Multsampled surface was/is rendered as a render target 952 MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTHSTENCIL = 1, //!< Multisampled surface was rendered as a depth or stencil buffer 953 }; 954 955 //! \brief RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 956 //! \details 957 //! For Render Target Surfaces: 958 //! This field specifies the rotation of this render target surface 959 //! when being written to memory. 960 enum RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 961 { 962 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0, //!< No rotation (0 degrees) 963 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 1, //!< Rotate by 90 degrees 964 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 2, //!< Rotate by 180 degrees [for sample_unorm message] 965 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 3, //!< Rotate by 270 degrees 966 }; 967 968 enum DECOMPRESS_IN_L3 969 { 970 DECOMPRESS_IN_L3_DISABLE = 0, //!< When this field is set to 0h, the associated compressible surface, when accessed by sampler, can be compressed in L3. If the surface is not compressible, this bit field is ignored. 971 DECOMPRESS_IN_L3_ENABLE = 1, //!< When this field is set to 1h, the associated compressible surface, when accessed by sampler, will be uncompressed in L3. If the surface is not compressible, this bit field is ignored. 972 }; 973 974 //! \brief MIP_TAIL_START_LOD 975 //! \details 976 //! For Sampling Engine, Render Target, and Typed Surfaces: 977 //! This field indicates which LOD is the first one in the MIP tail 978 //! if Tiled Mode is programmed to Tile64. The MIP tail has a different 979 //! layout than the rest of the surface. Refer to the Memory Data 980 //! Formats section for more details. For other tiled formats and 981 //! linear surfaces: This field is ignored. 982 enum DISAPLE_MIP_SURFACE 983 { 984 MIP_TAIL_FOR_TILE64_DISABLE = 15, //To disable Mip Tail for a Tile64 surface, this field must be programmed to a MIP that is larger than those present in the surface (i.e. 15). 985 }; 986 987 //! \brief COHERENCY_TYPE 988 //! \details 989 //! Specifies the type of coherency maintained for this surface. 990 enum COHERENCY_TYPE 991 { 992 COHERENCY_TYPE_GPUCOHERENT = 0, //!< Surface memory is kept coherent with GPU threads using GPU read/write ordering rules. Surface memory is backed by system memory but is not kept coherent with CPU (LLC). 993 COHERENCY_TYPE_IACOHERENT = 1, //!< Surface memory is kept coherent with CPU (LLC). 994 }; 995 996 //! \brief TILED_RESOURCE_MODE 997 //! \details 998 //! For Sampling Engine, Render Target, and Typed/Untyped Surfaces: 999 //! This field specifies the tiled resource mode. 1000 //! 1001 //! For other surfaces: 1002 //! This field is ignored. 1003 enum TILED_RESOURCE_MODE 1004 { 1005 TILED_RESOURCE_MODE_NONE = 0, //!< No tiled resource 1006 TILED_RESOURCE_MODE_4KB = 1, //!< 4KB tiled resources 1007 TILED_RESOURCE_MODE_TILEYF = 1, //!< 4KB tiled resources 1008 TILED_RESOURCE_MODE_64KB = 2, //!< 64KB tiled resources 1009 TILED_RESOURCE_MODE_TILEYS = 2, //!< 64KB tiled resources 1010 }; 1011 1012 //! \brief EWA_DISABLE_FOR_CUBE 1013 //! \details 1014 //! Specifies if EWA mode for LOD quality improvement needs to be disabled 1015 //! for cube maps. 1016 enum EWA_DISABLE_FOR_CUBE 1017 { 1018 EWA_DISABLE_FOR_CUBE_ENABLE = 0, //!< EWA is enabled for cube maps 1019 EWA_DISABLE_FOR_CUBE_DISABLE = 1, //!< EWA is disabled for cube maps 1020 }; 1021 1022 //! \brief AUXILIARY_SURFACE_MODE 1023 //! \details 1024 //! Specifies what type of surface the Auxiliary surface is. The Auxiliary 1025 //! surface has its own base address and pitch, but otherwise shares or 1026 //! overrides other fields set for the primary surface, detailed in the 1027 //! programming notes below. 1028 enum AUXILIARY_SURFACE_MODE 1029 { 1030 AUXILIARY_SURFACE_MODE_AUXNONE = 0, //!< No Auxiliary surface is used 1031 AUXILIARY_SURFACE_MODE_AUXCCSD = 1, //!< The Auxiliary surface is a CCS (Color Control Surface) with color compression disabled. The Auxiliary surface is a MCS (Multisample Control Surface) with MSAA compression disabled. MCS is tiled y 1032 AUXILIARY_SURFACE_MODE_AUXAPPEND = 2, //!< The Auxiliary surface is an append buffer 1033 AUXILIARY_SURFACE_MODE_AUXMCSLCE = 4, //!< Enables lossless compresion on the top of MSAA compression for RTs with Number of Multisamples not equal to MULTISAMPLECOUNT_1.CCS is tiling format is linear.MCS tiling format is always tiledY. 1034 AUXILIARY_SURFACE_MODE_AUXCCSE = 5, //!< If Number of multisamples = 1, programming this value means lossless compression is enabled for that surface.Auxiliary surface is a CCS with linear tiling. If Number of multisamples > 1, programming this value means MSAA compression is enabled for that surface. Auxillary surafce is MSC with tile y. 1035 }; 1036 1037 //! \brief YUV_INTERPOLATION_ENABLE 1038 //! \details 1039 //! This bit controls whether a Non-Planar YUV4:2:2 and Planar YUV4:2:0 1040 //! surface use interpolated or replicated U and V channels for input to the 1041 //! Sampler filter. Programming to 1h causes interpolation of U and V 1042 //! channels. In this case the chrominance for odd pixels is computed by an 1043 //! interpolation between adjacent even pixels. Programming to 0h causes the 1044 //! chrominance to be copied from the pixel to the left. 1045 enum YUV_INTERPOLATION_ENABLE 1046 { 1047 YUV_INTERPOLATION_ENABLE_DISABLE = 0, //!< Programming to 0h causes the sampler to replicate U and V channels. This will lead to lower quality in certain cases where the YUV surface is being filtered (e.g. linear). 1048 YUV_INTERPOLATION_ENABLE_ENABLE = 1, //!< Programming to 1h causes the sampler to interpolate the U and V channels between the horizonally neighboring pixels. This will improvie image quality if the surface is being filtered. 1049 }; 1050 1051 //! \brief HALF_PITCH_FOR_CHROMA 1052 //! \details 1053 //! style="font-family: "Arial","sans-serif"; 1054 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1055 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1056 //! mso-bidi-language: AR-SA;"><font color="#000000">This bit enables 1057 //! support for half-pitch chroma planes for Planar YUV surfaces. It is 1058 //! ignored for Non-Planar surfaces. For planar surfaces it allows the 1059 //! chroma planes to be one-half the width of a the Y (Luma) 1060 //! plane.</font> 1061 //! style="font-family: "Arial","sans-serif"; 1062 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1063 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1064 //! mso-bidi-language: AR-SA;"><font color="#000000">For example, should be 1065 //! set to 0h for NV12 surfaces.</font> 1066 //! style="font-family: "Arial","sans-serif"; 1067 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1068 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1069 //! mso-bidi-language: AR-SA;"><font color="#000000">Must be set to 1h for 1070 //! YV12 surfaces.</font> 1071 enum HALF_PITCH_FOR_CHROMA 1072 { 1073 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< <font color="#000000">Setting this bit to 0h (default) causes Chroma planes to be treated as full width (same as Y plane).</font> 1074 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< <font color="#000000">Setting this bit to 1h causes Chroma planes (U and V) to be treated as half the width of the Luma (Y) plane.</font> 1075 }; 1076 1077 //! \brief SHADER_CHANNEL_SELECT_ALPHA 1078 //! \details 1079 //! See Shader Channel Select Red for details. 1080 enum SHADER_CHANNEL_SELECT_ALPHA 1081 { 1082 SHADER_CHANNEL_SELECT_ALPHA_ZERO = 0, //!< No additional details 1083 SHADER_CHANNEL_SELECT_ALPHA_ONE = 1, //!< No additional details 1084 SHADER_CHANNEL_SELECT_ALPHA_RED = 4, //!< Shader channel is set to surface red channel 1085 SHADER_CHANNEL_SELECT_ALPHA_GREEN = 5, //!< Shader channel is set to surface green channel 1086 SHADER_CHANNEL_SELECT_ALPHA_BLUE = 6, //!< Shader channel is set to surface blue channel 1087 SHADER_CHANNEL_SELECT_ALPHA_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1088 }; 1089 1090 //! \brief SHADER_CHANNEL_SELECT_BLUE 1091 //! \details 1092 //! See Shader Channel Select Red for details. 1093 enum SHADER_CHANNEL_SELECT_BLUE 1094 { 1095 SHADER_CHANNEL_SELECT_BLUE_ZERO = 0, //!< No additional details 1096 SHADER_CHANNEL_SELECT_BLUE_ONE = 1, //!< No additional details 1097 SHADER_CHANNEL_SELECT_BLUE_RED = 4, //!< Shader channel is set to surface red channel 1098 SHADER_CHANNEL_SELECT_BLUE_GREEN = 5, //!< Shader channel is set to surface green channel 1099 SHADER_CHANNEL_SELECT_BLUE_BLUE = 6, //!< Shader channel is set to surface blue channel 1100 SHADER_CHANNEL_SELECT_BLUE_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1101 }; 1102 1103 //! \brief SHADER_CHANNEL_SELECT_GREEN 1104 //! \details 1105 //! See Shader Channel Select Red for details. 1106 enum SHADER_CHANNEL_SELECT_GREEN 1107 { 1108 SHADER_CHANNEL_SELECT_GREEN_ZERO = 0, //!< No additional details 1109 SHADER_CHANNEL_SELECT_GREEN_ONE = 1, //!< No additional details 1110 SHADER_CHANNEL_SELECT_GREEN_RED = 4, //!< Shader channel is set to surface red channel 1111 SHADER_CHANNEL_SELECT_GREEN_GREEN = 5, //!< Shader channel is set to surface green channel 1112 SHADER_CHANNEL_SELECT_GREEN_BLUE = 6, //!< Shader channel is set to surface blue channel 1113 SHADER_CHANNEL_SELECT_GREEN_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1114 }; 1115 1116 //! \brief SHADER_CHANNEL_SELECT_RED 1117 //! \details 1118 //! Specifies which surface channel is read or written in the Red shader 1119 //! channel. 1120 enum SHADER_CHANNEL_SELECT_RED 1121 { 1122 SHADER_CHANNEL_SELECT_RED_ZERO = 0, //!< No additional details 1123 SHADER_CHANNEL_SELECT_RED_ONE = 1, //!< No additional details 1124 SHADER_CHANNEL_SELECT_RED_RED = 4, //!< Shader channel is set to surface red channel 1125 SHADER_CHANNEL_SELECT_RED_GREEN = 5, //!< Shader channel is set to surface green channel 1126 SHADER_CHANNEL_SELECT_RED_BLUE = 6, //!< Shader channel is set to surface blue channel 1127 SHADER_CHANNEL_SELECT_RED_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1128 }; 1129 1130 //! \brief MEMORY_COMPRESSION_MODE 1131 //! \details 1132 //! MBZ: Only Horizontal mode is supported. 1133 enum MEMORY_COMPRESSION_MODE 1134 { 1135 MEMORY_COMPRESSION_MODE_HORIZONTAL = 0, //!< No additional details 1136 }; 1137 1138 //! \brief CLEAR_VALUE_ADDRESS_ENABLE 1139 //! \details 1140 //! This field enables HW Managed Clear Value Layout for the Surface State. 1141 //! If this bit is enabled, Clear Value Address is present instead of 1142 //! explicit clear values. 1143 enum CLEAR_VALUE_ADDRESS_ENABLE 1144 { 1145 CLEAR_VALUE_ADDRESS_ENABLE_DISABLE = 0, //!< Clear values are present in the surface state explicitly. 1146 CLEAR_VALUE_ADDRESS_ENABLE_ENABLE = 1, //!< Clear value Address is present instead of explicit clear values. 1147 }; 1148 1149 //! \name Initializations 1150 1151 //! \brief Explicit member initialization function 1152 RENDER_SURFACE_STATE_CMD(); 1153 1154 static const size_t dwSize = 16; 1155 static const size_t byteSize = 64; 1156 }; 1157 1158 //! 1159 //! \brief MEDIA_SURFACE_STATE 1160 //! \details 1161 //! This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME 1162 //! messages. 1163 //! 1164 struct MEDIA_SURFACE_STATE_CMD 1165 { 1166 union 1167 { 1168 struct 1169 { 1170 uint32_t CompressionFormat : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1171 uint32_t Reserved0 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 1172 uint32_t YOffset : __CODEGEN_BITFIELD(16, 19) ; //!< Y Offset 1173 uint32_t XOffset : __CODEGEN_BITFIELD(20, 26) ; //!< X Offset 1174 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 29) ; //!< Reserved 1175 uint32_t Rotation : __CODEGEN_BITFIELD(30, 31) ; //!< ROTATION 1176 }; 1177 uint32_t Value; 1178 } DW0; 1179 union 1180 { 1181 struct 1182 { 1183 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION 1184 uint32_t PictureStructure : __CODEGEN_BITFIELD( 2, 3) ; //!< PICTURE_STRUCTURE 1185 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1186 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1187 }; 1188 uint32_t Value; 1189 } DW1; 1190 union 1191 { 1192 struct 1193 { 1194 uint32_t TileMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILE_MODE 1195 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 1196 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 20) ; //!< Surface Pitch 1197 uint32_t AddressControl : __CODEGEN_BITFIELD(21, 21) ; //!< ADDRESS_CONTROL 1198 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< Memory Compression Enable 1199 uint32_t MemoryCompressionType : __CODEGEN_BITFIELD(23, 23) ; //!< MEMORY_COMPRESSION_TYPE 1200 uint32_t CrVCbUPixelOffsetVDirectionMsb : __CODEGEN_BITFIELD(24, 24) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1201 uint32_t CrVCbUPixelOffsetUDirection : __CODEGEN_BITFIELD(25, 25) ; //!< CRVCBU_PIXEL_OFFSET_U_DIRECTION 1202 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(26, 26) ; //!< Interleave Chroma 1203 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1204 }; 1205 uint32_t Value; 1206 } DW2; 1207 union 1208 { 1209 struct 1210 { 1211 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U(Cb) 1212 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1213 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U(Cb) 1214 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1215 }; 1216 uint32_t Value; 1217 } DW3; 1218 union 1219 { 1220 struct 1221 { 1222 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V(Cr) 1223 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1224 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for V(Cr) 1225 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1226 }; 1227 uint32_t Value; 1228 } DW4; 1229 union 1230 { 1231 struct 1232 { 1233 uint32_t SurfaceMemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< SURFACE_MEMORY_OBJECT_CONTROL_STATE 1234 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 17) ; //!< Reserved 1235 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 1236 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 29) ; //!< Reserved 1237 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(30, 30) ; //!< Vertical Line Stride Offset 1238 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(31, 31) ; //!< Vertical Line Stride 1239 }; 1240 uint32_t Value; 1241 } DW5; 1242 union 1243 { 1244 struct 1245 { 1246 uint32_t SurfaceBaseAddress ; //!< Surface Base Address 1247 }; 1248 uint32_t Value; 1249 } DW6; 1250 union 1251 { 1252 struct 1253 { 1254 uint32_t SurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Surface Base Address High 1255 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1256 }; 1257 uint32_t Value; 1258 } DW7; 1259 1260 //! \name Local enumerations 1261 1262 //! \brief ROTATION 1263 //! \details 1264 //! Rotation is only supported only with AVS function messages and not with 1265 //! HDC direct write and 16x8 AVS messages. 1266 enum ROTATION 1267 { 1268 ROTATION_NOROTATIONOR0DEGREE = 0, //!< No additional details 1269 ROTATION_90DEGREEROTATION = 1, //!< No additional details 1270 ROTATION_180DEGREEROTATION = 2, //!< No additional details 1271 ROTATION_270DEGREEROTATION = 3, //!< No additional details 1272 }; 1273 1274 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION 1275 //! \details 1276 //! Specifies the distance to the U/V values with respect to the even 1277 //! numbered Y channels in the V direction 1278 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION 1279 { 1280 CRVCBU_PIXEL_OFFSET_V_DIRECTION_UNNAMED0 = 0, //!< No additional details 1281 }; 1282 1283 //! \brief PICTURE_STRUCTURE 1284 //! \details 1285 //! Specifies the encoding of the current picture. 1286 enum PICTURE_STRUCTURE 1287 { 1288 PICTURE_STRUCTURE_FRAMEPICTURE = 0, //!< No additional details 1289 PICTURE_STRUCTURE_TOPFIELDPICTURE = 1, //!< No additional details 1290 PICTURE_STRUCTURE_BOTTOMFIELDPICTURE = 2, //!< No additional details 1291 PICTURE_STRUCTURE_INVALID_NOTALLOWED = 3, //!< No additional details 1292 }; 1293 1294 //! \brief TILE_MODE 1295 //! \details 1296 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 1297 //! or YMajor) employed to tile this surface. See Memory Interface Functions 1298 //! for details on memory tiling and restrictions. 1299 enum TILE_MODE 1300 { 1301 TILE_MODE_TILEMODELINEAR = 0, //!< Linear mode (no tiling) 1302 TILE_MODE_TILEMODEXMAJOR = 2, //!< X major tiling 1303 TILE_MODE_TILEMODEYMAJOR = 3, //!< Y major tiling 1304 }; 1305 1306 enum ADDRESS_CONTROL 1307 { 1308 ADDRESS_CONTROL_CLAMP = 0, //!< Clamp 1309 ADDRESS_CONTROL_MIRROR = 1, //!< Mirror 1310 }; 1311 1312 //! \brief MEMORY_COMPRESSION_TYPE 1313 //! \details 1314 //! Specifies the type of memory compression used. 1315 enum MEMORY_COMPRESSION_TYPE 1316 { 1317 MEMORY_COMPRESSION_TYPE_MEDIACOMPRESSION = 0, //!< No additional details 1318 MEMORY_COMPRESSION_TYPE_RENDERCOMPRESSION = 1, //!< No additional details 1319 }; 1320 1321 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1322 //! \details 1323 //! Specifies the distance to the U/V values with respect to the even 1324 //! numbered Y channels in the V direction 1325 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1326 { 1327 CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB_UNNAMED0 = 0, //!< No additional details 1328 }; 1329 1330 //! \brief CRVCBU_PIXEL_OFFSET_U_DIRECTION 1331 //! \details 1332 //! Specifies the distance to the U/V values with respect to the even 1333 //! numbered Y channels in the U direction 1334 enum CRVCBU_PIXEL_OFFSET_U_DIRECTION 1335 { 1336 CRVCBU_PIXEL_OFFSET_U_DIRECTION_UNNAMED0 = 0, //!< No additional details 1337 }; 1338 1339 //! \brief SURFACE_FORMAT 1340 //! \details 1341 //! Specifies the format of the surface. All of the Y and G channels will 1342 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 1343 enum SURFACE_FORMAT 1344 { 1345 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1346 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1347 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1348 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1349 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 1350 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 only 1351 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 AVS only 1352 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 AVS only 1353 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 AVS only 1354 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 AVS only 1355 SURFACE_FORMAT_A8Y8U8V8UNORM = 13, //!< Sample_8x8 AVS only 1356 SURFACE_FORMAT_B8G8R8A8UNORM = 14, //!< Sample_8x8 AVS only 1357 SURFACE_FORMAT_R16G16B16A16 = 15, //!< Sample_8x8 AVS only 1358 SURFACE_FORMAT_PLANAR4228 = 18, //!< Sample_8x8 AVS only 1359 SURFACE_FORMAT_PLANAR42016 = 23, //!< Sample_8x8 AVS only 1360 SURFACE_FORMAT_R16B16UNORM_CRCB = 24, //!< Sample_8x8 AVS only 1361 SURFACE_FORMAT_R16UNORM_CRCB = 25, //!< Sample_8x8 AVS only 1362 SURFACE_FORMAT_Y16UNORM = 26, //!< Sample_8x8 AVS only 1363 }; 1364 1365 //! \brief SURFACE_MEMORY_OBJECT_CONTROL_STATE 1366 //! \details 1367 //! This 7-bit field is used in various state commands and indirect state 1368 //! objects to define cacheability and other attributes related to memory 1369 //! objects. 1370 enum SURFACE_MEMORY_OBJECT_CONTROL_STATE 1371 { 1372 SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0, //!< No additional details 1373 }; 1374 1375 //! \brief TILED_RESOURCE_MODE 1376 //! \details 1377 //! For Sampling Engine, Render Target, and Typed/Untyped Surfaces: 1378 //! This field specifies the tiled resource mode. 1379 //! For other surfaces: 1380 //! This field is ignored. 1381 enum TILED_RESOURCE_MODE 1382 { 1383 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1384 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1385 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1386 }; 1387 1388 //! \name Initializations 1389 1390 //! \brief Explicit member initialization function 1391 MEDIA_SURFACE_STATE_CMD(); 1392 1393 static const size_t dwSize = 8; 1394 static const size_t byteSize = 32; 1395 }; 1396 1397 //! 1398 //! \brief SAMPLER_STATE 1399 //! \details 1400 //! This is the normal sampler state used by all messages that use 1401 //! SAMPLER_STATE except sample_8x8 and deinterlace. The sampler state is 1402 //! stored as an array of up to 16 elements, each of which contains the 1403 //! dwords described here. The start of each element is spaced 4 dwords 1404 //! apart. The first element of the sampler state array is aligned to a 1405 //! 32-byte boundary. 1406 //! 1407 struct SAMPLER_STATE_CMD 1408 { 1409 union 1410 { 1411 struct 1412 { 1413 uint32_t LodAlgorithm : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_ALGORITHM 1414 uint32_t TextureLodBias : __CODEGEN_BITFIELD( 1, 13) ; //!< Texture LOD Bias 1415 uint32_t MinModeFilter : __CODEGEN_BITFIELD(14, 16) ; //!< MIN_MODE_FILTER 1416 uint32_t MagModeFilter : __CODEGEN_BITFIELD(17, 19) ; //!< MAG_MODE_FILTER 1417 uint32_t MipModeFilter : __CODEGEN_BITFIELD(20, 21) ; //!< MIP_MODE_FILTER 1418 uint32_t CoarseLodQualityMode : __CODEGEN_BITFIELD(22, 26) ; //!< COARSE_LOD_QUALITY_MODE 1419 uint32_t LodPreclampMode : __CODEGEN_BITFIELD(27, 28) ; //!< LOD_PRECLAMP_MODE 1420 uint32_t Reserved29 : __CODEGEN_BITFIELD(29, 29) ; //!< Reserved 1421 uint32_t CpsLodCompensationEnable : __CODEGEN_BITFIELD(30, 30) ; //!< CPS LOD Compensation Enable 1422 uint32_t SamplerDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Sampler Disable 1423 }; 1424 uint32_t Value; 1425 } DW0; 1426 union 1427 { 1428 struct 1429 { 1430 uint32_t CubeSurfaceControlMode : __CODEGEN_BITFIELD( 0, 0) ; //!< CUBE_SURFACE_CONTROL_MODE 1431 uint32_t ShadowFunction : __CODEGEN_BITFIELD( 1, 3) ; //!< SHADOW_FUNCTION 1432 uint32_t ChromakeyMode : __CODEGEN_BITFIELD( 4, 4) ; //!< CHROMAKEY_MODE 1433 uint32_t ChromakeyIndex : __CODEGEN_BITFIELD( 5, 6) ; //!< ChromaKey Index 1434 uint32_t ChromakeyEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< ChromaKey Enable 1435 uint32_t MaxLod : __CODEGEN_BITFIELD( 8, 19) ; //!< Max LOD 1436 uint32_t MinLod : __CODEGEN_BITFIELD(20, 31) ; //!< Min LOD 1437 }; 1438 uint32_t Value; 1439 } DW1; 1440 union 1441 { 1442 struct 1443 { 1444 uint32_t LodClampMagnificationMode : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_CLAMP_MAGNIFICATION_MODE 1445 uint32_t SrgbDecode : __CODEGEN_BITFIELD( 1, 1) ; //!< SRGB_DECODE 1446 uint32_t ReturnFilterWeightForNullTexels : __CODEGEN_BITFIELD( 2, 2) ; //!< RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1447 uint32_t ReturnFilterWeightForBorderTexels : __CODEGEN_BITFIELD( 3, 3) ; //!< RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1448 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 1449 uint32_t IndirectStatePointer : __CODEGEN_BITFIELD( 6, 23) ; //!< Indirect State Pointer 1450 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1451 }; 1452 uint32_t Value; 1453 } DW2; 1454 union 1455 { 1456 struct 1457 { 1458 uint32_t TczAddressControlMode : __CODEGEN_BITFIELD( 0, 2) ; //!< TCZ_ADDRESS_CONTROL_MODE 1459 uint32_t TcyAddressControlMode : __CODEGEN_BITFIELD( 3, 5) ; //!< TCY_ADDRESS_CONTROL_MODE 1460 uint32_t TcxAddressControlMode : __CODEGEN_BITFIELD( 6, 8) ; //!< TCX_ADDRESS_CONTROL_MODE 1461 uint32_t ReductionTypeEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Reduction Type Enable 1462 uint32_t NonNormalizedCoordinateEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Non-normalized Coordinate Enable 1463 uint32_t TrilinearFilterQuality : __CODEGEN_BITFIELD(11, 12) ; //!< TRILINEAR_FILTER_QUALITY 1464 uint32_t RAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(13, 13) ; //!< R Address Min Filter Rounding Enable 1465 uint32_t RAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(14, 14) ; //!< R Address Mag Filter Rounding Enable 1466 uint32_t VAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(15, 15) ; //!< V Address Min Filter Rounding Enable 1467 uint32_t VAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(16, 16) ; //!< V Address Mag Filter Rounding Enable 1468 uint32_t UAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< U Address Min Filter Rounding Enable 1469 uint32_t UAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< U Address Mag Filter Rounding Enable 1470 uint32_t MaximumAnisotropy : __CODEGEN_BITFIELD(19, 21) ; //!< MAXIMUM_ANISOTROPY 1471 uint32_t ReductionType : __CODEGEN_BITFIELD(22, 23) ; //!< REDUCTION_TYPE 1472 uint32_t AllowLowQualityLodCalculation : __CODEGEN_BITFIELD(24, 24) ; //!< Allow low quality LOD calculation 1473 uint32_t Reserved121 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1474 }; 1475 uint32_t Value; 1476 } DW3; 1477 1478 //! \name Local enumerations 1479 1480 //! \brief LOD_ALGORITHM 1481 //! \details 1482 //! Controls which algorithm is used for LOD calculation. Generally, the EWA 1483 //! approximation algorithm results in higher image quality than the legacy 1484 //! algorithm. 1485 enum LOD_ALGORITHM 1486 { 1487 LOD_ALGORITHM_LEGACY = 0, //!< Use the legacy algorithm for non-anisotropic filtering 1488 LOD_ALGORITHM_EWAAPPROXIMATION = 1, //!< Use the new EWA approximation algorithm for anisotropic filtering 1489 }; 1490 1491 //! \brief MIN_MODE_FILTER 1492 //! \details 1493 //! This field determines how texels are sampled/filtered when a texture is 1494 //! being "minified" (shrunk). For volume maps, this filter mode selection 1495 //! also applies to the 3rd (inter-layer) dimension.See Mag Mode Filter 1496 enum MIN_MODE_FILTER 1497 { 1498 MIN_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1499 MIN_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1500 MIN_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1501 }; 1502 1503 //! \brief MAG_MODE_FILTER 1504 //! \details 1505 //! This field determines how texels are sampled/filtered when a texture is 1506 //! being "magnified" (enlarged). For volume maps, this filter mode 1507 //! selection also applies to the 3rd (inter-layer) dimension. 1508 enum MAG_MODE_FILTER 1509 { 1510 MAG_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1511 MAG_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1512 MAG_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1513 }; 1514 1515 //! \brief MIP_MODE_FILTER 1516 //! \details 1517 //! This field determines if and how mip map levels are chosen and/or 1518 //! combined when texture filtering. 1519 enum MIP_MODE_FILTER 1520 { 1521 MIP_MODE_FILTER_NONE = 0, //!< Disable mip mapping - force use of the mipmap level corresponding to Min LOD. 1522 MIP_MODE_FILTER_NEAREST = 1, //!< Nearest, Select the nearest mip map 1523 MIP_MODE_FILTER_LINEAR = 3, //!< Linearly interpolate between nearest mip maps (combined with linear min/mag filters this is analogous to "Trilinear" filtering). 1524 }; 1525 1526 //! \brief COARSE_LOD_QUALITY_MODE 1527 //! \details 1528 //! This field configures the coarse LOD image quality mode for the 1529 //! sample_d, sample_l, and sample_b messages in the sampling engine. In 1530 //! general, performance will increase and power consumption will decrease 1531 //! with each step of reduced quality (performance gain for sample_l and 1532 //! sample_b will be minimal). 1533 enum COARSE_LOD_QUALITY_MODE 1534 { 1535 COARSE_LOD_QUALITY_MODE_DISABLED = 0, //!< Full quality is enabled, matching prior products 1536 }; 1537 1538 //! \brief LOD_PRECLAMP_MODE 1539 //! \details 1540 //! This field determines whether the computed LOD is clamped to 1541 //! [max,min] mip level 1542 //! before the mag-vs-min determination is performed. 1543 enum LOD_PRECLAMP_MODE 1544 { 1545 LOD_PRECLAMP_MODE_NONE = 0, //!< LOD PreClamp disabled 1546 LOD_PRECLAMP_MODE_OGL = 2, //!< LOD PreClamp enabled (OGL mode) 1547 }; 1548 1549 //! \brief CUBE_SURFACE_CONTROL_MODE 1550 //! \details 1551 //! When sampling from a SURFTYPE_CUBE surface, this field controls whether 1552 //! the TC* Address Control Mode fields are interpreted as programmed or 1553 //! overridden to TEXCOORDMODE_CUBE. 1554 enum CUBE_SURFACE_CONTROL_MODE 1555 { 1556 CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0, //!< No additional details 1557 CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 1, //!< No additional details 1558 }; 1559 1560 //! \brief SHADOW_FUNCTION 1561 //! \details 1562 //! This field is used for shadow mapping support via the sample_c message 1563 //! type, and specifies the specific comparison operation to be used. The 1564 //! comparison is between the texture sample red channel (except for 1565 //! alpha-only formats which use the alpha channel), and the "ref" value 1566 //! provided in the input message. 1567 enum SHADOW_FUNCTION 1568 { 1569 SHADOW_FUNCTION_PREFILTEROPALWAYS = 0, //!< No additional details 1570 SHADOW_FUNCTION_PREFILTEROPNEVER = 1, //!< No additional details 1571 SHADOW_FUNCTION_PREFILTEROPLESS = 2, //!< No additional details 1572 SHADOW_FUNCTION_PREFILTEROPEQUAL = 3, //!< No additional details 1573 SHADOW_FUNCTION_PREFILTEROPLEQUAL = 4, //!< No additional details 1574 SHADOW_FUNCTION_PREFILTEROPGREATER = 5, //!< No additional details 1575 SHADOW_FUNCTION_PREFILTEROPNOTEQUAL = 6, //!< No additional details 1576 SHADOW_FUNCTION_PREFILTEROPGEQUAL = 7, //!< No additional details 1577 }; 1578 1579 //! \brief CHROMAKEY_MODE 1580 //! \details 1581 //! This field specifies the behavior of the device in the event of a 1582 //! ChromaKey match. This field is ignored if ChromaKey is disabled. 1583 enum CHROMAKEY_MODE 1584 { 1585 CHROMAKEY_MODE_KEYFILTERKILLONANYMATCH = 0, //!< In this mode, if any contributing texel matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this operation is observable only if the Killed Pixel Mask Return flag is set on the input message. 1586 CHROMAKEY_MODE_KEYFILTERREPLACEBLACK = 1, //!< In this mode, each texel that matches the chroma key is replaced with (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha test, etc. 1587 }; 1588 1589 //! \brief LOD_CLAMP_MAGNIFICATION_MODE 1590 //! \details 1591 //! This field allows the flexibility to control how LOD clamping is handled 1592 //! when in magnification mode. 1593 enum LOD_CLAMP_MAGNIFICATION_MODE 1594 { 1595 LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0, //!< When in magnification mode, Sampler will clamp LOD as if the Mip Mode Filteris MIPFILTER_NONE. This is how OpenGL defines magnification, and therefore it isexpected that those drivers would not set this bit. 1596 LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 1, //!< When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter. 1597 }; 1598 1599 //! \brief SRGB_DECODE 1600 //! \details 1601 //! This bit controls whether the 3D sampler will decode an sRGB 1602 //! formatted surface into RGB prior to any filtering operation. 1603 //! When set, it does not convert to linear RGB (via a reverse gamma 1604 //! conversion). This bit is ignored for ASTC formats, which are always 1605 //! converted to linear RGB prior to filtering. 1606 enum SRGB_DECODE 1607 { 1608 SRGB_DECODE_DECODEEXT = 0, //!< When set to 0h, the 3D sampler will convert texels from an sRGB surface to linear RGB prior to filtering and/or returning the value. 1609 SRGB_DECODE_SKIPDECODEEXT = 1, //!< When set to 1h, the 3D sampler will not convert texels to linear RGB before filtering and returning results. 1610 }; 1611 1612 //! \brief RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1613 //! \details 1614 //! This bit, when set, causes samples to return filter_weight of all 1615 //! non-NULL texels in the Alpha channel; Red, Green, and Blue channels are 1616 //! contain the filter result with NULL texels excluded; A non-NULL texel is 1617 //! a texel which does not reference a Null Tile. 1618 //! For cases where Tiled_Resource_Mode is TR_NONE, the result will 1619 //! always be 1.0 since no texels would be NULL. 1620 //! For cases where the surface format contains an Alpha channel, the 1621 //! result returned will be overridden to return the filter weight. 1622 //! For cases where the surface format does not contain Alpha, the result 1623 //! will still be returned in the Alpha Channel. 1624 enum RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1625 { 1626 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE = 0, //!< When programmed to 0h, filter weight will not be returned, and normal data will be returned on the Alpha channel. 1627 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_ENABLE = 1, //!< When programmed to 1h, filter weight will be returned on the Alpha channel rather than the normal data expected on the Alpha channel. 1628 }; 1629 1630 //! \brief RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1631 //! \details 1632 //! This bit, when set, returns the filter_weight in the Alpha channel of 1633 //! all non-border texels. Red, Green, and Blue channels will contain the 1634 //! sample result with border texels excluded. 1635 //! For cases where the surface format contains an Alpha channel, the 1636 //! result returned will be ovewritten to return the filter weight. 1637 //! For cases where the surface format does not contain Alpha, the result 1638 //! will still be returned in the Alpha Channel. 1639 enum RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1640 { 1641 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE = 0, //!< When programmed to 0h, normal data will be returned on RGBA channels, including contribution from border color texels. 1642 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_ENABLE = 1, //!< When programmed to 1h, RGB channels return filter data contributed from non-border color texels, and A channel returns filter weight of contributing texels. 1643 }; 1644 1645 //! \brief TCZ_ADDRESS_CONTROL_MODE 1646 //! \details 1647 //! Controls how the 3rd (TCZ) component of input texture coordinates are 1648 //! mapped to texture map addresses - specifically, how coordinates 1649 //! "outside" the texture are handled (wrap/clamp/mirror).See Address TCX 1650 //! Control Mode above for details 1651 enum TCZ_ADDRESS_CONTROL_MODE 1652 { 1653 TCZ_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1654 TCZ_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1655 TCZ_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1656 TCZ_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1657 TCZ_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1658 TCZ_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1659 TCZ_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1660 TCZ_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces. 1661 }; 1662 1663 //! \brief TCY_ADDRESS_CONTROL_MODE 1664 //! \details 1665 //! Controls how the 2nd (TCY, aka V) component of input texture coordinates 1666 //! are mapped to texture map addresses - specifically, how coordinates 1667 //! "outside" the texture are handled (wrap/clamp/mirror). See Address TCX 1668 //! Control Mode above for details 1669 enum TCY_ADDRESS_CONTROL_MODE 1670 { 1671 TCY_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1672 TCY_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1673 TCY_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1674 TCY_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1675 TCY_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1676 TCY_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1677 TCY_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1678 TCY_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces. 1679 }; 1680 1681 //! \brief TCX_ADDRESS_CONTROL_MODE 1682 //! \details 1683 //! Controls how the 1st (TCX, aka U) component of input texture coordinates 1684 //! are mapped to texture map addresses - specifically, how coordinates 1685 //! "outside" the texture are handled (wrap/clamp/mirror). The setting of 1686 //! this field is subject to being overridden by the Cube Surface Control 1687 //! Mode field when sampling from a SURFTYPE_CUBE surface. 1688 enum TCX_ADDRESS_CONTROL_MODE 1689 { 1690 TCX_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1691 TCX_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1692 TCX_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1693 TCX_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1694 TCX_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1695 TCX_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1696 TCX_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1697 TCX_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces. 1698 }; 1699 1700 //! \brief TRILINEAR_FILTER_QUALITY 1701 //! \details 1702 //! Selects the quality level for the trilinear filter. 1703 enum TRILINEAR_FILTER_QUALITY 1704 { 1705 TRILINEAR_FILTER_QUALITY_FULL = 0, //!< Full Quality. Both mip maps are sampled under all circumstances. 1706 TRILINEAR_FILTER_QUALITY_TRIQUALHIGHMAGCLAMPMIPFILTER = 1, //!< High Quality. 1707 TRILINEAR_FILTER_QUALITY_MED = 2, //!< Medium Quality. 1708 TRILINEAR_FILTER_QUALITY_LOW = 3, //!< Low Quality. 1709 }; 1710 1711 //! \brief MAXIMUM_ANISOTROPY 1712 //! \details 1713 //! This field clamps the maximum value of the anisotropy ratio used by the 1714 //! MAPFILTER_ANISOTROPIC filter (Min or Mag Mode Filter). 1715 enum MAXIMUM_ANISOTROPY 1716 { 1717 MAXIMUM_ANISOTROPY_RATIO21 = 0, //!< At most a 2:1 aspect ratio filter is used 1718 MAXIMUM_ANISOTROPY_RATIO41 = 1, //!< At most a 4:1 aspect ratio filter is used 1719 MAXIMUM_ANISOTROPY_RATIO61 = 2, //!< At most a 6:1 aspect ratio filter is used 1720 MAXIMUM_ANISOTROPY_RATIO81 = 3, //!< At most a 8:1 aspect ratio filter is used 1721 MAXIMUM_ANISOTROPY_RATIO101 = 4, //!< At most a 10:1 aspect ratio filter is used 1722 MAXIMUM_ANISOTROPY_RATIO121 = 5, //!< At most a 12:1 aspect ratio filter is used 1723 MAXIMUM_ANISOTROPY_RATIO141 = 6, //!< At most a 14:1 aspect ratio filter is used 1724 MAXIMUM_ANISOTROPY_RATIO161 = 7, //!< At most a 16:1 aspect ratio filter is used 1725 }; 1726 1727 //! \brief REDUCTION_TYPE 1728 //! \details 1729 //! This field defines the type of reduction that will be performed on the 1730 //! texels in the footprint defined by the Min/Mag/Mip Filter Mode 1731 //! fields. This field is ignored if Reduction Type Enable is 1732 //! disabled. 1733 enum REDUCTION_TYPE 1734 { 1735 REDUCTION_TYPE_STDFILTER = 0, //!< standard filter 1736 REDUCTION_TYPE_COMPARISON = 1, //!< comparison followed by standard filter 1737 REDUCTION_TYPE_MINIMUM = 2, //!< minimum of footprint 1738 REDUCTION_TYPE_MAXIMUM = 3, //!< maximum of footprint 1739 }; 1740 1741 //! \name Initializations 1742 1743 //! \brief Explicit member initialization function 1744 SAMPLER_STATE_CMD(); 1745 1746 static const size_t dwSize = 4; 1747 static const size_t byteSize = 16; 1748 }; 1749 1750 //! 1751 //! \brief SAMPLER_STATE_8x8_AVS_COEFFICIENTS 1752 //! \details 1753 //! ExistsIf = AVS && (Function_mode = 0) 1754 //! 1755 struct SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD 1756 { 1757 union 1758 { 1759 struct 1760 { 1761 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,0] 1762 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,0] 1763 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,1] 1764 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,1] 1765 }; 1766 uint32_t Value; 1767 } DW0; 1768 union 1769 { 1770 struct 1771 { 1772 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,2] 1773 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,2] 1774 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,3] 1775 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,3] 1776 }; 1777 uint32_t Value; 1778 } DW1; 1779 union 1780 { 1781 struct 1782 { 1783 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,4] 1784 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,4] 1785 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,5] 1786 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,5] 1787 }; 1788 uint32_t Value; 1789 } DW2; 1790 union 1791 { 1792 struct 1793 { 1794 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,6] 1795 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,6] 1796 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,7] 1797 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,7] 1798 }; 1799 uint32_t Value; 1800 } DW3; 1801 union 1802 { 1803 struct 1804 { 1805 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1806 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[n,2] 1807 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1X Filter Coefficient[n,3] 1808 }; 1809 uint32_t Value; 1810 } DW4; 1811 union 1812 { 1813 struct 1814 { 1815 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[n,4] 1816 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1X Filter Coefficient[n,5] 1817 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1818 }; 1819 uint32_t Value; 1820 } DW5; 1821 union 1822 { 1823 struct 1824 { 1825 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1826 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1Y Filter Coefficient[n,2] 1827 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[n,3] 1828 }; 1829 uint32_t Value; 1830 } DW6; 1831 union 1832 { 1833 struct 1834 { 1835 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1Y Filter Coefficient[n,4] 1836 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[n,5] 1837 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1838 }; 1839 uint32_t Value; 1840 } DW7; 1841 1842 //! \name Local enumerations 1843 1844 //! \name Initializations 1845 1846 //! \brief Explicit member initialization function 1847 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD(); 1848 1849 static const size_t dwSize = 8; 1850 static const size_t byteSize = 32; 1851 }; 1852 1853 //! 1854 //! \brief SAMPLER_STATE_8x8_AVS 1855 //! \details 1856 //! ExistsIf = AVS 1857 //! 1858 struct SAMPLER_STATE_8x8_AVS_CMD 1859 { 1860 uint32_t Reserved0[3]; //!< Reserved 1861 union 1862 { 1863 struct 1864 { 1865 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 27) ; //!< Reserved 1866 uint32_t Enable8TapFilter : __CODEGEN_BITFIELD(28, 29) ; //!< ENABLE_8_TAP_FILTER 1867 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1868 }; 1869 uint32_t Value; 1870 } DW3; 1871 union 1872 { 1873 struct 1874 { 1875 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 10) ; //!< Reserved 1876 uint32_t ShuffleOutputwritebackForSample8X8 : __CODEGEN_BITFIELD(11, 11) ; //!< SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1877 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 1878 }; 1879 uint32_t Value; 1880 } DW4; 1881 uint32_t Reserved160[11]; //!< Reserved 1882 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient016[17]; //!< DW16..151, Filter Coefficient[0..16] 1883 union 1884 { 1885 struct 1886 { 1887 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 1888 uint32_t Reserved4867 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 1889 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 1890 uint32_t Reserved4871 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 1891 uint32_t MaxDerivative8Pixels : __CODEGEN_BITFIELD( 8, 15) ; //!< Max Derivative 8 Pixels 1892 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 1893 uint32_t DefaultSharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< DEFAULT_SHARPNESS_LEVEL 1894 }; 1895 uint32_t Value; 1896 } DW152; 1897 union 1898 { 1899 struct 1900 { 1901 uint32_t RgbAdaptive : __CODEGEN_BITFIELD( 0, 0) ; //!< RGB_ADAPTIVE 1902 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1903 uint32_t Reserved4898 : __CODEGEN_BITFIELD( 2, 20) ; //!< Reserved 1904 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD(21, 21) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1905 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD(22, 22) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1906 uint32_t Reserved4919 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1907 }; 1908 uint32_t Value; 1909 } DW153; 1910 uint32_t Reserved4928[6]; //!< Reserved 1911 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient1731[15]; //!< DW160..279, Filter Coefficient[17..31] 1912 1913 //! \name Local enumerations 1914 1915 //! \brief ENABLE_8_TAP_FILTER 1916 //! \details 1917 //! Adaptive Filtering (Mode = 11) ExistsIf: 1918 //! R10G10B10A2_UNORM R8G8B8A8_UNORM (AYUV also) R8B8G8A8_UNORM 1919 //! B8G8R8A8_UNORM R16G16B16A16 1920 enum ENABLE_8_TAP_FILTER 1921 { 1922 ENABLE_8_TAP_FILTER_UNNAMED0 = 0, //!< 4-tap filter is only done on all channels. 1923 ENABLE_8_TAP_FILTER_UNNAMED1 = 1, //!< Enable 8-tap Adaptive filter on G-channel. 4-tap filter on other channels. 1924 ENABLE_8_TAP_FILTER_UNNAMED2 = 2, //!< 8-tap filter is done on all channels (UV-ch uses the Y-coefficients) 1925 ENABLE_8_TAP_FILTER_UNNAMED3 = 3, //!< Enable 8-tap Adaptive filter all channels (UV-ch uses the Y-coefficients). 1926 }; 1927 1928 enum SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1929 { 1930 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED0 = 0, //!< Writeback same as Original Sample_8x8 1931 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED1 = 1, //!< Writeback of Sample_8x8 Is Modified to Suite Sample_Unorm 1932 }; 1933 1934 //! \brief DEFAULT_SHARPNESS_LEVEL 1935 //! \details 1936 //! When adaptive scaling is off, determines the balance between sharp and 1937 //! smooth scalers. 1938 enum DEFAULT_SHARPNESS_LEVEL 1939 { 1940 DEFAULT_SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 1941 DEFAULT_SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 1942 }; 1943 1944 //! \brief RGB_ADAPTIVE 1945 //! \details 1946 //! This should be always set to 0 for YUV input and can be enabled/disabled 1947 //! for RGB input. 1948 //! This should be enabled only if we enable 8-tap adaptive filter for 1949 //! RGB input. 1950 enum RGB_ADAPTIVE 1951 { 1952 RGB_ADAPTIVE_DISBLE = 0, //!< Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter 1953 RGB_ADAPTIVE_ENABLE = 1, //!< Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) 1954 }; 1955 1956 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1957 //! \details 1958 //! Only to be enabled if 8-tap Adaptive filter mode is on, eElse it should 1959 //! be disabled. 1960 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1961 { 1962 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISBLE = 0, //!< Disable Adaptive Filter on UV/RB Channels 1963 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLE = 1, //!< Enable Adaptive Filter on UV/RB Channels 1964 }; 1965 1966 //! \brief BYPASS_Y_ADAPTIVE_FILTERING 1967 //! \details 1968 //! When disabled, the Y direction will use Default Sharpness Level 1969 //! to blend between the smooth and sharp filters rather than the calculated 1970 //! value. 1971 enum BYPASS_Y_ADAPTIVE_FILTERING 1972 { 1973 BYPASS_Y_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable Y Adaptive Filtering 1974 BYPASS_Y_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable Y Adaptive Filtering 1975 }; 1976 1977 //! \brief BYPASS_X_ADAPTIVE_FILTERING 1978 //! \details 1979 //! When disabled, the X direction will use Default Sharpness Level 1980 //! to blend between the smooth and sharp filters rather than the calculated 1981 //! value. 1982 enum BYPASS_X_ADAPTIVE_FILTERING 1983 { 1984 BYPASS_X_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable X Adaptive Filtering 1985 BYPASS_X_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable X Adaptive Filtering 1986 }; 1987 1988 //! \name Initializations 1989 1990 //! \brief Explicit member initialization function 1991 SAMPLER_STATE_8x8_AVS_CMD(); 1992 1993 static const size_t dwSize = 280; 1994 static const size_t byteSize = 1120; 1995 }; 1996 1997 //! 1998 //! \brief SAMPLER_INDIRECT_STATE 1999 //! \details 2000 //! Note: There are three variations of this structure, defined separately 2001 //! because their payloads have different lengths. Currently only 2002 //! SAMPLER_INDIRECT_STATE_BORDER_COLOR is fully defined. 2003 //! This structure is pointed to by Indirect State Pointer (SAMPLER_STATE). 2004 //! 2005 //! The format of the border color is R32G32B32A32_FLOAT, 2006 //! R32G32B32A32_SINT, or R32G32B32A32_UINT, depending on the surface format 2007 //! chosen. For surface formats with one or more channels missing, the value 2008 //! from the border color is not used for the missing channels, resulting in 2009 //! these channels resulting in the overall default value (0 for colors and 2010 //! 1 for alpha) regardless of whether border color is chosen. The surface 2011 //! formats with "L" and "I" have special behavior with respect to the 2012 //! border color. The border color value used for the replicated channels 2013 //! (RGB for "L" formats and RGBA for "I" formats) comes from the red 2014 //! channel of border color. In these cases, the green and blue channels, 2015 //! and also alpha for "I", of the border color are ignored. 2016 //! 2017 //! The conditions under which this color is used depend on the Surface 2018 //! Type - 1D/2D/3D surfaces use the border color when the coordinates 2019 //! extend beyond the surface extent; cube surfaces use the border color for 2020 //! "empty" (disabled) faces. 2021 //! 2022 //! The border color itself is accessed through the texture cache hierarchy 2023 //! rather than the state cache hierarchy. Thus, if the border color is 2024 //! changed in memory, the texture cache must be invalidated and the state 2025 //! cache does not need to be invalidated. 2026 //! 2027 //! 2028 struct SAMPLER_INDIRECT_STATE_CMD 2029 { 2030 union 2031 { 2032 struct 2033 { 2034 uint32_t BorderColorRed : __CODEGEN_BITFIELD(0, 31); //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2035 }; 2036 uint32_t Value; 2037 } DW0; 2038 union 2039 { 2040 struct 2041 { 2042 uint32_t BorderColorGreen : __CODEGEN_BITFIELD(0, 31); //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2043 }; 2044 uint32_t Value; 2045 } DW1; 2046 union 2047 { 2048 struct 2049 { 2050 uint32_t BorderColorBlue : __CODEGEN_BITFIELD(0, 31); //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2051 }; 2052 uint32_t Value; 2053 } DW2; 2054 union 2055 { 2056 struct 2057 { 2058 uint32_t BorderColorAlpha : __CODEGEN_BITFIELD(0, 31); //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2059 }; 2060 uint32_t Value; 2061 } DW3; 2062 uint32_t Reserved128[12]; //!< Reserved 2063 2064 //! \name Local enumerations 2065 2066 //! \name Initializations 2067 2068 //! \brief Explicit member initialization function 2069 SAMPLER_INDIRECT_STATE_CMD(); 2070 2071 static const size_t dwSize = 16; 2072 static const size_t byteSize = 64; 2073 }; 2074 2075 }; 2076 2077 #pragma pack() 2078 2079 #endif // __MHW_STATE_HEAP_HWCMD_XE_XPM_H__