1 /* 2 * Copyright (c) 2021-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_avp_impl_xe_hpm.h 24 //! \brief MHW VDBOX AVP interface common base for Xe_HPM platforms 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_AVP_IMPL_XE_HPM_H__ 29 #define __MHW_VDBOX_AVP_IMPL_XE_HPM_H__ 30 31 #include "mhw_vdbox_avp_hwcmd_xe_hpm.h" 32 #include "mhw_vdbox_avp_impl.h" 33 #include "mhw_mi_hwcmd_g12_X.h" // refactor 34 #include "mhw_mi_itf.h" 35 36 namespace mhw 37 { 38 namespace vdbox 39 { 40 namespace avp 41 { 42 namespace xe_hpm 43 { 44 class Impl : public avp::Impl<Cmd> 45 { 46 public: Impl(PMOS_INTERFACE osItf)47 Impl(PMOS_INTERFACE osItf) : base_t(osItf){}; 48 GetAvpStateCmdSize(uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)49 MOS_STATUS GetAvpStateCmdSize(uint32_t* commandsSize, uint32_t* patchListSize, PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) override 50 { 51 MHW_FUNCTION_ENTER; 52 53 MHW_MI_CHK_NULL(commandsSize); 54 MHW_MI_CHK_NULL(patchListSize); 55 56 uint32_t maxSize = 0; 57 uint32_t patchListMaxSize = 0; 58 59 maxSize = 60 8 + 61 mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize + 62 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PIPE_MODE_SELECT_CMD::byteSize + 63 mhw::vdbox::avp::xe_hpm::Cmd::AVP_SURFACE_STATE_CMD::byteSize * 11 + 64 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PIPE_BUF_ADDR_STATE_CMD::byteSize + 65 mhw::vdbox::avp::xe_hpm::Cmd::AVP_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 66 mhw::vdbox::avp::xe_hpm::Cmd::AVP_SEGMENT_STATE_CMD::byteSize * 8 + 67 mhw::vdbox::avp::xe_hpm::Cmd::AVP_INLOOP_FILTER_STATE_CMD::byteSize + 68 mhw::vdbox::avp::xe_hpm::Cmd::AVP_INTER_PRED_STATE_CMD::byteSize; 69 70 patchListMaxSize = 71 PATCH_LIST_COMMAND(avp::Itf::VD_PIPELINE_FLUSH_CMD) + 72 PATCH_LIST_COMMAND(mi::Itf::MI_FLUSH_DW_CMD) + 73 PATCH_LIST_COMMAND(avp::Itf::AVP_PIPE_MODE_SELECT_CMD) + 74 PATCH_LIST_COMMAND(avp::Itf::AVP_SURFACE_STATE_CMD) * 11 + 75 PATCH_LIST_COMMAND(avp::Itf::AVP_PIPE_BUF_ADDR_STATE_CMD) + 76 PATCH_LIST_COMMAND(avp::Itf::AVP_IND_OBJ_BASE_ADDR_STATE_CMD) + 77 PATCH_LIST_COMMAND(avp::Itf::AVP_SEGMENT_STATE_CMD) * 8 + 78 PATCH_LIST_COMMAND(avp::Itf::AVP_INTER_PRED_STATE_CMD) + 79 PATCH_LIST_COMMAND(avp::Itf::AVP_INLOOP_FILTER_STATE_CMD); 80 81 if (params->bDecodeInUse) 82 { 83 maxSize += 84 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PIC_STATE_CMD::byteSize + 85 mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize * 2; 86 87 patchListMaxSize += PATCH_LIST_COMMAND(avp::Itf::AVP_PIC_STATE_CMD); 88 89 MHW_CHK_NULL_RETURN(params); 90 auto paramsG12 = dynamic_cast<PMHW_VDBOX_STATE_CMDSIZE_PARAMS_G12>(params); 91 MHW_CHK_NULL_RETURN(paramsG12); 92 if (paramsG12->bScalableMode) 93 { 94 // VD_CONTROL_STATE AVP lock and unlock 95 maxSize += 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize; 96 } 97 } 98 99 *commandsSize = maxSize; 100 *patchListSize = patchListMaxSize; 101 102 return MOS_STATUS_SUCCESS; 103 } 104 GetAvpPrimitiveCmdSize(uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)105 MOS_STATUS GetAvpPrimitiveCmdSize(uint32_t* commandsSize, uint32_t* patchListSize, PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) override 106 { 107 MHW_FUNCTION_ENTER; 108 109 MHW_MI_CHK_NULL(commandsSize); 110 MHW_MI_CHK_NULL(patchListSize); 111 112 uint32_t maxSize = 0; 113 uint32_t patchListMaxSize = 0; 114 115 if (params->bDecodeInUse) 116 { 117 maxSize = 118 mhw::vdbox::avp::xe_hpm::Cmd::AVP_TILE_CODING_CMD::byteSize + 119 mhw::vdbox::avp::xe_hpm::Cmd::AVP_BSD_OBJECT_CMD::byteSize + 120 mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize; 121 122 patchListMaxSize = 123 PATCH_LIST_COMMAND(avp::Itf::AVP_TILE_CODING_CMD) + 124 PATCH_LIST_COMMAND(avp::Itf::AVP_BSD_OBJECT_CMD); 125 } 126 else 127 { 128 maxSize = mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize * 5 + 129 mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize + 130 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PIPE_MODE_SELECT_CMD::byteSize * 2 + 131 mhw::vdbox::avp::xe_hpm::Cmd::AVP_SURFACE_STATE_CMD::byteSize * 11 + 132 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PIPE_BUF_ADDR_STATE_CMD::byteSize + 133 mhw::vdbox::avp::xe_hpm::Cmd::AVP_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 134 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PIC_STATE_CMD::byteSize + 135 mhw::vdbox::avp::xe_hpm::Cmd::AVP_INTER_PRED_STATE_CMD::byteSize + 136 mhw::vdbox::avp::xe_hpm::Cmd::AVP_SEGMENT_STATE_CMD::byteSize * 8 + 137 mhw::vdbox::avp::xe_hpm::Cmd::AVP_INLOOP_FILTER_STATE_CMD::byteSize + 138 mhw::vdbox::avp::xe_hpm::Cmd::AVP_TILE_CODING_CMD::byteSize + 139 mhw::vdbox::avp::xe_hpm::Cmd::AVP_PAK_INSERT_OBJECT_CMD::byteSize * 9 + 140 mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize; 141 142 patchListMaxSize = 143 PATCH_LIST_COMMAND(avp::Itf::VD_PIPELINE_FLUSH_CMD) + 144 PATCH_LIST_COMMAND(avp::Itf::AVP_PIPE_MODE_SELECT_CMD) + 145 PATCH_LIST_COMMAND(avp::Itf::AVP_SURFACE_STATE_CMD) * 11 + 146 PATCH_LIST_COMMAND(avp::Itf::AVP_PIPE_BUF_ADDR_STATE_CMD) + 147 PATCH_LIST_COMMAND(avp::Itf::AVP_IND_OBJ_BASE_ADDR_STATE_CMD) + 148 PATCH_LIST_COMMAND(avp::Itf::AVP_PIC_STATE_CMD) + 149 PATCH_LIST_COMMAND(avp::Itf::AVP_INTER_PRED_STATE_CMD) + 150 PATCH_LIST_COMMAND(avp::Itf::AVP_SEGMENT_STATE_CMD) * 8 + 151 PATCH_LIST_COMMAND(avp::Itf::AVP_INLOOP_FILTER_STATE_CMD) + 152 PATCH_LIST_COMMAND(avp::Itf::AVP_TILE_CODING_CMD) + 153 PATCH_LIST_COMMAND(avp::Itf::AVP_PAK_INSERT_OBJECT_CMD); 154 } 155 156 *commandsSize = maxSize; 157 *patchListSize = patchListMaxSize; 158 159 return MOS_STATUS_SUCCESS; 160 } 161 162 protected: 163 using cmd_t = Cmd; 164 using base_t = avp::Impl<Cmd>; 165 166 // Programming Note: CodecHAL layer must add MFX wait command 167 // for both KIN and VRT before and after AVP_PIPE_MODE_SELECT _MHW_SETCMD_OVERRIDE_DECL(AVP_PIPE_MODE_SELECT)168 _MHW_SETCMD_OVERRIDE_DECL(AVP_PIPE_MODE_SELECT) 169 { 170 _MHW_SETCMD_CALLBASE(AVP_PIPE_MODE_SELECT); 171 172 #define DO_FIELDS() \ 173 DO_FIELD(DW1, TileStatsStreamoutEnable, params.tileStatsStreamoutEnable ? 1 : 0); \ 174 \ 175 DO_FIELD(DW6, PAKFrameLevelStreamOutEnable, params.pakFrameLevelStreamOutEnable); \ 176 DO_FIELD(DW6, MotionCompMemoryTrackerCntEnable, params.motionCompMemoryTrackerCntEnable ? 1 : 0); \ 177 DO_FIELD(DW6, SourcePixelPrefetchLen, params.srcPixelPrefetchLen); \ 178 DO_FIELD(DW6, SourcePixelPrefetchEnable, params.srcPixelPrefetchEnable ? 1 : 0) 179 180 #include "mhw_hwcmd_process_cmdfields.h" 181 } 182 _MHW_SETCMD_OVERRIDE_DECL(AVP_SURFACE_STATE)183 _MHW_SETCMD_OVERRIDE_DECL(AVP_SURFACE_STATE) 184 { 185 _MHW_SETCMD_CALLBASE(AVP_SURFACE_STATE); 186 187 constexpr uint32_t m_rawUVPlaneAlignment = 4; 188 constexpr uint32_t m_reconUVPlaneAlignment = 8; 189 constexpr uint32_t m_uvPlaneAlignmentLegacy = 8; 190 191 uint32_t uvPlaneAlignment = m_uvPlaneAlignmentLegacy; 192 if (params.surfaceStateId == srcInputPic) 193 { 194 uvPlaneAlignment = params.uvPlaneAlignment ? params.uvPlaneAlignment : m_rawUVPlaneAlignment; 195 } 196 else 197 { 198 uvPlaneAlignment = params.uvPlaneAlignment ? params.uvPlaneAlignment : m_reconUVPlaneAlignment; 199 } 200 201 #define DO_FIELDS() \ 202 DO_FIELD(DW2, YOffsetForUCbInPixel, MOS_ALIGN_CEIL(params.uOffset, uvPlaneAlignment)); \ 203 \ 204 DO_FIELD(DW4, MemoryCompressionEnableForAv1IntraFrame, MmcEnabled(params.mmcState[intraFrame]) ? 0xff : 0); \ 205 DO_FIELD(DW4, MemoryCompressionEnableForAv1LastFrame, MmcEnabled(params.mmcState[lastFrame]) ? 0xff : 0); \ 206 DO_FIELD(DW4, MemoryCompressionEnableForAv1Last2Frame, MmcEnabled(params.mmcState[last2Frame]) ? 0xff : 0); \ 207 DO_FIELD(DW4, MemoryCompressionEnableForAv1Last3Frame, MmcEnabled(params.mmcState[last3Frame]) ? 0xff : 0); \ 208 DO_FIELD(DW4, MemoryCompressionEnableForAv1GoldenFrame, MmcEnabled(params.mmcState[goldenFrame]) ? 0xff : 0); \ 209 DO_FIELD(DW4, MemoryCompressionEnableForAv1BwdrefFrame, MmcEnabled(params.mmcState[bwdRefFrame]) ? 0xff : 0); \ 210 DO_FIELD(DW4, MemoryCompressionEnableForAv1Altref2Frame, MmcEnabled(params.mmcState[altRef2Frame]) ? 0xff : 0); \ 211 DO_FIELD(DW4, MemoryCompressionEnableForAv1AltrefFrame, MmcEnabled(params.mmcState[altRefFrame]) ? 0xff : 0); \ 212 DO_FIELD(DW4, CompressionTypeForIntraFrame, MmcRcEnabled(params.mmcState[intraFrame]) ? 0xff : 0); \ 213 DO_FIELD(DW4, CompressionTypeForLastFrame, MmcRcEnabled(params.mmcState[lastFrame]) ? 0xff : 0); \ 214 DO_FIELD(DW4, CompressionTypeForLast2Frame, MmcRcEnabled(params.mmcState[last2Frame]) ? 0xff : 0); \ 215 DO_FIELD(DW4, CompressionTypeForLast3Frame, MmcRcEnabled(params.mmcState[last3Frame]) ? 0xff : 0); \ 216 DO_FIELD(DW4, CompressionTypeForGoldenFrame, MmcRcEnabled(params.mmcState[goldenFrame]) ? 0xff : 0); \ 217 DO_FIELD(DW4, CompressionTypeForBwdrefFrame, MmcRcEnabled(params.mmcState[bwdRefFrame]) ? 0xff : 0); \ 218 DO_FIELD(DW4, CompressionTypeForAltref2Frame, MmcRcEnabled(params.mmcState[altRef2Frame]) ? 0xff : 0); \ 219 DO_FIELD(DW4, CompressionTypeForAltrefFrame, MmcRcEnabled(params.mmcState[altRefFrame]) ? 0xff : 0) 220 221 #include "mhw_hwcmd_process_cmdfields.h" 222 } 223 224 }; 225 } // xe_hpm 226 } // avp 227 } // vdbox 228 } // mhw 229 230 #endif // __MHW_VDBOX_AVP_IMPL_XE_HPM_H__ 231