xref: /aosp_15_r20/external/intel-media-driver/media_driver/agnostic/gen11/hw/vdbox/mhw_vdbox_g11_X.h (revision ba62d9d3abf0e404f2022b4cd7a85e107f48596f)
1 /*
2 * Copyright (c) 2014-2018, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file      mhw_vdbox.h
24 //! \brief     This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across MHW components.
25 //!
26 //!
27 //! \file     mhw_vdbox_g11_X.h
28 //! \brief    Defines structures used for constructing Vdbox commands on Gen11-based platforms
29 //!
30 
31 #ifndef _MHW_VDBOX_G11_H_
32 #define _MHW_VDBOX_G11_H_
33 
34 #include "mos_os.h"
35 #include "mhw_vdbox.h"
36 
37 struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G11 : public MHW_VDBOX_PIPE_MODE_SELECT_PARAMS
38 {
39     MHW_VDBOX_HCP_PIPE_WORK_MODE      PipeWorkMode = MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY;
40     MHW_VDBOX_HCP_MULTI_ENGINE_MODE   MultiEngineMode = MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY;
~MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G11MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G1141     virtual ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G11(){}
42 };
43 using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G11 = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G11 *;
44 
45 struct MHW_VDBOX_STATE_CMDSIZE_PARAMS_G11 : public MHW_VDBOX_STATE_CMDSIZE_PARAMS
46 {
47     bool                        bScalableMode = false;
48 };
49 using PMHW_VDBOX_STATE_CMDSIZE_PARAMS_G11 = MHW_VDBOX_STATE_CMDSIZE_PARAMS_G11 *;
50 
51 struct MHW_VDBOX_HCP_TILE_CODING_PARAMS_G11
52 {
53     uint32_t        NumOfTilesInFrame;
54     uint32_t        NumOfTileColumnsInFrame;
55     uint32_t        TileStartLCUX;
56     uint32_t        TileStartLCUY;
57     uint16_t        TileHeightInMinCbMinus1;
58     uint16_t        TileWidthInMinCbMinus1;
59     bool            IsLastTileofColumn;
60     bool            IsLastTileofRow;
61     uint32_t        TileRowStoreSelect;
62     uint32_t        TileColumnStoreSelect;
63     uint32_t        Mode;
64     bool            IsFirstPass;
65     bool            IsLastPass;
66 
67     // Offsets for scalability
68     uint32_t        NumberOfActiveBePipes;
69     uint32_t        BitstreamByteOffset;
70     uint32_t        PakTileStatisticsOffset;
71     uint32_t        CuLevelStreamoutOffset;
72     uint32_t        SliceSizeStreamoutOffset;
73     uint32_t        CuRecordOffset;
74     uint32_t        SseRowstoreOffset;
75     uint32_t        SaoRowstoreOffset;
76     uint32_t        TileSizeStreamoutOffset;
77     uint32_t        Vp9ProbabilityCounterStreamoutOffset;
78     uint32_t        TileStreaminOffset;
79 
80     PMOS_RESOURCE   presHcpSyncBuffer; // this buffer is not used for either HEVC/VP9 encoder and decoder.
81 
82     //Decode specific sparameters
83     uint8_t         ucNumDecodePipes;
84     uint8_t         ucPipeIdx;
85 };
86 using PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 = MHW_VDBOX_HCP_TILE_CODING_PARAMS_G11 *;
87 
88 #endif
89