1 2 /*===================== begin_copyright_notice ================================== 3 4 # Copyright (c) 2024, Intel Corporation 5 # 6 # Permission is hereby granted, free of charge, to any person obtaining a 7 # copy of this software and associated documentation files (the "Software"), 8 # to deal in the Software without restriction, including without limitation 9 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 # and/or sell copies of the Software, and to permit persons to whom the 11 # Software is furnished to do so, subject to the following conditions: 12 # 13 # The above copyright notice and this permission notice shall be included 14 # in all copies or substantial portions of the Software. 15 # 16 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 # OTHER DEALINGS IN THE SOFTWARE. 23 24 ======================= end_copyright_notice ==================================*/ 25 //! 26 //! \file mhw_vdbox_hcp_hwcmd_xe2_lpm.h 27 //! \brief Auto-generated constructors for MHW and states. 28 //! \details This file may not be included outside of xe2_lpm as other components 29 //! should use MHW interface to interact with MHW commands and states. 30 //! 31 32 // DO NOT EDIT 33 34 #ifndef __MHW_VDBOX_HCP_HWCMD_XE2_LPM_H__ 35 #define __MHW_VDBOX_HCP_HWCMD_XE2_LPM_H__ 36 #include "mhw_hwcmd.h" 37 38 #pragma once 39 #pragma pack(1) 40 41 #include "mhw_hwcmd.h" 42 #include <cstdint> 43 #include <cstddef> 44 #include "media_class_trace.h" 45 46 namespace mhw 47 { 48 namespace vdbox 49 { 50 namespace hcp 51 { 52 namespace xe2_lpm_base 53 { 54 namespace xe2_lpm 55 { 56 class Cmd 57 { 58 public: GetOpLength(uint32_t uiLength)59 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 60 61 //! 62 //! \brief MEMORYADDRESSATTRIBUTES 63 //! \details 64 //! This field controls the priority of arbitration used in the GAC/GAM 65 //! pipeline for this surface. It defines the attributes for VDBOX addresses 66 //! on BDW+. 67 //! 68 struct MEMORYADDRESSATTRIBUTES_CMD 69 { 70 union 71 { 72 struct 73 { 74 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved0 75 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 76 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 77 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 78 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< COMPRESSION_TYPE 79 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 80 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 81 uint32_t TileMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILEMODE 82 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 83 }; 84 uint32_t Value; 85 } DW0; 86 87 //! \name Local enumerations 88 89 //! \brief COMPRESSION_TYPE 90 //! \details 91 //! Indicates if buffer is render/media compressed. 92 enum COMPRESSION_TYPE 93 { 94 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 95 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< Only support rendered compression with unified memory 96 }; 97 98 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 99 //! \details 100 //! This field controls if the Row Store is going to store inside Media 101 //! Cache (rowstore cache) or to LLC. 102 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 103 { 104 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 105 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 106 }; 107 108 enum TILEMODE 109 { 110 TILEMODE_LINEAR = 0, //!< No additional details 111 TILEMODE_TILES_64K = 1, //!< No additional details 112 TILEMODE_TILEX = 2, //!< No additional details 113 TILEMODE_TILEF = 3, //!< No additional details 114 }; 115 116 //! \name Initializations 117 118 //! \brief Explicit member initialization function MEMORYADDRESSATTRIBUTES_CMDMEMORYADDRESSATTRIBUTES_CMD119 MEMORYADDRESSATTRIBUTES_CMD() 120 { 121 DW0.Value = 0x00000000; 122 //DW0.CompressionType = COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE; 123 //DW0.BaseAddressRowStoreScratchBufferCacheSelect = BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0; 124 //DW0.TileMode = TILEMODE_LINEAR; 125 } 126 127 static const size_t dwSize = 1; 128 static const size_t byteSize = 4; 129 }; 130 131 //! 132 //! \brief SPLITBASEADDRESS64BYTEALIGNED 133 //! \details 134 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 135 //! address. 136 //! 137 //! Bits 63:48 must be zero. 138 //! 139 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 140 { 141 union 142 { 143 struct 144 { 145 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 146 uint64_t BaseAddress : __CODEGEN_BITFIELD( 6, 56) ; //!< Base Address 147 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63) ; //!< Reserved 148 }; 149 uint32_t Value[2]; 150 } DW0_1; 151 152 //! \name Local enumerations 153 154 //! \name Initializations 155 156 //! \brief Explicit member initialization function SPLITBASEADDRESS64BYTEALIGNED_CMDSPLITBASEADDRESS64BYTEALIGNED_CMD157 SPLITBASEADDRESS64BYTEALIGNED_CMD() 158 { 159 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 160 } 161 162 static const size_t dwSize = 2; 163 static const size_t byteSize = 8; 164 }; 165 166 //! 167 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 168 //! \details 169 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 170 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 171 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 172 //! 173 //! Bits 63:48 must be zero. 174 //! 175 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 176 { 177 union 178 { 179 struct 180 { 181 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 182 uint64_t BaseAddress : __CODEGEN_BITFIELD(12, 56) ; //!< Base Address 183 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63) ; //!< Reserved 184 }; 185 uint32_t Value[2]; 186 } DW0_1; 187 188 //! \name Local enumerations 189 190 //! \name Initializations 191 192 //! \brief Explicit member initialization function SPLITBASEADDRESS4KBYTEALIGNED_CMDSPLITBASEADDRESS4KBYTEALIGNED_CMD193 SPLITBASEADDRESS4KBYTEALIGNED_CMD() 194 { 195 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 196 } 197 198 static const size_t dwSize = 2; 199 static const size_t byteSize = 8; 200 }; 201 202 //! 203 //! \brief HCP_PIPE_MODE_SELECT 204 //! \details 205 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 206 //! Commands. Each HCP command has assigned a media instruction command as 207 //! defined in DWord 0, BitField 22:16. 208 //! 209 //! The workload for the HCP is based upon a single frame decode. There are 210 //! no states saved between framedecodes in the HCP. Once the bit stream DMA 211 //! is configured with the HCP_BSD_OBJECT command, and the bitstream is 212 //! presented to the HCP, the frame decode will begin.The 213 //! HCP_PIPE_MODE_SELECT command is responsible for general pipeline level 214 //! configuration that would normallybe set once for a single stream encode 215 //! or decode and would not be modified on a frame workload basis.This is a 216 //! picture level state command and is shared by both encoding and decoding 217 //! processes. 218 //! 219 struct HCP_PIPE_MODE_SELECT_CMD 220 { 221 union 222 { 223 struct 224 { 225 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 226 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 227 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 228 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 229 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 230 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 231 }; 232 uint32_t Value; 233 } DW0; 234 union 235 { 236 struct 237 { 238 uint32_t CodecSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< CODEC_SELECT 239 uint32_t DeblockerStreamoutEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< DEBLOCKER_STREAMOUT_ENABLE 240 uint32_t PakPipelineStreamoutEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< PAK_PIPELINE_STREAMOUT_ENABLE 241 uint32_t PicStatusErrorReportEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< PIC_STATUSERROR_REPORT_ENABLE 242 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 243 uint32_t CodecStandardSelect : __CODEGEN_BITFIELD( 5, 7) ; //!< CODEC_STANDARD_SELECT 244 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 245 uint32_t AdvancedRateControlEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Advanced Rate Control Enable 246 uint32_t VdencMode : __CODEGEN_BITFIELD(10, 10) ; //!< VDEnc_Mode 247 uint32_t RdoqEnabledFlag : __CODEGEN_BITFIELD(11, 11) ; //!< RDOQ_ENABLED_FLAG 248 uint32_t PakFrameLevelStreamoutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< PAK Frame Level StreamOut enable 249 uint32_t MultiEngineMode : __CODEGEN_BITFIELD(13, 14) ; //!< MULTI_ENGINE_MODE 250 uint32_t PipeWorkingMode : __CODEGEN_BITFIELD(15, 16) ; //!< PIPE_WORKING_MODE 251 uint32_t TileBasedEngine : __CODEGEN_BITFIELD(17, 17) ; //!< Tile Based Engine 252 uint32_t PrefetchDisable : __CODEGEN_BITFIELD(18, 18) ; //!< Prefetch Disable 253 uint32_t Vp9DynamicScalingEnable : __CODEGEN_BITFIELD(19, 19) ; //!< VP9 Dynamic scaling enable 254 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 255 uint32_t MotionCompMemoryTrackerCounterEnable : __CODEGEN_BITFIELD(23, 23) ; //!< Motion Comp Memory Tracker Counter Enable 256 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 257 }; 258 uint32_t Value; 259 } DW1; 260 union 261 { 262 struct 263 { 264 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 265 }; 266 uint32_t Value; 267 } DW2; 268 union 269 { 270 struct 271 { 272 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 273 }; 274 uint32_t Value; 275 } DW3; 276 union 277 { 278 struct 279 { 280 uint32_t Vp9FlushHandling : __CODEGEN_BITFIELD( 0, 0) ; //!< VP9_FLUSH_HANDLING 281 uint32_t Reserved129 : __CODEGEN_BITFIELD( 1, 1) ; //!< Reserved 282 uint32_t XformskipPaletteFix : __CODEGEN_BITFIELD( 2, 2) ; //!< xformskip_palette_fix 283 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 15) ; //!< Reserved 284 uint32_t Reserved132 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 285 uint32_t BitstreamDecoderErrorHandlingMode : __CODEGEN_BITFIELD(18, 18) ; //!< BITSTREAM_DECODER_ERROR_HANDLING_MODE 286 uint32_t Reserved147 : __CODEGEN_BITFIELD(19, 29) ; //!< Reserved 287 uint32_t HedIFrameMbConcealmentSchmooIssueEcoDisable : __CODEGEN_BITFIELD(30, 30) ; //!< HED_I_FRAME_MB_CONCEALMENT_SCHMOO_ISSUE_ECO_DISABLE 288 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 289 }; 290 uint32_t Value; 291 } DW4; 292 union 293 { 294 struct 295 { 296 uint32_t Reserved160 ; //!< Reserved 297 }; 298 uint32_t Value; 299 } DW5; 300 union 301 { 302 struct 303 { 304 uint32_t PhaseIndicator : __CODEGEN_BITFIELD( 0, 1) ; //!< PHASE_INDICATOR 305 uint32_t HevcSeparateTileProgramming : __CODEGEN_BITFIELD( 2, 2) ; //!< HEVC Separate Tile Programming 306 uint32_t FrameReconstructionDisable : __CODEGEN_BITFIELD( 3, 3) ; //!< Frame reconstruction disable 307 uint32_t SourcePixelPrefetchLength : __CODEGEN_BITFIELD( 4, 6) ; //!< Source Pixel Prefetch Length 308 uint32_t SourcePixelPrefetchEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Source Pixel PreFetch Enable 309 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 310 }; 311 uint32_t Value; 312 } DW6; 313 314 //! \name Local enumerations 315 316 enum MEDIA_INSTRUCTION_COMMAND 317 { 318 MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT = 0, //!< No additional details 319 }; 320 321 //! \brief MEDIA_INSTRUCTION_OPCODE 322 //! \details 323 //! Codec/Engine Name = HCP = 7h 324 enum MEDIA_INSTRUCTION_OPCODE 325 { 326 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 327 }; 328 329 enum PIPELINE_TYPE 330 { 331 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 332 }; 333 334 enum COMMAND_TYPE 335 { 336 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 337 }; 338 339 enum CODEC_SELECT 340 { 341 CODEC_SELECT_DECODE = 0, //!< No additional details 342 CODEC_SELECT_ENCODE = 1, //!< No additional details 343 }; 344 345 //! \brief DEBLOCKER_STREAMOUT_ENABLE 346 //! \details 347 //! Deblocker Streamout Enable not currently supported for Encode or Decode 348 enum DEBLOCKER_STREAMOUT_ENABLE 349 { 350 DEBLOCKER_STREAMOUT_ENABLE_DISABLE = 0, //!< Disable deblocker-only parameter streamout 351 DEBLOCKER_STREAMOUT_ENABLE_ENABLE = 1, //!< Enable deblocker-only parameter streamout 352 }; 353 354 //! \brief PAK_PIPELINE_STREAMOUT_ENABLE 355 //! \details 356 //! Pipeline Streamout Enable is only defined for encode. It is ignored for 357 //! decode. 358 enum PAK_PIPELINE_STREAMOUT_ENABLE 359 { 360 PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 0, //!< No additional details 361 PAK_PIPELINE_STREAMOUT_ENABLE_ENABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 1, //!< No additional details 362 }; 363 364 enum PIC_STATUSERROR_REPORT_ENABLE 365 { 366 PIC_STATUSERROR_REPORT_ENABLE_DISABLE = 0, //!< Disable status/error reporting 367 PIC_STATUSERROR_REPORT_ENABLE_ENABLE = 1, //!< Status/Error reporting is written out once per picture. The Pic Status/Error Report ID in DWord3along with the status/error status bits are packed into one cache line and written to theStatus/Error Buffer address in the HCP_PIPE_BUF_ADDR_STATE command. Must be zero for encoder mode. 368 }; 369 370 enum CODEC_STANDARD_SELECT 371 { 372 CODEC_STANDARD_SELECT_HEVC = 0, //!< No additional details 373 CODEC_STANDARD_SELECT_VP9 = 1, //!< No additional details 374 }; 375 376 enum RDOQ_ENABLED_FLAG 377 { 378 RDOQ_ENABLED_FLAG_DISABLED = 0, //!< No additional details 379 RDOQ_ENABLED_FLAG_ENABLED = 1, //!< No additional details 380 }; 381 382 //! \brief MULTI_ENGINE_MODE 383 //! \details 384 //! This indicates the current pipe is in single pipe mode or if in 385 //! scalable mode is in left/right/middle pipe in multi-engine mode. 386 enum MULTI_ENGINE_MODE 387 { 388 MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE = 0, //!< This is for single engine mode (legacy) OR CABAC FE only decode mode 389 MULTI_ENGINE_MODE_PIPEISTHELEFTENGINEINAMULTI_ENGINEMODE = 1, //!< Current pipe is the most left engine while running in scalable multi-engine mode 390 MULTI_ENGINE_MODE_PIPEISTHERIGHTENGINEINAMULTI_ENGINEMODE = 2, //!< Current pipe is the most right engine while running in scalable multi-engine mode 391 MULTI_ENGINE_MODE_PIPEISONEOFTHEMIDDLEENGINEINAMULTI_ENGINEMODE = 3, //!< Current pipe is in one of the middle engine while running in scalable multi-engine mode 392 }; 393 394 //! \brief PIPE_WORKING_MODE 395 //! \details 396 //! This programs the working mode for HCP pipe. 397 enum PIPE_WORKING_MODE 398 { 399 PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE = 0, //!< This is for single pipe mode non-scalable mode. It is used by both decoder and encoder. 400 PIPE_WORKING_MODE_CABACFEONLYDECODEMODE_SINGLECABACPIPE = 1, //!< This is for the single CABAC FE only in decoder mode. This will be only run CABAC and streamout syntax element. 401 PIPE_WORKING_MODE_DECODERBEONLYORENCODERMODE_SCALABLEMULTI_PIPE = 2, //!< This is for multiple-pipe scalable mode. In decoder, it is only on BE reconstruction. In encoder, it is for PAK. 402 PIPE_WORKING_MODE_DECODERSCALABLEMODEWITHCABACINREALTILES_SCALABLEMULTI_PIPE = 3, //!< This is for multiple-pipe scalable mode decoder mode in real tiles. CABAC and reconstruction will run together. Each pipes will run in real tiles vertically. 403 }; 404 405 //! \brief DECODER_FRAME_AND_CU_DATA_STREAMOUT_ENABLE 406 //! \details 407 //! Decoder Frame and CU Data Streamout Enable is for decoder only. 408 //! Encoder should set this to "0". 409 //! This enables frame/CU data streamout for transcoding later 410 //! during decode pass. 411 //! This streamout is supported in single pipe and real tile 412 //! scalability mode. 413 enum DECODER_FRAME_AND_CU_DATA_STREAMOUT_ENABLE 414 { 415 DECODER_FRAME_AND_CU_DATA_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 416 DECODER_FRAME_AND_CU_DATA_STREAMOUT_ENABLE_ENABLE = 1, //!< Not allowed in encoder mode 417 }; 418 419 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 420 //! \details 421 //! In decoder modes, this counter value specifies the number of clocks (per 422 //! 1000) of GAC inactivitybefore a media soft-reset is applied to the HCP 423 //! and HuC. If counter value is set to 0, the mediasoft-reset feature is 424 //! disabled and no reset will occur.In encoder modes, this counter must 425 //! be set to 0 to disable media soft reset. This feature is notsupported 426 //! for the encoder. 427 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 428 { 429 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 430 }; 431 432 //! \brief PIC_STATUSERROR_REPORT_ID 433 //! \details 434 //! The Pic Status/Error Report ID is a unique 32-bit unsigned integer 435 //! assigned to each picturestatus/error output. Must be zero for encoder 436 //! mode. 437 enum PIC_STATUSERROR_REPORT_ID 438 { 439 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 440 }; 441 442 //! \brief VP9_FLUSH_HANDLING 443 //! \details 444 //! This modifies how flush is handled "0"--In VP9 mode, 445 //! all unit done is accounted for before flush; "1"--In VP9 446 //! mode, only frame done is accounted for before flush; 447 enum VP9_FLUSH_HANDLING 448 { 449 VP9_FLUSH_HANDLING_FLUSHUSINGUNITDONE = 0, //!< No additional details 450 VP9_FLUSH_HANDLING_FLUSHUSINGFRAMEDONE = 1, //!< No additional details 451 }; 452 453 //! \brief BITSTREAM_DECODER_ERROR_HANDLING_MODE 454 //! \details 455 //! This modifies how bitstream decoder handles error when there are 456 //! extra bitstream within the tiles "0"--Decoder will trust 457 //! the tile byte length and flush extra unused bitstream 458 //! "1"--Decoder will trust its own decoding logic (ignore byte length). 459 //! Decoder will start decoding the next tile right after the previous tile 460 //! finished decoding (bitstream handling) 461 enum BITSTREAM_DECODER_ERROR_HANDLING_MODE 462 { 463 BITSTREAM_DECODER_ERROR_HANDLING_MODE_TRUSTBYTELENGTH = 0, //!< No additional details 464 BITSTREAM_DECODER_ERROR_HANDLING_MODE_TRUSTDECODINGLOGIC = 1, //!< No additional details 465 }; 466 467 //! \brief HED_I_FRAME_MB_CONCEALMENT_SCHMOO_ISSUE_ECO_DISABLE 468 //! \details 469 //! This is chicken bit for HED I Frame MB Concealment issue. During MB 470 //! Concealment at the end of MB, HED generates an extra TU state causing 471 //! HPP to generate MV request to HMC. Since HMC is not programmed, it is 472 //! causing page fault. An ECO is made and this is chicken bit to disable. 473 enum HED_I_FRAME_MB_CONCEALMENT_SCHMOO_ISSUE_ECO_DISABLE 474 { 475 HED_I_FRAME_MB_CONCEALMENT_SCHMOO_ISSUE_ECO_DISABLE_ENABLE = 0, //!< No additional details 476 HED_I_FRAME_MB_CONCEALMENT_SCHMOO_ISSUE_ECO_DISABLE_DISABLE = 1, //!< No additional details 477 }; 478 479 //! \brief PHASE_INDICATOR 480 //! \details 481 //! This is used to indicate whether this is first, middle or last phase 482 //! of programming during Real-Tile Decoder Mode. Since HEVC can have up to 483 //! 20 tile columns, maximum 10 phases are possible during 2 VDbox scalable 484 //! mode. This is used by hardware to know if the current programming is 485 //! first or last phases. This field is ignored (programmed 486 //! to 0) for other modes other than HEVC Real-Tile Decoder Mode. 487 enum PHASE_INDICATOR 488 { 489 PHASE_INDICATOR_FIRSTPHASE = 0, //!< No additional details 490 PHASE_INDICATOR_MIDDLEPHASE = 1, //!< No additional details 491 PHASE_INDICATOR_LASTPHASE = 2, //!< No additional details 492 }; 493 494 //! \name Initializations 495 496 //! \brief Explicit member initialization function HCP_PIPE_MODE_SELECT_CMDHCP_PIPE_MODE_SELECT_CMD497 HCP_PIPE_MODE_SELECT_CMD() 498 { 499 DW0.Value = 0x73800005; 500 //DW0.DwordLength = GetOpLength(dwSize); 501 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT; 502 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 503 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 504 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 505 506 DW1.Value = 0x00000000; 507 //DW1.CodecSelect = CODEC_SELECT_DECODE; 508 //DW1.DeblockerStreamoutEnable = DEBLOCKER_STREAMOUT_ENABLE_DISABLE; 509 //DW1.PakPipelineStreamoutEnable = PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT; 510 //DW1.PicStatusErrorReportEnable = PIC_STATUSERROR_REPORT_ENABLE_DISABLE; 511 //DW1.CodecStandardSelect = CODEC_STANDARD_SELECT_HEVC; 512 //DW1.RdoqEnabledFlag = RDOQ_ENABLED_FLAG_DISABLED; 513 //DW1.MultiEngineMode = MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE; 514 //DW1.PipeWorkingMode = PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE; 515 //DW1.DecoderFrameAndCuDataStreamoutEnable = DECODER_FRAME_AND_CU_DATA_STREAMOUT_ENABLE_DISABLE; 516 517 DW2.Value = 0x00000000; 518 //DW2.MediaSoftResetCounterPer1000Clocks = MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE; 519 520 DW3.Value = 0x00000000; 521 //DW3.PicStatusErrorReportId = PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED; 522 523 DW4.Value = 0x00000000; 524 //DW4.Vp9FlushHandling = VP9_FLUSH_HANDLING_FLUSHUSINGUNITDONE; 525 //DW4.BitstreamDecoderErrorHandlingMode = BITSTREAM_DECODER_ERROR_HANDLING_MODE_TRUSTBYTELENGTH; 526 //DW4.HedIFrameMbConcealmentSchmooIssueEcoDisable = HED_I_FRAME_MB_CONCEALMENT_SCHMOO_ISSUE_ECO_DISABLE_ENABLE; 527 528 DW5.Value = 0x00000000; 529 530 DW6.Value = 0x00000000; 531 //DW6.PhaseIndicator = PHASE_INDICATOR_FIRSTPHASE; 532 } 533 534 static const size_t dwSize = 7; 535 static const size_t byteSize = 28; 536 }; 537 538 //! 539 //! \brief HCP_SURFACE_STATE 540 //! \details 541 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 542 //! Commands.Each HCP command has assigned a media instruction command as 543 //! defined in DWord 0, BitField 22:16. 544 //! 545 //! The HCP_SURFACE_STATE command is responsible for defining the frame 546 //! buffer pitch and the offset of the chroma component.This is a picture 547 //! level state command and is shared by both encoding and decoding 548 //! processes.Note : When NV12/P010 and Tile Y are being used, full pitch 549 //! and interleaved UV is always in use. U and V Xoffset must be set to 0; U 550 //! and V Yoffset must be 4-pixel aligned. For 10-bit pixel, P010 surface 551 //! definition is being used. 552 //! 553 struct HCP_SURFACE_STATE_CMD 554 { 555 union 556 { 557 struct 558 { 559 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 560 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 561 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 562 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 563 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 564 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 565 }; 566 uint32_t Value; 567 } DW0; 568 union 569 { 570 struct 571 { 572 uint32_t SurfacePitchMinus1 : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch Minus1 573 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 27) ; //!< Reserved 574 uint32_t SurfaceId : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_ID 575 }; 576 uint32_t Value; 577 } DW1; 578 union 579 { 580 struct 581 { 582 uint32_t YOffsetForUCbInPixel : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) in pixel 583 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 584 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 585 }; 586 uint32_t Value; 587 } DW2; 588 union 589 { 590 struct 591 { 592 uint32_t DefaultAlphaValue : __CODEGEN_BITFIELD( 0, 15) ; //!< Default Alpha Value 593 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(16, 31) ; //!< Y Offset for V(Cr) 594 }; 595 uint32_t Value; 596 } DW3; 597 union 598 { 599 struct 600 { 601 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 7) ; //!< MEMORY_COMPRESSION_ENABLE 602 uint32_t CompressionType : __CODEGEN_BITFIELD( 8, 15) ; //!< COMPRESSION_TYPE 603 uint32_t CompressionFormat : __CODEGEN_BITFIELD(16, 20) ; //!< COMPRESSION_FORMAT 604 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 605 }; 606 uint32_t Value; 607 } DW4; 608 609 //! \name Local enumerations 610 611 enum MEDIA_INSTRUCTION_COMMAND 612 { 613 MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE = 1, //!< No additional details 614 }; 615 616 //! \brief MEDIA_INSTRUCTION_OPCODE 617 //! \details 618 //! Codec/Engine Name = HCP = 7h 619 enum MEDIA_INSTRUCTION_OPCODE 620 { 621 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 622 }; 623 624 enum PIPELINE_TYPE 625 { 626 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 627 }; 628 629 enum COMMAND_TYPE 630 { 631 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 632 }; 633 634 enum SURFACE_ID 635 { 636 SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE = 0, //!< 8-bit uncompressed data 637 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 1, //!< 8-bit uncompressed data 638 SURFACE_ID_PREVREFERENCEPICTURE = 2, //!< (VP9 only) Previous Reference 639 SURFACE_ID_GOLDENREFERENCEPICTURE = 3, //!< (VP9 only) Golden Reference 640 SURFACE_ID_ALTREFREFERENCEPICTURE = 4, //!< (VP9 only) AltRef Reference 641 SURFACE_ID_HEVCREFERENCEPICTURES = 5, //!< (HEVC only) Reference. Also, this will have separate compressible bits per reference surfaces for HEVC 642 }; 643 644 //! \brief SURFACE_FORMAT 645 //! \details 646 //! Specifies the format of the surface. 647 enum SURFACE_FORMAT 648 { 649 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details 650 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details 651 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details 652 SURFACE_FORMAT_P010VARIANT = 3, //!< P010Variant is a modified P010 format, >8 bit planar 420 with MSB together and LSB at an offset in x direction where the x-offset should be 32-bit aligned. 653 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 654 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details 655 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details 656 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details 657 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210 658 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details 659 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details 660 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details 661 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details 662 SURFACE_FORMAT_P010 = 13, //!< No additional details 663 SURFACE_FORMAT_P016 = 14, //!< No additional details 664 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details 665 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details 666 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 667 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 668 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 669 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 670 }; 671 672 //! \brief MEMORY_COMPRESSION_ENABLE 673 //! \details 674 //! In HEVC mode, each bit is used for 1 reference starting with Bit 0 675 //! for Ref 0 in the ref list and Bit 1 for Ref 1 and so on. 676 //! In VP9 mode, Bit 0 is for Previous Reference; Bit 1 is for Golden 677 //! Reference and Bit 2 is for Alterante Reference; Bits 3-7 are unused and 678 //! should be programmed to 0. 679 enum MEMORY_COMPRESSION_ENABLE 680 { 681 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE = 0, //!< No additional details 682 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONENABLE = 1, //!< No additional details 683 }; 684 685 //! \brief COMPRESSION_TYPE 686 //! \details 687 //! This field indicates if the compression type for the reference 688 //! surface is media or render compressed. In HEVC mode, 689 //! each bit is used for 1 reference starting with Bit 8for Ref 0 in the ref 690 //! list and Bit 9for Ref 1 and so on. In VP9 mode, Bit 8is 691 //! for Previous Reference; Bit 9is for Golden Reference and Bit 10is for 692 //! Alterante Reference; Bits11-15are unused and should be programmed to 693 //! 0 694 enum COMPRESSION_TYPE 695 { 696 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 697 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 698 }; 699 700 //! \brief COMPRESSION_FORMAT 701 //! \details 702 //! Specifies the compression format to be used. 703 enum COMPRESSION_FORMAT 704 { 705 COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 706 COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 707 COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 708 COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 709 COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 710 COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 711 COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 712 COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 713 COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 714 COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 715 COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 716 COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 717 COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 718 }; 719 720 //! \name Initializations 721 722 //! \brief Explicit member initialization function HCP_SURFACE_STATE_CMDHCP_SURFACE_STATE_CMD723 HCP_SURFACE_STATE_CMD() 724 { 725 DW0.Value = 0x73810003; 726 //DW0.DwordLength = GetOpLength(dwSize); 727 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE; 728 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 729 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 730 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 731 732 DW1.Value = 0x00000000; 733 //DW1.SurfaceId = SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE; 734 735 DW2.Value = 0x00000000; 736 //DW2.SurfaceFormat = SURFACE_FORMAT_YUY2FORMAT; 737 738 DW3.Value = 0x00000000; 739 740 DW4.Value = 0x00000000; 741 //DW4.MemoryCompressionEnable = MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE; 742 //DW4.CompressionType = COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED; 743 //DW4.CompressionFormat = COMPRESSION_FORMAT_CMFR8; 744 } 745 746 static const size_t dwSize = 5; 747 static const size_t byteSize = 20; 748 }; 749 750 //! 751 //! \brief HCP_PIPE_BUF_ADDR_STATE 752 //! \details 753 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 754 //! Commands.Each HCP command has assigned a media instruction command as 755 //! defined in DWord 0, BitField 22:16. 756 //! 757 //! This state command provides the memory base addresses for the row store 758 //! buffer and reconstructed pictureoutput buffers required by the HCP.This 759 //! is a picture level state command and is shared by both encoding and 760 //! decoding processes. 761 //! 762 //! All pixel surface addresses must be 4K byte aligned. There is a max of 8 763 //! Reference Picture BufferAddresses, and all share the same third address 764 //! DW in specifying 48-bit address. 765 //! 766 struct HCP_PIPE_BUF_ADDR_STATE_CMD 767 { 768 union 769 { 770 struct 771 { 772 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 773 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 774 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 775 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 776 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 777 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 778 }; 779 uint32_t Value; 780 } DW0; 781 SPLITBASEADDRESS4KBYTEALIGNED_CMD DecodedPicture; //!< DW1..2, Decoded Picture 782 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureMemoryAddressAttributes; //!< DW3, Decoded Picture Memory Address Attributes 783 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterLineBuffer; //!< DW4..5, Deblocking Filter Line Buffer 784 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterLineBufferMemoryAddressAttributes; //!< DW6, Deblocking Filter Line Buffer Memory Address Attributes 785 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileLineBuffer; //!< DW7..8, Deblocking Filter Tile Line Buffer 786 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileLineBufferMemoryAddressAttributes; //!< DW9, Deblocking Filter Tile Line Buffer Memory Address Attributes 787 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileColumnBuffer; //!< DW10..11, Deblocking Filter Tile Column Buffer 788 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileColumnBufferMemoryAddressAttributes; //!< DW12, Deblocking Filter Tile Column Buffer Memory Address Attributes 789 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataLineBuffer; //!< DW13..14, Metadata Line Buffer 790 MEMORYADDRESSATTRIBUTES_CMD MetadataLineBufferMemoryAddressAttributes; //!< DW15, Metadata Line Buffer Memory Address Attributes 791 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileLineBuffer; //!< DW16..17, Metadata Tile Line Buffer 792 MEMORYADDRESSATTRIBUTES_CMD MetadataTileLineBufferMemoryAddressAttributes; //!< DW18, Metadata Tile Line Buffer Memory Address Attributes 793 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileColumnBuffer; //!< DW19..20, Metadata Tile Column Buffer 794 MEMORYADDRESSATTRIBUTES_CMD MetadataTileColumnBufferMemoryAddressAttributes; //!< DW21, Metadata Tile Column Buffer Memory Address Attributes 795 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoLineBuffer; //!< DW22..23, SAO Line Buffer 796 MEMORYADDRESSATTRIBUTES_CMD SaoLineBufferMemoryAddressAttributes; //!< DW24, SAO Line Buffer Memory Address Attributes 797 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileLineBuffer; //!< DW25..26, SAO Tile Line Buffer 798 MEMORYADDRESSATTRIBUTES_CMD SaoTileLineBufferMemoryAddressAttributes; //!< DW27, SAO Tile Line Buffer Memory Address Attributes 799 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileColumnBuffer; //!< DW28..29, SAO Tile Column Buffer 800 MEMORYADDRESSATTRIBUTES_CMD SaoTileColumnBufferMemoryAddressAttributes; //!< DW30, SAO Tile Column Buffer Memory Address Attributes 801 SPLITBASEADDRESS64BYTEALIGNED_CMD CurrentMotionVectorTemporalBuffer; //!< DW31..32, Current Motion Vector Temporal Buffer 802 MEMORYADDRESSATTRIBUTES_CMD CurrentMotionVectorTemporalBufferMemoryAddressAttributes; //!< DW33, Current Motion Vector Temporal Buffer Memory Address Attributes 803 union 804 { 805 struct 806 { 807 uint64_t Reserved1088 ; //!< Reserved 808 }; 809 uint32_t Value[2]; 810 } DW34_35; 811 union 812 { 813 struct 814 { 815 uint32_t Reserved1152 ; //!< Reserved 816 }; 817 uint32_t Value; 818 } DW36; 819 SPLITBASEADDRESS64BYTEALIGNED_CMD ReferencePictureBaseAddressRefaddr07[8]; //!< DW37..52, Reference Picture Base Address (RefAddr[0-7]) 820 MEMORYADDRESSATTRIBUTES_CMD ReferencePictureBaseAddressMemoryAddressAttributes; //!< DW53, Reference Picture Base Address Memory Address Attributes 821 SPLITBASEADDRESS64BYTEALIGNED_CMD OriginalUncompressedPictureSource; //!< DW54..55, Original Uncompressed Picture Source 822 MEMORYADDRESSATTRIBUTES_CMD OriginalUncompressedPictureSourceMemoryAddressAttributes; //!< DW56, Original Uncompressed Picture Source Memory Address Attributes 823 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutDataDestination; //!< DW57..58, Streamout Data Destination 824 MEMORYADDRESSATTRIBUTES_CMD StreamoutDataDestinationMemoryAddressAttributes; //!< DW59, Streamout Data Destination Memory Address Attributes 825 SPLITBASEADDRESS64BYTEALIGNED_CMD DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress;//!< DW60..61, Decoded Picture Status/Error Buffer Base Address or Encoded slice size streamout Base Address 826 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes; //!< DW62, Decoded Picture Status/Error Buffer Base Address Memory Address Attributes 827 SPLITBASEADDRESS64BYTEALIGNED_CMD LcuIldbStreamoutBuffer; //!< DW63..64, LCU ILDB Streamout Buffer 828 MEMORYADDRESSATTRIBUTES_CMD LcuIldbStreamoutBufferMemoryAddressAttributes; //!< DW65, LCU ILDB Streamout Buffer Memory Address Attributes 829 SPLITBASEADDRESS64BYTEALIGNED_CMD CollocatedMotionVectorTemporalBuffer07[8]; //!< DW66..81, Collocated Motion Vector Temporal Buffer[0-7] 830 MEMORYADDRESSATTRIBUTES_CMD CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes; //!< DW82, Collocated Motion Vector Temporal Buffer[0-7] Memory Address Attributes 831 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9ProbabilityBufferReadWrite; //!< DW83..84, VP9 Probability Buffer Read/Write 832 MEMORYADDRESSATTRIBUTES_CMD Vp9ProbabilityBufferReadWriteMemoryAddressAttributes; //!< DW85, VP9 Probability Buffer Read/Write Memory Address Attributes 833 union 834 { 835 struct 836 { 837 uint64_t Vp9SegmentIdBufferReadWrite ; //!< VP9 Segment ID Buffer Read/Write 838 }; 839 uint32_t Value[2]; 840 } DW86_87; 841 MEMORYADDRESSATTRIBUTES_CMD Vp9SegmentIdBufferReadWriteMemoryAddressAttributes; //!< DW88, VP9 Segment ID buffer Read/Write Memory Address Attributes 842 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdLineRowstoreBufferReadWrite; //!< DW89..90, VP9 HVD Line Rowstore Buffer Read/Write 843 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW91, VP9 HVD Line Rowstore buffer Read/Write Memory Address Attributes 844 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdTileRowstoreBufferReadWrite; //!< DW92..93, VP9 HVD Tile Rowstore Buffer Read/Write 845 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW94, VP9 HVD Tile Rowstore buffer Read/Write Memory Address Attributes 846 union 847 { 848 struct 849 { 850 uint64_t SaoRowstoreBufferBaseAddress ; //!< SAO Rowstore Buffer Base Address 851 }; 852 uint32_t Value[2]; 853 } DW95_96; 854 MEMORYADDRESSATTRIBUTES_CMD SaoRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW97, SAO Rowstore Buffer Read/Write Memory Address Attributes 855 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameStatisticsStreamoutDataDestinationBufferBaseAddress; //!< DW98..99, Frame Statistics Streamout Data Destination Buffer Base Address 856 MEMORYADDRESSATTRIBUTES_CMD FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite; //!< DW100, Frame Statistics Streamout Data Destination buffer (attributes) Read/Write 857 SPLITBASEADDRESS64BYTEALIGNED_CMD SseSourcePixelRowstoreBufferBaseAddress; //!< DW101..102, SSE Source Pixel RowStore Buffer Base Address 858 MEMORYADDRESSATTRIBUTES_CMD SseSourcePixelRowstoreBufferAttributesReadWrite; //!< DW103, SSE Source Pixel RowStore buffer (attributes) Read/Write 859 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySliceStateBufferBaseAddress; //!< DW104..105, HCP Scalability Slice State Buffer Base Address 860 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySliceStateBufferAttributesReadWrite; //!< DW106, HCP Scalability Slice State Buffer (attributes) Read/Write 861 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress; //!< DW107..108, HCP Scalability CABAC Decoded Syntax Elements Buffer Base Address 862 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite; //!< DW109, HCP Scalability CABAC Decoded Syntax Elements Buffer (attributes) Read/Write 863 SPLITBASEADDRESS64BYTEALIGNED_CMD MotionVectorUpperRightColumnStoreBufferBaseAddress; //!< DW110..111, Motion Vector Upper Right Column Store Buffer Base Address 864 MEMORYADDRESSATTRIBUTES_CMD MotionVectorUpperRightColumnStoreBufferAttributesReadWrite; //!< DW112, Motion Vector Upper Right Column Store Buffer (attributes) Read/Write 865 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionUpperRightColumnStoreBufferBaseAddress; //!< DW113..114, Intra Prediction Upper Right Column Store Buffer Base Address 866 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite; //!< DW115, Intra Prediction Upper Right Column Store Buffer (attributes) Read/Write 867 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionLeftReconColumnStoreBufferBaseAddress; //!< DW116..117, Intra Prediction Left Recon Column Store Buffer Base Address 868 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite; //!< DW118, Intra Prediction Left Recon Column Store Buffer (attributes) Read/Write 869 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress; //!< DW119..120, HCP Scalability CABAC Decoded Syntax Elements Buffer Max Address 870 871 //! \name Local enumerations 872 873 enum MEDIA_INSTRUCTION_COMMAND 874 { 875 MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE = 2, //!< No additional details 876 }; 877 878 //! \brief MEDIA_INSTRUCTION_OPCODE 879 //! \details 880 //! Codec/Engine Name = HCP = 7h 881 enum MEDIA_INSTRUCTION_OPCODE 882 { 883 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 884 }; 885 886 enum PIPELINE_TYPE 887 { 888 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 889 }; 890 891 enum COMMAND_TYPE 892 { 893 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 894 }; 895 896 //! \name Initializations 897 898 //! \brief Explicit member initialization function HCP_PIPE_BUF_ADDR_STATE_CMDHCP_PIPE_BUF_ADDR_STATE_CMD899 HCP_PIPE_BUF_ADDR_STATE_CMD() 900 { 901 DW0.Value = 0x73820077; 902 //DW0.DwordLength = GetOpLength(dwSize); 903 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE; 904 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 905 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 906 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 907 908 DW34_35.Value[0] = DW34_35.Value[1] = 0x00000000; 909 910 DW36.Value = 0x00000000; 911 912 DW86_87.Value[0] = DW86_87.Value[1] = 0x00000000; 913 914 DW95_96.Value[0] = DW95_96.Value[1] = 0x00000000; 915 } 916 917 static const size_t dwSize = 121; 918 static const size_t byteSize = 484; 919 }; 920 921 //! 922 //! \brief HCP_IND_OBJ_BASE_ADDR_STATE 923 //! \details 924 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 925 //! Commands.Each HCP command has assigned a media instruction command as 926 //! defined in DWord 0, BitField 22:16. 927 //! 928 //! The HCP_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 929 //! object base address of the stream in graphics memory. This is a frame 930 //! level command. (Is it frame or picture level?) This is a picture level 931 //! state command and is issued in both encoding and decoding processes. 932 //! 933 //! Compressed Header Format 934 //! 935 struct HCP_IND_OBJ_BASE_ADDR_STATE_CMD 936 { 937 union 938 { 939 struct 940 { 941 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 942 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 943 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 944 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 945 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 946 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 947 }; 948 uint32_t Value; 949 } DW0; 950 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectBaseAddress; //!< DW1..2, HCP Indirect Bitstream Object Base Address 951 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectBitstreamObjectMemoryAddressAttributes; //!< DW3, HCP Indirect Bitstream Object Memory Address Attributes 952 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectAccessUpperBound; //!< DW4..5, HCP Indirect Bitstream Object Access Upper Bound 953 union 954 { 955 struct 956 { 957 uint64_t HcpIndirectCuObjectBaseAddress ; //!< HCP Indirect CU Object Base Address 958 }; 959 uint32_t Value[2]; 960 } DW6_7; 961 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectCuObjectObjectMemoryAddressAttributes; //!< DW8, HCP Indirect CU Object Object Memory Address Attributes 962 union 963 { 964 struct 965 { 966 uint64_t HcpPakBseObjectBaseAddress ; //!< HCP PAK-BSE Object Base Address 967 }; 968 uint32_t Value[2]; 969 } DW9_10; 970 MEMORYADDRESSATTRIBUTES_CMD HcpPakBseObjectAddressMemoryAddressAttributes; //!< DW11, HCP PAK-BSE Object Address Memory Address Attributes 971 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpPakBseObjectAccessUpperBound; //!< DW12..13, HCP PAK-BSE Object Access Upper Bound 972 union 973 { 974 struct 975 { 976 uint64_t HcpVp9PakCompressedHeaderSyntaxStreaminBaseAddress ; //!< HCP VP9 PAK Compressed Header Syntax Streamin- Base Address 977 }; 978 uint32_t Value[2]; 979 } DW14_15; 980 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes; //!< DW16, HCP VP9 PAK Compressed Header Syntax StreamIn Memory Address Attributes 981 union 982 { 983 struct 984 { 985 uint64_t HcpVp9PakProbabilityCounterStreamoutBaseAddress ; //!< HCP VP9 PAK Probability Counter StreamOut- Base Address 986 }; 987 uint32_t Value[2]; 988 } DW17_18; 989 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes; //!< DW19, HCP VP9 PAK Probability Counter StreamOut Memory Address Attributes 990 union 991 { 992 struct 993 { 994 uint64_t HcpVp9PakProbabilityDeltasStreaminBaseAddress ; //!< HCP VP9 PAK Probability Deltas StreamIn- Base Address 995 }; 996 uint32_t Value[2]; 997 } DW20_21; 998 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes; //!< DW22, HCP VP9 PAK Probability Deltas StreamIn Memory Address Attributes 999 union 1000 { 1001 struct 1002 { 1003 uint64_t HcpVp9PakTileRecordStreamoutBaseAddress ; //!< HCP VP9 PAK Tile Record StreamOut- Base Address 1004 }; 1005 uint32_t Value[2]; 1006 } DW23_24; 1007 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakTileRecordStreamoutMemoryAddressAttributes; //!< DW25, HCP VP9 PAK Tile Record StreamOut Memory Address Attributes 1008 union 1009 { 1010 struct 1011 { 1012 uint64_t HcpVp9PakCuLevelStatisticStreamoutBaseAddress ; //!< HCP VP9 PAK CU Level Statistic StreamOut- Base Address 1013 }; 1014 uint32_t Value[2]; 1015 } DW26_27; 1016 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCuLevelStatisticStreamoutMemoryAddressAttributes; //!< DW28, HCP VP9 PAK CU Level Statistic StreamOut Memory Address Attributes 1017 1018 //! \name Local enumerations 1019 1020 enum MEDIA_INSTRUCTION_COMMAND 1021 { 1022 MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE = 3, //!< No additional details 1023 }; 1024 1025 //! \brief MEDIA_INSTRUCTION_OPCODE 1026 //! \details 1027 //! Codec/Engine Name = HCP = 7h 1028 enum MEDIA_INSTRUCTION_OPCODE 1029 { 1030 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1031 }; 1032 1033 enum PIPELINE_TYPE 1034 { 1035 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1036 }; 1037 1038 enum COMMAND_TYPE 1039 { 1040 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1041 }; 1042 1043 //! \name Initializations 1044 1045 //! \brief Explicit member initialization function HCP_IND_OBJ_BASE_ADDR_STATE_CMDHCP_IND_OBJ_BASE_ADDR_STATE_CMD1046 HCP_IND_OBJ_BASE_ADDR_STATE_CMD() 1047 { 1048 DW0.Value = 0x7383001b; 1049 //DW0.DwordLength = GetOpLength(dwSize); 1050 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE; 1051 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1052 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1053 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1054 1055 DW6_7.Value[0] = DW6_7.Value[1] = 0x00000000; 1056 1057 DW9_10.Value[0] = DW9_10.Value[1] = 0x00000000; 1058 1059 DW14_15.Value[0] = DW14_15.Value[1] = 0x00000000; 1060 1061 DW17_18.Value[0] = DW17_18.Value[1] = 0x00000000; 1062 1063 DW20_21.Value[0] = DW20_21.Value[1] = 0x00000000; 1064 1065 DW23_24.Value[0] = DW23_24.Value[1] = 0x00000000; 1066 1067 DW26_27.Value[0] = DW26_27.Value[1] = 0x00000000; 1068 } 1069 1070 static const size_t dwSize = 29; 1071 static const size_t byteSize = 116; 1072 }; 1073 1074 //! 1075 //! \brief HCP_QM_STATE 1076 //! \details 1077 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1078 //! Commands.Each HCP command has assigned a media instruction command as 1079 //! defined in DWord 0, BitField 22:16. 1080 //! 1081 //! The HCP_QM_STATE command loads the custom HEVC quantization tables into 1082 //! local RAM and may be issued up to20 times: 3x Colour Component plus 2x 1083 //! intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components.When 1084 //! the scaling_list_enable_flag is set to disable, the scaling matrix is 1085 //! still sent to the decoder, andwith all entries programmed to the same 1086 //! value = 16.This is a picture level state command and is issued in both 1087 //! encoding and decoding processes. 1088 //! 1089 //! Dwords 2-17 form a table for the DCT coefficients, 4 8-bit 1090 //! coefficients/DWord.Size 4x4 for SizeID0, DWords 2-5. 1091 //! Size 8x8 for SizeID1/2/3, DWords 2-17. 1092 //! 1093 //! 1094 //! SizeID 0 (Table 4-10) 1095 //! 1096 struct HCP_QM_STATE_CMD 1097 { 1098 union 1099 { 1100 struct 1101 { 1102 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1103 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1104 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1105 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1106 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1107 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1108 }; 1109 uint32_t Value; 1110 } DW0; 1111 union 1112 { 1113 struct 1114 { 1115 uint32_t PredictionType : __CODEGEN_BITFIELD( 0, 0) ; //!< PREDICTION_TYPE 1116 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 1117 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 1118 uint32_t DcCoefficient : __CODEGEN_BITFIELD( 5, 12) ; //!< DC Coefficient 1119 uint32_t Reserved45 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1120 }; 1121 uint32_t Value; 1122 } DW1; 1123 uint32_t Quantizermatrix[16]; //!< QuantizerMatrix 1124 1125 //! \name Local enumerations 1126 1127 enum MEDIA_INSTRUCTION_COMMAND 1128 { 1129 MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE = 4, //!< No additional details 1130 }; 1131 1132 //! \brief MEDIA_INSTRUCTION_OPCODE 1133 //! \details 1134 //! Codec/Engine Name = HCP = 7h 1135 enum MEDIA_INSTRUCTION_OPCODE 1136 { 1137 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1138 }; 1139 1140 enum PIPELINE_TYPE 1141 { 1142 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1143 }; 1144 1145 enum COMMAND_TYPE 1146 { 1147 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1148 }; 1149 1150 enum PREDICTION_TYPE 1151 { 1152 PREDICTION_TYPE_INTRA = 0, //!< No additional details 1153 PREDICTION_TYPE_INTER = 1, //!< No additional details 1154 }; 1155 1156 enum SIZEID 1157 { 1158 SIZEID_4X4 = 0, //!< No additional details 1159 SIZEID_8X8 = 1, //!< No additional details 1160 SIZEID_16X16 = 2, //!< No additional details 1161 SIZEID_32X32 = 3, //!< (Illegal Value for Colour Component Chroma Cr and Cb.) 1162 }; 1163 1164 //! \brief COLOR_COMPONENT 1165 //! \details 1166 //! Encoder: When RDOQ is enabled, scaling list for all 3 color components 1167 //! must be same. So this field is set to always 0. 1168 enum COLOR_COMPONENT 1169 { 1170 COLOR_COMPONENT_LUMA = 0, //!< No additional details 1171 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 1172 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 1173 }; 1174 1175 //! \name Initializations 1176 1177 //! \brief Explicit member initialization function HCP_QM_STATE_CMDHCP_QM_STATE_CMD1178 HCP_QM_STATE_CMD() 1179 { 1180 DW0.Value = 0x73840010; 1181 //DW0.DwordLength = GetOpLength(dwSize); 1182 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE; 1183 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1184 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1185 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1186 1187 DW1.Value = 0x00000000; 1188 //DW1.PredictionType = PREDICTION_TYPE_INTRA; 1189 //DW1.Sizeid = SIZEID_4X4; 1190 //DW1.ColorComponent = COLOR_COMPONENT_LUMA; 1191 1192 memset(&Quantizermatrix, 0, sizeof(Quantizermatrix)); 1193 } 1194 1195 static const size_t dwSize = 18; 1196 static const size_t byteSize = 72; 1197 }; 1198 1199 //! 1200 //! \brief HCP_PIC_STATE 1201 //! \details 1202 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1203 //! Commands.Each HCP command has assigned a media instruction command as 1204 //! defined in DWord 0, BitField 22:16. 1205 //! 1206 //! This is a picture level command and is issued only once per workload for 1207 //! both encoding and decoding processes. 1208 //! 1209 struct HCP_PIC_STATE_CMD 1210 { 1211 union 1212 { 1213 struct 1214 { 1215 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1216 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1217 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1218 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1219 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1220 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1221 }; 1222 uint32_t Value; 1223 } DW0; 1224 union 1225 { 1226 struct 1227 { 1228 uint32_t Framewidthinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< FrameWidthInMinCbMinus1 1229 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 14) ; //!< Reserved 1230 uint32_t PakTransformSkipEnable : __CODEGEN_BITFIELD(15, 15) ; //!< PAK Transform Skip Enable 1231 uint32_t Frameheightinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< FrameHeightInMinCbMinus1 1232 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1233 }; 1234 uint32_t Value; 1235 } DW1; 1236 union 1237 { 1238 struct 1239 { 1240 uint32_t Mincusize : __CODEGEN_BITFIELD( 0, 1) ; //!< MINCUSIZE 1241 uint32_t CtbsizeLcusize : __CODEGEN_BITFIELD( 2, 3) ; //!< CTBSIZE_LCUSIZE 1242 uint32_t Mintusize : __CODEGEN_BITFIELD( 4, 5) ; //!< MINTUSIZE 1243 uint32_t Maxtusize : __CODEGEN_BITFIELD( 6, 7) ; //!< MAXTUSIZE 1244 uint32_t Minpcmsize : __CODEGEN_BITFIELD( 8, 9) ; //!< MINPCMSIZE 1245 uint32_t Maxpcmsize : __CODEGEN_BITFIELD(10, 11) ; //!< MAXPCMSIZE 1246 uint32_t Log2SaoOffsetScaleLuma : __CODEGEN_BITFIELD(12, 14) ; //!< LOG2_SAO_OFFSET_SCALE_LUMA 1247 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1248 uint32_t Log2SaoOffsetScaleChroma : __CODEGEN_BITFIELD(16, 18) ; //!< LOG2_SAO_OFFSET_SCALE_CHROMA 1249 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 1250 uint32_t ChromaQpOffsetListLenMinus1 : __CODEGEN_BITFIELD(20, 22) ; //!< chroma_qp_offset_list_len_minus1 1251 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 1252 uint32_t DiffCuChromaQpOffsetDepth : __CODEGEN_BITFIELD(24, 27) ; //!< diff_cu_chroma_qp_offset_depth 1253 uint32_t ChromaQpOffsetListEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< chroma_qp_offset_list_enabled_flag 1254 uint32_t ChromaSubsampling : __CODEGEN_BITFIELD(29, 31) ; //!< CHROMA_SUBSAMPLING 1255 }; 1256 uint32_t Value; 1257 } DW2; 1258 union 1259 { 1260 struct 1261 { 1262 uint32_t Colpicisi : __CODEGEN_BITFIELD( 0, 0) ; //!< COLPICISI 1263 uint32_t Curpicisi : __CODEGEN_BITFIELD( 1, 1) ; //!< CURPICISI 1264 uint32_t Inserttestflag : __CODEGEN_BITFIELD( 2, 2) ; //!< INSERTTESTFLAG 1265 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1266 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 1267 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame number 1268 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 1269 uint32_t HighPrecisionOffsetsEnableFlag : __CODEGEN_BITFIELD(19, 19) ; //!< High Precision Offsets Enable Flag 1270 uint32_t Log2Maxtransformskipsize : __CODEGEN_BITFIELD(20, 22) ; //!< Log2MaxTransformSkipSize 1271 uint32_t CrossComponentPredictionEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cross_component_prediction_enabled_flag 1272 uint32_t CabacBypassAlignmentEnabledFlag : __CODEGEN_BITFIELD(24, 24) ; //!< cabac_bypass_alignment_enabled_flag 1273 uint32_t PersistentRiceAdaptationEnabledFlag : __CODEGEN_BITFIELD(25, 25) ; //!< persistent_rice_adaptation_enabled_flag 1274 uint32_t IntraSmoothingDisabledFlag : __CODEGEN_BITFIELD(26, 26) ; //!< intra_smoothing_disabled_flag 1275 uint32_t ExplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< explicit_rdpcm_enabled_flag 1276 uint32_t ImplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< implicit_rdpcm_enabled_flag 1277 uint32_t TransformSkipContextEnabledFlag : __CODEGEN_BITFIELD(29, 29) ; //!< transform_skip_context_enabled_flag 1278 uint32_t TransformSkipRotationEnabledFlag : __CODEGEN_BITFIELD(30, 30) ; //!< transform_skip_rotation_enabled_flag 1279 uint32_t SpsRangeExtensionEnableFlag : __CODEGEN_BITFIELD(31, 31) ; //!< sps_range_extension_enable_flag 1280 }; 1281 uint32_t Value; 1282 } DW3; 1283 union 1284 { 1285 struct 1286 { 1287 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1288 uint32_t SampleAdaptiveOffsetEnabledFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< sample_adaptive_offset_enabled_flag 1289 uint32_t PcmEnabledFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< pcm_enabled_flag 1290 uint32_t CuQpDeltaEnabledFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< CU_QP_DELTA_ENABLED_FLAG 1291 uint32_t DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth : __CODEGEN_BITFIELD( 6, 7) ; //!< diff_cu_qp_delta_depth (or named as max_dqp_depth) 1292 uint32_t PcmLoopFilterDisableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< pcm_loop_filter_disable_flag 1293 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< constrained_intra_pred_flag 1294 uint32_t Log2ParallelMergeLevelMinus2 : __CODEGEN_BITFIELD(10, 12) ; //!< log2_parallel_merge_level_minus2 1295 uint32_t SignDataHidingFlag : __CODEGEN_BITFIELD(13, 13) ; //!< SIGN_DATA_HIDING_FLAG 1296 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 1297 uint32_t LoopFilterAcrossTilesEnabledFlag : __CODEGEN_BITFIELD(15, 15) ; //!< loop_filter_across_tiles_enabled_flag 1298 uint32_t EntropyCodingSyncEnabledFlag : __CODEGEN_BITFIELD(16, 16) ; //!< entropy_coding_sync_enabled_flag 1299 uint32_t TilesEnabledFlag : __CODEGEN_BITFIELD(17, 17) ; //!< tiles_enabled_flag 1300 uint32_t WeightedBipredFlag : __CODEGEN_BITFIELD(18, 18) ; //!< weighted_bipred_flag 1301 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(19, 19) ; //!< weighted_pred_flag 1302 uint32_t Fieldpic : __CODEGEN_BITFIELD(20, 20) ; //!< FIELDPIC 1303 uint32_t Bottomfield : __CODEGEN_BITFIELD(21, 21) ; //!< BOTTOMFIELD 1304 uint32_t TransformSkipEnabledFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TRANSFORM_SKIP_ENABLED_FLAG 1305 uint32_t AmpEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< AMP_ENABLED_FLAG 1306 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 1307 uint32_t TransquantBypassEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< TRANSQUANT_BYPASS_ENABLE_FLAG 1308 uint32_t StrongIntraSmoothingEnableFlag : __CODEGEN_BITFIELD(26, 26) ; //!< strong_intra_smoothing_enable_flag 1309 uint32_t CuPacketStructure : __CODEGEN_BITFIELD(27, 27) ; //!< CU packet structure 1310 uint32_t Reserved156 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1311 }; 1312 uint32_t Value; 1313 } DW4; 1314 union 1315 { 1316 struct 1317 { 1318 uint32_t PicCbQpOffset : __CODEGEN_BITFIELD( 0, 4) ; //!< pic_cb_qp_offset 1319 uint32_t PicCrQpOffset : __CODEGEN_BITFIELD( 5, 9) ; //!< pic_cr_qp_offset 1320 uint32_t MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra : __CODEGEN_BITFIELD(10, 12) ; //!< max_transform_hierarchy_depth_intra (or named as tu_max_depth_intra) 1321 uint32_t MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter : __CODEGEN_BITFIELD(13, 15) ; //!< max_transform_hierarchy_depth_inter(or named as tu_max_depth_inter) 1322 uint32_t PcmSampleBitDepthChromaMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< pcm_sample_bit_depth_chroma_minus1 1323 uint32_t PcmSampleBitDepthLumaMinus1 : __CODEGEN_BITFIELD(20, 23) ; //!< pcm_sample_bit_depth_luma_minus1 1324 uint32_t BitDepthChromaMinus8 : __CODEGEN_BITFIELD(24, 26) ; //!< BIT_DEPTH_CHROMA_MINUS8 1325 uint32_t BitDepthLumaMinus8 : __CODEGEN_BITFIELD(27, 29) ; //!< BIT_DEPTH_LUMA_MINUS8 1326 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 1327 uint32_t HrsunitlevelclockgateEnChickenBit : __CODEGEN_BITFIELD(31, 31) ; //!< HRSUnitLevelClockGate_en Chicken Bit 1328 }; 1329 uint32_t Value; 1330 } DW5; 1331 union 1332 { 1333 struct 1334 { 1335 uint32_t LcuMaxBitsizeAllowed : __CODEGEN_BITFIELD( 0, 15) ; //!< LCU Max BitSize Allowed 1336 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 1337 uint32_t LcuMaxBitSizeAllowedMsb2its : __CODEGEN_BITFIELD(17, 18) ; //!< LCU Max BitSize Allowed (MSB - 2 Bits) 1338 uint32_t Reserved211 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1339 uint32_t LcumaxbitstatusenLcumaxsizereportmask : __CODEGEN_BITFIELD(24, 24) ; //!< LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1340 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1341 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1342 uint32_t Reserved219 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1343 uint32_t LoadSlicePointerFlag : __CODEGEN_BITFIELD(29, 29) ; //!< LOAD_SLICE_POINTER_FLAG 1344 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1345 }; 1346 uint32_t Value; 1347 } DW6; 1348 union 1349 { 1350 struct 1351 { 1352 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 1353 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1354 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 1355 }; 1356 uint32_t Value; 1357 } DW7; 1358 union 1359 { 1360 struct 1361 { 1362 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1363 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1364 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 1365 }; 1366 uint32_t Value; 1367 } DW8; 1368 union 1369 { 1370 struct 1371 { 1372 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FRAMEBITRATEMINDELTA 1373 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1374 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1375 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1376 }; 1377 uint32_t Value; 1378 } DW9; 1379 union 1380 { 1381 struct 1382 { 1383 uint64_t Framedeltaqpmax ; //!< FrameDeltaQpMax 1384 }; 1385 uint32_t Value[2]; 1386 } DW10_11; 1387 union 1388 { 1389 struct 1390 { 1391 uint64_t Framedeltaqpmin ; //!< FrameDeltaQpMin 1392 }; 1393 uint32_t Value[2]; 1394 } DW12_13; 1395 union 1396 { 1397 struct 1398 { 1399 uint64_t Framedeltaqpmaxrange ; //!< FrameDeltaQpMaxRange 1400 }; 1401 uint32_t Value[2]; 1402 } DW14_15; 1403 union 1404 { 1405 struct 1406 { 1407 uint64_t Framedeltaqpminrange ; //!< FrameDeltaQpMinRange 1408 }; 1409 uint32_t Value[2]; 1410 } DW16_17; 1411 union 1412 { 1413 struct 1414 { 1415 uint32_t Minframesize : __CODEGEN_BITFIELD( 0, 15) ; //!< MINFRAMESIZE 1416 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 1417 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 1418 }; 1419 uint32_t Value; 1420 } DW18; 1421 union 1422 { 1423 struct 1424 { 1425 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP Input 1426 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP Offset 1427 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RhoDomain Rate Control Enable 1428 uint32_t FractionalQpAdjustmentEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Fractional QP adjustment enable 1429 uint32_t Rhodomainframelevelqp : __CODEGEN_BITFIELD( 8, 13) ; //!< RhoDomainFrameLevelQP 1430 uint32_t PakDynamicSliceModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< PAK Dynamic Slice Mode Enable 1431 uint32_t NoOutputOfPriorPicsFlag : __CODEGEN_BITFIELD(15, 15) ; //!< no_output_of_prior_pics_flag 1432 uint32_t FirstSliceSegmentInPicFlag : __CODEGEN_BITFIELD(16, 16) ; //!< first_slice_segment_in_pic_flag 1433 uint32_t Nalunittypeflag : __CODEGEN_BITFIELD(17, 17) ; //!< NalUnitTypeFlag 1434 uint32_t SlicePicParameterSetId : __CODEGEN_BITFIELD(18, 23) ; //!< slice_pic_parameter_set_id 1435 uint32_t SseEnable : __CODEGEN_BITFIELD(24, 24) ; //!< SSE Enable 1436 uint32_t RdoqEnable : __CODEGEN_BITFIELD(25, 25) ; //!< RDOQ Enable 1437 uint32_t NumberoflcusinnormalSliceSizeConformanceMode : __CODEGEN_BITFIELD(26, 27) ; //!< NumberOfLCUsInNormal Slice size conformance Mode 1438 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 1439 uint32_t PartialFrameUpdateMode : __CODEGEN_BITFIELD(30, 30) ; //!< Partial Frame Update Mode 1440 uint32_t TemporalMvPredDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Temporal MV pred disable 1441 }; 1442 uint32_t Value; 1443 } DW19; 1444 union 1445 { 1446 struct 1447 { 1448 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1449 uint32_t Intratucountbasedrdoqdisable : __CODEGEN_BITFIELD( 6, 6) ; //!< IntraTuCountBasedRDOQdisable 1450 uint32_t Reserved647 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 1451 }; 1452 uint32_t Value; 1453 } DW20; 1454 union 1455 { 1456 struct 1457 { 1458 uint32_t SliceSizeThresholdInBytes ; //!< Slice Size Threshold in Bytes 1459 }; 1460 uint32_t Value; 1461 } DW21; 1462 union 1463 { 1464 struct 1465 { 1466 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 1467 }; 1468 uint32_t Value; 1469 } DW22; 1470 union 1471 { 1472 struct 1473 { 1474 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 1475 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 1476 }; 1477 uint32_t Value; 1478 } DW23; 1479 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 1480 union 1481 { 1482 struct 1483 { 1484 uint32_t CbQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cb_qp_offset_list[0] 1485 uint32_t CbQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cb_qp_offset_list[1] 1486 uint32_t CbQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cb_qp_offset_list[2] 1487 uint32_t CbQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cb_qp_offset_list[3] 1488 uint32_t CbQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cb_qp_offset_list[4] 1489 uint32_t CbQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cb_qp_offset_list[5] 1490 uint32_t Reserved1054 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1491 }; 1492 uint32_t Value; 1493 } DW32; 1494 union 1495 { 1496 struct 1497 { 1498 uint32_t CrQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cr_qp_offset_list[0] 1499 uint32_t CrQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cr_qp_offset_list[1] 1500 uint32_t CrQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cr_qp_offset_list[2] 1501 uint32_t CrQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cr_qp_offset_list[3] 1502 uint32_t CrQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cr_qp_offset_list[4] 1503 uint32_t CrQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cr_qp_offset_list[5] 1504 uint32_t Reserved1086 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1505 }; 1506 uint32_t Value; 1507 } DW33; 1508 union 1509 { 1510 struct 1511 { 1512 uint32_t IbcMotionCompensationBufferReferenceIdc : __CODEGEN_BITFIELD( 0, 2) ; //!< IBC Motion Compensation Buffer Reference IDC 1513 uint32_t Reserved1091 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 1514 uint32_t DeblockingFilterOverrideEnabledFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< deblocking_filter_override_enabled_flag 1515 uint32_t PpsDeblockingFilterDisabledFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< pps_deblocking_filter_disabled_flag 1516 uint32_t PpsActCrQpOffsetPlus3 : __CODEGEN_BITFIELD( 8, 13) ; //!< pps_act_cr_qp_offset_plus3 1517 uint32_t PpsActCbQpOffsetPlus5 : __CODEGEN_BITFIELD(14, 19) ; //!< pps_act_cb_qp_offset_plus5 1518 uint32_t PpsActYOffsetPlus5 : __CODEGEN_BITFIELD(20, 25) ; //!< pps_act_y_offset_plus5 1519 uint32_t PpsSliceActQpOffsetsPresentFlag : __CODEGEN_BITFIELD(26, 26) ; //!< pps_slice_act_qp_offsets_present_flag 1520 uint32_t ResidualAdaptiveColourTransformEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< residual_adaptive_colour_transform_enabled_flag 1521 uint32_t PpsCurrPicRefEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< pps_curr_pic_ref_enabled_flag 1522 uint32_t MotionVectorResolutionControlIdc : __CODEGEN_BITFIELD(29, 30) ; //!< MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1523 uint32_t IntraBoundaryFilteringDisabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< intra_boundary_filtering_disabled_flag 1524 }; 1525 uint32_t Value; 1526 } DW34; 1527 union 1528 { 1529 struct 1530 { 1531 uint32_t PaletteMaxSize : __CODEGEN_BITFIELD( 0, 6) ; //!< palette_max_size 1532 uint32_t Reserved1127 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 1533 uint32_t DeltaPaletteMaxPredictorSize : __CODEGEN_BITFIELD(10, 16) ; //!< delta_palette_max_predictor_size 1534 uint32_t Reserved1137 : __CODEGEN_BITFIELD(17, 18) ; //!< Reserved 1535 uint32_t IbcMotionVectorErrorHandlingDisable : __CODEGEN_BITFIELD(19, 19) ; //!< IBC Motion Vector Error Handling Disable 1536 uint32_t ChromaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(20, 23) ; //!< chroma_bit_depth_entry_minus8 1537 uint32_t LumaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(24, 27) ; //!< luma_bit_depth_entry_minus8 1538 uint32_t IbcConfiguration : __CODEGEN_BITFIELD(28, 29) ; //!< IBC_CONFIGURATION 1539 uint32_t MonochromePaletteFlag : __CODEGEN_BITFIELD(30, 30) ; //!< monochrome_palette_flag 1540 uint32_t PaletteModeEnabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< palette_mode_enabled_flag 1541 }; 1542 uint32_t Value; 1543 } DW35; 1544 union 1545 { 1546 struct 1547 { 1548 uint32_t EnableFpakMessaging : __CODEGEN_BITFIELD( 0, 0) ; //!< Enable FPAK Messaging 1549 uint32_t Reserved1153 : __CODEGEN_BITFIELD( 1, 1) ; //!< Reserved1153 1550 uint32_t Reserved1154 : __CODEGEN_BITFIELD( 2, 29) ; //!< Reserved 1551 uint32_t FrameCrcType : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_CRC_TYPE 1552 uint32_t FrameCrcEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Frame CRC Enable 1553 }; 1554 uint32_t Value; 1555 } DW36; 1556 union 1557 { 1558 struct 1559 { 1560 uint32_t Rdoqintratuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntraTUThreshold 1561 uint32_t Reserved1200 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1562 }; 1563 uint32_t Value; 1564 } DW37; 1565 union 1566 { 1567 struct 1568 { 1569 uint32_t Rdoqintra16X16Tuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntra16x16TUThreshold 1570 uint32_t Rdoqintra32X32Tuthreshold : __CODEGEN_BITFIELD(16, 31) ; //!< RDOQIntra32x32TUThreshold 1571 }; 1572 uint32_t Value; 1573 } DW38; 1574 union 1575 { 1576 struct 1577 { 1578 uint64_t SsethresholdsForClass910 ; //!< SSEThresholds for Class9 ..10 1579 }; 1580 uint32_t Value[2]; 1581 } DW39_40; 1582 1583 //! \name Local enumerations 1584 1585 enum MEDIA_INSTRUCTION_COMMAND 1586 { 1587 MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE = 16, //!< No additional details 1588 }; 1589 1590 //! \brief MEDIA_INSTRUCTION_OPCODE 1591 //! \details 1592 //! Codec/Engine Name = HCP = 7h 1593 enum MEDIA_INSTRUCTION_OPCODE 1594 { 1595 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1596 }; 1597 1598 enum PIPELINE_TYPE 1599 { 1600 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1601 }; 1602 1603 enum COMMAND_TYPE 1604 { 1605 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1606 }; 1607 1608 //! \brief MINCUSIZE 1609 //! \details 1610 //! Specifies the smallest coding block size. 1611 enum MINCUSIZE 1612 { 1613 MINCUSIZE_8X8 = 0, //!< No additional details 1614 MINCUSIZE_16X16 = 1, //!< No additional details 1615 MINCUSIZE_32X32 = 2, //!< No additional details 1616 MINCUSIZE_64X64 = 3, //!< No additional details 1617 }; 1618 1619 //! \brief CTBSIZE_LCUSIZE 1620 //! \details 1621 //! Specifies the coding tree block size. 1622 enum CTBSIZE_LCUSIZE 1623 { 1624 CTBSIZE_LCUSIZE_ILLEGALRESERVED = 0, //!< No additional details 1625 CTBSIZE_LCUSIZE_16X16 = 1, //!< This can only be used when both picture width and height are fewer than or equal to 4222 pixels. 1626 CTBSIZE_LCUSIZE_32X32 = 2, //!< No additional details 1627 CTBSIZE_LCUSIZE_64X64 = 3, //!< In VDENC, mode this should be set to 3. 1628 }; 1629 1630 //! \brief MINTUSIZE 1631 //! \details 1632 //! Specifies the smallest allowed transform block size. 1633 enum MINTUSIZE 1634 { 1635 MINTUSIZE_4X4 = 0, //!< No additional details 1636 MINTUSIZE_8X8 = 1, //!< No additional details 1637 MINTUSIZE_16X16 = 2, //!< No additional details 1638 MINTUSIZE_32X32 = 3, //!< No additional details 1639 }; 1640 1641 //! \brief MAXTUSIZE 1642 //! \details 1643 //! Specifies the largest allowed transform block size. 1644 enum MAXTUSIZE 1645 { 1646 MAXTUSIZE_4X4 = 0, //!< No additional details 1647 MAXTUSIZE_8X8 = 1, //!< No additional details 1648 MAXTUSIZE_16X16 = 2, //!< No additional details 1649 MAXTUSIZE_32X32 = 3, //!< No additional details 1650 }; 1651 1652 //! \brief MINPCMSIZE 1653 //! \details 1654 //! Specifies the smallest allowed PCM coding block size. 1655 enum MINPCMSIZE 1656 { 1657 MINPCMSIZE_8X8 = 0, //!< No additional details 1658 MINPCMSIZE_16X16 = 1, //!< No additional details 1659 MINPCMSIZE_32X32 = 2, //!< No additional details 1660 }; 1661 1662 //! \brief MAXPCMSIZE 1663 //! \details 1664 //! Specifies the largest allowed PCM coding block size. 1665 enum MAXPCMSIZE 1666 { 1667 MAXPCMSIZE_8X8 = 0, //!< No additional details 1668 MAXPCMSIZE_16X16 = 1, //!< No additional details 1669 MAXPCMSIZE_32X32 = 2, //!< No additional details 1670 }; 1671 1672 //! \brief LOG2_SAO_OFFSET_SCALE_LUMA 1673 //! \details 1674 //! To scale SAO offset values for luma samples 0 to 1675 //! Max(0,BitDepth<sub><font size="2">C</font></sub>10) 1676 //! Default = 0 1677 enum LOG2_SAO_OFFSET_SCALE_LUMA 1678 { 1679 LOG2_SAO_OFFSET_SCALE_LUMA_0 = 0, //!< No additional details 1680 LOG2_SAO_OFFSET_SCALE_LUMA_1 = 1, //!< No additional details 1681 LOG2_SAO_OFFSET_SCALE_LUMA_2 = 2, //!< No additional details 1682 }; 1683 1684 //! \brief LOG2_SAO_OFFSET_SCALE_CHROMA 1685 //! \details 1686 //! To scale SAO offset values for chroma samples. 0 to 1687 //! Max(0,BitDepth<sub>C</sub>10) default = 0 1688 //! Decoder Only 1689 enum LOG2_SAO_OFFSET_SCALE_CHROMA 1690 { 1691 LOG2_SAO_OFFSET_SCALE_CHROMA_0 = 0, //!< No additional details 1692 LOG2_SAO_OFFSET_SCALE_CHROMA_1 = 1, //!< No additional details 1693 LOG2_SAO_OFFSET_SCALE_CHROMA_2 = 2, //!< No additional details 1694 }; 1695 1696 //! \brief CHROMA_SUBSAMPLING 1697 //! \details 1698 //! Specify the chroma subsampling of the current bitstream to be decoded 1699 //! or encoded. 1700 enum CHROMA_SUBSAMPLING 1701 { 1702 CHROMA_SUBSAMPLING_420 = 1, //!< 4:2:0 Format 1703 CHROMA_SUBSAMPLING_422 = 2, //!< 4:2:2 Format 1704 CHROMA_SUBSAMPLING_444 = 3, //!< 4:4:4 Format 1705 }; 1706 1707 //! \brief COLPICISI 1708 //! \details 1709 //! Specifies that the collocated picture is comprised solely of I slices 1710 //! and that there are no P or B slices in the picture. 1711 enum COLPICISI 1712 { 1713 COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1714 }; 1715 1716 //! \brief CURPICISI 1717 //! \details 1718 //! Specifies that the current picture is comprised solely of I slices and 1719 //! that there are no P or B slices in the picture. 1720 enum CURPICISI 1721 { 1722 CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1723 }; 1724 1725 //! \brief INSERTTESTFLAG 1726 //! \details 1727 //! CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 1728 //! CABAC K equation so that a positive K value can be generated easily. 1729 //! This is done for validation purpose only. In normal usage this bit 1730 //! should be set to 0. Regular equation for generating 'K' 1731 //! value when CABAC 0 Word Insertion Test Enable is set to 0. 1732 //! <pre>K = {[((96 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs *3) 1733 //! + 1023) / 1024] - bytes_in_picture} / 3</pre> Modified 1734 //! equation when CABAC 0 Word Insertion Test Enable bit set to 1. 1735 //! <pre>K = {[((1536 * pic_bin_count()) - (RawMinCUBits * 1736 //! PicSizeInMinCUs *3) + 1023) / 1024] - bytes_in_picture} / 3</pre> 1737 //! Encoder only feature. 1738 enum INSERTTESTFLAG 1739 { 1740 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 1741 INSERTTESTFLAG_UNNAMED1 = 1, //!< No additional details 1742 }; 1743 1744 //! \brief CU_QP_DELTA_ENABLED_FLAG 1745 //! \details 1746 //! cu_qp_delta_enabled_flag = 1 and Max_DQP_Level = 0 or 3 is supported 1747 //! for PAK standalone andVDEnc modes. 1748 enum CU_QP_DELTA_ENABLED_FLAG 1749 { 1750 CU_QP_DELTA_ENABLED_FLAG_DISABLE = 0, //!< Does not allow QP change at CU or LCU level, the same QP is used for the entire slice. Max_DQP_Level = 0 (i.e. diff_cu_qp_delta_depath = 0). 1751 CU_QP_DELTA_ENABLED_FLAG_ENABLE = 1, //!< Allow QP change at CU level. MAX_DQP_level can be >0. 1752 }; 1753 1754 //! \brief SIGN_DATA_HIDING_FLAG 1755 //! \details 1756 //! Currently not supported in encoder, so must be set to 0 for encoding 1757 //! session. 1758 enum SIGN_DATA_HIDING_FLAG 1759 { 1760 SIGN_DATA_HIDING_FLAG_DISABLE = 0, //!< Specifies that sign bit hiding is disabled. 1761 SIGN_DATA_HIDING_FLAG_ENABLE = 1, //!< Specifies that sign bit hiding is enabled. 1762 }; 1763 1764 //! \brief FIELDPIC 1765 //! \details 1766 //! Must be zero for encoder only. 1767 enum FIELDPIC 1768 { 1769 FIELDPIC_VIDEOFRAME = 0, //!< No additional details 1770 FIELDPIC_VIDEOFIELD = 1, //!< No additional details 1771 }; 1772 1773 //! \brief BOTTOMFIELD 1774 //! \details 1775 //! Must be zero for encoder only 1776 enum BOTTOMFIELD 1777 { 1778 BOTTOMFIELD_BOTTOMFIELD = 0, //!< No additional details 1779 BOTTOMFIELD_TOPFIELD = 1, //!< No additional details 1780 }; 1781 1782 enum TRANSFORM_SKIP_ENABLED_FLAG 1783 { 1784 TRANSFORM_SKIP_ENABLED_FLAG_DISABLE = 0, //!< transform_skip_flag is not supported in the residual coding 1785 TRANSFORM_SKIP_ENABLED_FLAG_ENABLE = 1, //!< transform_skip_flag is supported 1786 }; 1787 1788 //! \brief AMP_ENABLED_FLAG 1789 //! \details 1790 //! In VDENC mode, this bit should be set to 1. 1791 enum AMP_ENABLED_FLAG 1792 { 1793 AMP_ENABLED_FLAG_DISABLE = 0, //!< Asymmetric motion partitions cannot be used in coding tree blocks. 1794 AMP_ENABLED_FLAG_ENABLE = 1, //!< Support asymmetric motion partitions, i.e. PartMode equal to PART_2NxnU, PART_2NxnD, PART_nLx2N, or PART_nRx2N. 1795 }; 1796 1797 enum TRANSQUANT_BYPASS_ENABLE_FLAG 1798 { 1799 TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE = 0, //!< cu_transquant_bypass is not supported 1800 TRANSQUANT_BYPASS_ENABLE_FLAG_ENABLE = 1, //!< cu_transquant_bypass is supported 1801 }; 1802 1803 //! \brief BIT_DEPTH_CHROMA_MINUS8 1804 //! \details 1805 //! This specifies the number of bit allow for Chroma pixels. In 8 bit mode, 1806 //! this must be set to 0. Encoder: Supports bit depths 8, 10 and 12 only. 1807 //! And also it must be same as Luma. Encoder: Does not support 10 or 12 bit 1808 //! Source Pixels and 8bit PAK. i.e. The source pixel depth should be less 1809 //! than or equal to the PAK bit depth. 1810 enum BIT_DEPTH_CHROMA_MINUS8 1811 { 1812 BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT = 0, //!< No additional details 1813 BIT_DEPTH_CHROMA_MINUS8_CHROMA9BIT = 1, //!< Only HEVC decoder supports 9 bits chroma.HEVC encoder does not supports 9 bits chroma. 1814 BIT_DEPTH_CHROMA_MINUS8_CHROMA10BIT = 2, //!< No additional details 1815 BIT_DEPTH_CHROMA_MINUS8_CHROMA11BIT = 3, //!< HEVC SCC does not support 11 bits chromaAlso only HEVC decoder (non-SCC) support 11 bits chromaHEVC encoder (non-SCC) does not support 11 bits chroma 1816 BIT_DEPTH_CHROMA_MINUS8_CHROMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1817 }; 1818 1819 //! \brief BIT_DEPTH_LUMA_MINUS8 1820 //! \details 1821 //! This specifies the number of bit allow for Luma pixels. In 8 bit mode, 1822 //! this must be set to 0. Encoder: Suports bit depths 8, 10 and 12 only. 1823 //! Encoder: Does not support 10 or 12 bit Source Pixels and 8bit PAK i.e. 1824 //! the source pixel depth should be less than or equal to PAK bit depth. 1825 enum BIT_DEPTH_LUMA_MINUS8 1826 { 1827 BIT_DEPTH_LUMA_MINUS8_LUMA8BIT = 0, //!< No additional details 1828 BIT_DEPTH_LUMA_MINUS8_LUMA9BIT = 1, //!< Only HEVC decoder supports 9 bits luma.HEVC encoder does not supports 9 bits luma. 1829 BIT_DEPTH_LUMA_MINUS8_LUMA10BIT = 2, //!< No additional details 1830 BIT_DEPTH_LUMA_MINUS8_LUMA11BIT = 3, //!< HEVC SCC does not support 11 bits LumaAlso only HEVC decoder (non-SCC) support 11 bits LumaHEVC encoder (non-SCC) does not support 11 bits Luma 1831 BIT_DEPTH_LUMA_MINUS8_LUMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1832 }; 1833 1834 //! \brief NONFIRSTPASSFLAG 1835 //! \details 1836 //! This signals the current pass is not the first pass. It will imply 1837 //! designate HW behavior. 1838 enum NONFIRSTPASSFLAG 1839 { 1840 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 1841 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 1842 }; 1843 1844 //! \brief LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1845 //! \details 1846 //! This is a mask bit controlling if the condition of any LCU in the frame 1847 //! exceeds LCUMaxSize. 1848 enum LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1849 { 1850 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit 0 of HCP_IMAGE_STATUS control register. 1851 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit 0 of HCP_IMAGE_STATUS control register if the total bit counter for the current LCU isgreater than the LCU Conformance Max size limit. 1852 }; 1853 1854 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1855 //! \details 1856 //! This is a mask bit controlling if the condition of frame level bit count 1857 //! exceeds FrameBitRateMax. 1858 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1859 { 1860 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_IMAGE_STATUS control register. 1861 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_IMAGE_STATUS control register if the total frame level bit counter isgreater than or equal to Frame Bit Rate Maximum limit. 1862 }; 1863 1864 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1865 //! \details 1866 //! This is a mask bit controlling if the condition of frame level bit count 1867 //! is less than FrameBitRateMin. 1868 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1869 { 1870 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register. 1871 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 1872 }; 1873 1874 //! \brief LOAD_SLICE_POINTER_FLAG 1875 //! \details 1876 //! LoadBitStreamPointerPerSlice (Encoder-only) To 1877 //! support multiple slice picture and additional header/data insertion 1878 //! before and after an encoded slice. When this field is set to 0, 1879 //! bitstream pointer is only loaded once for the first slice of a frame. 1880 //! For subsequent slices in the frame, bitstream data are stitched together 1881 //! to form a single output data stream. When this field is set to 1, 1882 //! bitstream pointer is loaded for each slice of a frame. Basically 1883 //! bitstream data for different slices of a frame will be written to 1884 //! different memory locations. 1885 enum LOAD_SLICE_POINTER_FLAG 1886 { 1887 LOAD_SLICE_POINTER_FLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame. 1888 LOAD_SLICE_POINTER_FLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of thebitstream buffer from the Indirect PAK-BSE Object Data Start Address field. 1889 }; 1890 1891 //! \brief FRAMEBITRATEMAXUNIT 1892 //! \details 1893 //! This field is the Frame Bitrate Maximum Limit Units. 1894 enum FRAMEBITRATEMAXUNIT 1895 { 1896 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 1897 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4kbyte unit 1898 }; 1899 1900 //! \brief FRAMEBITRATEMINUNIT 1901 //! \details 1902 //! This field is the Frame Bitrate Minimum Limit Units. 1903 enum FRAMEBITRATEMINUNIT 1904 { 1905 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 1906 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4kbyte unit 1907 }; 1908 1909 //! \brief FRAMEBITRATEMINDELTA 1910 //! \details 1911 //! This field is used to select the slice delta QP when FrameBitRateMin Is 1912 //! exceeded. It shares the sameFrameBitrateMinUnit. 1913 enum FRAMEBITRATEMINDELTA 1914 { 1915 FRAMEBITRATEMINDELTA_UNNAMED0 = 0, //!< No additional details 1916 }; 1917 1918 //! \brief FRAMEBITRATEMAXDELTA 1919 //! \details 1920 //! This field is used to select the slice delta QP when FrameBitRateMax Is 1921 //! exceeded. It shares the sameFrameBitrateMaxUnit. 1922 enum FRAMEBITRATEMAXDELTA 1923 { 1924 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 1925 }; 1926 1927 //! \brief MINFRAMESIZE 1928 //! \details 1929 //! Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only) 1930 //! Mininum Frame Size is specified to compensate for intel Rate Control 1931 //! Currently zero fill (no need to perform emulation byte insertion) is 1932 //! done only to the end of the CABAC_ZERO_WORD insertion (if any) at the 1933 //! last slice of a picture. It is needed for CBR. Intel encoder parameter. 1934 //! The caller should always make sure that the value, represented by 1935 //! Mininum Frame Size, is always less than maximum frame size 1936 //! FrameBitRateMax. This field is reserved in Decode mode. 1937 enum MINFRAMESIZE 1938 { 1939 MINFRAMESIZE_UNNAMED0 = 0, //!< No additional details 1940 }; 1941 1942 //! \brief MINFRAMESIZEUNITS 1943 //! \details 1944 //! This field is the Minimum Frame Size Units 1945 enum MINFRAMESIZEUNITS 1946 { 1947 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 1948 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 16Kbytes. 1949 MINFRAMESIZEUNITS_COMPATIBILITYMODE = 2, //!< Minimum Frame Size is in 4bytes 1950 MINFRAMESIZEUNITS_16BYTES = 3, //!< Minimum Frame Size is 16 bytes. 1951 }; 1952 1953 //! \brief MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1954 //! \details 1955 //! This controls the presense and inference of the use_integer_mv_flag 1956 //! that specifies the resolution of motion vectors for inter 1957 //! prediction. Decoder only (Encoder default to "00") 1958 enum MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1959 { 1960 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME = 0, //!< No additional details 1961 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ONLYINTEGERMVFORTHEFRAME = 1, //!< No additional details 1962 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ADAPTIVEINTEGERMVFORTHEFRAME = 2, //!< Slice signal use_inter_mv_flag will indicate if the slice will use interger MV or not 1963 }; 1964 1965 //! \brief IBC_CONFIGURATION 1966 //! \details 1967 //! IBC configuration is used configure Intra block copy. 1968 //! - Disable Intra block copy. - Limit Intra block copy 1969 //! from Left blocks only. - Allow full range of Intra block 1970 //! copy as specified in spec. /> 1971 enum IBC_CONFIGURATION 1972 { 1973 IBC_CONFIGURATION_UNNAMED0 = 0, //!< When IBC configuration is 0, intra block copy is disabled and it applies for both Fixed function encoder and decoder. 1974 IBC_CONFIGURATION_UNNAMED1 = 1, //!< When IBC configuration in fixed function encoder (VDENC) mode is set to 1, Intra block search includes only left region. 1975 IBC_CONFIGURATION_UNNAMED2 = 2, //!< This is invalid value. 1976 IBC_CONFIGURATION_UNNAMED3 = 3, //!< When IBC configuration in VDENC mode is set to 3, Intra block search includes top and left regions.In decoder mode, When SCC is enabled this field should be set to 3. 1977 }; 1978 1979 //! \brief FRAME_CRC_TYPE 1980 //! \details 1981 //! This indicates how CRC is generated. This bit is ignored and must be 1982 //! programmed to 0 if Frame CRC Enable is "0" 1983 enum FRAME_CRC_TYPE 1984 { 1985 FRAME_CRC_TYPE_CRCWITHYUVVALUE = 0, //!< No additional details 1986 FRAME_CRC_TYPE_CRCWITHYVALUEONLY = 1, //!< No additional details 1987 }; 1988 1989 //! \name Initializations 1990 1991 //! \brief Explicit member initialization function HCP_PIC_STATE_CMDHCP_PIC_STATE_CMD1992 HCP_PIC_STATE_CMD() 1993 { 1994 DW0.Value = 0x73900027; 1995 //DW0.DwordLength = GetOpLength(dwSize); 1996 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE; 1997 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1998 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1999 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2000 2001 DW1.Value = 0x00000000; 2002 2003 DW2.Value = 0x00000000; 2004 //DW2.Mincusize = MINCUSIZE_8X8; 2005 //DW2.CtbsizeLcusize = CTBSIZE_LCUSIZE_ILLEGALRESERVED; 2006 //DW2.Mintusize = MINTUSIZE_4X4; 2007 //DW2.Maxtusize = MAXTUSIZE_4X4; 2008 //DW2.Minpcmsize = MINPCMSIZE_8X8; 2009 //DW2.Maxpcmsize = MAXPCMSIZE_8X8; 2010 //DW2.Log2SaoOffsetScaleLuma = LOG2_SAO_OFFSET_SCALE_LUMA_0; 2011 //DW2.Log2SaoOffsetScaleChroma = LOG2_SAO_OFFSET_SCALE_CHROMA_0; 2012 //DW2.ChromaSubsampling = 0; 2013 2014 DW3.Value = 0x00000000; 2015 //DW3.Colpicisi = COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE; 2016 //DW3.Curpicisi = CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE; 2017 //DW3.Inserttestflag = INSERTTESTFLAG_UNNAMED0; 2018 2019 DW4.Value = 0x00000000; 2020 //DW4.CuQpDeltaEnabledFlag = CU_QP_DELTA_ENABLED_FLAG_DISABLE; 2021 //DW4.SignDataHidingFlag = SIGN_DATA_HIDING_FLAG_DISABLE; 2022 //DW4.Fieldpic = FIELDPIC_VIDEOFRAME; 2023 //DW4.Bottomfield = BOTTOMFIELD_BOTTOMFIELD; 2024 //DW4.TransformSkipEnabledFlag = TRANSFORM_SKIP_ENABLED_FLAG_DISABLE; 2025 //DW4.AmpEnabledFlag = AMP_ENABLED_FLAG_DISABLE; 2026 //DW4.TransquantBypassEnableFlag = TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE; 2027 2028 DW5.Value = 0x00000000; 2029 //DW5.BitDepthChromaMinus8 = BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT; 2030 //DW5.BitDepthLumaMinus8 = BIT_DEPTH_LUMA_MINUS8_LUMA8BIT; 2031 2032 DW6.Value = 0x00000000; 2033 //DW6.Nonfirstpassflag = NONFIRSTPASSFLAG_DISABLE; 2034 //DW6.LcumaxbitstatusenLcumaxsizereportmask = LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE; 2035 //DW6.FrameszoverstatusenFramebitratemaxreportmask = FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE; 2036 //DW6.FrameszunderstatusenFramebitrateminreportmask = FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE; 2037 //DW6.LoadSlicePointerFlag = LOAD_SLICE_POINTER_FLAG_DISABLE; 2038 2039 DW7.Value = 0x00000000; 2040 //DW7.Framebitratemaxunit = FRAMEBITRATEMAXUNIT_BYTE; 2041 2042 DW8.Value = 0x00000000; 2043 //DW8.Framebitrateminunit = FRAMEBITRATEMINUNIT_BYTE; 2044 2045 DW9.Value = 0x00000000; 2046 //DW9.Framebitratemindelta = FRAMEBITRATEMINDELTA_UNNAMED0; 2047 //DW9.Framebitratemaxdelta = FRAMEBITRATEMAXDELTA_UNNAMED0; 2048 2049 DW10_11.Value[0] = DW10_11.Value[1] = 0x00000000; 2050 2051 DW12_13.Value[0] = DW12_13.Value[1] = 0x00000000; 2052 2053 DW14_15.Value[0] = DW14_15.Value[1] = 0x00000000; 2054 2055 DW16_17.Value[0] = DW16_17.Value[1] = 0x00000000; 2056 2057 DW18.Value = 0x00000000; 2058 //DW18.Minframesize = MINFRAMESIZE_UNNAMED0; 2059 //DW18.Minframesizeunits = MINFRAMESIZEUNITS_4KB; 2060 2061 DW19.Value = 0x00000000; 2062 2063 DW20.Value = 0x00000000; 2064 2065 DW21.Value = 0x00000000; 2066 2067 DW22.Value = 0x00000000; 2068 2069 DW23.Value = 0x00000000; 2070 2071 memset(&SseThresholdsForClass18, 0, sizeof(SseThresholdsForClass18)); 2072 2073 DW32.Value = 0x00000000; 2074 2075 DW33.Value = 0x00000000; 2076 2077 DW34.Value = 0x00000000; 2078 //DW34.MotionVectorResolutionControlIdc = MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME; 2079 2080 DW35.Value = 0x00000000; 2081 //DW35.IbcConfiguration = IBC_CONFIGURATION_UNNAMED0; 2082 2083 DW36.Value = 0x00000000; 2084 //DW36.FrameCrcType = FRAME_CRC_TYPE_CRCWITHYUVVALUE; 2085 2086 DW37.Value = 0x00000000; 2087 2088 DW38.Value = 0x00000000; 2089 2090 DW39_40.Value[0] = DW39_40.Value[1] = 0x00000000; 2091 } 2092 2093 static const size_t dwSize = 41; 2094 static const size_t byteSize = 164; 2095 }; 2096 2097 //! 2098 //! \brief HCP_TILE_POSITION_IN_CTB 2099 //! \details 2100 //! 2101 //! 2102 struct HCP_TILE_POSITION_IN_CTB_CMD 2103 { 2104 union 2105 { 2106 struct 2107 { 2108 uint32_t Ctbpos0I : __CODEGEN_BITFIELD( 0, 7) ; //!< CtbPos0+i 2109 uint32_t Ctbpos1I : __CODEGEN_BITFIELD( 8, 15) ; //!< CtbPos1+i 2110 uint32_t Ctbpos2I : __CODEGEN_BITFIELD(16, 23) ; //!< CtbPos2+i 2111 uint32_t Ctbpos3I : __CODEGEN_BITFIELD(24, 31) ; //!< CtbPos3+i 2112 }; 2113 uint32_t Value; 2114 } DW0; 2115 2116 //! \name Local enumerations 2117 2118 //! \name Initializations 2119 2120 //! \brief Explicit member initialization function HCP_TILE_POSITION_IN_CTB_CMDHCP_TILE_POSITION_IN_CTB_CMD2121 HCP_TILE_POSITION_IN_CTB_CMD() 2122 { 2123 DW0.Value = 0x00000000; 2124 } 2125 2126 static const size_t dwSize = 1; 2127 static const size_t byteSize = 4; 2128 }; 2129 2130 //! 2131 //! \brief HCP_TILE_POSITION_IN_CTB_MSB 2132 //! \details 2133 //! Added to support 16k picture size. 2134 //! 2135 struct HCP_TILE_POSITION_IN_CTB_MSB_CMD 2136 { 2137 union 2138 { 2139 struct 2140 { 2141 uint32_t CtbRowPositionOfTileColumn098 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 0 [9:8] 2142 uint32_t CtbRowPositionOfTileColumn198 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 1 [9:8] 2143 uint32_t CtbRowPositionOfTileColumn298 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 2 [9:8] 2144 uint32_t CtbRowPositionOfTileColumn398 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 3 [9:8] 2145 uint32_t CtbRowPositionOfTileColumn498 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 4 [9:8] 2146 uint32_t CtbRowPositionOfTileColumn598 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb row position of tile column 5 [9:8] 2147 uint32_t CtbRowPositionOfTileColumn698 : __CODEGEN_BITFIELD(12, 13) ; //!< Ctb row position of tile column 6 [9:8] 2148 uint32_t CtbRowPositionOfTileColumn798 : __CODEGEN_BITFIELD(14, 15) ; //!< Ctb row position of tile column 7 [9:8] 2149 uint32_t CtbRowPositionOfTileColumn898 : __CODEGEN_BITFIELD(16, 17) ; //!< Ctb row position of tile column 8 [9:8] 2150 uint32_t CtbRowPositionOfTileColumn998 : __CODEGEN_BITFIELD(18, 19) ; //!< Ctb row position of tile column 9 [9:8] 2151 uint32_t CtbRowPositionOfTileColumn1098 : __CODEGEN_BITFIELD(20, 21) ; //!< Ctb row position of tile column 10 [9:8] 2152 uint32_t CtbRowPositionOfTileColumn1198 : __CODEGEN_BITFIELD(22, 23) ; //!< Ctb row position of tile column 11 [9:8] 2153 uint32_t CtbRowPositionOfTileColumn1298 : __CODEGEN_BITFIELD(24, 25) ; //!< Ctb row position of tile column 12 [9:8] 2154 uint32_t CtbRowPositionOfTileColumn1398 : __CODEGEN_BITFIELD(26, 27) ; //!< Ctb row position of tile column 13 [9:8] 2155 uint32_t CtbRowPositionOfTileColumn1498 : __CODEGEN_BITFIELD(28, 29) ; //!< Ctb row position of tile column 14 [9:8] 2156 uint32_t CtbRowPositionOfTileColumn1598 : __CODEGEN_BITFIELD(30, 31) ; //!< Ctb row position of tile column 15 [9:8] 2157 }; 2158 uint32_t Value; 2159 } DW0; 2160 union 2161 { 2162 struct 2163 { 2164 uint32_t CtbRowPositionOfTileColumn1698 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 16 [9:8] 2165 uint32_t CtbRowPositionOfTileColumn1798 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 17 [9:8] 2166 uint32_t CtbRowPositionOfTileColumn1898 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 18 [9:8] 2167 uint32_t CtbRowPositionOfTileColumn1998 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 19 [9:8] 2168 uint32_t CtbRowPositionOfTileColumn2098 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 20 [9:8] 2169 uint32_t CtbPositionOfTile2198 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb position of tile 21 [9:8] 2170 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 2171 }; 2172 uint32_t Value; 2173 } DW1; 2174 2175 //! \name Local enumerations 2176 2177 //! \name Initializations 2178 2179 //! \brief Explicit member initialization function HCP_TILE_POSITION_IN_CTB_MSB_CMDHCP_TILE_POSITION_IN_CTB_MSB_CMD2180 HCP_TILE_POSITION_IN_CTB_MSB_CMD() 2181 { 2182 DW0.Value = 0x00000000; 2183 2184 DW1.Value = 0x00000000; 2185 } 2186 2187 static const size_t dwSize = 2; 2188 static const size_t byteSize = 8; 2189 }; 2190 2191 //! 2192 //! \brief HCP_TILE_STATE 2193 //! \details 2194 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2195 //! Commands.Each HCP command has assigned a media instruction command as 2196 //! defined in DWord 0, BitField 22:16. 2197 //! 2198 //! This command is valid for decoder only. 2199 //! 2200 struct HCP_TILE_STATE_CMD 2201 { 2202 union 2203 { 2204 struct 2205 { 2206 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2207 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2208 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2209 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2210 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2211 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2212 }; 2213 uint32_t Value; 2214 } DW0; 2215 union 2216 { 2217 struct 2218 { 2219 uint32_t Numtilerowsminus1 : __CODEGEN_BITFIELD( 0, 4) ; //!< NumTileRowsMinus1 2220 uint32_t Numtilecolumnsminus1 : __CODEGEN_BITFIELD( 5, 9) ; //!< NumTileColumnsMinus1 2221 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2222 }; 2223 uint32_t Value; 2224 } DW1; 2225 HCP_TILE_POSITION_IN_CTB_CMD CtbColumnPositionOfTileColumn[5]; //!< DW2..6, Ctb column position of tile column 2226 HCP_TILE_POSITION_IN_CTB_CMD CtbRowPositionOfTileRow[6]; //!< DW7..12, Ctb row position of tile row 2227 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbColumnPositionMsb; //!< DW13..14, Ctb column position MSB 2228 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbRowPositionMsb; //!< DW15..16, Ctb row position MSB 2229 2230 //! \name Local enumerations 2231 2232 enum MEDIA_INSTRUCTION_COMMAND 2233 { 2234 MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE = 17, //!< No additional details 2235 }; 2236 2237 //! \brief MEDIA_INSTRUCTION_OPCODE 2238 //! \details 2239 //! Codec/Engine Name = HCP = 7h 2240 enum MEDIA_INSTRUCTION_OPCODE 2241 { 2242 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2243 }; 2244 2245 enum PIPELINE_TYPE 2246 { 2247 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2248 }; 2249 2250 enum COMMAND_TYPE 2251 { 2252 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2253 }; 2254 2255 //! \name Initializations 2256 2257 //! \brief Explicit member initialization function HCP_TILE_STATE_CMDHCP_TILE_STATE_CMD2258 HCP_TILE_STATE_CMD() 2259 { 2260 DW0.Value = 0x7391000f; 2261 //DW0.DwordLength = GetOpLength(dwSize); 2262 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE; 2263 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2264 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2265 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2266 2267 DW1.Value = 0x00000000; 2268 } 2269 2270 static const size_t dwSize = 17; 2271 static const size_t byteSize = 68; 2272 }; 2273 2274 //! 2275 //! \brief HCP_REF_LIST_ENTRY 2276 //! \details 2277 //! 2278 //! 2279 struct HCP_REF_LIST_ENTRY_CMD 2280 { 2281 union 2282 { 2283 struct 2284 { 2285 uint32_t ReferencePictureTbValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Reference Picture tb Value 2286 uint32_t ListEntryLxReferencePictureFrameIdRefaddr07 : __CODEGEN_BITFIELD( 8, 10) ; //!< list_entry_lX: Reference Picture Frame ID (RefAddr[0-7]) 2287 uint32_t ChromaWeightLxFlag : __CODEGEN_BITFIELD(11, 11) ; //!< CHROMA_WEIGHT_LX_FLAG 2288 uint32_t LumaWeightLxFlag : __CODEGEN_BITFIELD(12, 12) ; //!< LUMA_WEIGHT_LX_FLAG 2289 uint32_t Longtermreference : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERMREFERENCE 2290 uint32_t FieldPicFlag : __CODEGEN_BITFIELD(14, 14) ; //!< FIELD_PIC_FLAG 2291 uint32_t BottomFieldFlag : __CODEGEN_BITFIELD(15, 15) ; //!< BOTTOM_FIELD_FLAG 2292 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2293 }; 2294 uint32_t Value; 2295 } DW0; 2296 2297 //! \name Local enumerations 2298 2299 //! \brief CHROMA_WEIGHT_LX_FLAG 2300 //! \details 2301 //! Where X is the RefPicListNum and i is the list entry number 0 through 2302 //! 15. DW2 corresponds to i=0,DW17 corresponds to i=15. 2303 enum CHROMA_WEIGHT_LX_FLAG 2304 { 2305 CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA = 0, //!< No additional details 2306 CHROMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORCHROMA = 1, //!< No additional details 2307 }; 2308 2309 //! \brief LUMA_WEIGHT_LX_FLAG 2310 //! \details 2311 //! Where X is the RefPicListNum and i is the list entry number 0 through 2312 //! 15. DW2 corresponds to i=0,DW17 corresponds to i=15. 2313 enum LUMA_WEIGHT_LX_FLAG 2314 { 2315 LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA = 0, //!< No additional details 2316 LUMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORLUMA = 1, //!< No additional details 2317 }; 2318 2319 //! \brief LONGTERMREFERENCE 2320 //! \details 2321 //! Where X is the RefPicListNum and i is the list entry number 0 through 2322 //! 15. DW2 corresponds to i=0,DW17 corresponds to i=15. 2323 enum LONGTERMREFERENCE 2324 { 2325 LONGTERMREFERENCE_SHORTTERMREFERENCE = 0, //!< No additional details 2326 LONGTERMREFERENCE_LONGTERMREFERENCE = 1, //!< No additional details 2327 }; 2328 2329 //! \brief FIELD_PIC_FLAG 2330 //! \details 2331 //! Where X is the RefPicListNum and i is the list entry number 0 through 2332 //! 15. DW2 corresponds to i=0,DW17 corresponds to i=15. 2333 enum FIELD_PIC_FLAG 2334 { 2335 FIELD_PIC_FLAG_VIDEOFRAME = 0, //!< No additional details 2336 FIELD_PIC_FLAG_VIDEOFIELD = 1, //!< No additional details 2337 }; 2338 2339 //! \brief BOTTOM_FIELD_FLAG 2340 //! \details 2341 //! Where X is the RefPicListNum and i is the list entry number 0 through 2342 //! 15. DW2 corresponds to i=0,DW17 corresponds to i=15. 2343 enum BOTTOM_FIELD_FLAG 2344 { 2345 BOTTOM_FIELD_FLAG_BOTTOMFIELD = 0, //!< No additional details 2346 BOTTOM_FIELD_FLAG_TOPFIELD = 1, //!< No additional details 2347 }; 2348 2349 //! \name Initializations 2350 2351 //! \brief Explicit member initialization function HCP_REF_LIST_ENTRY_CMDHCP_REF_LIST_ENTRY_CMD2352 HCP_REF_LIST_ENTRY_CMD() 2353 { 2354 DW0.Value = 0x00000000; 2355 //DW0.ChromaWeightLxFlag = CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA; 2356 //DW0.LumaWeightLxFlag = LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA; 2357 //DW0.Longtermreference = LONGTERMREFERENCE_SHORTTERMREFERENCE; 2358 //DW0.FieldPicFlag = FIELD_PIC_FLAG_VIDEOFRAME; 2359 //DW0.BottomFieldFlag = BOTTOM_FIELD_FLAG_BOTTOMFIELD; 2360 } 2361 2362 static const size_t dwSize = 1; 2363 static const size_t byteSize = 4; 2364 }; 2365 2366 //! 2367 //! \brief HCP_REF_IDX_STATE 2368 //! \details 2369 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2370 //! Commands.Each HCP command has assigned a media instruction command as 2371 //! defined in DWord 0, BitField 22:16. 2372 //! 2373 //! This is a slice level command used in both encoding and decoding 2374 //! processes. For decoder, it is issued withthe HCP_BSD_OBJECT command. 2375 //! 2376 //! Unlike AVC, HEVC allows 16 reference idx entries in each of the L0 and 2377 //! L1 list for a progressive picture.Hence, a max total 32 reference idx in 2378 //! both lists together. The same when the picture is a field 2379 //! picture.Regardless the number of reference idx entries, there are only 2380 //! max 8 reference pictures exist at any one time.Multiple reference idx 2381 //! can point to the same reference picture and can optionally pic a top or 2382 //! bottom field,or frame. 2383 //! 2384 //! For P-Slice, this command is issued only once, representing L0 list. For 2385 //! B-Slice, this command can be issuedup to two times, one for L0 list and 2386 //! one for L1 list. 2387 //! 2388 struct HCP_REF_IDX_STATE_CMD 2389 { 2390 union 2391 { 2392 struct 2393 { 2394 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2395 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2396 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2397 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2398 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2399 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2400 }; 2401 uint32_t Value; 2402 } DW0; 2403 union 2404 { 2405 struct 2406 { 2407 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2408 uint32_t NumRefIdxLRefpiclistnumActiveMinus1 : __CODEGEN_BITFIELD( 1, 4) ; //!< num_ref_idx_l[RefPicListNum]_active_minus1 2409 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 2410 }; 2411 uint32_t Value; 2412 } DW1; 2413 HCP_REF_LIST_ENTRY_CMD Entries[16]; //!< DW2..17, Entries 2414 2415 //! \name Local enumerations 2416 2417 enum MEDIA_INSTRUCTION_COMMAND 2418 { 2419 MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE = 18, //!< No additional details 2420 }; 2421 2422 //! \brief MEDIA_INSTRUCTION_OPCODE 2423 //! \details 2424 //! Codec/Engine Name = HCP = 7h 2425 enum MEDIA_INSTRUCTION_OPCODE 2426 { 2427 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2428 }; 2429 2430 enum PIPELINE_TYPE 2431 { 2432 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2433 }; 2434 2435 enum COMMAND_TYPE 2436 { 2437 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2438 }; 2439 2440 enum REFPICLISTNUM 2441 { 2442 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2443 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2444 }; 2445 2446 //! \name Initializations 2447 2448 //! \brief Explicit member initialization function HCP_REF_IDX_STATE_CMDHCP_REF_IDX_STATE_CMD2449 HCP_REF_IDX_STATE_CMD() 2450 { 2451 DW0.Value = 0x73920010; 2452 //DW0.DwordLength = GetOpLength(dwSize); 2453 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE; 2454 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2455 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2456 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2457 2458 DW1.Value = 0x00000000; 2459 //DW1.Refpiclistnum = REFPICLISTNUM_REFERENCEPICTURELIST0; 2460 } 2461 2462 static const size_t dwSize = 18; 2463 static const size_t byteSize = 72; 2464 }; 2465 2466 //! 2467 //! \brief HCP_WEIGHTOFFSET_LUMA_ENTRY 2468 //! \details 2469 //! 2470 //! 2471 struct HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD 2472 { 2473 union 2474 { 2475 struct 2476 { 2477 uint32_t DeltaLumaWeightLxI : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_luma_weight_lX[i] 2478 uint32_t LumaOffsetLxI : __CODEGEN_BITFIELD( 8, 15) ; //!< luma_offset_lX[i] 2479 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2480 uint32_t LumaOffsetLxIMsbyte : __CODEGEN_BITFIELD(24, 31) ; //!< luma_offset_lX[i] MSByte 2481 }; 2482 uint32_t Value; 2483 } DW0; 2484 2485 //! \name Local enumerations 2486 2487 //! \name Initializations 2488 2489 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_LUMA_ENTRY_CMDHCP_WEIGHTOFFSET_LUMA_ENTRY_CMD2490 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD() 2491 { 2492 DW0.Value = 0x00000000; 2493 } 2494 2495 static const size_t dwSize = 1; 2496 static const size_t byteSize = 4; 2497 }; 2498 2499 //! 2500 //! \brief HCP_WEIGHTOFFSET_CHROMA_ENTRY 2501 //! \details 2502 //! 2503 //! 2504 struct HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD 2505 { 2506 union 2507 { 2508 struct 2509 { 2510 uint32_t DeltaChromaWeightLxI0 : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_chroma_weight_lX[i][0] 2511 uint32_t ChromaoffsetlxI0 : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i][0] 2512 uint32_t DeltaChromaWeightLxI1 : __CODEGEN_BITFIELD(16, 23) ; //!< delta_chroma_weight_lX[i][1] 2513 uint32_t ChromaoffsetlxI1 : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX [i][1] 2514 }; 2515 uint32_t Value; 2516 } DW0; 2517 2518 //! \name Local enumerations 2519 2520 //! \name Initializations 2521 2522 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMDHCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD2523 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD() 2524 { 2525 DW0.Value = 0x00000000; 2526 } 2527 2528 static const size_t dwSize = 1; 2529 static const size_t byteSize = 4; 2530 }; 2531 2532 //! 2533 //! \brief HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY 2534 //! \details 2535 //! 2536 //! 2537 struct HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD 2538 { 2539 union 2540 { 2541 struct 2542 { 2543 uint32_t ChromaoffsetlxI0Msbyte : __CODEGEN_BITFIELD( 0, 7) ; //!< ChromaOffsetLX[i][0] MSByte 2544 uint32_t ChromaoffsetlxI10Msbyte : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i+1][0] MSByte 2545 uint32_t ChromaoffsetlxI1Msbyte : __CODEGEN_BITFIELD(16, 23) ; //!< ChromaOffsetLX[i][1] MSByte 2546 uint32_t ChromaoffsetlxI11Msbyte : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX[i+1][1] MSByte 2547 }; 2548 uint32_t Value; 2549 } DW0; 2550 2551 //! \name Local enumerations 2552 2553 //! \name Initializations 2554 2555 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMDHCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD2556 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD() 2557 { 2558 DW0.Value = 0x00000000; 2559 } 2560 2561 static const size_t dwSize = 1; 2562 static const size_t byteSize = 4; 2563 }; 2564 2565 //! 2566 //! \brief HCP_WEIGHTOFFSET_STATE 2567 //! \details 2568 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2569 //! Commands.Each HCP command has assigned a media instruction command as 2570 //! defined in DWord 0, BitField 22:16. 2571 //! 2572 //! This slice level command is issued in both the encoding and decoding 2573 //! processes, if the weighted_pred_flag orweighted_bipred_flag equals one. 2574 //! If zero, then this command is not issued.Weight Prediction Values are 2575 //! provided in this command. Only Explicit Weight Prediction is supported 2576 //! inencoder.For P-Slice, this command is issued only once together with 2577 //! HCP_REF_IDX_STATE Command for L0 list. ForB-Slice, this command can be 2578 //! issued up to two times together with HCP_REF_IDX_STATE Command, one 2579 //! forL0 list and one for L1 list. 2580 //! 2581 struct HCP_WEIGHTOFFSET_STATE_CMD 2582 { 2583 union 2584 { 2585 struct 2586 { 2587 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2588 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2589 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2590 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2591 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2592 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2593 }; 2594 uint32_t Value; 2595 } DW0; 2596 union 2597 { 2598 struct 2599 { 2600 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2601 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2602 }; 2603 uint32_t Value; 2604 } DW1; 2605 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD Lumaoffsets[16]; //!< DW2..17, LumaOffsets 2606 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD Chromaoffsets[16]; //!< DW18..33, ChromaOffsets 2607 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD Chromaoffsetsext[8]; //!< DW34..41, ChromaOffsetsExt 2608 2609 //! \name Local enumerations 2610 2611 enum MEDIA_INSTRUCTION_COMMAND 2612 { 2613 MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE = 19, //!< No additional details 2614 }; 2615 2616 //! \brief MEDIA_INSTRUCTION_OPCODE 2617 //! \details 2618 //! Codec/Engine Name = HCP = 7h 2619 enum MEDIA_INSTRUCTION_OPCODE 2620 { 2621 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2622 }; 2623 2624 enum PIPELINE_TYPE 2625 { 2626 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2627 }; 2628 2629 enum COMMAND_TYPE 2630 { 2631 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2632 }; 2633 2634 enum REFPICLISTNUM 2635 { 2636 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2637 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2638 }; 2639 2640 //! \name Initializations 2641 2642 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_STATE_CMDHCP_WEIGHTOFFSET_STATE_CMD2643 HCP_WEIGHTOFFSET_STATE_CMD() 2644 { 2645 DW0.Value = 0x73930028; 2646 //DW0.DwordLength = GetOpLength(dwSize); 2647 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE; 2648 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2649 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2650 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2651 2652 DW1.Value = 0x00000000; 2653 //DW1.Refpiclistnum = REFPICLISTNUM_REFERENCEPICTURELIST0; 2654 } 2655 2656 static const size_t dwSize = 42; 2657 static const size_t byteSize = 168; 2658 }; 2659 2660 //! 2661 //! \brief HCP_SLICE_STATE 2662 //! \details 2663 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2664 //! Commands.Each HCP command has assigned a media instruction command as 2665 //! defined in DWord 0, BitField 22:16. 2666 //! 2667 //! This is a slice level command used in both encoding and decoding 2668 //! processes. For decoder, it is issued withthe HCP_BSD_OBJECT command. 2669 //! 2670 struct HCP_SLICE_STATE_CMD 2671 { 2672 union 2673 { 2674 struct 2675 { 2676 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2677 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2678 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2679 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2680 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2681 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2682 }; 2683 uint32_t Value; 2684 } DW0; 2685 union 2686 { 2687 struct 2688 { 2689 uint32_t SlicestartctbxOrSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< SliceStartCtbX or (slice_start_lcu_x encoder) 2690 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2691 uint32_t SlicestartctbyOrSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 25) ; //!< SliceStartCtbY or (slice_start_lcu_y encoder) 2692 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2693 }; 2694 uint32_t Value; 2695 } DW1; 2696 union 2697 { 2698 struct 2699 { 2700 uint32_t NextslicestartctbxOrNextSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSliceStartCtbX or (next_slice_start_lcu_x encoder) 2701 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2702 uint32_t NextslicestartctbyOrNextSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 26) ; //!< NextSliceStartCtbY or (next_slice_start_lcu_y encoder) 2703 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2704 }; 2705 uint32_t Value; 2706 } DW2; 2707 union 2708 { 2709 struct 2710 { 2711 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_TYPE 2712 uint32_t Lastsliceofpic : __CODEGEN_BITFIELD( 2, 2) ; //!< LASTSLICEOFPIC 2713 uint32_t SliceqpSignFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< SliceQp Sign Flag 2714 uint32_t DependentSliceFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< dependent_slice_flag 2715 uint32_t SliceTemporalMvpEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< slice_temporal_mvp_enable_flag 2716 uint32_t Sliceqp : __CODEGEN_BITFIELD( 6, 11) ; //!< SliceQp 2717 uint32_t SliceCbQpOffset : __CODEGEN_BITFIELD(12, 16) ; //!< SLICE_CB_QP_OFFSET 2718 uint32_t SliceCrQpOffset : __CODEGEN_BITFIELD(17, 21) ; //!< SLICE_CR_QP_OFFSET 2719 uint32_t Intrareffetchdisable : __CODEGEN_BITFIELD(22, 22) ; //!< IntraRefFetchDisable 2720 uint32_t CuChromaQpOffsetEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cu_chroma_qp_offset_enabled_flag 2721 uint32_t Lastsliceoftile : __CODEGEN_BITFIELD(24, 24) ; //!< LastSliceOfTile 2722 uint32_t Lastsliceoftilecolumn : __CODEGEN_BITFIELD(25, 25) ; //!< LastSliceOfTileColumn 2723 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2724 }; 2725 uint32_t Value; 2726 } DW3; 2727 union 2728 { 2729 struct 2730 { 2731 uint32_t SliceHeaderDisableDeblockingFilterFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< slice_header_disable_deblocking_filter_flag 2732 uint32_t SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder : __CODEGEN_BITFIELD( 1, 4) ; //!< slice_tc_offset_div2 or (final tc_offset_div2 Encoder) 2733 uint32_t SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder : __CODEGEN_BITFIELD( 5, 8) ; //!< slice_beta_offset_div2 or (final Beta_Offset_div2 Encoder) 2734 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 2735 uint32_t SliceLoopFilterAcrossSlicesEnabledFlag : __CODEGEN_BITFIELD(10, 10) ; //!< slice_loop_filter_across_slices_enabled_flag 2736 uint32_t SliceSaoChromaFlag : __CODEGEN_BITFIELD(11, 11) ; //!< slice_sao_chroma_flag 2737 uint32_t SliceSaoLumaFlag : __CODEGEN_BITFIELD(12, 12) ; //!< slice_sao_luma_flag 2738 uint32_t MvdL1ZeroFlag : __CODEGEN_BITFIELD(13, 13) ; //!< mvd_l1_zero_flag 2739 uint32_t Islowdelay : __CODEGEN_BITFIELD(14, 14) ; //!< isLowDelay 2740 uint32_t CollocatedFromL0Flag : __CODEGEN_BITFIELD(15, 15) ; //!< collocated_from_l0_flag 2741 uint32_t Chromalog2Weightdenom : __CODEGEN_BITFIELD(16, 18) ; //!< ChromaLog2WeightDenom 2742 uint32_t LumaLog2WeightDenom : __CODEGEN_BITFIELD(19, 21) ; //!< luma_log2_weight_denom 2743 uint32_t CabacInitFlag : __CODEGEN_BITFIELD(22, 22) ; //!< cabac_init_flag 2744 uint32_t Maxmergeidx : __CODEGEN_BITFIELD(23, 25) ; //!< MAXMERGEIDX 2745 uint32_t Collocatedrefidx : __CODEGEN_BITFIELD(26, 28) ; //!< CollocatedRefIDX 2746 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2747 }; 2748 uint32_t Value; 2749 } DW4; 2750 union 2751 { 2752 struct 2753 { 2754 uint32_t Sliceheaderlength : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceHeaderLength 2755 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2756 }; 2757 uint32_t Value; 2758 } DW5; 2759 union 2760 { 2761 struct 2762 { 2763 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 2764 uint32_t Roundintra : __CODEGEN_BITFIELD(20, 23) ; //!< ROUNDINTRA 2765 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 2766 uint32_t Roundinter : __CODEGEN_BITFIELD(26, 29) ; //!< ROUNDINTER 2767 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2768 }; 2769 uint32_t Value; 2770 } DW6; 2771 union 2772 { 2773 struct 2774 { 2775 uint32_t DependentSliceDueToTileSplit : __CODEGEN_BITFIELD( 0, 0) ; //!< Dependent Slice due to Tile Split 2776 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD( 1, 1) ; //!< CABACZEROWORDINSERTIONENABLE 2777 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD( 2, 2) ; //!< EMULATIONBYTESLICEINSERTENABLE 2778 uint32_t Reserved227 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2779 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< TAIL_INSERTION_ENABLE 2780 uint32_t SlicedataEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SLICEDATA_ENABLE 2781 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< HEADER_INSERTION_ENABLE 2782 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 2783 }; 2784 uint32_t Value; 2785 } DW7; 2786 union 2787 { 2788 struct 2789 { 2790 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 2791 uint32_t IndirectPakBseDataStartOffsetWrite : __CODEGEN_BITFIELD( 6, 28) ; //!< Indirect PAK-BSE Data Start Offset (Write) 2792 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2793 }; 2794 uint32_t Value; 2795 } DW8; 2796 union 2797 { 2798 struct 2799 { 2800 uint32_t TransformskipLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< Transformskip_lambda 2801 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 30) ; //!< Reserved 2802 uint32_t ForceSaoParametersToZero : __CODEGEN_BITFIELD(31, 31) ; //!< Force SAO parameters to zero 2803 }; 2804 uint32_t Value; 2805 } DW9; 2806 union 2807 { 2808 struct 2809 { 2810 uint32_t TransformskipNumzerocoeffsFactor0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Transformskip_numzerocoeffs_factor0 2811 uint32_t TransformskipNumnonzerocoeffsFactor0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Transformskip_numnonzerocoeffs_factor0 2812 uint32_t TransformskipNumzerocoeffsFactor1 : __CODEGEN_BITFIELD(16, 23) ; //!< Transformskip_numzerocoeffs_factor1 2813 uint32_t TransformskipNumnonzerocoeffsFactor1 : __CODEGEN_BITFIELD(24, 31) ; //!< Transformskip_numnonzerocoeffs_factor1 2814 }; 2815 uint32_t Value; 2816 } DW10; 2817 union 2818 { 2819 struct 2820 { 2821 uint32_t Originalslicestartctbx : __CODEGEN_BITFIELD( 0, 9) ; //!< OriginalSliceStartCtbX 2822 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2823 uint32_t Originalslicestartctby : __CODEGEN_BITFIELD(16, 25) ; //!< OriginalSliceStartCtbY 2824 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2825 }; 2826 uint32_t Value; 2827 } DW11; 2828 union 2829 { 2830 struct 2831 { 2832 uint32_t SliceActCrQpOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< slice_act_cr_qp_offset 2833 uint32_t SliceActCbQpOffset : __CODEGEN_BITFIELD( 6, 11) ; //!< slice_act_cb_qp_offset 2834 uint32_t SliceActYQpOffset : __CODEGEN_BITFIELD(12, 17) ; //!< slice_act_y_qp_offset 2835 uint32_t Reserved402 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2836 uint32_t UseIntegerMvFlag : __CODEGEN_BITFIELD(31, 31) ; //!< use_integer_mv_flag 2837 }; 2838 uint32_t Value; 2839 } DW12; 2840 2841 //! \name Local enumerations 2842 2843 enum MEDIA_INSTRUCTION_COMMAND 2844 { 2845 MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE = 20, //!< No additional details 2846 }; 2847 2848 //! \brief MEDIA_INSTRUCTION_OPCODE 2849 //! \details 2850 //! Codec/Engine Name = HCP = 7h 2851 enum MEDIA_INSTRUCTION_OPCODE 2852 { 2853 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2854 }; 2855 2856 enum PIPELINE_TYPE 2857 { 2858 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2859 }; 2860 2861 enum COMMAND_TYPE 2862 { 2863 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2864 }; 2865 2866 //! \brief SLICE_TYPE 2867 //! \details 2868 //! In VDENC mode, for HEVC standard this field can be 0 or 2 only. 2869 enum SLICE_TYPE 2870 { 2871 SLICE_TYPE_B_SLICE = 0, //!< No additional details 2872 SLICE_TYPE_P_SLICE = 1, //!< No additional details 2873 SLICE_TYPE_I_SLICE = 2, //!< No additional details 2874 SLICE_TYPE_ILLEGALRESERVED = 3, //!< No additional details 2875 }; 2876 2877 //! \brief LASTSLICEOFPIC 2878 //! \details 2879 //! This indicates the current slice is the very last slice of the current 2880 //! picture 2881 enum LASTSLICEOFPIC 2882 { 2883 LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE = 0, //!< No additional details 2884 LASTSLICEOFPIC_LASTSLICEOFTHEPICTURE = 1, //!< No additional details 2885 }; 2886 2887 //! \brief SLICE_CB_QP_OFFSET 2888 //! \details 2889 //! For deblocking purpose, the pic and slice level cb qp offset must be 2890 //! provided separately. 2891 enum SLICE_CB_QP_OFFSET 2892 { 2893 SLICE_CB_QP_OFFSET_0 = 0, //!< No additional details 2894 SLICE_CB_QP_OFFSET_1 = 1, //!< No additional details 2895 SLICE_CB_QP_OFFSET_2 = 2, //!< No additional details 2896 SLICE_CB_QP_OFFSET_3 = 3, //!< No additional details 2897 SLICE_CB_QP_OFFSET_4 = 4, //!< No additional details 2898 SLICE_CB_QP_OFFSET_5 = 5, //!< No additional details 2899 SLICE_CB_QP_OFFSET_6 = 6, //!< No additional details 2900 SLICE_CB_QP_OFFSET_7 = 7, //!< No additional details 2901 SLICE_CB_QP_OFFSET_8 = 8, //!< No additional details 2902 SLICE_CB_QP_OFFSET_9 = 9, //!< No additional details 2903 SLICE_CB_QP_OFFSET_10 = 10, //!< No additional details 2904 SLICE_CB_QP_OFFSET_11 = 11, //!< No additional details 2905 SLICE_CB_QP_OFFSET_12 = 12, //!< No additional details 2906 SLICE_CB_QP_OFFSET_NEG_12 = 20, //!< No additional details 2907 SLICE_CB_QP_OFFSET_NEG_11 = 21, //!< No additional details 2908 SLICE_CB_QP_OFFSET_NEG_10 = 22, //!< No additional details 2909 SLICE_CB_QP_OFFSET_NEG_9 = 23, //!< No additional details 2910 SLICE_CB_QP_OFFSET_NEG_8 = 24, //!< No additional details 2911 SLICE_CB_QP_OFFSET_NEG_7 = 25, //!< No additional details 2912 SLICE_CB_QP_OFFSET_NEG_6 = 26, //!< No additional details 2913 SLICE_CB_QP_OFFSET_NEG_5 = 27, //!< No additional details 2914 SLICE_CB_QP_OFFSET_NEG_4 = 28, //!< No additional details 2915 SLICE_CB_QP_OFFSET_NEG_3 = 29, //!< No additional details 2916 SLICE_CB_QP_OFFSET_NEG_2 = 30, //!< No additional details 2917 SLICE_CB_QP_OFFSET_NEG_1 = 31, //!< No additional details 2918 }; 2919 2920 //! \brief SLICE_CR_QP_OFFSET 2921 //! \details 2922 //! For deblocking purpose, the pic and slice level cr qp offset must be 2923 //! provided separately. 2924 enum SLICE_CR_QP_OFFSET 2925 { 2926 SLICE_CR_QP_OFFSET_0 = 0, //!< No additional details 2927 SLICE_CR_QP_OFFSET_1 = 1, //!< No additional details 2928 SLICE_CR_QP_OFFSET_2 = 2, //!< No additional details 2929 SLICE_CR_QP_OFFSET_3 = 3, //!< No additional details 2930 SLICE_CR_QP_OFFSET_4 = 4, //!< No additional details 2931 SLICE_CR_QP_OFFSET_5 = 5, //!< No additional details 2932 SLICE_CR_QP_OFFSET_6 = 6, //!< No additional details 2933 SLICE_CR_QP_OFFSET_7 = 7, //!< No additional details 2934 SLICE_CR_QP_OFFSET_8 = 8, //!< No additional details 2935 SLICE_CR_QP_OFFSET_9 = 9, //!< No additional details 2936 SLICE_CR_QP_OFFSET_10 = 10, //!< No additional details 2937 SLICE_CR_QP_OFFSET_11 = 11, //!< No additional details 2938 SLICE_CR_QP_OFFSET_12 = 12, //!< No additional details 2939 SLICE_CR_QP_OFFSET_NEG_12 = 20, //!< No additional details 2940 SLICE_CR_QP_OFFSET_NEG_11 = 21, //!< No additional details 2941 SLICE_CR_QP_OFFSET_NEG_10 = 22, //!< No additional details 2942 SLICE_CR_QP_OFFSET_NEG_9 = 23, //!< No additional details 2943 SLICE_CR_QP_OFFSET_NEG_8 = 24, //!< No additional details 2944 SLICE_CR_QP_OFFSET_NEG_7 = 25, //!< No additional details 2945 SLICE_CR_QP_OFFSET_NEG_6 = 26, //!< No additional details 2946 SLICE_CR_QP_OFFSET_NEG_5 = 27, //!< No additional details 2947 SLICE_CR_QP_OFFSET_NEG_4 = 28, //!< No additional details 2948 SLICE_CR_QP_OFFSET_NEG_3 = 29, //!< No additional details 2949 SLICE_CR_QP_OFFSET_NEG_2 = 30, //!< No additional details 2950 SLICE_CR_QP_OFFSET_NEG_1 = 31, //!< No additional details 2951 }; 2952 2953 //! \brief MAXMERGEIDX 2954 //! \details 2955 //! MaxNumMergeCand = 5 - five_minus_max_num_merge_cand -1. 2956 enum MAXMERGEIDX 2957 { 2958 MAXMERGEIDX_0 = 0, //!< No additional details 2959 MAXMERGEIDX_1 = 1, //!< No additional details 2960 MAXMERGEIDX_2 = 2, //!< No additional details 2961 MAXMERGEIDX_3 = 3, //!< No additional details 2962 MAXMERGEIDX_4 = 4, //!< No additional details 2963 }; 2964 2965 //! \brief ROUNDINTRA 2966 //! \details 2967 //! In VDENC mode, this field is ignored. 2968 enum ROUNDINTRA 2969 { 2970 ROUNDINTRA_132 = 0, //!< No additional details 2971 ROUNDINTRA_232 = 1, //!< No additional details 2972 ROUNDINTRA_332 = 2, //!< No additional details 2973 ROUNDINTRA_432 = 3, //!< No additional details 2974 ROUNDINTRA_532 = 4, //!< No additional details 2975 ROUNDINTRA_632 = 5, //!< No additional details 2976 ROUNDINTRA_732 = 6, //!< No additional details 2977 ROUNDINTRA_832 = 7, //!< No additional details 2978 ROUNDINTRA_932 = 8, //!< No additional details 2979 ROUNDINTRA_1032 = 9, //!< No additional details 2980 ROUNDINTRA_1132 = 10, //!< No additional details 2981 ROUNDINTRA_1232 = 11, //!< No additional details 2982 ROUNDINTRA_1332 = 12, //!< No additional details 2983 ROUNDINTRA_1432 = 13, //!< No additional details 2984 ROUNDINTRA_1532 = 14, //!< No additional details 2985 ROUNDINTRA_1632 = 15, //!< No additional details 2986 }; 2987 2988 //! \brief ROUNDINTER 2989 //! \details 2990 //! In VDENC mode, this field is ignored. 2991 enum ROUNDINTER 2992 { 2993 ROUNDINTER_132 = 0, //!< No additional details 2994 ROUNDINTER_232 = 1, //!< No additional details 2995 ROUNDINTER_332 = 2, //!< No additional details 2996 ROUNDINTER_432 = 3, //!< No additional details 2997 ROUNDINTER_532 = 4, //!< No additional details 2998 ROUNDINTER_632 = 5, //!< No additional details 2999 ROUNDINTER_732 = 6, //!< No additional details 3000 ROUNDINTER_832 = 7, //!< No additional details 3001 ROUNDINTER_932 = 8, //!< No additional details 3002 ROUNDINTER_1032 = 9, //!< No additional details 3003 ROUNDINTER_1132 = 10, //!< No additional details 3004 ROUNDINTER_1232 = 11, //!< No additional details 3005 ROUNDINTER_1332 = 12, //!< No additional details 3006 ROUNDINTER_1432 = 13, //!< No additional details 3007 ROUNDINTER_1532 = 14, //!< No additional details 3008 ROUNDINTER_1632 = 15, //!< No additional details 3009 }; 3010 3011 //! \brief CABACZEROWORDINSERTIONENABLE 3012 //! \details 3013 //! To pad the end of a SliceLayer RBSP to meet the encoded size 3014 //! requirement. 3015 enum CABACZEROWORDINSERTIONENABLE 3016 { 3017 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion. 3018 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP (effectively can be usedas an indicator for last slice of a picture, if the assumption is only the last slice of a pictureneeds to insert CABAC_ZERO_WORDs). 3019 }; 3020 3021 //! \brief EMULATIONBYTESLICEINSERTENABLE 3022 //! \details 3023 //! To have PAK outputting SODB or EBSP to the output bitstream buffer. 3024 enum EMULATIONBYTESLICEINSERTENABLE 3025 { 3026 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP = 0, //!< No additional details 3027 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGEBSP = 1, //!< No additional details 3028 }; 3029 3030 //! \brief TAIL_INSERTION_ENABLE 3031 //! \details 3032 //! Must be followed by the PAK Insertion Object Command to perform the 3033 //! actual insertion. 3034 enum TAIL_INSERTION_ENABLE 3035 { 3036 TAIL_INSERTION_ENABLE_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits. 3037 TAIL_INSERTION_ENABLE_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits.SKL restriction: Tail insertion is only possible at the end of frame but not in the middle (say slice end) 3038 }; 3039 3040 //! \brief SLICEDATA_ENABLE 3041 //! \details 3042 //! Must always be enabled. Encoder only feature. 3043 enum SLICEDATA_ENABLE 3044 { 3045 SLICEDATA_ENABLE_UNNAMED0 = 0, //!< No operation; no insertion. 3046 SLICEDATA_ENABLE_UNNAMED1 = 1, //!< Slice Data insertion by PAK Object Commands into the output bitstream buffer. 3047 }; 3048 3049 //! \brief HEADER_INSERTION_ENABLE 3050 //! \details 3051 //! Must be followed by the PAK Insertion Object Command to perform the 3052 //! actual insertion. 3053 enum HEADER_INSERTION_ENABLE 3054 { 3055 HEADER_INSERTION_ENABLE_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, before the current slice encoded bits. 3056 HEADER_INSERTION_ENABLE_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is before the current slice encoded bits. 3057 }; 3058 3059 //! \name Initializations 3060 3061 //! \brief Explicit member initialization function HCP_SLICE_STATE_CMDHCP_SLICE_STATE_CMD3062 HCP_SLICE_STATE_CMD() 3063 { 3064 DW0.Value = 0x7394000b; 3065 //DW0.DwordLength = GetOpLength(dwSize); 3066 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE; 3067 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3068 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3069 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3070 3071 DW1.Value = 0x00000000; 3072 3073 DW2.Value = 0x00000000; 3074 3075 DW3.Value = 0x00000000; 3076 //DW3.SliceType = SLICE_TYPE_B_SLICE; 3077 //DW3.Lastsliceofpic = LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE; 3078 //DW3.SliceCbQpOffset = SLICE_CB_QP_OFFSET_0; 3079 //DW3.SliceCrQpOffset = SLICE_CR_QP_OFFSET_0; 3080 3081 DW4.Value = 0x00000000; 3082 //DW4.Maxmergeidx = MAXMERGEIDX_0; 3083 3084 DW5.Value = 0x00000000; 3085 3086 DW6.Value = 0x10400000; 3087 //DW6.Roundintra = ROUNDINTRA_532; 3088 //DW6.Roundinter = ROUNDINTER_532; 3089 3090 DW7.Value = 0x00000000; 3091 //DW7.Cabaczerowordinsertionenable = CABACZEROWORDINSERTIONENABLE_UNNAMED0; 3092 //DW7.Emulationbytesliceinsertenable = EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP; 3093 //DW7.TailInsertionEnable = TAIL_INSERTION_ENABLE_UNNAMED0; 3094 //DW7.SlicedataEnable = SLICEDATA_ENABLE_UNNAMED0; 3095 //DW7.HeaderInsertionEnable = HEADER_INSERTION_ENABLE_UNNAMED0; 3096 3097 DW8.Value = 0x00000000; 3098 3099 DW9.Value = 0x00000000; 3100 3101 DW10.Value = 0x00000000; 3102 3103 DW11.Value = 0x00000000; 3104 3105 DW12.Value = 0x00000000; 3106 } 3107 3108 static const size_t dwSize = 13; 3109 static const size_t byteSize = 52; 3110 }; 3111 3112 //! 3113 //! \brief HCP_BSD_OBJECT 3114 //! \details 3115 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 3116 //! Commands.Each HCP command has assigned a media instruction command as 3117 //! defined in DWord 0, BitField 22:16. 3118 //! 3119 //! The HCP_BSD_OBJECT command fetches the HEVC bit stream for a slice 3120 //! starting with the first byte in the slice.The bit stream ends with the 3121 //! last non-zero bit of the frame and does not include any zero-padding at 3122 //! the end of the bit stream.There can be multiple slices in a HEVC frame 3123 //! and thus this command can be issued multiple times per frame. 3124 //! 3125 //! The HCP_BSD_OBJECT command must be the last command issued in the 3126 //! sequence of batch commands before the HCPstarts decoding. Prior to 3127 //! issuing this command, it is assumed that all configuration parameters in 3128 //! the HCPhave been loaded including workload configuration registers and 3129 //! configuration tables.When this command is issued, the HCP is waiting for 3130 //! bit stream data to be presented to the shift register. 3131 //! 3132 struct HCP_BSD_OBJECT_CMD 3133 { 3134 union 3135 { 3136 struct 3137 { 3138 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3139 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3140 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3141 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3142 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3143 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3144 }; 3145 uint32_t Value; 3146 } DW0; 3147 union 3148 { 3149 struct 3150 { 3151 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3152 }; 3153 uint32_t Value; 3154 } DW1; 3155 union 3156 { 3157 struct 3158 { 3159 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 3160 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3161 }; 3162 uint32_t Value; 3163 } DW2; 3164 3165 //! \name Local enumerations 3166 3167 enum MEDIA_INSTRUCTION_COMMAND 3168 { 3169 MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE = 32, //!< No additional details 3170 }; 3171 3172 //! \brief MEDIA_INSTRUCTION_OPCODE 3173 //! \details 3174 //! Codec/Engine Name = HCP = 7h 3175 enum MEDIA_INSTRUCTION_OPCODE 3176 { 3177 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3178 }; 3179 3180 enum PIPELINE_TYPE 3181 { 3182 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3183 }; 3184 3185 enum COMMAND_TYPE 3186 { 3187 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3188 }; 3189 3190 //! \name Initializations 3191 3192 //! \brief Explicit member initialization function HCP_BSD_OBJECT_CMDHCP_BSD_OBJECT_CMD3193 HCP_BSD_OBJECT_CMD() 3194 { 3195 DW0.Value = 0x73a00001; 3196 //DW0.DwordLength = GetOpLength(dwSize); 3197 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE; 3198 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3199 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3200 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3201 3202 DW1.Value = 0x00000000; 3203 3204 DW2.Value = 0x00000000; 3205 } 3206 3207 static const size_t dwSize = 3; 3208 static const size_t byteSize = 12; 3209 }; 3210 3211 //! 3212 //! \brief HCP_VP9_SEGMENT_STATE 3213 //! \details 3214 //! 3215 //! 3216 struct HCP_VP9_SEGMENT_STATE_CMD 3217 { 3218 union 3219 { 3220 struct 3221 { 3222 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3223 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3224 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3225 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3226 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3227 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3228 }; 3229 uint32_t Value; 3230 } DW0; 3231 union 3232 { 3233 struct 3234 { 3235 uint32_t SegmentId : __CODEGEN_BITFIELD( 0, 2) ; //!< Segment ID 3236 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 3237 }; 3238 uint32_t Value; 3239 } DW1; 3240 union 3241 { 3242 struct 3243 { 3244 uint32_t SegmentSkipped : __CODEGEN_BITFIELD( 0, 0) ; //!< Segment Skipped 3245 uint32_t SegmentReference : __CODEGEN_BITFIELD( 1, 2) ; //!< Segment Reference 3246 uint32_t SegmentReferenceEnabled : __CODEGEN_BITFIELD( 3, 3) ; //!< Segment Reference Enabled 3247 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 3248 }; 3249 uint32_t Value; 3250 } DW2; 3251 union 3252 { 3253 struct 3254 { 3255 uint32_t Filterlevelref0Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef0Mode0 3256 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 3257 uint32_t Filterlevelref0Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef0Mode1 3258 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3259 uint32_t Filterlevelref1Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef1Mode0 3260 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3261 uint32_t Filterlevelref1Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef1Mode1 3262 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3263 }; 3264 uint32_t Value; 3265 } DW3; 3266 union 3267 { 3268 struct 3269 { 3270 uint32_t Filterlevelref2Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef2Mode0 3271 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 3272 uint32_t Filterlevelref2Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef2Mode1 3273 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3274 uint32_t Filterlevelref3Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef3Mode0 3275 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3276 uint32_t Filterlevelref3Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef3Mode1 3277 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3278 }; 3279 uint32_t Value; 3280 } DW4; 3281 union 3282 { 3283 struct 3284 { 3285 uint32_t LumaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 14) ; //!< Luma DC Quant Scale (Decode mode Only) 3286 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3287 uint32_t LumaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 30) ; //!< Luma AC Quant Scale (Decode mode Only) 3288 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3289 }; 3290 uint32_t Value; 3291 } DW5; 3292 union 3293 { 3294 struct 3295 { 3296 uint32_t ChromaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 14) ; //!< Chroma DC Quant Scale (Decode mode Only) 3297 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3298 uint32_t ChromaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 30) ; //!< Chroma AC Quant Scale (Decode mode Only) 3299 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3300 }; 3301 uint32_t Value; 3302 } DW6; 3303 union 3304 { 3305 struct 3306 { 3307 uint32_t SegmentQindexDeltaEncodeModeOnly : __CODEGEN_BITFIELD( 0, 8) ; //!< Segment QIndex Delta (encode mode only) 3308 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3309 uint32_t SegmentLfLevelDeltaEncodeModeOnly : __CODEGEN_BITFIELD(16, 22) ; //!< Segment LF Level Delta (Encode mode Only) 3310 uint32_t Reserved247 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 3311 }; 3312 uint32_t Value; 3313 } DW7; 3314 3315 //! \name Local enumerations 3316 3317 enum MEDIA_INSTRUCTION_COMMAND 3318 { 3319 MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE = 50, //!< No additional details 3320 }; 3321 3322 //! \brief MEDIA_INSTRUCTION_OPCODE 3323 //! \details 3324 //! Codec/Engine Name = HUC = Bh 3325 enum MEDIA_INSTRUCTION_OPCODE 3326 { 3327 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3328 }; 3329 3330 enum PIPELINE_TYPE 3331 { 3332 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3333 }; 3334 3335 enum COMMAND_TYPE 3336 { 3337 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3338 }; 3339 3340 //! \name Initializations 3341 3342 //! \brief Explicit member initialization function HCP_VP9_SEGMENT_STATE_CMDHCP_VP9_SEGMENT_STATE_CMD3343 HCP_VP9_SEGMENT_STATE_CMD() 3344 { 3345 DW0.Value = 0x73b20006; 3346 //DW0.DwordLength = GetOpLength(dwSize); 3347 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE; 3348 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3349 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3350 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3351 3352 DW1.Value = 0x00000000; 3353 3354 DW2.Value = 0x00000000; 3355 3356 DW3.Value = 0x00000000; 3357 3358 DW4.Value = 0x00000000; 3359 3360 DW5.Value = 0x00000000; 3361 3362 DW6.Value = 0x00000000; 3363 3364 DW7.Value = 0x00000000; 3365 } 3366 3367 static const size_t dwSize = 8; 3368 static const size_t byteSize = 32; 3369 }; 3370 3371 //! 3372 //! \brief HCP_FQM_STATE 3373 //! \details 3374 //! The HCP_FQM_STATE command loads the custom HEVC quantization tables into 3375 //! local RAM and may be issued up to8 times: 4 scaling list per intra and 3376 //! inter. 3377 //! 3378 //! Driver is responsible for performing the Scaling List division. So, save 3379 //! the division HW cost in HW.The 1/x value is provided in 16-bit 3380 //! fixed-point precision as ((1<<17)/QM +1) >> 1. . 3381 //! 3382 //! Note: FQM is computed as (2^16)/QM. If QM=1, FQM=all 1's. 3383 //! 3384 //! To simplify the design, only a limited number of scaling lists are 3385 //! provided at the PAK interface: defaulttwo SizeID0 and two SizeID123 (one 3386 //! set for inter and the other set for intra), and the encoder only 3387 //! allowscustom entries for these four matrices. The DC value of SizeID2 3388 //! and SizeID3 will be provided. 3389 //! 3390 //! When the scaling_list_enable_flag is set to disable, the scaling matrix 3391 //! is still sent to the PAK, and withall entries programmed to the same 3392 //! value of 16. 3393 //! 3394 //! This is a picture level state command and is issued in encoding 3395 //! processes only. 3396 //! 3397 //! Dwords 2-33 form a table for the DCT coefficients, 2 16-bit 3398 //! coefficients/DWord.Size 4x4 for SizeID0, DWords 2-9. 3399 //! Size 8x8 for SizeID1/2/3, DWords 2-33. 3400 //! 3401 //! 3402 //! SizeID 0 (Table 4-13) 3403 //! 3404 struct HCP_FQM_STATE_CMD 3405 { 3406 union 3407 { 3408 struct 3409 { 3410 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3411 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3412 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3413 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3414 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3415 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3416 }; 3417 uint32_t Value; 3418 } DW0; 3419 union 3420 { 3421 struct 3422 { 3423 uint32_t IntraInter : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAINTER 3424 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 3425 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 3426 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 3427 uint32_t FqmDcValue1Dc : __CODEGEN_BITFIELD(16, 31) ; //!< FQM DC Value: (1/DC): 3428 }; 3429 uint32_t Value; 3430 } DW1; 3431 uint32_t Quantizermatrix[32]; //!< QuantizerMatrix 3432 3433 //! \name Local enumerations 3434 3435 enum MEDIA_INSTRUCTION_COMMAND 3436 { 3437 MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE = 5, //!< No additional details 3438 }; 3439 3440 //! \brief MEDIA_INSTRUCTION_OPCODE 3441 //! \details 3442 //! Codec/Engine Name = HCP = 7h 3443 enum MEDIA_INSTRUCTION_OPCODE 3444 { 3445 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3446 }; 3447 3448 enum PIPELINE_TYPE 3449 { 3450 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3451 }; 3452 3453 enum COMMAND_TYPE 3454 { 3455 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3456 }; 3457 3458 //! \brief INTRAINTER 3459 //! \details 3460 //! This field specifies the quant matrix intra or inter type. 3461 enum INTRAINTER 3462 { 3463 INTRAINTER_INTRA = 0, //!< No additional details 3464 INTRAINTER_INTER = 1, //!< No additional details 3465 }; 3466 3467 enum SIZEID 3468 { 3469 SIZEID_SIZEID04X4 = 0, //!< No additional details 3470 SIZEID_SIZEID1_2_3_8X8_16X16_32X32 = 1, //!< No additional details 3471 SIZEID_SIZEID2_FORDCVALUEIN16X16 = 2, //!< No additional details 3472 SIZEID_SIZEID3_FORDCVALUEIN32X32 = 3, //!< No additional details 3473 }; 3474 3475 //! \brief COLOR_COMPONENT 3476 //! \details 3477 //! Luma and Chroma's share the same scaling list and DC value for the 3478 //! same SizeID. 3479 enum COLOR_COMPONENT 3480 { 3481 COLOR_COMPONENT_LUMA = 0, //!< No additional details 3482 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 3483 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 3484 }; 3485 3486 //! \name Initializations 3487 3488 //! \brief Explicit member initialization function HCP_FQM_STATE_CMDHCP_FQM_STATE_CMD3489 HCP_FQM_STATE_CMD() 3490 { 3491 DW0.Value = 0x73850020; 3492 //DW0.DwordLength = GetOpLength(dwSize); 3493 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE; 3494 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3495 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3496 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3497 3498 DW1.Value = 0x00000000; 3499 //DW1.IntraInter = INTRAINTER_INTRA; 3500 //DW1.Sizeid = SIZEID_SIZEID04X4; 3501 //DW1.ColorComponent = COLOR_COMPONENT_LUMA; 3502 3503 memset(&Quantizermatrix, 0, sizeof(Quantizermatrix)); 3504 } 3505 3506 static const size_t dwSize = 34; 3507 static const size_t byteSize = 136; 3508 }; 3509 3510 //! 3511 //! \brief HCP_PAK_INSERT_OBJECT 3512 //! \details 3513 //! It is an encoder only command, operating at bitstream level, before and 3514 //! after SliceData compressed bitstream. It is setup by the header and tail 3515 //! present flags in the Slice State command. If these flags are set and no 3516 //! subsequent PAK_INSERT_OBJECT commands are issued, the pipeline will 3517 //! hang. 3518 //! 3519 //! The HCP_ PAK_ INSERT _OBJECT command supports both inline and indirect 3520 //! data payload, but only one can be active at any time. It is issued to 3521 //! insert a chunk of bits (payload) into the current compressed bitstream 3522 //! output buffer (specified in the HCP_PAK-BSE Object Base Address field of 3523 //! the HCP_IND_OBJ_BASE_ADDR_STATE command) starting at its current write 3524 //! pointer bit position. Hardware will keep track of this write pointer's 3525 //! byte position and the associated next bit insertion position index. 3526 //! 3527 //! It is a variable length command when the payload (data to be inserted) 3528 //! is presented as inline data within the command itself. The inline 3529 //! payload is a multiple of 32-bit (1 DW), as the data bus to the 3530 //! compressed bitstream output buffer is 32-bit wide. 3531 //! 3532 //! The payload data is required to be byte aligned on the left (first 3533 //! transmitted bit order) and may or may not be byte aligned on the right 3534 //! (last transmitted bits). The command will specify the bit offset of the 3535 //! last valid DW. Note that : Stitch Command is used if the beginning 3536 //! position of data is in bit position. When PAK Insert Command is used the 3537 //! beginning position must be in byte position. 3538 //! 3539 //! Multiple insertion commands can be issued back to back in a series. It 3540 //! is host software's responsibility to make sure their corresponding data 3541 //! will properly stitch together to form a valid bitstream. 3542 //! 3543 //! Internally, HCP hardware will keep track of the very last two bytes' 3544 //! (the very last byte can be a partial byte) values of the previous 3545 //! insertion. It is required that the next Insertion Object Command or the 3546 //! next PAK Object Command to perform the start code emulation sequence 3547 //! check and prevention 0x03 byte insertion with this end condition of the 3548 //! previous insertion. 3549 //! 3550 //! The payload data may have already been processed for start code 3551 //! emulation byte insertion, except the possibility of the last 2 bytes 3552 //! plus the very last partial byte (if any). Hence, when hardware 3553 //! performing the concatenation of multiple consecutive insertion commands, 3554 //! or concatenation of an insertion command and a PAK object command, it 3555 //! must check and perform the necessary start code emulation byte insert at 3556 //! the junction. 3557 //! 3558 //! Data to be inserted can be a valid NAL units or a partial NAL unit. It 3559 //! can be any encoded syntax elements bit data before the encoded Slice 3560 //! Data (PAK Object Command) of the current Slice - SPS NAL, PPS NAL, SEI 3561 //! NAL and Other Non-Slice NAL, Leading_Zero_8_bits (as many bytes as there 3562 //! is), Start Code , Slice Header. Any encoded syntax elements bit data 3563 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3564 //! and prior to the next encoded Slice Data of the next Slice or prior to 3565 //! the end of the bitstream, whichever comes first Cabac_Zero_Word or 3566 //! Trailing_Zero_8bits (as many bytes as there is). 3567 //! 3568 //! Certain NAL unit has a minimum byte size requirement. As such the 3569 //! hardware will optionally (enabled by SLICE STATE Command) determines the 3570 //! number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, 3571 //! based on the minimum byte size of a NAL and the actual bin count of the 3572 //! encoded Slice. Since prior to the CABAC_ZERO_WORD insertion, the RBSP or 3573 //! EBSP is already byte-aligned, so each CABAC_ZERO_WORD insertion is 3574 //! actually a 3-byte sequence 0x00 00 03. 3575 //! 3576 //! Context switch interrupt is not supported by this command. 3577 //! 3578 struct HCP_PAK_INSERT_OBJECT_CMD 3579 { 3580 union 3581 { 3582 struct 3583 { 3584 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3585 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3586 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3587 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3588 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3589 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3590 }; 3591 uint32_t Value; 3592 } DW0; 3593 union 3594 { 3595 struct 3596 { 3597 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3598 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3599 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3600 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3601 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3602 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3603 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< Slice Header Indicator 3604 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3605 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3606 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 3607 uint32_t IndirectPayloadEnable : __CODEGEN_BITFIELD(31, 31) ; //!< INDIRECT_PAYLOAD_ENABLE 3608 }; 3609 uint32_t Value; 3610 } DW1; 3611 3612 //! \name Local enumerations 3613 3614 enum MEDIA_INSTRUCTION_COMMAND 3615 { 3616 MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT = 34, //!< No additional details 3617 }; 3618 3619 //! \brief MEDIA_INSTRUCTION_OPCODE 3620 //! \details 3621 //! Codec/Engine Name = HCP = 7h 3622 enum MEDIA_INSTRUCTION_OPCODE 3623 { 3624 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3625 }; 3626 3627 enum PIPELINE_TYPE 3628 { 3629 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3630 }; 3631 3632 enum COMMAND_TYPE 3633 { 3634 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3635 }; 3636 3637 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3638 //! \details 3639 //! Only valid for HEVC and reserved for VP9. 3640 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3641 { 3642 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_STARTCODEPREFIX = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between. 3643 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_INSERTIONCOMMAND = 2, //!< Insertion commands, or an insertion command followed by a PAK Object command. 3644 }; 3645 3646 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3647 //! \details 3648 //! <p>In case this flag is on, bits are NOT accumulated during current 3649 //! access unit coding neither for Cabac Zero Word insertion bits counting 3650 //! or for output in MMIO register 3651 //! HCP_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER.</p> 3652 //! <p>When using HeaderLenghtExcludeFrmSize for header insertion, the 3653 //! software needs to make sure that data comes already with inserted start 3654 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 3655 //! DWORD1 of HCP_PAK_INSERT_OBJECT).</p> 3656 //! <table border="1" cellpadding="0" cellspacing="0" style="width: 100%;" 3657 //! width="100%"> 3658 //! <tbody> 3659 //! <tr> 3660 //! <td> 3661 //! <p align="center"><b>Value</b></p></td> 3662 //! <td> 3663 //! <p align="center"><b style="text-align: 3664 //! -webkit-center;">Description</b></p></td> 3665 //! </tr> 3666 //! <tr> 3667 //! <td> 3668 //! <p>0</p></td> 3669 //! <td> 3670 //! <p>All bits accumulated</p></td> 3671 //! </tr> 3672 //! <tr> 3673 //! <td> 3674 //! <p>1</p></td> 3675 //! <td> 3676 //! <p>Bits during current call are not accumulated</p></td> 3677 //! </tr> 3678 //! </tbody> 3679 //! </table> 3680 //! 3681 //! <p></p> 3682 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3683 { 3684 HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED = 0, //!< No additional details 3685 HEADERLENGTHEXCLUDEFRMSIZE_BITSDURINGCURRENTCALLARENOTACCUMULATED = 1, //!< No additional details 3686 }; 3687 3688 //! \brief INDIRECT_PAYLOAD_ENABLE 3689 //! \details 3690 //! <p>Only one of these two payload modes can be active at any time.</p> 3691 //! <p>When Slice Size Conformance is enable the Payload(header) must be 3692 //! inline only so this bit set to MBZ.</p> 3693 enum INDIRECT_PAYLOAD_ENABLE 3694 { 3695 INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED = 0, //!< No additional details 3696 INDIRECT_PAYLOAD_ENABLE_INDIRECTPAYLOADISUSED = 1, //!< No additional details 3697 }; 3698 3699 //! \name Initializations 3700 3701 //! \brief Explicit member initialization function HCP_PAK_INSERT_OBJECT_CMDHCP_PAK_INSERT_OBJECT_CMD3702 HCP_PAK_INSERT_OBJECT_CMD() 3703 { 3704 DW0.Value = 0x73a20000; 3705 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT; 3706 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3707 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3708 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3709 3710 DW1.Value = 0x00000000; 3711 //DW1.EmulationflagEmulationbytebitsinsertenable = 0; 3712 //DW1.Headerlengthexcludefrmsize = HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED; 3713 //DW1.IndirectPayloadEnable = INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED; 3714 } 3715 3716 static const size_t dwSize = 2; 3717 static const size_t byteSize = 8; 3718 }; 3719 3720 //! 3721 //! \brief HCP_VP9_PIC_STATE 3722 //! \details 3723 //! 3724 //! 3725 struct HCP_VP9_PIC_STATE_CMD 3726 { 3727 union 3728 { 3729 struct 3730 { 3731 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3732 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3733 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3734 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3735 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3736 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3737 }; 3738 uint32_t Value; 3739 } DW0; 3740 union 3741 { 3742 struct 3743 { 3744 uint32_t FrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Width In Pixels Minus 1 3745 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3746 uint32_t FrameHeightInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Height In Pixels Minus 1 3747 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3748 }; 3749 uint32_t Value; 3750 } DW1; 3751 union 3752 { 3753 struct 3754 { 3755 uint32_t FrameType : __CODEGEN_BITFIELD( 0, 0) ; //!< FRAME_TYPE 3756 uint32_t AdaptProbabilitiesFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPT_PROBABILITIES_FLAG 3757 uint32_t IntraonlyFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< IntraOnly Flag 3758 uint32_t AllowHiPrecisionMv : __CODEGEN_BITFIELD( 3, 3) ; //!< ALLOW_HI_PRECISION_MV 3759 uint32_t McompFilterType : __CODEGEN_BITFIELD( 4, 6) ; //!< MCOMP_FILTER_TYPE 3760 uint32_t RefFrameSignBias02 : __CODEGEN_BITFIELD( 7, 9) ; //!< Ref Frame Sign Bias[0..2] 3761 uint32_t UsePrevInFindMvReferences : __CODEGEN_BITFIELD(10, 10) ; //!< Use Prev in Find MV References 3762 uint32_t HybridPredictionMode : __CODEGEN_BITFIELD(11, 11) ; //!< HYBRID_PREDICTION_MODE 3763 uint32_t SelectableTxMode : __CODEGEN_BITFIELD(12, 12) ; //!< SELECTABLE_TX_MODE 3764 uint32_t LastFrameType : __CODEGEN_BITFIELD(13, 13) ; //!< LAST_FRAME_TYPE 3765 uint32_t RefreshFrameContext : __CODEGEN_BITFIELD(14, 14) ; //!< REFRESH_FRAME_CONTEXT 3766 uint32_t ErrorResilientMode : __CODEGEN_BITFIELD(15, 15) ; //!< ERROR_RESILIENT_MODE 3767 uint32_t FrameParallelDecodingMode : __CODEGEN_BITFIELD(16, 16) ; //!< FRAME_PARALLEL_DECODING_MODE 3768 uint32_t FilterLevel : __CODEGEN_BITFIELD(17, 22) ; //!< Filter Level 3769 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(23, 25) ; //!< Sharpness Level 3770 uint32_t SegmentationEnabled : __CODEGEN_BITFIELD(26, 26) ; //!< SEGMENTATION_ENABLED 3771 uint32_t SegmentationUpdateMap : __CODEGEN_BITFIELD(27, 27) ; //!< SEGMENTATION_UPDATE_MAP 3772 uint32_t SegmentationTemporalUpdate : __CODEGEN_BITFIELD(28, 28) ; //!< SEGMENTATION_TEMPORAL_UPDATE 3773 uint32_t LosslessMode : __CODEGEN_BITFIELD(29, 29) ; //!< LOSSLESS_MODE 3774 uint32_t SegmentIdStreamoutEnable : __CODEGEN_BITFIELD(30, 30) ; //!< SEGMENT_ID_STREAMOUT_ENABLE 3775 uint32_t SegmentIdStreaminEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SEGMENT_ID_STREAMIN_ENABLE 3776 }; 3777 uint32_t Value; 3778 } DW2; 3779 union 3780 { 3781 struct 3782 { 3783 uint32_t Log2TileColumn : __CODEGEN_BITFIELD( 0, 3) ; //!< LOG2_TILE_COLUMN 3784 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 3785 uint32_t Log2TileRow : __CODEGEN_BITFIELD( 8, 9) ; //!< LOG2_TILE_ROW 3786 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 3787 uint32_t SseEnable : __CODEGEN_BITFIELD(21, 21) ; //!< SSE Enable 3788 uint32_t ChromaSamplingFormat : __CODEGEN_BITFIELD(22, 23) ; //!< CHROMA_SAMPLING_FORMAT 3789 uint32_t Bitdepthminus8 : __CODEGEN_BITFIELD(24, 27) ; //!< BITDEPTHMINUS8 3790 uint32_t ProfileLevel : __CODEGEN_BITFIELD(28, 31) ; //!< PROFILE_LEVEL 3791 }; 3792 uint32_t Value; 3793 } DW3; 3794 union 3795 { 3796 struct 3797 { 3798 uint32_t VerticalScaleFactorForLast : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for LAST 3799 uint32_t HorizontalScaleFactorForLast : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for LAST 3800 }; 3801 uint32_t Value; 3802 } DW4; 3803 union 3804 { 3805 struct 3806 { 3807 uint32_t VerticalScaleFactorForGolden : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for GOLDEN 3808 uint32_t HorizontalScaleFactorForGolden : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for GOLDEN 3809 }; 3810 uint32_t Value; 3811 } DW5; 3812 union 3813 { 3814 struct 3815 { 3816 uint32_t VerticalScaleFactorForAltref : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for ALTREF 3817 uint32_t HorizontalScaleFactorForAltref : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for ALTREF 3818 }; 3819 uint32_t Value; 3820 } DW6; 3821 union 3822 { 3823 struct 3824 { 3825 uint32_t LastFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Last Frame Width In Pixels Minus 1 3826 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3827 uint32_t LastFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Last Frame Hieght In Pixels Minus 1 3828 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 3829 uint32_t HrsunitlevelclockgateEnChickenBit : __CODEGEN_BITFIELD(31, 31) ; //!< HRSUnitLevelClockGate_en Chicken Bit 3830 }; 3831 uint32_t Value; 3832 } DW7; 3833 union 3834 { 3835 struct 3836 { 3837 uint32_t GoldenFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Golden Frame Width In Pixels Minus 1 3838 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3839 uint32_t GoldenFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Golden Frame Hieght In Pixels Minus 1 3840 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3841 }; 3842 uint32_t Value; 3843 } DW8; 3844 union 3845 { 3846 struct 3847 { 3848 uint32_t AltrefFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Altref Frame Width In Pixels Minus 1 3849 uint32_t Reserved302 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3850 uint32_t AltrefFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Altref Frame Hieght In Pixels Minus 1 3851 uint32_t Reserved318 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3852 }; 3853 uint32_t Value; 3854 } DW9; 3855 union 3856 { 3857 struct 3858 { 3859 uint32_t UncompressedHeaderLengthInBytes70 : __CODEGEN_BITFIELD( 0, 7) ; //!< Uncompressed Header Length in Bytes [7:0] 3860 uint32_t Reserved328 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3861 uint32_t FirstPartitionSizeInBytes150 : __CODEGEN_BITFIELD(16, 31) ; //!< First Partition Size in Bytes [15:0] 3862 }; 3863 uint32_t Value; 3864 } DW10; 3865 union 3866 { 3867 struct 3868 { 3869 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3870 uint32_t MotionCompScalingEnableBit : __CODEGEN_BITFIELD( 1, 1) ; //!< MOTION_COMP_SCALING_ENABLE_BIT 3871 uint32_t MvClampDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< MV_CLAMP_DISABLE 3872 uint32_t ChromaFractionalCalculationModified : __CODEGEN_BITFIELD( 3, 3) ; //!< CHROMA_FRACTIONAL_CALCULATION_MODIFIED 3873 uint32_t Reserved356 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 3874 }; 3875 uint32_t Value; 3876 } DW11; 3877 union 3878 { 3879 struct 3880 { 3881 uint32_t Reserved384 ; //!< Reserved 3882 }; 3883 uint32_t Value; 3884 } DW12; 3885 union 3886 { 3887 struct 3888 { 3889 uint32_t CompressedHeaderBinCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Compressed header BIN count 3890 uint32_t BaseQIndexSameAsLumaAc : __CODEGEN_BITFIELD(16, 23) ; //!< Base Q Index (Same as Luma AC) 3891 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< Tail Insertion Enable 3892 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Header Insertion Enable 3893 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 3894 uint32_t Reserved443 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3895 }; 3896 uint32_t Value; 3897 } DW13; 3898 union 3899 { 3900 struct 3901 { 3902 uint32_t ChromaacQindexdelta : __CODEGEN_BITFIELD( 0, 4) ; //!< ChromaAC_QindexDelta 3903 uint32_t Reserved453 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 3904 uint32_t ChromadcQindexdelta : __CODEGEN_BITFIELD( 8, 12) ; //!< ChromaDC_QindexDelta 3905 uint32_t Reserved461 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 3906 uint32_t LumaDcQIndexDelta : __CODEGEN_BITFIELD(16, 20) ; //!< Luma DC Q Index Delta 3907 uint32_t Reserved469 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3908 }; 3909 uint32_t Value; 3910 } DW14; 3911 union 3912 { 3913 struct 3914 { 3915 uint32_t LfRefDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF_ref_delta0 3916 uint32_t Reserved487 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3917 uint32_t LfRefDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF_ref_delta1 3918 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3919 uint32_t LfRefDelta2 : __CODEGEN_BITFIELD(16, 22) ; //!< LF_ref_delta2 3920 uint32_t Reserved503 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 3921 uint32_t LfRefDelta3 : __CODEGEN_BITFIELD(24, 30) ; //!< LF_ref_delta3 3922 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3923 }; 3924 uint32_t Value; 3925 } DW15; 3926 union 3927 { 3928 struct 3929 { 3930 uint32_t LfModeDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF Mode Delta 0 3931 uint32_t Reserved519 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3932 uint32_t LfModeDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF Mode Delta 1 3933 uint32_t Reserved527 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 3934 }; 3935 uint32_t Value; 3936 } DW16; 3937 union 3938 { 3939 struct 3940 { 3941 uint32_t Bitoffsetforlfrefdelta : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForLFRefDelta 3942 uint32_t Bitoffsetforlfmodedelta : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFModeDelta 3943 }; 3944 uint32_t Value; 3945 } DW17; 3946 union 3947 { 3948 struct 3949 { 3950 uint32_t Bitoffsetforqindex : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForQindex 3951 uint32_t Bitoffsetforlflevel : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFLevel 3952 }; 3953 uint32_t Value; 3954 } DW18; 3955 union 3956 { 3957 struct 3958 { 3959 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 3960 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 3961 uint32_t VdencPakOnlyPass : __CODEGEN_BITFIELD(17, 17) ; //!< VDENC PAK_ONLY PASS 3962 uint32_t Reserved626 : __CODEGEN_BITFIELD(18, 24) ; //!< Reserved 3963 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3964 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3965 uint32_t Reserved635 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3966 }; 3967 uint32_t Value; 3968 } DW19; 3969 union 3970 { 3971 struct 3972 { 3973 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 3974 uint32_t Reserved654 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3975 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 3976 }; 3977 uint32_t Value; 3978 } DW20; 3979 union 3980 { 3981 struct 3982 { 3983 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 3984 uint32_t Reserved686 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3985 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 3986 }; 3987 uint32_t Value; 3988 } DW21; 3989 union 3990 { 3991 struct 3992 { 3993 uint64_t Framedeltaqindexmax ; //!< FrameDeltaQindexMax 3994 }; 3995 uint32_t Value[2]; 3996 } DW22_23; 3997 union 3998 { 3999 struct 4000 { 4001 uint32_t Framedeltaqindexmin ; //!< FrameDeltaQindexMin 4002 }; 4003 uint32_t Value; 4004 } DW24; 4005 union 4006 { 4007 struct 4008 { 4009 uint64_t Framedeltalfmax ; //!< FrameDeltaLFMax 4010 }; 4011 uint32_t Value[2]; 4012 } DW25_26; 4013 union 4014 { 4015 struct 4016 { 4017 uint32_t Framedeltalfmin ; //!< FrameDeltaLFMin 4018 }; 4019 uint32_t Value; 4020 } DW27; 4021 union 4022 { 4023 struct 4024 { 4025 uint64_t Framedeltaqindexlfmaxrange ; //!< FrameDeltaQindexLFMaxRange 4026 }; 4027 uint32_t Value[2]; 4028 } DW28_29; 4029 union 4030 { 4031 struct 4032 { 4033 uint32_t Framedeltaqindexlfminrange ; //!< FrameDeltaQindexLFMinRange 4034 }; 4035 uint32_t Value; 4036 } DW30; 4037 union 4038 { 4039 struct 4040 { 4041 uint32_t Minframsize : __CODEGEN_BITFIELD( 0, 15) ; //!< MinFramSize 4042 uint32_t Reserved1008 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 4043 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 4044 }; 4045 uint32_t Value; 4046 } DW31; 4047 union 4048 { 4049 struct 4050 { 4051 uint32_t Bitoffsetforfirstpartitionsize : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForFirstPartitionSize 4052 uint32_t Reserved1040 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4053 }; 4054 uint32_t Value; 4055 } DW32; 4056 union 4057 { 4058 struct 4059 { 4060 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 4061 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 4062 }; 4063 uint32_t Value; 4064 } DW33; 4065 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 4066 4067 //! \name Local enumerations 4068 4069 enum MEDIA_INSTRUCTION_COMMAND 4070 { 4071 MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE = 48, //!< No additional details 4072 }; 4073 4074 //! \brief MEDIA_INSTRUCTION_OPCODE 4075 //! \details 4076 //! Codec/Engine Name = HUC = Bh 4077 enum MEDIA_INSTRUCTION_OPCODE 4078 { 4079 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4080 }; 4081 4082 enum PIPELINE_TYPE 4083 { 4084 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4085 }; 4086 4087 enum COMMAND_TYPE 4088 { 4089 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4090 }; 4091 4092 //! \brief FRAME_TYPE 4093 //! \details 4094 //! Specifies the VP9 frame type 4095 enum FRAME_TYPE 4096 { 4097 FRAME_TYPE_KEYFRAME = 0, //!< No additional details 4098 FRAME_TYPE_INTERFRAME = 1, //!< No additional details 4099 }; 4100 4101 //! \brief ADAPT_PROBABILITIES_FLAG 4102 //! \details 4103 //! Indicates that the probabilities used to decode this frame should be 4104 //! adapted 4105 enum ADAPT_PROBABILITIES_FLAG 4106 { 4107 ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET = 0, //!< No additional details 4108 ADAPT_PROBABILITIES_FLAG_1ADAPT_NOTERRORRESILIENTANDNOTFRAMEPARALLELMODE = 1, //!< No additional details 4109 }; 4110 4111 //! \brief ALLOW_HI_PRECISION_MV 4112 //! \details 4113 //! Indicate high precision mode for Motion Vector prediction 4114 enum ALLOW_HI_PRECISION_MV 4115 { 4116 ALLOW_HI_PRECISION_MV_NORMALMODE = 0, //!< No additional details 4117 ALLOW_HI_PRECISION_MV_HIGHPRECISIONMODE = 1, //!< No additional details 4118 }; 4119 4120 //! \brief MCOMP_FILTER_TYPE 4121 //! \details 4122 //! Indicate Motion Compensation Filter type. 4123 enum MCOMP_FILTER_TYPE 4124 { 4125 MCOMP_FILTER_TYPE_EIGHT_TAP = 0, //!< No additional details 4126 MCOMP_FILTER_TYPE_EIGHT_TAP_SMOOTH = 1, //!< No additional details 4127 MCOMP_FILTER_TYPE_EIGHT_TAP_SHARP = 2, //!< No additional details 4128 MCOMP_FILTER_TYPE_BILINEAR = 3, //!< No additional details 4129 MCOMP_FILTER_TYPE_SWITCHABLE = 4, //!< No additional details 4130 }; 4131 4132 //! \brief HYBRID_PREDICTION_MODE 4133 //! \details 4134 //! Indicates if comp_pred_mode is hybrid 4135 enum HYBRID_PREDICTION_MODE 4136 { 4137 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM = 0, //!< No additional details 4138 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERPACKSCOMPPREDMODEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 1, //!< No additional details 4139 }; 4140 4141 //! \brief SELECTABLE_TX_MODE 4142 //! \details 4143 //! Indicates if tx_mode is selectable 4144 enum SELECTABLE_TX_MODE 4145 { 4146 SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 0, //!< No additional details 4147 SELECTABLE_TX_MODE_ENCODERPACKSTUSIZEINTOBITSTREAM = 1, //!< No additional details 4148 }; 4149 4150 //! \brief LAST_FRAME_TYPE 4151 //! \details 4152 //! It indicates the frame type of previous frame (Key or Non-Key 4153 //! Frame) 4154 enum LAST_FRAME_TYPE 4155 { 4156 LAST_FRAME_TYPE_KEYFRAME = 0, //!< No additional details 4157 LAST_FRAME_TYPE_NONKEYFRAME = 1, //!< No additional details 4158 }; 4159 4160 //! \brief REFRESH_FRAME_CONTEXT 4161 //! \details 4162 //! Indicates if Frame Context should be refresh. This bit should come 4163 //! from Uncompressed header 4164 enum REFRESH_FRAME_CONTEXT 4165 { 4166 REFRESH_FRAME_CONTEXT_DISABLE = 0, //!< No additional details 4167 REFRESH_FRAME_CONTEXT_ENABLE = 1, //!< No additional details 4168 }; 4169 4170 //! \brief ERROR_RESILIENT_MODE 4171 //! \details 4172 //! Indicates if error resilient mode is enabled.This bit should come 4173 //! from Uncompressed header.When error resilient is 1, Frame Parallel 4174 //! Decoding Mode will be 1, and Refresh Frame Context will be 0.When error 4175 //! resilient is 0, Frame Parallel Decoding Mode and Refresh Frame Context 4176 //! read from bit stream.Together with Frame Parallel Decoding mode, they 4177 //! decide the value of AdaptProbabilityFlag. 4178 enum ERROR_RESILIENT_MODE 4179 { 4180 ERROR_RESILIENT_MODE_DISABLE = 0, //!< No additional details 4181 ERROR_RESILIENT_MODE_ENABLE = 1, //!< No additional details 4182 }; 4183 4184 //! \brief FRAME_PARALLEL_DECODING_MODE 4185 //! \details 4186 //! Indicates if parallel decoding mode is enabled. This bit should come 4187 //! from Uncompressed header. Together with Error Resilient mode, they 4188 //! decide the value of AdaptProbabilityFlag. 4189 enum FRAME_PARALLEL_DECODING_MODE 4190 { 4191 FRAME_PARALLEL_DECODING_MODE_DISABLE = 0, //!< No additional details 4192 FRAME_PARALLEL_DECODING_MODE_ENABLE = 1, //!< No additional details 4193 }; 4194 4195 //! \brief SEGMENTATION_ENABLED 4196 //! \details 4197 //! Indicate if segementation is enabled or not 4198 enum SEGMENTATION_ENABLED 4199 { 4200 SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0 = 0, //!< No additional details 4201 SEGMENTATION_ENABLED_SEGIDDETERMINATIONDEPENDSONSEGMENTATIONUPDATEMAPSETTING = 1, //!< No additional details 4202 }; 4203 4204 //! \brief SEGMENTATION_UPDATE_MAP 4205 //! \details 4206 //! Indicates how hardware determines segmentation ID 4207 enum SEGMENTATION_UPDATE_MAP 4208 { 4209 SEGMENTATION_UPDATE_MAP_UNNAMED0 = 0, //!< Intra block: segment ID is zero Inter block: get segment ID from previous frame (streamIN) 4210 SEGMENTATION_UPDATE_MAP_UNNAMED1 = 1, //!< Intra block: decode segment ID from bitstream. Inter block: determins from segmentation_temporal_update setting 4211 }; 4212 4213 //! \brief SEGMENTATION_TEMPORAL_UPDATE 4214 //! \details 4215 //! Indicates whether segID is decoding from bitstream or predicted from 4216 //! previous frame. 4217 enum SEGMENTATION_TEMPORAL_UPDATE 4218 { 4219 SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM = 0, //!< No additional details 4220 SEGMENTATION_TEMPORAL_UPDATE_GETSEGIDEITHERFROMBITSTREAMORFROMPREVIOUSFRAME = 1, //!< No additional details 4221 }; 4222 4223 //! \brief LOSSLESS_MODE 4224 //! \details 4225 //! This bitSet to indicate lossless coding mode. 4226 enum LOSSLESS_MODE 4227 { 4228 LOSSLESS_MODE_NORMALMODE = 0, //!< No additional details 4229 LOSSLESS_MODE_LOLESSMODE = 1, //!< No additional details 4230 }; 4231 4232 //! \brief SEGMENT_ID_STREAMOUT_ENABLE 4233 //! \details 4234 //! Indicates SegmentID of current frame needs to be streamOut for next 4235 //! frame 4236 enum SEGMENT_ID_STREAMOUT_ENABLE 4237 { 4238 SEGMENT_ID_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 4239 SEGMENT_ID_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 4240 }; 4241 4242 //! \brief SEGMENT_ID_STREAMIN_ENABLE 4243 //! \details 4244 //! Indicates SegmentID from previous frame needs to be streamIn for Segment 4245 //! ID prediction 4246 enum SEGMENT_ID_STREAMIN_ENABLE 4247 { 4248 SEGMENT_ID_STREAMIN_ENABLE_DISABLE = 0, //!< No additional details 4249 SEGMENT_ID_STREAMIN_ENABLE_ENABLE = 1, //!< No additional details 4250 }; 4251 4252 //! \brief LOG2_TILE_COLUMN 4253 //! \details 4254 //! This indicates the number of tile rows (log2). 4255 enum LOG2_TILE_COLUMN 4256 { 4257 LOG2_TILE_COLUMN_1TILECOLUMN = 0, //!< No additional details 4258 LOG2_TILE_COLUMN_2TILECOLUMN = 1, //!< No additional details 4259 LOG2_TILE_COLUMN_4TILECOLUMN = 2, //!< No additional details 4260 LOG2_TILE_COLUMN_8TILECOLUMN = 3, //!< No additional details 4261 LOG2_TILE_COLUMN_16TILECOLUMN = 4, //!< No additional details 4262 LOG2_TILE_COLUMN_32TILECOLUMN = 5, //!< No additional details 4263 LOG2_TILE_COLUMN_64TILECOLUMN = 6, //!< No additional details 4264 }; 4265 4266 //! \brief LOG2_TILE_ROW 4267 //! \details 4268 //! This indicates the number of tile rows (log2). 4269 enum LOG2_TILE_ROW 4270 { 4271 LOG2_TILE_ROW_1TILEROW = 0, //!< No additional details 4272 LOG2_TILE_ROW_2TILEROW = 1, //!< No additional details 4273 LOG2_TILE_ROW_4TILEROW = 2, //!< No additional details 4274 }; 4275 4276 //! \brief CHROMA_SAMPLING_FORMAT 4277 //! \details 4278 //! This indicates the chroma sampling format of the bitstream 4279 enum CHROMA_SAMPLING_FORMAT 4280 { 4281 CHROMA_SAMPLING_FORMAT_FORMAT420 = 0, //!< Chroma Format 420, supported by profile 0 and 2 4282 CHROMA_SAMPLING_FORMAT_FORMAT444 = 2, //!< Chroma Format 444, suported by Profile 1 and 3 4283 }; 4284 4285 //! \brief BITDEPTHMINUS8 4286 //! \details 4287 //! This indicates the bitdepth (minus 8) of the pixels 4288 enum BITDEPTHMINUS8 4289 { 4290 BITDEPTHMINUS8_BITDEPTH8 = 0, //!< It indicates pixel bitdepth is 8. Only profile 0 is allowed in this mode. 4291 BITDEPTHMINUS8_BITDEPTH10 = 2, //!< It indicates pixel bitdepth is 10. Only profile 2 is allowed in this mode. 4292 BITDEPTHMINUS8_BITDEPTH12 = 4, //!< It indicates pixel bitdepth is 12. Only profile 2 is allowed in this mode. 4293 }; 4294 4295 //! \brief PROFILE_LEVEL 4296 //! \details 4297 //! This indicates VP9 Profile level from bitstream 4298 enum PROFILE_LEVEL 4299 { 4300 PROFILE_LEVEL_PROFILE0 = 0, //!< Profile 0 only supports 8 bit 420 only 4301 PROFILE_LEVEL_PROFILE1 = 1, //!< Profile 1 only supports 8 bit 444 only 4302 PROFILE_LEVEL_PROFILE2 = 2, //!< Profile 2 only supports 10 bits 420 only 4303 PROFILE_LEVEL_PROFILE3 = 3, //!< Profile 3 only supports 10-bit 444 only 4304 }; 4305 4306 //! \brief MOTION_COMP_SCALING_ENABLE_BIT 4307 //! \details 4308 //! This bit must be set to "1" 4309 enum MOTION_COMP_SCALING_ENABLE_BIT 4310 { 4311 MOTION_COMP_SCALING_ENABLE_BIT_DISABLE = 0, //!< This setting will use Pre-Dec13 version 4312 MOTION_COMP_SCALING_ENABLE_BIT_ENABLE = 1, //!< This enables Motion Comp Scaling 4313 }; 4314 4315 //! \brief MV_CLAMP_DISABLE 4316 //! \details 4317 //! This modifies how hardware handles MV clamping logic 4318 //! "0"--MV clamping logic is enabled; "1"--MV clamping logic is 4319 //! disabled Not used in Encoder Mode 4320 enum MV_CLAMP_DISABLE 4321 { 4322 MV_CLAMP_DISABLE_ENABLE = 0, //!< No additional details 4323 MV_CLAMP_DISABLE_DISABLE = 1, //!< No additional details 4324 }; 4325 4326 //! \brief CHROMA_FRACTIONAL_CALCULATION_MODIFIED 4327 //! \details 4328 //! This changes how Chroma Fractional Calculation is handled in MC 4329 //! "0"--Default version (current); "1"--Matched an earlier 4330 //! version of ref decoder 4331 enum CHROMA_FRACTIONAL_CALCULATION_MODIFIED 4332 { 4333 CHROMA_FRACTIONAL_CALCULATION_MODIFIED_CURRENT = 0, //!< No additional details 4334 CHROMA_FRACTIONAL_CALCULATION_MODIFIED_OUTDATED = 1, //!< No additional details 4335 }; 4336 4337 //! \brief NONFIRSTPASSFLAG 4338 //! \details 4339 //! This signals the current pass is not the first pass. It will imply 4340 //! designate HW behavior. 4341 enum NONFIRSTPASSFLAG 4342 { 4343 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 4344 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 4345 }; 4346 4347 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 4348 //! \details 4349 //! This is a mask bit controlling if the condition of frame level bit count 4350 //! exceeds FrameBitRateMax. 4351 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 4352 { 4353 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_VP9_IMAGE_STATUS control register. 4354 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit Rate Maximum limit. 4355 }; 4356 4357 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 4358 //! \details 4359 //! This is a mask bit controlling if the condition of frame level bit count 4360 //! is less than FrameBitRateMin. 4361 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 4362 { 4363 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register. 4364 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 4365 }; 4366 4367 //! \brief FRAMEBITRATEMAXUNIT 4368 //! \details 4369 //! This field is the Frame Bitrate Maximum Limit Units. 4370 enum FRAMEBITRATEMAXUNIT 4371 { 4372 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 4373 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4Kbyte unit 4374 }; 4375 4376 //! \brief FRAMEBITRATEMINUNIT 4377 //! \details 4378 //! This field is the Frame Bitrate Maximum Limit Units. 4379 enum FRAMEBITRATEMINUNIT 4380 { 4381 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 4382 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4Kbyte unit 4383 }; 4384 4385 //! \brief MINFRAMESIZEUNITS 4386 //! \details 4387 //! This field is the Minimum Frame Size Units 4388 enum MINFRAMESIZEUNITS 4389 { 4390 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 4391 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 4Kbytes. 4392 MINFRAMESIZEUNITS_COMAPTIBILITYMODE = 2, //!< No additional details 4393 MINFRAMESIZEUNITS_6BYTES = 3, //!< No additional details 4394 }; 4395 4396 //! \name Initializations 4397 4398 //! \brief Explicit member initialization function HCP_VP9_PIC_STATE_CMDHCP_VP9_PIC_STATE_CMD4399 HCP_VP9_PIC_STATE_CMD() 4400 { 4401 DW0.Value = 0x73b00028; 4402 //DW0.DwordLength = GetOpLength(dwSize); 4403 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE; 4404 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4405 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4406 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4407 4408 DW1.Value = 0x00000000; 4409 4410 DW2.Value = 0x00000000; 4411 //DW2.FrameType = FRAME_TYPE_KEYFRAME; 4412 //DW2.AdaptProbabilitiesFlag = ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET; 4413 //DW2.AllowHiPrecisionMv = ALLOW_HI_PRECISION_MV_NORMALMODE; 4414 //DW2.McompFilterType = MCOMP_FILTER_TYPE_EIGHT_TAP; 4415 //DW2.HybridPredictionMode = HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM; 4416 //DW2.SelectableTxMode = SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER; 4417 //DW2.LastFrameType = LAST_FRAME_TYPE_KEYFRAME; 4418 //DW2.RefreshFrameContext = REFRESH_FRAME_CONTEXT_DISABLE; 4419 //DW2.ErrorResilientMode = ERROR_RESILIENT_MODE_DISABLE; 4420 //DW2.FrameParallelDecodingMode = FRAME_PARALLEL_DECODING_MODE_DISABLE; 4421 //DW2.SegmentationEnabled = SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0; 4422 //DW2.SegmentationUpdateMap = SEGMENTATION_UPDATE_MAP_UNNAMED0; 4423 //DW2.SegmentationTemporalUpdate = SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM; 4424 //DW2.LosslessMode = LOSSLESS_MODE_NORMALMODE; 4425 //DW2.SegmentIdStreamoutEnable = SEGMENT_ID_STREAMOUT_ENABLE_DISABLE; 4426 //DW2.SegmentIdStreaminEnable = SEGMENT_ID_STREAMIN_ENABLE_DISABLE; 4427 4428 DW3.Value = 0x00000000; 4429 //DW3.Log2TileColumn = LOG2_TILE_COLUMN_1TILECOLUMN; 4430 //DW3.Log2TileRow = LOG2_TILE_ROW_1TILEROW; 4431 //DW3.ChromaSamplingFormat = CHROMA_SAMPLING_FORMAT_FORMAT420; 4432 //DW3.Bitdepthminus8 = BITDEPTHMINUS8_BITDEPTH8; 4433 //DW3.ProfileLevel = PROFILE_LEVEL_PROFILE0; 4434 4435 DW4.Value = 0x00000000; 4436 4437 DW5.Value = 0x00000000; 4438 4439 DW6.Value = 0x00000000; 4440 4441 DW7.Value = 0x00000000; 4442 4443 DW8.Value = 0x00000000; 4444 4445 DW9.Value = 0x00000000; 4446 4447 DW10.Value = 0x00000000; 4448 4449 DW11.Value = 0x00000002; 4450 //DW11.MotionCompScalingEnableBit = MOTION_COMP_SCALING_ENABLE_BIT_ENABLE; 4451 //DW11.MvClampDisable = MV_CLAMP_DISABLE_ENABLE; 4452 //DW11.ChromaFractionalCalculationModified = CHROMA_FRACTIONAL_CALCULATION_MODIFIED_CURRENT; 4453 4454 DW12.Value = 0x00000000; 4455 4456 DW13.Value = 0x00000000; 4457 4458 DW14.Value = 0x00000000; 4459 4460 DW15.Value = 0x00000000; 4461 4462 DW16.Value = 0x00000000; 4463 4464 DW17.Value = 0x00000000; 4465 4466 DW18.Value = 0x00000000; 4467 4468 DW19.Value = 0x00000000; 4469 //DW19.Nonfirstpassflag = NONFIRSTPASSFLAG_DISABLE; 4470 //DW19.FrameszoverstatusenFramebitratemaxreportmask = FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE; 4471 //DW19.FrameszunderstatusenFramebitrateminreportmask = FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE; 4472 4473 DW20.Value = 0x00000000; 4474 //DW20.Framebitratemaxunit = FRAMEBITRATEMAXUNIT_BYTE; 4475 4476 DW21.Value = 0x00000000; 4477 //DW21.Framebitrateminunit = FRAMEBITRATEMINUNIT_BYTE; 4478 4479 DW22_23.Value[0] = DW22_23.Value[1] = 0x00000000; 4480 4481 DW24.Value = 0x00000000; 4482 4483 DW25_26.Value[0] = DW25_26.Value[1] = 0x00000000; 4484 4485 DW27.Value = 0x00000000; 4486 4487 DW28_29.Value[0] = DW28_29.Value[1] = 0x00000000; 4488 4489 DW30.Value = 0x00000000; 4490 4491 DW31.Value = 0x00000000; 4492 //DW31.Minframesizeunits = MINFRAMESIZEUNITS_4KB; 4493 4494 DW32.Value = 0x00000000; 4495 4496 DW33.Value = 0x00000000; 4497 4498 memset(&SseThresholdsForClass18, 0, sizeof(SseThresholdsForClass18)); 4499 } 4500 4501 static const size_t dwSize = 42; 4502 static const size_t byteSize = 168; 4503 }; 4504 4505 //! 4506 //! \brief HEVC_VP9_RDOQ_LAMBDA_FIELDS 4507 //! \details 4508 //! 4509 //! 4510 struct HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD 4511 { 4512 union 4513 { 4514 struct 4515 { 4516 uint32_t Lambdavalue0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LambdaValue0 4517 uint32_t Lambdavalue1 : __CODEGEN_BITFIELD(16, 31) ; //!< LambdaValue1 4518 }; 4519 uint32_t Value; 4520 } DW0; 4521 4522 //! \name Local enumerations 4523 4524 //! \name Initializations 4525 4526 //! \brief Explicit member initialization function HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMDHEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD4527 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD() 4528 { 4529 DW0.Value = 0x00000000; 4530 } 4531 4532 static const size_t dwSize = 1; 4533 static const size_t byteSize = 4; 4534 }; 4535 4536 //! 4537 //! \brief HEVC_VP9_RDOQ_STATE 4538 //! \details 4539 //! 4540 //! 4541 struct HEVC_VP9_RDOQ_STATE_CMD 4542 { 4543 union 4544 { 4545 struct 4546 { 4547 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4548 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4549 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 4550 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 4551 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 4552 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4553 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4554 }; 4555 uint32_t Value; 4556 } DW0; 4557 union 4558 { 4559 struct 4560 { 4561 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 4562 uint32_t DisableHtqPerformanceFix1 : __CODEGEN_BITFIELD(30, 30) ; //!< Disable HTQ performance fix1 4563 uint32_t DisableHtqPerformanceFix0 : __CODEGEN_BITFIELD(31, 31) ; //!< Disable HTQ performance fix0 4564 }; 4565 uint32_t Value; 4566 } DW1; 4567 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda[32]; //!< DW2..33, IntraLumaLambda 4568 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda[32]; //!< DW34..65, IntraChromaLambda 4569 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda[32]; //!< DW66..97, InterLumaLambda 4570 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda[32]; //!< DW98..129, InterChromaLambda 4571 4572 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda12bit[6]; //!< DW130..135, IntraLumaLambda 4573 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda12bit[6]; //!< DW136..141, IntraChromaLambda 4574 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda12bit[6]; //!< DW142..147, InterLumaLambda 4575 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda12bit[6]; //!< DW148..153, InterChromaLambda 4576 4577 //! \name Local enumerations 4578 4579 enum SUBOPB 4580 { 4581 SUBOPB_UNNAMED8 = 8, //!< No additional details 4582 }; 4583 4584 enum SUBOPA 4585 { 4586 SUBOPA_UNNAMED0 = 0, //!< No additional details 4587 }; 4588 4589 //! \brief OPCODE 4590 //! \details 4591 //! Codec/Engine Name = HCP = 7h 4592 enum OPCODE 4593 { 4594 OPCODE_UNNAMED7 = 7, //!< No additional details 4595 }; 4596 4597 //! \brief PIPELINE 4598 //! \details 4599 //! MFX_COMMON 4600 enum PIPELINE 4601 { 4602 PIPELINE_UNNAMED2 = 2, //!< No additional details 4603 }; 4604 4605 //! \brief COMMAND_TYPE 4606 //! \details 4607 //! PARALLEL_VIDEO_PIPE 4608 enum COMMAND_TYPE 4609 { 4610 COMMAND_TYPE_UNNAMED3 = 3, //!< No additional details 4611 }; 4612 4613 //! \name Initializations 4614 4615 //! \brief Explicit member initialization function HEVC_VP9_RDOQ_STATE_CMDHEVC_VP9_RDOQ_STATE_CMD4616 HEVC_VP9_RDOQ_STATE_CMD() 4617 { 4618 DW0.Value = 0x73880098; 4619 //DW0.DwordLength = GetOpLength(dwSize); 4620 //DW0.Subopb = SUBOPB_UNNAMED8; 4621 //DW0.Subopa = SUBOPA_UNNAMED0; 4622 //DW0.Opcode = OPCODE_UNNAMED7; 4623 //DW0.Pipeline = PIPELINE_UNNAMED2; 4624 //DW0.CommandType = COMMAND_TYPE_UNNAMED3; 4625 4626 DW1.Value = 0x00000000; 4627 } 4628 4629 static const size_t dwSize = 154; 4630 static const size_t byteSize = 616; 4631 }; 4632 4633 //! 4634 //! \brief HCP_TILE_CODING 4635 //! \details 4636 //! This command is used for both HEVC and VP9 codecs 4637 //! 4638 struct HCP_TILE_CODING_CMD 4639 { 4640 union 4641 { 4642 struct 4643 { 4644 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4645 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4646 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4647 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4648 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4649 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4650 }; 4651 uint32_t Value; 4652 } DW0; 4653 union 4654 { 4655 struct 4656 { 4657 uint32_t NumberOfActiveBePipes : __CODEGEN_BITFIELD( 0, 7) ; //!< Number of Active BE Pipes 4658 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD( 8, 8) ; //!< Tile Row store Select 4659 uint32_t TileColumnStoreSelect : __CODEGEN_BITFIELD( 9, 9) ; //!< Tile Column store Select 4660 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved MBZ 4661 uint32_t NumOfTileColumnsInAFrame : __CODEGEN_BITFIELD(16, 31) ; //!< Num of Tile columns in a Frame 4662 }; 4663 uint32_t Value; 4664 } DW1; 4665 union 4666 { 4667 struct 4668 { 4669 uint32_t TileColumnPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< Tile Column Position 4670 uint32_t NonFirstPassTile : __CODEGEN_BITFIELD(10, 10) ; //!< Non First Pass Tile 4671 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4672 uint32_t TileRowPosition : __CODEGEN_BITFIELD(16, 25) ; //!< Tile Row Position 4673 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 29) ; //!< Reserved 4674 uint32_t Islasttileofrow : __CODEGEN_BITFIELD(30, 30) ; //!< IsLastTileOfRow 4675 uint32_t Islasttileofcolumn : __CODEGEN_BITFIELD(31, 31) ; //!< IsLastTileOfColumn 4676 }; 4677 uint32_t Value; 4678 } DW2; 4679 union 4680 { 4681 struct 4682 { 4683 uint32_t Tileheightinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< TileHeightInMinCbMinus1 4684 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4685 uint32_t Tilewidthinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< TileWidthInMinCbMinus1 4686 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 30) ; //!< Reserved 4687 uint32_t LastpassoftileValidationonly : __CODEGEN_BITFIELD(31, 31) ; //!< LastPassOfTile (ValidationOnly) 4688 }; 4689 uint32_t Value; 4690 } DW3; 4691 union 4692 { 4693 struct 4694 { 4695 uint32_t BitstreamByteOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Bitstream Byte Offset Enable 4696 uint32_t Reserved129 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 4697 uint32_t BitstreamByteOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitstream Byte Offset 4698 }; 4699 uint32_t Value; 4700 } DW4; 4701 union 4702 { 4703 struct 4704 { 4705 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4706 uint32_t PakFrameStatisticsOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< PAK Frame Statistics Offset 4707 }; 4708 uint32_t Value; 4709 } DW5; 4710 union 4711 { 4712 struct 4713 { 4714 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4715 uint32_t CuLevelStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU Level Streamout Offset 4716 }; 4717 uint32_t Value; 4718 } DW6; 4719 union 4720 { 4721 struct 4722 { 4723 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4724 uint32_t SliceSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Slice Size Streamout Offset 4725 }; 4726 uint32_t Value; 4727 } DW7; 4728 union 4729 { 4730 struct 4731 { 4732 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4733 uint32_t CuRecordOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU record offset 4734 }; 4735 uint32_t Value; 4736 } DW8; 4737 union 4738 { 4739 struct 4740 { 4741 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4742 uint32_t SseRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SSE RowStore offset 4743 }; 4744 uint32_t Value; 4745 } DW9; 4746 union 4747 { 4748 struct 4749 { 4750 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4751 uint32_t SaoRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SAO RowStore offset 4752 }; 4753 uint32_t Value; 4754 } DW10; 4755 union 4756 { 4757 struct 4758 { 4759 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4760 uint32_t TileSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Size StreamOut Offset 4761 }; 4762 uint32_t Value; 4763 } DW11; 4764 union 4765 { 4766 struct 4767 { 4768 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4769 uint32_t Vp9ProbabilityCounterStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< VP9 Probability Counter Streamout Offset 4770 }; 4771 uint32_t Value; 4772 } DW12; 4773 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySynchronizeBufferBaseAddress; //!< DW13..14, HCP Scalability Synchronize Buffer - Base Address 4774 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySynchronizeBufferAttributes; //!< DW15, HCP Scalability Synchronize Buffer - Attributes 4775 union 4776 { 4777 struct 4778 { 4779 uint32_t Reserved512 ; //!< Reserved 4780 }; 4781 uint32_t Value; 4782 } DW16; 4783 union 4784 { 4785 struct 4786 { 4787 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4788 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 4789 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame Number 4790 uint32_t Reserved562 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 4791 }; 4792 uint32_t Value; 4793 } DW17; 4794 union 4795 { 4796 struct 4797 { 4798 uint32_t TilemetadataDw1 ; //!< TileMetaData_DW1 4799 }; 4800 uint32_t Value; 4801 } DW18; 4802 union 4803 { 4804 struct 4805 { 4806 uint32_t TilemetadataDw2 ; //!< TileMetaData_DW2 4807 }; 4808 uint32_t Value; 4809 } DW19; 4810 4811 //! \name Local enumerations 4812 4813 enum MEDIA_INSTRUCTION_COMMAND 4814 { 4815 MEDIA_INSTRUCTION_COMMAND_HCPTILECODING = 21, //!< No additional details 4816 }; 4817 4818 enum MEDIA_INSTRUCTION_OPCODE 4819 { 4820 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4821 }; 4822 4823 enum PIPELINE_TYPE 4824 { 4825 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4826 }; 4827 4828 enum COMMAND_TYPE 4829 { 4830 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4831 }; 4832 4833 //! \name Initializations 4834 4835 //! \brief Explicit member initialization function HCP_TILE_CODING_CMDHCP_TILE_CODING_CMD4836 HCP_TILE_CODING_CMD() 4837 { 4838 DW0.Value = 0x73950012; 4839 //DW0.DwordLength = GetOpLength(dwSize); 4840 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPTILECODING; 4841 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4842 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4843 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4844 4845 DW1.Value = 0x00000000; 4846 4847 DW2.Value = 0x00000000; 4848 4849 DW3.Value = 0x00000000; 4850 4851 DW4.Value = 0x00000000; 4852 4853 DW5.Value = 0x00000000; 4854 4855 DW6.Value = 0x00000000; 4856 4857 DW7.Value = 0x00000000; 4858 4859 DW8.Value = 0x00000000; 4860 4861 DW9.Value = 0x00000000; 4862 4863 DW10.Value = 0x00000000; 4864 4865 DW11.Value = 0x00000000; 4866 4867 DW12.Value = 0x00000000; 4868 4869 DW16.Value = 0x00000000; 4870 4871 DW17.Value = 0x00000000; 4872 4873 DW18.Value = 0x00000000; 4874 4875 DW19.Value = 0x00000000; 4876 4877 } 4878 4879 static const size_t dwSize = 20; 4880 static const size_t byteSize = 80; 4881 }; 4882 4883 //! 4884 //! \brief HCP_PALETTE_INITIALIZER_STATE 4885 //! \details 4886 //! The HCP is selected with theMedia Instruction Opcode "7h"for all HCP 4887 //! Commands. Each HCP command has assigned a media instruction command as 4888 //! defined in DWord 0, BitField 22:16. 4889 //! 4890 //! The HCP_PALETTE_INITIALIZER_STATE command loads in the SCC Palette 4891 //! Initilizer Table to the HW. Decoder only command. 4892 //! 4893 //! Dword#2 - 193form a fixed size table for the Palette Initializer Table. 4894 //! Max PaletteInitializer Table is 128entries. Each entry has 3 components 4895 //! (Y, Cb and Cr) for a color. Each component is 16-bits, even though 4896 //! currently only support up to 10-bit SCC extension. The upper (higher 4897 //! bits) 6 bits are set to zero - that is Least Significant Bit alignment. 4898 //! Each entry of thePalette Initializer Table will consume 1.5 Dwords. 4899 //! Every two entries will consume 2 Dwords. Hence, total requires 96 4900 //! Dwords. Dword#2 Bit 31 Cb#0 15:0 Luma#0 15:0 Bit 0 Dword#3 Bit 31 4901 //! Luma#115:0 Cr#015:0 Bit 0 Dword#4 Bit 31 Cr#115:0 Cb#115:0 Bit 0 4902 //! Dword#2 correspondsto the entry# 0 of thePalette Initializer Table. 4903 //! Dword#193correspondsto the entry# 127of thePalette Initializer Table. 4904 //! 4905 //! Palette Initialization needs to happen at the beginning of each 4906 //! frame/tiles or start of each independent slice. Palette initialization 4907 //! is not needed at the start of dependent slices (except the start of a 4908 //! new tiles since each tile needs to re-initialize the palette list) and 4909 //! the palette list is inherited from previous slice. The following is the 4910 //! programming restriction: (1) Palette Initialization commandmust be 4911 //! programmedin palette mode at the beginning of each frame and tiles 4912 //! (regardless if the slice isindependent/dependent)and also the start of 4913 //! each independent slices. (2) Palette Initialization command must not be 4914 //! programmed for dependent slices except the dependent slices are start of 4915 //! tiles (first slice in frame must be independent slice). /> 4916 //! 4917 struct HCP_PALETTE_INITIALIZER_STATE_CMD 4918 { 4919 union 4920 { 4921 struct 4922 { 4923 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4924 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4925 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4926 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4927 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4928 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4929 }; 4930 uint32_t Value; 4931 } DW0; 4932 union 4933 { 4934 struct 4935 { 4936 uint32_t ActivePaletteInitializerTableEntries : __CODEGEN_BITFIELD( 0, 7) ; //!< Active Palette Initializer Table Entries 4937 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 4938 }; 4939 uint32_t Value; 4940 } DW1; 4941 uint32_t First64ColorEntries[96]; //!< First 64 Color Entries 4942 uint32_t Second64ColorEntries[96]; //!< Second 64 Color Entries 4943 4944 //! \name Local enumerations 4945 4946 enum MEDIA_INSTRUCTION_COMMAND 4947 { 4948 MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE = 9, //!< No additional details 4949 }; 4950 4951 //! \brief MEDIA_INSTRUCTION_OPCODE 4952 //! \details 4953 //! Codec/Engine Name = HCP = 7h 4954 enum MEDIA_INSTRUCTION_OPCODE 4955 { 4956 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4957 }; 4958 4959 enum PIPELINE_TYPE 4960 { 4961 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4962 }; 4963 4964 enum COMMAND_TYPE 4965 { 4966 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4967 }; 4968 4969 //! \name Initializations 4970 4971 //! \brief Explicit member initialization function HCP_PALETTE_INITIALIZER_STATE_CMDHCP_PALETTE_INITIALIZER_STATE_CMD4972 HCP_PALETTE_INITIALIZER_STATE_CMD() 4973 { 4974 DW0.Value = 0x738900c0; 4975 //DW0.DwordLength = GetOpLength(dwSize); 4976 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE; 4977 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4978 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4979 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4980 4981 DW1.Value = 0x00000000; 4982 4983 memset(&First64ColorEntries, 0, sizeof(First64ColorEntries)); 4984 4985 memset(&Second64ColorEntries, 0, sizeof(Second64ColorEntries)); 4986 } 4987 4988 static const size_t dwSize = 194; 4989 static const size_t byteSize = 776; 4990 }; 4991 4992 MEDIA_CLASS_DEFINE_END(mhw__vdbox__hcp__xe2_lpm_base__xe2_lpm__Cmd) 4993 }; // cmd 4994 } // namespace xe2_lpm 4995 } // namespace xe2_lpm_base 4996 } // namespace hcp 4997 } // namespace vdbox 4998 } // namespace mhw 4999 5000 #pragma pack() 5001 5002 #endif // __MHW_VDBOX_HCP_HWCMD_XE2_LPM_H__ 5003