1 /* 2 # Copyright (c) 2024, Intel Corporation 3 # 4 # Permission is hereby granted, free of charge, to any person obtaining a 5 # copy of this software and associated documentation files (the "Software"), 6 # to deal in the Software without restriction, including without limitation 7 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 # and/or sell copies of the Software, and to permit persons to whom the 9 # Software is furnished to do so, subject to the following conditions: 10 # 11 # The above copyright notice and this permission notice shall be included 12 # in all copies or substantial portions of the Software. 13 # 14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 # OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_hcp_impl_xe2_lpm_base.h 24 //! \brief MHW VDBOX HCP interface common base for all XE2_LPM platforms 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_HCP_IMPL_XE2_LPM_BASE_H__ 29 #define __MHW_VDBOX_HCP_IMPL_XE2_LPM_BASE_H__ 30 31 #include "mhw_vdbox_hcp_impl.h" 32 #include "mhw_mi_hwcmd_xe2_lpm_base_next.h" 33 #include "mhw_sfc_hwcmd_xe2_lpm_base_next.h" 34 #include "mhw_vdbox_xe2_lpm_base.h" 35 36 namespace mhw 37 { 38 namespace vdbox 39 { 40 namespace hcp 41 { 42 namespace xe2_lpm_base 43 { 44 template <typename cmd_t> 45 class BaseImpl : public hcp::Impl<cmd_t> 46 { 47 public: GetHcpVp9PicStateCommandSize()48 uint32_t GetHcpVp9PicStateCommandSize() 49 { 50 return cmd_t::HCP_VP9_PIC_STATE_CMD::byteSize; 51 } 52 GetHcpVp9SegmentStateCommandSize()53 uint32_t GetHcpVp9SegmentStateCommandSize() 54 { 55 return cmd_t::HCP_VP9_SEGMENT_STATE_CMD::byteSize; 56 } 57 GetHcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)58 MOS_STATUS GetHcpStateCommandSize( 59 uint32_t mode, 60 uint32_t * commandsSize, 61 uint32_t * patchListSize, 62 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) 63 { 64 MOS_STATUS eStatus = MOS_STATUS_SUCCESS; 65 66 MHW_FUNCTION_ENTER; 67 68 uint32_t maxSize = 0; 69 uint32_t patchListMaxSize = 0; 70 uint32_t standard = CodecHal_GetStandardFromMode(mode); 71 MHW_CHK_NULL_RETURN(params); 72 auto par = dynamic_cast<mhw::vdbox::xe2_lpm_base::PMHW_VDBOX_STATE_CMDSIZE_PARAMS_XE2_LPM_BASE>(params); 73 MHW_CHK_NULL_RETURN(par); 74 75 if (standard == CODECHAL_HEVC) 76 { 77 maxSize = 78 8 + 79 mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize + 80 cmd_t::HCP_PIPE_MODE_SELECT_CMD::byteSize + 81 cmd_t::HCP_SURFACE_STATE_CMD::byteSize + 82 cmd_t::HCP_PIPE_BUF_ADDR_STATE_CMD::byteSize + 83 cmd_t::HCP_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 84 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize * 8; 85 86 patchListMaxSize = 87 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::VD_PIPELINE_FLUSH_CMD) + 88 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) + 89 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PIPE_MODE_SELECT_CMD) + 90 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_SURFACE_STATE_CMD) + 91 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PIPE_BUF_ADDR_STATE_CMD) + 92 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_IND_OBJ_BASE_ADDR_STATE_CMD); 93 94 if (mode == CODECHAL_ENCODE_MODE_HEVC) 95 { 96 /* HCP_QM_STATE_CMD may be issued up to 20 times: 3x Colour Component plus 2x intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components. 97 HCP_FQP_STATE_CMD may be issued up to 8 times: 4 scaling list per intra and inter. */ 98 maxSize += 99 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 100 cmd_t::HCP_SURFACE_STATE_CMD::byteSize + // encoder needs two surface state commands. One is for raw and another one is for recon surfaces. 101 20 * cmd_t::HCP_QM_STATE_CMD::byteSize + 102 8 * cmd_t::HCP_FQM_STATE_CMD::byteSize + 103 cmd_t::HCP_PIC_STATE_CMD::byteSize + 104 cmd_t::HEVC_VP9_RDOQ_STATE_CMD::byteSize + // RDOQ 105 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize + // Slice level commands 106 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize + // need for Status report, Mfc Status and 107 10 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_REGISTER_MEM_CMD::byteSize + // 8 for BRCStatistics and 2 for RC6 WAs 108 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_MEM_CMD::byteSize + // 1 for RC6 WA 109 2 * cmd_t::HCP_PAK_INSERT_OBJECT_CMD::byteSize + // Two PAK insert object commands are for headers before the slice header and the header for the end of stream 110 4 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize + // two (BRC+reference frame) for clean-up HW semaphore memory and another two for signal it 111 17 * mhw::mi::xe2_lpm_base_next::Cmd::MI_SEMAPHORE_WAIT_CMD::byteSize + // Use HW wait command for each reference and one wait for current semaphore object 112 mhw::mi::xe2_lpm_base_next::Cmd::MI_SEMAPHORE_WAIT_CMD::byteSize + // Use HW wait command for each BRC pass 113 +mhw::mi::xe2_lpm_base_next::Cmd::MI_SEMAPHORE_WAIT_CMD::byteSize // Use HW wait command for each VDBOX 114 + 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize // One is for reset and another one for set per VDBOX 115 + 8 * mhw::mi::xe2_lpm_base_next::Cmd::MI_COPY_MEM_MEM_CMD::byteSize // Need to copy SSE statistics/ Slice Size overflow into memory 116 ; 117 118 patchListMaxSize += 119 20 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_QM_STATE_CMD) + 120 8 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_FQM_STATE_CMD) + 121 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PIC_STATE_CMD) + 122 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD) + // When BRC is on, HCP_PIC_STATE_CMD command is in the BB 123 2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) + // Slice level commands 124 2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) + // need for Status report, Mfc Status and 125 11 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_REGISTER_MEM_CMD) + // 8 for BRCStatistics and 3 for RC6 WAs 126 22 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) // Use HW wait commands plus its memory clean-up and signal (4+ 16 + 1 + 1) 127 + 8 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD) // At maximal, there are 8 batch buffers for 8 VDBOXes for VE. Each box has one BB. 128 + PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) // Need one flush before copy command 129 + PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_WAIT_CMD) // Need one wait after copy command 130 + 3 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) // one wait commands and two for reset and set semaphore memory 131 + 8 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_COPY_MEM_MEM_CMD) // Need to copy SSE statistics/ Slice Size overflow into memory 132 ; 133 } 134 else 135 { 136 maxSize += 137 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + // VD_CONTROL_STATE Hcp init and flush 138 20 * cmd_t::HCP_QM_STATE_CMD::byteSize + 139 cmd_t::HCP_PIC_STATE_CMD::byteSize + 140 cmd_t::HCP_TILE_STATE_CMD::byteSize; 141 142 patchListMaxSize += 143 20 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_QM_STATE_CMD) + 144 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PIC_STATE_CMD) + 145 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_TILE_STATE_CMD); 146 147 if (params->bSfcInUse) 148 { 149 maxSize += 150 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_LOCK_CMD::byteSize + 151 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 152 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_STATE_CMD::byteSize + 153 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_STATE_CMD::byteSize + 154 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize + 155 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize + 156 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_IEF_STATE_CMD::byteSize + 157 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_FRAME_START_CMD::byteSize; 158 patchListMaxSize += 159 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_STATE_CMD_NUMBER_OF_ADDRESSES + 160 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_AVS_CHROMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES + 161 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_AVS_LUMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES + 162 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_AVS_STATE_CMD_NUMBER_OF_ADDRESSES + 163 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_FRAME_START_CMD_NUMBER_OF_ADDRESSES + 164 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_IEF_STATE_CMD_NUMBER_OF_ADDRESSES + 165 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_LOCK_CMD_NUMBER_OF_ADDRESSES; 166 } 167 168 if (par->bScalableMode) 169 { 170 // VD_CONTROL_STATE Hcp lock and unlock 171 maxSize += 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize; 172 173 // Due to the fact that there is no slice level command in BE status, we mainly consider commands in FE. 174 maxSize += 175 4 * mhw::mi::xe2_lpm_base_next::Cmd::MI_ATOMIC_CMD::byteSize + // used to reset semaphore in BEs 176 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize + // 1 Conditional BB END for FE hang, 1 for streamout buffer writing over allocated size 177 3 * mhw::mi::xe2_lpm_base_next::Cmd::MI_SEMAPHORE_WAIT_CMD::byteSize + // for FE & BE0, BEs sync 178 15 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize + // for placeholder cmds to resolve the hazard between BEs sync 179 3 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize + // for FE status set and clear 180 3 * mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_IMM_CMD::byteSize + // for FE status set 181 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize + // 2 needed for command flush in slice level 182 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_REGISTER_MEM_CMD::byteSize + // store the carry flag of reported size in FE 183 4 * sizeof(MHW_MI_ALU_PARAMS) + // 4 ALU commands needed for substract opertaion in FE 184 mhw::mi::xe2_lpm_base_next::Cmd::MI_MATH_CMD::byteSize + // 1 needed for FE status set 185 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set 186 mhw::mi::xe2_lpm_base_next::Cmd::MI_MATH_CMD::byteSize + // 1 needed for FE status set 187 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set 188 189 patchListMaxSize += 190 4 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_ATOMIC_CMD) + 191 2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_CONDITIONAL_BATCH_BUFFER_END_CMD) + 192 3 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_SEMAPHORE_WAIT_CMD) + 193 18 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) + 194 2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) + 195 2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_REGISTER_MEM_CMD); 196 197 if (params->bSfcInUse) 198 { 199 maxSize += 200 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_LOCK_CMD::byteSize + 201 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 202 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_STATE_CMD::byteSize + 203 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_STATE_CMD::byteSize + 204 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize + 205 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize + 206 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_IEF_STATE_CMD::byteSize + 207 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_FRAME_START_CMD::byteSize; 208 patchListMaxSize += 209 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_STATE_CMD_NUMBER_OF_ADDRESSES + 210 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_AVS_CHROMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES + 211 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_AVS_LUMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES + 212 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_AVS_STATE_CMD_NUMBER_OF_ADDRESSES + 213 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_FRAME_START_CMD_NUMBER_OF_ADDRESSES + 214 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_IEF_STATE_CMD_NUMBER_OF_ADDRESSES + 215 mhw::sfc::Itf::CommandsNumberOfAddresses::SFC_LOCK_CMD_NUMBER_OF_ADDRESSES; 216 } 217 } 218 } 219 } 220 else if (standard == CODECHAL_VP9) // VP9 Clear Decode 221 { 222 maxSize = 223 8 + 224 mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize + 225 cmd_t::HCP_PIPE_MODE_SELECT_CMD::byteSize + 226 cmd_t::HCP_SURFACE_STATE_CMD::byteSize * 4 + 227 cmd_t::HCP_PIPE_BUF_ADDR_STATE_CMD::byteSize + 228 cmd_t::HCP_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 229 cmd_t::HCP_VP9_SEGMENT_STATE_CMD::byteSize * 8 + 230 cmd_t::HCP_BSD_OBJECT_CMD::byteSize + 231 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize * 8; 232 233 patchListMaxSize = 234 PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD) + 235 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) + 236 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PIPE_MODE_SELECT_CMD) + 237 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_SURFACE_STATE_CMD) * 4 + 238 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PIPE_BUF_ADDR_STATE_CMD) + 239 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_IND_OBJ_BASE_ADDR_STATE_CMD) + 240 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_VP9_SEGMENT_STATE_CMD) * 8 + 241 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_BSD_OBJECT_CMD); 242 243 if (mode == CODECHAL_ENCODE_MODE_VP9) 244 { 245 maxSize += 246 cmd_t::HCP_VP9_PIC_STATE_CMD::byteSize + 247 mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize * 2 + 248 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize * 4 + 249 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_REGISTER_MEM_CMD::byteSize * 11 + 250 mhw::mi::xe2_lpm_base_next::Cmd::MI_COPY_MEM_MEM_CMD::byteSize * 4 + 251 mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_START_CMD::byteSize * 3 + 252 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize * 2 + // Slice level commands 253 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_MEM_CMD::byteSize * 2 + 254 cmd_t::HCP_PAK_INSERT_OBJECT_CMD::byteSize * 2 + 255 cmd_t::HCP_TILE_CODING_CMD::byteSize + 256 mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_START_CMD::byteSize + 257 mhw::mi::xe2_lpm_base_next::Cmd::MI_SEMAPHORE_WAIT_CMD::byteSize + // Use HW wait command for each VDBOX 258 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize * 3; // One is for reset and another one for set per VDBOX, one for wait 259 260 maxSize += 3 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize; // VD_CONTROL_STATE Hcp init + flush + vdenc init 261 262 patchListMaxSize += 263 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_VP9_PIC_STATE_CMD) + 264 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) * 2 + 265 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) * 4 + 266 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_REGISTER_MEM_CMD) * 11 + 267 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_COPY_MEM_MEM_CMD) * 4 + 268 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD) * 3 + 269 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) * 2 + 270 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PAK_INSERT_OBJECT_CMD) * 2 + 271 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_TILE_CODING_COMMAND) + 272 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD) + 273 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) * 2; 274 } 275 else 276 { 277 maxSize += cmd_t::HCP_VP9_PIC_STATE_CMD::byteSize; 278 279 // VD_CONTROL_STATE Hcp init and flush 280 maxSize += 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize; 281 282 patchListMaxSize += PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_VP9_PIC_STATE_CMD); 283 284 if (params->bSfcInUse) 285 { 286 maxSize += 287 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_LOCK_CMD::byteSize + 288 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 289 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_STATE_CMD::byteSize + 290 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_STATE_CMD::byteSize + 291 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize + 292 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize + 293 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_IEF_STATE_CMD::byteSize + 294 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_FRAME_START_CMD::byteSize; 295 } 296 297 if (par->bScalableMode) 298 { 299 // VD_CONTROL_STATE Hcp lock and unlock 300 maxSize += 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize; 301 302 maxSize += 303 cmd_t::HCP_TILE_CODING_CMD::byteSize + 304 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 305 mhw::mi::xe2_lpm_base_next::Cmd::MI_ATOMIC_CMD::byteSize * 4 + // used to reset semaphore in BEs 306 mhw::mi::xe2_lpm_base_next::Cmd::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize + // for streamout buffer writing over allocated size 307 mhw::mi::xe2_lpm_base_next::Cmd::MI_SEMAPHORE_WAIT_CMD::byteSize * 3 + // for FE & BE0, BEs sync 308 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize * 15 + // for placeholder cmds to resolve the hazard between BEs sync 309 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize + // for FE status set 310 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_IMM_CMD::byteSize * 3 + // for FE status set 311 mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize + // for command flush in partition level 312 mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_REGISTER_MEM_CMD::byteSize * 2 + // store the carry flag of reported size in FE 313 4 * sizeof(MHW_MI_ALU_PARAMS) + // 4 ALU commands needed for substract opertaion in FE 314 mhw::mi::xe2_lpm_base_next::Cmd::MI_MATH_CMD::byteSize + // 1 needed for FE status set 315 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set 316 mhw::mi::xe2_lpm_base_next::Cmd::MI_MATH_CMD::byteSize + // 1 needed for FE status set 317 mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set 318 319 patchListMaxSize += 320 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_TILE_CODING_COMMAND) + 321 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_ATOMIC_CMD) * 4 + 322 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_CONDITIONAL_BATCH_BUFFER_END_CMD) + 323 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_SEMAPHORE_WAIT_CMD) * 3 + 324 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) + 325 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) + 326 PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_REGISTER_MEM_CMD) * 2; 327 328 if (params->bSfcInUse) 329 { 330 maxSize += 331 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_LOCK_CMD::byteSize + 332 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 333 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_STATE_CMD::byteSize + 334 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_STATE_CMD::byteSize + 335 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize + 336 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize + 337 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_IEF_STATE_CMD::byteSize + 338 mhw::sfc::xe2_lpm_base_next::Cmd::SFC_FRAME_START_CMD::byteSize; 339 } 340 } 341 } 342 } 343 else 344 { 345 MHW_ASSERTMESSAGE("Unsupported standard."); 346 eStatus = MOS_STATUS_UNKNOWN; 347 } 348 349 *commandsSize = maxSize; 350 *patchListSize = patchListMaxSize; 351 352 return eStatus; 353 } 354 GetHcpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)355 MOS_STATUS GetHcpPrimitiveCommandSize( 356 uint32_t mode, 357 uint32_t *commandsSize, 358 uint32_t *patchListSize, 359 bool modeSpecific) 360 { 361 MOS_STATUS eStatus = MOS_STATUS_SUCCESS; 362 363 MHW_FUNCTION_ENTER; 364 365 uint32_t standard = CodecHal_GetStandardFromMode(mode); 366 uint32_t maxSize = 0; 367 uint32_t patchListMaxSize = 0; 368 369 if (standard == CODECHAL_HEVC) 370 { 371 if (mode == CODECHAL_ENCODE_MODE_HEVC) 372 { 373 maxSize = 374 2 * cmd_t::HCP_REF_IDX_STATE_CMD::byteSize + 375 2 * cmd_t::HCP_WEIGHTOFFSET_STATE_CMD::byteSize + 376 cmd_t::HCP_SLICE_STATE_CMD::byteSize + 377 cmd_t::HCP_PAK_INSERT_OBJECT_CMD::byteSize + 378 2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_START_CMD::byteSize + 379 cmd_t::HCP_TILE_CODING_CMD::byteSize; // one slice cannot be with more than one tile 380 381 patchListMaxSize = 382 2 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_REF_IDX_STATE_CMD) + 383 2 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_WEIGHTOFFSET_STATE_CMD) + 384 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_SLICE_STATE_CMD) + 385 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PAK_INSERT_OBJECT_CMD) + 386 2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD) + // One is for the PAK command and another one is for the BB when BRC and single task mode are on 387 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_TILE_CODING_COMMAND); // HCP_TILE_CODING_STATE command 388 } 389 else 390 { 391 maxSize = 392 2 * cmd_t::HCP_REF_IDX_STATE_CMD::byteSize + 393 2 * cmd_t::HCP_WEIGHTOFFSET_STATE_CMD::byteSize + 394 cmd_t::HCP_SLICE_STATE_CMD::byteSize + 395 2 * mhw::mi::xe2_lpm_base_next::Cmd::VD_CONTROL_STATE_CMD::byteSize + 396 cmd_t::HCP_TILE_CODING_CMD::byteSize + 397 cmd_t::HCP_PALETTE_INITIALIZER_STATE_CMD::byteSize + 398 cmd_t::HCP_BSD_OBJECT_CMD::byteSize + 399 mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_END_CMD::byteSize; 400 401 patchListMaxSize = 402 2 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_REF_IDX_STATE_CMD) + 403 2 * PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_WEIGHTOFFSET_STATE_CMD) + 404 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_SLICE_STATE_CMD) + 405 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_PALETTE_INITIALIZER_STATE_CMD) + 406 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_TILE_CODING_COMMAND) + 407 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_BSD_OBJECT_CMD); 408 } 409 } 410 else if (standard == CODECHAL_VP9) // VP9 Clear decode does not require primitive level commands. VP9 DRM does. 411 { 412 if (modeSpecific) // VP9 DRM 413 { 414 maxSize += 415 cmd_t::HCP_VP9_SEGMENT_STATE_CMD::byteSize * 8 + 416 cmd_t::HCP_VP9_PIC_STATE_CMD::byteSize + 417 cmd_t::HCP_BSD_OBJECT_CMD::byteSize + 418 mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_END_CMD::byteSize; 419 420 patchListMaxSize = 421 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_VP9_SEGMENT_STATE_CMD) * 8 + 422 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_VP9_PIC_STATE_CMD) + 423 PATCH_LIST_COMMAND(mhw::vdbox::hcp::Itf::HCP_BSD_OBJECT_CMD); 424 } 425 } 426 else 427 { 428 MHW_ASSERTMESSAGE("Unsupported standard."); 429 eStatus = MOS_STATUS_UNKNOWN; 430 } 431 432 *commandsSize = maxSize; 433 *patchListSize = patchListMaxSize; 434 435 return eStatus; 436 } 437 438 protected: 439 using base_t = hcp::Impl<cmd_t>; 440 BaseImpl(PMOS_INTERFACE osItf)441 BaseImpl(PMOS_INTERFACE osItf) : base_t(osItf){}; 442 _MHW_SETCMD_OVERRIDE_DECL(HCP_PIC_STATE)443 _MHW_SETCMD_OVERRIDE_DECL(HCP_PIC_STATE) 444 { 445 _MHW_SETCMD_CALLBASE(HCP_PIC_STATE); 446 447 #define DO_FIELDS() \ 448 DO_FIELD(DW36, Reserved1153, params.vdaqmEnable) 449 450 #include "mhw_hwcmd_process_cmdfields.h" 451 } 452 MEDIA_CLASS_DEFINE_END(mhw__vdbox__hcp__xe2_lpm_base__BaseImpl) 453 }; 454 } // namespace xe2_lpm_base 455 } // namespace hcp 456 } // namespace vdbox 457 } // namespace mhw 458 459 #endif // __MHW_VDBOX_HCP_IMPL_XE2_LPM_BASE_H__ 460