1 /* 2 * Copyright (c) 2021-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_hcp_itf.h 24 //! \brief MHW VDBOX HCP interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_HCP_ITF_H__ 29 #define __MHW_VDBOX_HCP_ITF_H__ 30 31 #include "mhw_itf.h" 32 #include "mhw_vdbox_hcp_cmdpar.h" 33 34 #define _HCP_CMD_DEF(DEF) \ 35 DEF(HCP_SURFACE_STATE); \ 36 DEF(HCP_PIC_STATE); \ 37 DEF(HCP_SLICE_STATE); \ 38 DEF(HCP_IND_OBJ_BASE_ADDR_STATE); \ 39 DEF(HCP_QM_STATE); \ 40 DEF(HCP_BSD_OBJECT); \ 41 DEF(HCP_TILE_STATE); \ 42 DEF(HCP_REF_IDX_STATE); \ 43 DEF(HCP_WEIGHTOFFSET_STATE); \ 44 DEF(HCP_PIPE_MODE_SELECT); \ 45 DEF(HCP_PIPE_BUF_ADDR_STATE); \ 46 DEF(HCP_FQM_STATE); \ 47 DEF(HCP_PAK_INSERT_OBJECT); \ 48 DEF(HCP_VP9_PIC_STATE); \ 49 DEF(HCP_VP9_SEGMENT_STATE); \ 50 DEF(HEVC_VP9_RDOQ_STATE); \ 51 DEF(HCP_TILE_CODING); \ 52 DEF(HCP_PALETTE_INITIALIZER_STATE) 53 54 namespace mhw 55 { 56 namespace vdbox 57 { 58 namespace hcp 59 { 60 enum HevcSliceType 61 { 62 hevcSliceB = 0, 63 hevcSliceP = 1, 64 hevcSliceI = 2 65 }; 66 67 class Itf 68 { 69 public: 70 enum CommandsNumberOfAddresses 71 { 72 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 73 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 74 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 75 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 76 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 77 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 4, // 4 DW for 2 address fields 78 MI_SEMAPHORE_WAIT_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address fields 79 MI_ATOMIC_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 80 81 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 82 83 HCP_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 84 HCP_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 85 HCP_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 45, // 45 address fields 86 HCP_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 11, // 22 DW for 11 address field 87 HCP_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 88 HCP_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 89 HCP_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 90 HCP_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 91 HCP_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 92 HCP_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 93 HCP_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 94 HCP_TILE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 95 HCP_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 96 HCP_VP9_SEGMENT_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 97 HCP_VP9_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 98 HCP_TILE_CODING_COMMAND_NUMBER_OF_ADDRESSES = 1, // 0 DW for address fields 99 HCP_PALETTE_INITIALIZER_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 100 101 VDENC_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 12, // 12 DW for 12 address fields 102 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields 103 }; 104 105 class ParSetting 106 { 107 public: 108 virtual ~ParSetting() = default; 109 110 _HCP_CMD_DEF(_MHW_SETPAR_DEF); 111 }; 112 113 virtual ~Itf() = default; 114 115 virtual MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) = 0; 116 117 virtual MOS_STATUS GetHcpBufSize(const HcpBufferSizePar &par, uint32_t &size) = 0; 118 119 virtual MOS_STATUS GetVP9BufSize(const HcpBufferSizePar &par, uint32_t &size) = 0; 120 121 virtual const HcpMmioRegisters *GetMmioRegisters(const MHW_VDBOX_NODE_IND index) const = 0; 122 123 virtual uint32_t GetEncCuRecordSize() = 0; 124 125 virtual uint32_t GetHcpPakObjSize() = 0; 126 127 virtual bool IsRowStoreCachingSupported() = 0; 128 129 virtual uint32_t GetPakHWTileSizeRecordSize() = 0; 130 131 virtual MOS_STATUS SetRowstoreCachingOffsets(const HcpVdboxRowStorePar &rowstoreParams) = 0; 132 133 virtual uint32_t GetHcpVp9PicStateCommandSize() = 0; 134 135 virtual uint32_t GetHcpVp9SegmentStateCommandSize() = 0; 136 137 virtual MOS_STATUS GetHcpStateCommandSize( 138 uint32_t mode, 139 uint32_t * commandsSize, 140 uint32_t * patchListSize, 141 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) = 0; 142 143 virtual MOS_STATUS GetHcpPrimitiveCommandSize( 144 uint32_t mode, 145 uint32_t *commandsSize, 146 uint32_t *patchListSize, 147 bool modeSpecific) = 0; 148 //! 149 //! \brief Get Hcp Cabac Error Flags Mask 150 //! 151 //! \return [out] uint32_t 152 //! Mask got. 153 //! GetHcpCabacErrorFlagsMask()154 virtual inline uint32_t GetHcpCabacErrorFlagsMask() 155 { 156 return m_hcpCabacErrorFlagsMask; 157 } 158 159 //! 160 //! \brief Judge if hevc sao row store caching enabled 161 //! 162 //! \return bool 163 //! true if enabled, else false 164 //! IsHevcSaoRowstoreCacheEnabled()165 inline bool IsHevcSaoRowstoreCacheEnabled() 166 { 167 return m_hevcSaoRowStoreCache.enabled ? true : false; 168 } 169 170 //! 171 //! \brief Judge if hevc df row store caching enabled 172 //! 173 //! \return bool 174 //! true if enabled, else false 175 //! IsHevcDfRowstoreCacheEnabled()176 inline bool IsHevcDfRowstoreCacheEnabled() 177 { 178 return m_hevcDfRowStoreCache.enabled ? true : false; 179 } 180 181 //! 182 //! \brief Judge if hevc dat store caching enabled 183 //! 184 //! \return bool 185 //! true if enabled, else false 186 //! IsHevcDatRowstoreCacheEnabled()187 inline bool IsHevcDatRowstoreCacheEnabled() 188 { 189 return m_hevcDatRowStoreCache.enabled ? true : false; 190 } 191 192 //! 193 //! \brief Determines if the slice is I slice 194 //! \param [in] sliceType 195 //! slice type 196 //! \return bool 197 //! True if it's I slice, otherwise return false 198 //! IsHevcISlice(uint8_t sliceType)199 inline bool IsHevcISlice(uint8_t sliceType) 200 { 201 return (sliceType < MHW_ARRAY_SIZE(m_hevcBsdSliceType)) ? (m_hevcBsdSliceType[sliceType] == hevcSliceI) : false; 202 } 203 204 //! 205 //! \brief Determines if the slice is P slice 206 //! \param [in] sliceType 207 //! slice type 208 //! \return bool 209 //! True if it's P slice, otherwise return false 210 //! IsHevcPSlice(uint8_t sliceType)211 inline bool IsHevcPSlice(uint8_t sliceType) 212 { 213 return (sliceType < MHW_ARRAY_SIZE(m_hevcBsdSliceType)) ? (m_hevcBsdSliceType[sliceType] == hevcSliceP) : false; 214 } 215 216 //! 217 //! \brief Determines if the slice is B slice 218 //! \param [in] sliceType 219 //! slice type 220 //! \return bool 221 //! True if it's B slice, otherwise return false 222 //! IsHevcBSlice(uint8_t sliceType)223 inline bool IsHevcBSlice(uint8_t sliceType) 224 { 225 return (sliceType < MHW_ARRAY_SIZE(m_hevcBsdSliceType)) ? (m_hevcBsdSliceType[sliceType] == hevcSliceB) : false; 226 } 227 IsVp9DfRowstoreCacheEnabled()228 bool IsVp9DfRowstoreCacheEnabled() 229 { 230 return m_vp9DfRowStoreCache.enabled ? true : false; 231 } 232 233 enum HevcSliceType 234 { 235 hevcSliceB = 0, 236 hevcSliceP = 1, 237 hevcSliceI = 2 238 }; 239 GetVp9BufferSize(HCP_INTERNAL_BUFFER_TYPE bufferType,HcpBufferSizePar * hcpBufSizeParam)240 MOS_STATUS GetVp9BufferSize( 241 HCP_INTERNAL_BUFFER_TYPE bufferType, 242 HcpBufferSizePar *hcpBufSizeParam) 243 { 244 MOS_STATUS eStatus = MOS_STATUS_SUCCESS; 245 246 MHW_FUNCTION_ENTER; 247 248 MHW_MI_CHK_NULL(hcpBufSizeParam); 249 250 uint32_t bufferSize = 0; 251 uint32_t dblkRsbSizeMultiplier = 0; 252 uint32_t dblkCsbSizeMultiplier = 0; 253 uint32_t intraPredMultiplier = 0; 254 255 uint8_t maxBitDepth = hcpBufSizeParam->ucMaxBitDepth; 256 uint32_t widthInSb = hcpBufSizeParam->dwPicWidth; 257 uint32_t heightInSb = hcpBufSizeParam->dwPicHeight; 258 uint32_t widthInMinCb = widthInSb * 64 / 8; //using smallest cb to get max width 259 uint32_t heightInMinCb = heightInSb * 64 / 8; 260 HCP_CHROMA_FORMAT_IDC chromaFormat = (HCP_CHROMA_FORMAT_IDC)hcpBufSizeParam->ucChromaFormat; 261 uint32_t maxFrameSize = hcpBufSizeParam->dwMaxFrameSize; 262 263 if (chromaFormat == HCP_CHROMA_FORMAT_YUV420) 264 { 265 dblkRsbSizeMultiplier = (maxBitDepth > 8) ? 36 : 18; 266 dblkCsbSizeMultiplier = (maxBitDepth > 8) ? 34 : 17; 267 intraPredMultiplier = (maxBitDepth > 8) ? 4 : 2; 268 } 269 else if (chromaFormat == HCP_CHROMA_FORMAT_YUV444) 270 { 271 dblkRsbSizeMultiplier = (maxBitDepth > 8) ? 54 : 27; 272 dblkCsbSizeMultiplier = (maxBitDepth > 8) ? 50 : 25; 273 intraPredMultiplier = (maxBitDepth > 8) ? 6 : 3; 274 } 275 else 276 { 277 eStatus = MOS_STATUS_INVALID_PARAMETER; 278 MHW_ASSERTMESSAGE("Format not supported."); 279 return eStatus; 280 } 281 282 switch (bufferType) 283 { 284 case HCP_INTERNAL_BUFFER_TYPE::DBLK_LINE: 285 case HCP_INTERNAL_BUFFER_TYPE::DBLK_TILE_LINE: 286 bufferSize = widthInSb * dblkRsbSizeMultiplier * MHW_CACHELINE_SIZE; 287 break; 288 case HCP_INTERNAL_BUFFER_TYPE::DBLK_TILE_COL: 289 bufferSize = heightInSb * dblkCsbSizeMultiplier * MHW_CACHELINE_SIZE; 290 break; 291 case HCP_INTERNAL_BUFFER_TYPE::META_LINE: 292 case HCP_INTERNAL_BUFFER_TYPE::META_TILE_LINE: 293 bufferSize = widthInSb * 5 * MHW_CACHELINE_SIZE; 294 break; 295 case HCP_INTERNAL_BUFFER_TYPE::META_TILE_COL: 296 bufferSize = heightInSb * 5 * MHW_CACHELINE_SIZE; 297 break; 298 case HCP_INTERNAL_BUFFER_TYPE::CURR_MV_TEMPORAL: 299 case HCP_INTERNAL_BUFFER_TYPE::COLL_MV_TEMPORAL: 300 bufferSize = widthInSb * heightInSb * 9 * MHW_CACHELINE_SIZE; 301 break; 302 case HCP_INTERNAL_BUFFER_TYPE::SEGMENT_ID: 303 bufferSize = widthInSb * heightInSb * MHW_CACHELINE_SIZE; 304 break; 305 case HCP_INTERNAL_BUFFER_TYPE::HVD_LINE: 306 case HCP_INTERNAL_BUFFER_TYPE::HVD_TILE: 307 bufferSize = widthInSb * MHW_CACHELINE_SIZE; 308 break; 309 //scalable mode specific buffers 310 case HCP_INTERNAL_BUFFER_TYPE::INTRA_PRED_UP_RIGHT_COL: 311 case HCP_INTERNAL_BUFFER_TYPE::INTRA_PRED_LFT_RECON_COL: 312 bufferSize = intraPredMultiplier * heightInSb * MHW_CACHELINE_SIZE; 313 break; 314 case HCP_INTERNAL_BUFFER_TYPE::CABAC_STREAMOUT: 315 //From sas, cabac stream out buffer size = 316 //(#LCU) in picture * (Worst case LCU_CU_TU_info) + 1 byte aligned per LCU + Bitstream Size * 3 317 if ((chromaFormat == HCP_CHROMA_FORMAT_YUV420) && (maxBitDepth == 8)) 318 { 319 bufferSize = widthInMinCb * heightInMinCb * m_hcpWorstCaseCuTuInfo + widthInMinCb * heightInMinCb + maxFrameSize * 3; 320 } 321 else 322 { 323 bufferSize = widthInMinCb * heightInMinCb * m_hcpWorstCaseCuTuInfoRext + widthInMinCb * heightInMinCb + maxFrameSize * 3; 324 } 325 bufferSize = MOS_ALIGN_CEIL(bufferSize, MHW_CACHELINE_SIZE); 326 break; 327 default: 328 eStatus = MOS_STATUS_INVALID_PARAMETER; 329 break; 330 } 331 332 hcpBufSizeParam->dwBufferSize = bufferSize; 333 334 return eStatus; 335 } 336 337 protected: 338 RowStoreCache m_hevcDatRowStoreCache = {}; 339 RowStoreCache m_hevcDfRowStoreCache = {}; 340 RowStoreCache m_hevcSaoRowStoreCache = {}; 341 RowStoreCache m_hevcHSaoRowStoreCache = {}; 342 RowStoreCache m_vp9HvdRowStoreCache = {}; 343 RowStoreCache m_vp9DfRowStoreCache = {}; 344 RowStoreCache m_vp9DatRowStoreCache = {}; 345 346 static const uint32_t m_hcpCabacErrorFlagsMask = 0x0879; //<! Hcp CABAC error flags mask 347 348 static const HevcSliceType m_hevcBsdSliceType[3]; //!< HEVC Slice Types for Long Format 349 350 static const uint32_t m_hcpWorstCaseCuTuInfo = 4 * MHW_CACHELINE_SIZE; 351 352 static const uint32_t m_hcpWorstCaseCuTuInfoRext = 6 * MHW_CACHELINE_SIZE; 353 354 _HCP_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 355 MEDIA_CLASS_DEFINE_END(mhw__vdbox__hcp__Itf) 356 }; 357 } // namespace hcp 358 } // namespace vdbox 359 } // namespace mhw 360 361 #endif // __MHW_VDBOX_AVP_ITF_H__ 362