1 /* 2 # Copyright (c) 2024, Intel Corporation 3 # 4 # Permission is hereby granted, free of charge, to any person obtaining a 5 # copy of this software and associated documentation files (the "Software"), 6 # to deal in the Software without restriction, including without limitation 7 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 # and/or sell copies of the Software, and to permit persons to whom the 9 # Software is furnished to do so, subject to the following conditions: 10 # 11 # The above copyright notice and this permission notice shall be included 12 # in all copies or substantial portions of the Software. 13 # 14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 # OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_huc_hwcmd_xe2_lpm.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g12_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 29 // DO NOT EDIT 30 31 #ifndef __MHW_VDBOX_HUC_HWCMD_XE2_LPM_H__ 32 #define __MHW_VDBOX_HUC_HWCMD_XE2_LPM_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include "mhw_hwcmd.h" 38 #include <cstdint> 39 #include <cstddef> 40 #include "media_class_trace.h" 41 42 namespace mhw 43 { 44 namespace vdbox 45 { 46 namespace huc 47 { 48 namespace xe2_lpm_base 49 { 50 namespace xe2_lpm 51 { 52 class Cmd 53 { 54 public: GetOpLength(uint32_t uiLength)55 static uint32_t GetOpLength(uint32_t uiLength) 56 { 57 return __CODEGEN_OP_LENGTH(uiLength); 58 } 59 60 //! 61 //! \brief MEMORYADDRESSATTRIBUTES 62 //! \details 63 //! This field controls the priority of arbitration used in the GAC/GAM 64 //! pipeline for this surface. It defines the attributes for VDBOX addresses 65 //! on BDW+. 66 //! 67 struct MEMORYADDRESSATTRIBUTES_CMD 68 { 69 union 70 { 71 struct 72 { 73 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 74 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< Base Address - Index to Memory Object Control State (MOCS) Tables 75 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Base Address - Arbitration Priority Control 76 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Base Address - Memory Compression Enable 77 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10); //!< COMPRESSION_TYPE 78 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 79 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 80 uint32_t BaseAddressTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< BASE_ADDRESS_TILED_RESOURCE_MODE 81 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 82 }; 83 uint32_t Value; 84 } DW0; 85 86 //! \name Local enumerations 87 88 //! \brief COMPRESSION_TYPE 89 //! \details 90 //! Indicates if buffer is render/media compressed. 91 enum COMPRESSION_TYPE 92 { 93 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 94 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< No additional details 95 }; 96 97 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 98 //! \details 99 //! This field controls if the Row Store is going to store inside Media 100 //! Cache (rowstore cache) or to LLC. 101 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 102 { 103 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 104 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 105 }; 106 107 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 108 //! \details 109 //! For Media Surfaces: This field specifies the tiled resource mode. 110 enum BASE_ADDRESS_TILED_RESOURCE_MODE 111 { 112 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 113 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 114 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 115 }; 116 117 //! \name Initializations 118 119 //! \brief Explicit member initialization function MEMORYADDRESSATTRIBUTES_CMDMEMORYADDRESSATTRIBUTES_CMD120 MEMORYADDRESSATTRIBUTES_CMD() 121 { 122 DW0.Value = 0x00000000; 123 } 124 125 static const size_t dwSize = 1; 126 static const size_t byteSize = 4; 127 }; 128 129 //! 130 //! \brief SPLITBASEADDRESS64BYTEALIGNED 131 //! \details 132 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 133 //! address. 134 //! 135 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 136 { 137 union 138 { 139 struct 140 { 141 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 142 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD(6, 47); //!< GraphicsAddress47-6 143 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63); //!< Reserved 144 }; 145 uint32_t Value[2]; 146 } DW0_1; 147 148 //! \name Local enumerations 149 150 //! \name Initializations 151 152 //! \brief Explicit member initialization function SPLITBASEADDRESS64BYTEALIGNED_CMDSPLITBASEADDRESS64BYTEALIGNED_CMD153 SPLITBASEADDRESS64BYTEALIGNED_CMD() 154 { 155 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 156 } 157 158 static const size_t dwSize = 2; 159 static const size_t byteSize = 8; 160 }; 161 162 //! 163 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 164 //! \details 165 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 166 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 167 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 168 //! 169 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 170 { 171 union 172 { 173 struct 174 { 175 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 176 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47); //!< GraphicsAddress47-12 177 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63); //!< Reserved 178 }; 179 uint32_t Value[2]; 180 } DW0_1; 181 182 //! \name Local enumerations 183 184 //! \name Initializations 185 186 //! \brief Explicit member initialization function SPLITBASEADDRESS4KBYTEALIGNED_CMDSPLITBASEADDRESS4KBYTEALIGNED_CMD187 SPLITBASEADDRESS4KBYTEALIGNED_CMD() 188 { 189 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 190 } 191 192 static const size_t dwSize = 2; 193 static const size_t byteSize = 8; 194 }; 195 196 //! 197 //! \brief HUC_PIPE_MODE_SELECT 198 //! \details 199 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 200 //! Commands. Each HUC command has assigned a media instruction command as 201 //! defined in DWord 0, BitField 22:16. 202 //! 203 //! The HUC_PIPE_MODE_SELECT command is responsible for general pipeline 204 //! level configuration that would normally be set once for a single stream 205 //! decode and would not be modified on a frame workload basis. 206 //! 207 struct HUC_PIPE_MODE_SELECT_CMD 208 { 209 union 210 { 211 struct 212 { 213 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 214 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 215 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 216 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 217 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 218 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 219 }; 220 uint32_t Value; 221 } DW0; 222 union 223 { 224 struct 225 { 226 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 3); //!< Reserved 227 uint32_t IndirectStreamOutEnable : __CODEGEN_BITFIELD(4, 4); //!< INDIRECT_STREAM_OUT_ENABLE 228 uint32_t Reserved37 : __CODEGEN_BITFIELD(5, 31); //!< Reserved 229 }; 230 uint32_t Value; 231 } DW1; 232 union 233 { 234 struct 235 { 236 uint32_t MediaSoftResetCounterPer1000Clocks; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 237 }; 238 uint32_t Value; 239 } DW2; 240 241 //! \name Local enumerations 242 243 enum MEDIA_INSTRUCTION_COMMAND 244 { 245 MEDIA_INSTRUCTION_COMMAND_HUCPIPEMODESELECT = 0, //!< No additional details 246 }; 247 248 //! \brief MEDIA_INSTRUCTION_OPCODE 249 //! \details 250 //! Codec/Engine Name = HUP = Bh 251 enum MEDIA_INSTRUCTION_OPCODE 252 { 253 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 254 }; 255 256 enum PIPELINE_TYPE 257 { 258 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 259 }; 260 261 enum COMMAND_TYPE 262 { 263 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 264 }; 265 266 //! \brief INDIRECT_STREAM_OUT_ENABLE 267 //! \details 268 //! Enables the bitstream to be written out to memory immediately following 269 //! the output of the bit stream. The memory buffer is addressed through 270 //! the HuC Indirect Stream Out ObjectBase Address. 271 enum INDIRECT_STREAM_OUT_ENABLE 272 { 273 INDIRECT_STREAM_OUT_ENABLE_DISABLEINDIRECTSTREAMOUT = 0, //!< No additional details 274 INDIRECT_STREAM_OUT_ENABLE_ENABLEINDIRECTSTREAMOUT = 1, //!< No additional details 275 }; 276 277 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 278 //! \details 279 //! In decoder modes, this counter value specifies the number of clocks (per 280 //! 1000) of GAC inactivity 281 //! before a media soft-reset is applied to the HCP and HuC. If counter 282 //! value is set to 0, the media 283 //! soft-reset feature is disabled and no reset will occur. 284 //! In encoder modes, this counter must be set to 0 to disable media 285 //! soft reset. This feature is not 286 //! supported for the encoder. 287 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 288 { 289 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 290 }; 291 292 //! \name Initializations 293 294 //! \brief Explicit member initialization function HUC_PIPE_MODE_SELECT_CMDHUC_PIPE_MODE_SELECT_CMD295 HUC_PIPE_MODE_SELECT_CMD() 296 { 297 DW0.Value = 0x75800001; 298 299 DW1.Value = 0x00000000; 300 301 DW2.Value = 0x00000000; 302 } 303 304 static const size_t dwSize = 3; 305 static const size_t byteSize = 12; 306 }; 307 308 //! 309 //! \brief HUC_IMEM_STATE 310 //! \details 311 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 312 //! Commands. Each HUC command has assigned a media instruction command as 313 //! defined in DWord 0, BitField 22:16. 314 //! 315 //! The HUC_IMEM_STATE command is used to fetch the HUC firmware from the 316 //! WOPCM region and load it into the HUC 96KB L2 storage RAM. The 317 //! HUC_IMEM_STATE specifies the firmware's offset in WOPCM which is a cache 318 //! line aligned 32-bit offset address. The firmware, code and data segment 319 //! size should always be less than 96KB. If its greater than 96KB then the 320 //! firmware should be broken into smaller functions so that there is no 321 //! firmware straddling case. 322 //! When the HUC_IMEM_STATE command is received, the hardware confirms that 323 //! the code has been successfully authenticated by checking the VCR 324 //! provided authentication successful signal. If this signal is asserted, 325 //! the firmware is loaded by the HUC DMA into the 96KB L2 storage RAM. Once 326 //! the firmware is loaded, the VALID IMEM LOADED bit in the HUC_STATUS2 327 //! register is asserted high in the. If the authentication signal is not 328 //! asserted, the DMA aborts the HUC_IMEM_STATE command, the firmware is not 329 //! loaded, and the VALID IMEM LOADED bit remains low. 330 //! 331 struct HUC_IMEM_STATE_CMD 332 { 333 union 334 { 335 struct 336 { 337 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 338 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 339 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 340 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 341 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 342 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 343 }; 344 uint32_t Value; 345 } DW0; 346 union 347 { 348 struct 349 { 350 uint32_t Reserved32; //!< Reserved 351 }; 352 uint32_t Value; 353 } DW1; 354 union 355 { 356 struct 357 { 358 uint32_t Reserved64; //!< Reserved 359 }; 360 uint32_t Value; 361 } DW2; 362 union 363 { 364 struct 365 { 366 uint32_t Reserved96; //!< Reserved 367 }; 368 uint32_t Value; 369 } DW3; 370 union 371 { 372 struct 373 { 374 uint32_t HucFirmwareDescriptor : __CODEGEN_BITFIELD(0, 7); //!< HUC_FIRMWARE_DESCRIPTOR 375 uint32_t Reserved136 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 376 }; 377 uint32_t Value; 378 } DW4; 379 380 //! \name Local enumerations 381 382 enum MEDIA_INSTRUCTION_COMMAND 383 { 384 MEDIA_INSTRUCTION_COMMAND_HUCIMEMSTATE = 1, //!< No additional details 385 }; 386 387 //! \brief MEDIA_INSTRUCTION_OPCODE 388 //! \details 389 //! Codec/Engine Name = HUC = Bh 390 enum MEDIA_INSTRUCTION_OPCODE 391 { 392 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 393 }; 394 395 enum PIPELINE_TYPE 396 { 397 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 398 }; 399 400 enum COMMAND_TYPE 401 { 402 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 403 }; 404 405 //! \brief HUC_FIRMWARE_DESCRIPTOR 406 //! \details 407 //! This field specifies 1 of 255 firmware descriptors which describe 408 //! which firmware is be loaded in the L2 storage RAM. If the firmware 409 //! descriptor is set to zero, the HUC will not load the firmware. 410 enum HUC_FIRMWARE_DESCRIPTOR 411 { 412 HUC_FIRMWARE_DESCRIPTOR_UNNAMED0 = 0, //!< Illegal 413 }; 414 415 //! \name Initializations 416 417 //! \brief Explicit member initialization function HUC_IMEM_STATE_CMDHUC_IMEM_STATE_CMD418 HUC_IMEM_STATE_CMD() 419 { 420 DW0.Value = 0x75810003; 421 422 DW1.Value = 0x00000000; 423 424 DW2.Value = 0x00000000; 425 426 DW3.Value = 0x00000000; 427 428 DW4.Value = 0x00000000; 429 } 430 431 static const size_t dwSize = 5; 432 static const size_t byteSize = 20; 433 }; 434 435 //! 436 //! \brief HUC_DMEM_STATE 437 //! \details 438 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 439 //! Commands. Each HUC command has assigned a media instruction command as 440 //! defined in DWord 0, BitField 22:16. 441 //! 442 //! The HUC_DMEM_STATE command is used to fetch the HUC data from the 443 //! graphics memory and load it into the HUC 96KB L2 storage RAM. The 444 //! HUC_DMEM_STATE specifies the data source base address in graphics 445 //! memory. 446 //! 447 //! When the HUC_DMEM_STATE command is received, the data is loaded by the 448 //! HUC DMA into the 96KB L2 storage RAM at the location provided in the 449 //! HUC_DMEM_STATE command. This command also specifies the length of the 450 //! data, which is specified in bytes but must be in increments of 64 byte 451 //! cache lines. 452 //! 453 struct HUC_DMEM_STATE_CMD 454 { 455 union 456 { 457 struct 458 { 459 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 460 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 461 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 462 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 463 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 464 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 465 }; 466 uint32_t Value; 467 } DW0; 468 SPLITBASEADDRESS64BYTEALIGNED_CMD HucDataSourceBaseAddress; //!< DW1..2, HUC Data Source - Base Address 469 MEMORYADDRESSATTRIBUTES_CMD HucDataSourceAttributes; //!< DW3, HUC Data Source - Attributes 470 union 471 { 472 struct 473 { 474 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 475 uint32_t HucDataDestinationBaseAddress : __CODEGEN_BITFIELD(6, 16); //!< HUC Data Destination Base Address 476 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 477 }; 478 uint32_t Value; 479 } DW4; 480 union 481 { 482 struct 483 { 484 uint32_t Reserved160 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 485 uint32_t HucDataLength : __CODEGEN_BITFIELD(6, 16); //!< HUC Data Length 486 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 487 }; 488 uint32_t Value; 489 } DW5; 490 491 //! \name Local enumerations 492 493 enum MEDIA_INSTRUCTION_COMMAND 494 { 495 MEDIA_INSTRUCTION_COMMAND_HUCDMEMSTATE = 2, //!< No additional details 496 }; 497 498 //! \brief MEDIA_INSTRUCTION_OPCODE 499 //! \details 500 //! Codec/Engine Name = HUC = Bh 501 enum MEDIA_INSTRUCTION_OPCODE 502 { 503 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 504 }; 505 506 enum PIPELINE_TYPE 507 { 508 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 509 }; 510 511 enum COMMAND_TYPE 512 { 513 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 514 }; 515 516 //! \name Initializations 517 518 //! \brief Explicit member initialization function HUC_DMEM_STATE_CMDHUC_DMEM_STATE_CMD519 HUC_DMEM_STATE_CMD() 520 { 521 DW0.Value = 0x75820004; 522 523 HucDataSourceAttributes.DW0.Value = 0x00000000; 524 525 DW4.Value = 0x00000000; 526 527 DW5.Value = 0x00000000; 528 } 529 530 static const size_t dwSize = 6; 531 static const size_t byteSize = 24; 532 }; 533 534 //! 535 //! \brief HUC_CFG_STATE 536 //! \details 537 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 538 //! Commands. Each HUC command has assigned a media instruction command as 539 //! defined in DWord 0, BitField 22:16. 540 //! 541 //! The HUC_CFG_STATE command is used to force the P24C (MinuteIA) into a 542 //! reset condition as well as forcing it out of a reset condition. This 543 //! command is not normally required since the hardware will handle placing 544 //! the P24C into a reset condition and releasing it from reset, but there 545 //! may be conditions that require a forced reset. 546 //! 547 struct HUC_CFG_STATE_CMD 548 { 549 union 550 { 551 struct 552 { 553 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 554 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 555 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 556 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 557 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 558 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 559 }; 560 uint32_t Value; 561 } DW0; 562 union 563 { 564 struct 565 { 566 uint32_t P24CMinuteia : __CODEGEN_BITFIELD(0, 0); //!< P24C_MINUTEIA 567 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 568 }; 569 uint32_t Value; 570 } DW1; 571 572 //! \name Local enumerations 573 574 enum MEDIA_INSTRUCTION_COMMAND 575 { 576 MEDIA_INSTRUCTION_COMMAND_HUCCFGSTATE = 3, //!< No additional details 577 }; 578 579 //! \brief MEDIA_INSTRUCTION_OPCODE 580 //! \details 581 //! Codec/Engine Name = HUC = Bh 582 enum MEDIA_INSTRUCTION_OPCODE 583 { 584 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 585 }; 586 587 enum PIPELINE_TYPE 588 { 589 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 590 }; 591 592 enum COMMAND_TYPE 593 { 594 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 595 }; 596 597 enum P24C_MINUTEIA 598 { 599 P24C_MINUTEIA_NORMALOPERATION = 0, //!< No reset. 600 P24C_MINUTEIA_FORCERESET = 1, //!< No additional details 601 }; 602 603 //! \name Initializations 604 605 //! \brief Explicit member initialization function HUC_CFG_STATE_CMDHUC_CFG_STATE_CMD606 HUC_CFG_STATE_CMD() 607 { 608 DW0.Value = 0x75830000; 609 610 DW1.Value = 0x00000000; 611 } 612 613 static const size_t dwSize = 2; 614 static const size_t byteSize = 8; 615 }; 616 617 //! 618 //! \brief HUC_VIRTUAL_ADDR_REGION 619 //! \details 620 //! 621 //! 622 struct HUC_VIRTUAL_ADDR_REGION_CMD 623 { 624 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucSurfaceBaseAddressVirtualaddrregion015; //!< DW0..2, HUC Surface Base Address (VirtualAddrRegion[0-15]) 625 MEMORYADDRESSATTRIBUTES_CMD HucSurfaceVirtualaddrregion015; //!< DW0..2, HUC Surface (VirtualAddrRegion[0-15]) 626 627 //! \name Local enumerations 628 629 //! \name Initializations 630 631 //! \brief Explicit member initialization function HUC_VIRTUAL_ADDR_REGION_CMDHUC_VIRTUAL_ADDR_REGION_CMD632 HUC_VIRTUAL_ADDR_REGION_CMD() 633 { 634 HucSurfaceVirtualaddrregion015.DW0.Value = 0x00000000; 635 } 636 637 static const size_t dwSize = 3; 638 static const size_t byteSize = 12; 639 }; 640 641 //! 642 //! \brief HUC_VIRTUAL_ADDR_STATE 643 //! \details 644 //! HUC is selected with the Media Instruction Opcode "Bh" for all HUC 645 //! Commands. Each HUC command has assigned a media instruction command as 646 //! defined in DWord 0, BitField 22:16. 647 //! 648 //! The HUC_VIRTUAL_ADDR_STATE command is used to define the 48-bit HUC 649 //! Surface Base Address and HUC Surface for each region. 650 //! 651 struct HUC_VIRTUAL_ADDR_STATE_CMD 652 { 653 union 654 { 655 struct 656 { 657 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 658 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 659 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 660 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 661 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 662 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 663 }; 664 uint32_t Value; 665 } DW0; 666 HUC_VIRTUAL_ADDR_REGION_CMD HucVirtualAddressRegion[16]; //!< DW1..48, Huc Virtual Address Region 667 668 //! \name Local enumerations 669 670 enum MEDIA_INSTRUCTION_COMMAND 671 { 672 MEDIA_INSTRUCTION_COMMAND_HUCVIRTUALADDRSTATE = 4, //!< No additional details 673 }; 674 675 //! \brief MEDIA_INSTRUCTION_OPCODE 676 //! \details 677 //! Codec/Engine Name = HUC = Bh 678 enum MEDIA_INSTRUCTION_OPCODE 679 { 680 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 681 }; 682 683 enum PIPELINE_TYPE 684 { 685 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 686 }; 687 688 enum COMMAND_TYPE 689 { 690 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 691 }; 692 693 //! \name Initializations 694 695 //! \brief Explicit member initialization function HUC_VIRTUAL_ADDR_STATE_CMDHUC_VIRTUAL_ADDR_STATE_CMD696 HUC_VIRTUAL_ADDR_STATE_CMD() 697 { 698 DW0.Value = 0x7584002f; 699 } 700 701 static const size_t dwSize = 49; 702 static const size_t byteSize = 196; 703 }; 704 705 //! 706 //! \brief HUC_IND_OBJ_BASE_ADDR_STATE 707 //! \details 708 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 709 //! Commands. Each HUC command has assigned a media instruction command as 710 //! defined in DWord 0, BitField 22:16. 711 //! 712 //! The HUC_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 713 //! object base address of the stream in graphics memory. This is a frame 714 //! level command. 715 //! 716 struct HUC_IND_OBJ_BASE_ADDR_STATE_CMD 717 { 718 union 719 { 720 struct 721 { 722 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 723 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 724 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 725 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 726 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 727 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 728 }; 729 uint32_t Value; 730 } DW0; 731 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamInObjectbaseAddress; //!< DW1..2, HUC Indirect Stream In ObjectBase Address 732 MEMORYADDRESSATTRIBUTES_CMD HucIndirectStreamInObjectbaseAttributes; //!< DW3, HUC Indirect Stream In ObjectBase Attributes 733 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamInObjectaccessUpperBound; //!< DW4..5, HUC Indirect Stream In ObjectAccess Upper Bound 734 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamOutObjectbaseAddress; //!< DW6..7, HUC Indirect Stream Out ObjectBase Address 735 MEMORYADDRESSATTRIBUTES_CMD HucIndirectStreamOutObjectbaseAttributes; //!< DW8, HUC Indirect Stream Out ObjectBase Attributes 736 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamOutObjectaccessUpperBound; //!< DW9..10, HUC Indirect Stream Out ObjectAccess Upper Bound 737 738 //! \name Local enumerations 739 740 enum MEDIA_INSTRUCTION_COMMAND 741 { 742 MEDIA_INSTRUCTION_COMMAND_HUCINDOBJBASEADDRSTATE = 5, //!< No additional details 743 }; 744 745 //! \brief MEDIA_INSTRUCTION_OPCODE 746 //! \details 747 //! Codec/Engine Name = HUC = Bh 748 enum MEDIA_INSTRUCTION_OPCODE 749 { 750 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 751 }; 752 753 enum PIPELINE_TYPE 754 { 755 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 756 }; 757 758 enum COMMAND_TYPE 759 { 760 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 761 }; 762 763 //! \name Initializations 764 765 //! \brief Explicit member initialization function HUC_IND_OBJ_BASE_ADDR_STATE_CMDHUC_IND_OBJ_BASE_ADDR_STATE_CMD766 HUC_IND_OBJ_BASE_ADDR_STATE_CMD() 767 { 768 DW0.Value = 0x75850009; 769 770 HucIndirectStreamInObjectbaseAttributes.DW0.Value = 0x00000000; 771 772 HucIndirectStreamOutObjectbaseAttributes.DW0.Value = 0x00000000; 773 } 774 775 static const size_t dwSize = 11; 776 static const size_t byteSize = 44; 777 }; 778 779 //! 780 //! \brief HUC_STREAM_OBJECT 781 //! \details 782 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 783 //! Commands. Each HUC command has assigned a media instruction command as 784 //! defined in DWord 0, BitField 22:16. 785 //! 786 //! The HUC_STREAM_OBJECT command is used to define the bit stream address 787 //! offset to the Stream Indirect Object base Address and the length of the 788 //! bit stream. The bitstream buffer the HUC operates upon is specified 789 //! through indirect addressing. 790 //! 791 struct HUC_STREAM_OBJECT_CMD 792 { 793 union 794 { 795 struct 796 { 797 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 798 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 799 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 800 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 801 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 802 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 803 }; 804 uint32_t Value; 805 } DW0; 806 union 807 { 808 struct 809 { 810 uint32_t IndirectStreamInDataLength; //!< Indirect Stream In Data Length 811 }; 812 uint32_t Value; 813 } DW1; 814 union 815 { 816 struct 817 { 818 uint32_t IndirectStreamInStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Stream In Start Address 819 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 30); //!< Reserved 820 uint32_t HucProcessing : __CODEGEN_BITFIELD(31, 31); //!< HUC_PROCESSING 821 }; 822 uint32_t Value; 823 } DW2; 824 union 825 { 826 struct 827 { 828 uint32_t IndirectStreamOutStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Stream Out Start Address 829 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 830 }; 831 uint32_t Value; 832 } DW3; 833 union 834 { 835 struct 836 { 837 uint32_t StartCodeByte0 : __CODEGEN_BITFIELD(0, 7); //!< Start Code Byte [0] 838 uint32_t StartCodeByte1 : __CODEGEN_BITFIELD(8, 15); //!< Start Code Byte [1] 839 uint32_t StartCodeByte2 : __CODEGEN_BITFIELD(16, 23); //!< Start Code Byte [2] 840 uint32_t StartCodeSearchEngine : __CODEGEN_BITFIELD(24, 24); //!< START_CODE_SEARCH_ENGINE 841 uint32_t EmulationPreventionByteRemoval : __CODEGEN_BITFIELD(25, 25); //!< EMULATION_PREVENTION_BYTE_REMOVAL 842 uint32_t StreamOut : __CODEGEN_BITFIELD(26, 26); //!< STREAM_OUT 843 uint32_t Drmlengthmode : __CODEGEN_BITFIELD(27, 28); //!< DRMLENGTHMODE 844 uint32_t HucBitstreamEnable : __CODEGEN_BITFIELD(29, 29); //!< HUC_BITSTREAM_ENABLE 845 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 846 }; 847 uint32_t Value; 848 } DW4; 849 850 //! \name Local enumerations 851 852 enum MEDIA_INSTRUCTION_COMMAND 853 { 854 MEDIA_INSTRUCTION_COMMAND_HUCSTREAMOBJECT = 32, //!< No additional details 855 }; 856 857 //! \brief MEDIA_INSTRUCTION_OPCODE 858 //! \details 859 //! Codec/Engine Name = HUC = Bh 860 enum MEDIA_INSTRUCTION_OPCODE 861 { 862 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 863 }; 864 865 enum PIPELINE_TYPE 866 { 867 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 868 }; 869 870 enum COMMAND_TYPE 871 { 872 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 873 }; 874 875 //! \brief HUC_PROCESSING 876 //! \details 877 //! Disables the HEVC Decoder CABAC engine to prevent it from starting 878 //! while the HuC is processing. Must be set to "1" for HUC processing so 879 //! that the stream is directed to the HuC and not the CABAC engine. 880 enum HUC_PROCESSING 881 { 882 HUC_PROCESSING_DISABLE = 1, //!< No additional details 883 }; 884 885 enum START_CODE_SEARCH_ENGINE 886 { 887 START_CODE_SEARCH_ENGINE_DISABLE = 0, //!< Bypass Start Code Search Engine 888 START_CODE_SEARCH_ENGINE_ENABLE = 1, //!< Enables the start code search engine to stop on every third byte start code defined by Start Code Byte [2:0] defined in this DWord. 889 }; 890 891 enum EMULATION_PREVENTION_BYTE_REMOVAL 892 { 893 EMULATION_PREVENTION_BYTE_REMOVAL_DISABLE = 0, //!< Bypass Emulation Prevention Byte Removal. 894 EMULATION_PREVENTION_BYTE_REMOVAL_ENABLE = 1, //!< Emulation prevention bytes will be removed after the start code search engine. 895 }; 896 897 //! \brief STREAM_OUT 898 //! \details 899 //! Enables the stream output. 900 enum STREAM_OUT 901 { 902 STREAM_OUT_DISABLE = 0, //!< Disable the stream output. 903 STREAM_OUT_ENABLE = 1, //!< Enable the stream output. 904 }; 905 906 enum DRMLENGTHMODE 907 { 908 DRMLENGTHMODE_STARTCODEMODE = 0, //!< Stops on a start code 909 DRMLENGTHMODE_LENGTHMODE = 1, //!< Stops after a number of bytes are reached in the length counter 910 }; 911 912 //! \brief HUC_BITSTREAM_ENABLE 913 //! \details 914 //! style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 915 //! line-height: normal;">Enables the bitstream to be sent to the HuC 916 enum HUC_BITSTREAM_ENABLE 917 { 918 HUC_BITSTREAM_ENABLE_DISABLE = 0, //!< No additional details 919 HUC_BITSTREAM_ENABLE_ENABLE = 1, //!< No additional details 920 }; 921 922 //! \name Initializations 923 924 //! \brief Explicit member initialization function HUC_STREAM_OBJECT_CMDHUC_STREAM_OBJECT_CMD925 HUC_STREAM_OBJECT_CMD() 926 { 927 DW0.Value = 0x75a00003; 928 929 DW1.Value = 0x00000000; 930 931 DW2.Value = 0x00000000; 932 933 DW3.Value = 0x00000000; 934 935 DW4.Value = 0x00000000; 936 } 937 938 static const size_t dwSize = 5; 939 static const size_t byteSize = 20; 940 }; 941 942 //! 943 //! \brief HUC_START 944 //! \details 945 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 946 //! Commands. Each HUC command has assigned a media instruction command as 947 //! defined in DWord 0, BitField 22:16. 948 //! 949 struct HUC_START_CMD 950 { 951 union 952 { 953 struct 954 { 955 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 956 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 957 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 958 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 959 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 960 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 961 }; 962 uint32_t Value; 963 } DW0; 964 union 965 { 966 struct 967 { 968 uint32_t Laststreamobject : __CODEGEN_BITFIELD(0, 0); //!< LASTSTREAMOBJECT 969 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 970 }; 971 uint32_t Value; 972 } DW1; 973 974 //! \name Local enumerations 975 976 enum MEDIA_INSTRUCTION_COMMAND 977 { 978 MEDIA_INSTRUCTION_COMMAND_HUCSTART = 33, //!< No additional details 979 }; 980 981 //! \brief MEDIA_INSTRUCTION_OPCODE 982 //! \details 983 //! Codec/Engine Name = HUC = Bh 984 enum MEDIA_INSTRUCTION_OPCODE 985 { 986 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 987 }; 988 989 enum PIPELINE_TYPE 990 { 991 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 992 }; 993 994 enum COMMAND_TYPE 995 { 996 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 997 }; 998 999 enum LASTSTREAMOBJECT 1000 { 1001 LASTSTREAMOBJECT_NOTLASTSTREAMOBJECT = 0, //!< Not the last stream object in the workload. 1002 LASTSTREAMOBJECT_LASTSTREAMOBJECT = 1, //!< Last stream object in the workload. 1003 }; 1004 1005 //! \name Initializations 1006 1007 //! \brief Explicit member initialization function HUC_START_CMDHUC_START_CMD1008 HUC_START_CMD() 1009 { 1010 DW0.Value = 0x75a10000; 1011 1012 DW1.Value = 0x00000000; 1013 } 1014 1015 static const size_t dwSize = 2; 1016 static const size_t byteSize = 8; 1017 }; 1018 MEDIA_CLASS_DEFINE_END(mhw__vdbox__huc__xe2_lpm_base__xe2_lpm__Cmd) 1019 }; 1020 } // namespace xe2_lpm 1021 } // namespace xe2_lpm_base 1022 } // namespace huc 1023 } // namespace vdbox 1024 } // namespace mhw 1025 1026 #pragma pack() 1027 1028 #endif // __MHW_VDBOX_HUC_HWCMD_XE2_LPM_H__ 1029