1 /* 2 * Copyright (c) 2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_huc_impl.h 24 //! \brief MHW VDBOX HUC interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_HUC_IMPL_H__ 29 #define __MHW_VDBOX_HUC_IMPL_H__ 30 31 #include "mhw_vdbox_huc_itf.h" 32 #include "mhw_impl.h" 33 34 namespace mhw 35 { 36 namespace vdbox 37 { 38 namespace huc 39 { 40 static constexpr uint32_t MEMORY_ADDRESS_ATTRIBUTES_MOCS_CLEAN_MASK = 0xFFFFFF81; 41 42 static constexpr uint32_t HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT = 0x1C2014; 43 static constexpr uint32_t HUC_STATUS_REG_OFFSET_NODE_1_INIT = 0x1C2000; 44 static constexpr uint32_t HUC_STATUS2_REG_OFFSET_NODE_1_INIT = 0x1C23B0; 45 static constexpr uint32_t HUC_LOAD_INFO_REG_OFFSET_NODE_1_INIT = 0xC1DC; 46 47 template <typename cmd_t> 48 class Impl : public Itf, public mhw::Impl 49 { 50 _HUC_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_IMPL); 51 52 public: SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])53 MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) override 54 { 55 MHW_FUNCTION_ENTER; 56 57 MHW_CHK_NULL_RETURN(settings); 58 59 size_t size = MOS_CODEC_RESOURCE_USAGE_END_CODEC * sizeof(MHW_MEMORY_OBJECT_CONTROL_PARAMS); 60 61 return MOS_SecureMemcpy(m_cacheabilitySettings, size, settings, size); 62 } 63 64 //! 65 //! \brief Get mmio registers 66 //! 67 //! \param [in] index 68 //! mmio registers index. 69 //! 70 //! \return [out] MmioRegistersHuc* 71 //! mmio registers got. 72 //! GetMmioRegisters(MHW_VDBOX_NODE_IND index)73 HucMmioRegisters* GetMmioRegisters(MHW_VDBOX_NODE_IND index) override 74 { 75 if (index < MHW_VDBOX_NODE_MAX) 76 { 77 return &m_mmioRegisters[index]; 78 } 79 else 80 { 81 MHW_ASSERT("index is out of range!"); 82 return &m_mmioRegisters[MHW_VDBOX_NODE_1]; 83 } 84 } 85 86 private: InitMmioRegisters()87 void InitMmioRegisters() 88 { 89 HucMmioRegisters *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1]; 90 91 mmioRegisters->hucUKernelHdrInfoRegOffset = HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT; 92 mmioRegisters->hucStatusRegOffset = HUC_STATUS_REG_OFFSET_NODE_1_INIT; 93 mmioRegisters->hucStatus2RegOffset = HUC_STATUS2_REG_OFFSET_NODE_1_INIT; 94 mmioRegisters->hucLoadInfoOffset = HUC_LOAD_INFO_REG_OFFSET_NODE_1_INIT; 95 96 m_mmioRegisters[MHW_VDBOX_NODE_2] = m_mmioRegisters[MHW_VDBOX_NODE_1]; 97 } 98 GetHucStatusReEncodeMask()99 uint32_t GetHucStatusReEncodeMask() override 100 { 101 return m_hucStatusReEncodeMask; 102 } 103 GetHucStatusHevcS2lFailureMask()104 uint32_t GetHucStatusHevcS2lFailureMask() override 105 { 106 return m_hucStatusHevcS2lFailureMask; 107 } 108 GetHucStatus2ImemLoadedMask()109 uint32_t GetHucStatus2ImemLoadedMask() override 110 { 111 return m_hucStatus2ImemLoadedMask; 112 } 113 GetHucErrorFlagsMask()114 uint32_t GetHucErrorFlagsMask() override 115 { 116 return m_hucErrorFlagsMask; 117 } 118 GetHucProductFamily()119 uint32_t GetHucProductFamily() override 120 { 121 return m_hucFamily; 122 } 123 124 protected: 125 using base_t = Itf; 126 HucMmioRegisters m_mmioRegisters[MHW_VDBOX_NODE_MAX] = {}; //!< HuC mmio registers 127 MhwCpInterface *m_cpItf = nullptr; 128 static const uint32_t m_hucStatusReEncodeMask = 0x80000000; 129 static const uint32_t m_hucStatusHevcS2lFailureMask = 0x8000; 130 static const uint32_t m_hucStatus2ImemLoadedMask = 0x40; 131 static const uint32_t m_hucErrorFlagsMask = 0xFFFE; //!< HuC error 2 flags mask 132 static const uint32_t m_hucFamily = 8; 133 134 MHW_MEMORY_OBJECT_CONTROL_PARAMS m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC] = {}; 135 Impl(PMOS_INTERFACE osItf,MhwCpInterface * cpItf)136 Impl(PMOS_INTERFACE osItf, MhwCpInterface *cpItf) : mhw::Impl(osItf) 137 { 138 m_cpItf = cpItf; 139 140 InitMmioRegisters(); 141 } 142 _MHW_SETCMD_OVERRIDE_DECL(HUC_PIPE_MODE_SELECT)143 _MHW_SETCMD_OVERRIDE_DECL(HUC_PIPE_MODE_SELECT) 144 { 145 _MHW_SETCMD_CALLBASE(HUC_PIPE_MODE_SELECT); 146 147 if (!params.disableProtectionSetting) 148 { 149 MHW_MI_CHK_STATUS(m_cpItf->SetProtectionSettingsForHucPipeModeSelect((uint32_t *)&cmd)); 150 } 151 152 #define DO_FIELDS() \ 153 DO_FIELD(DW1, IndirectStreamOutEnable, params.streamOutEnabled ? 1 : 0); \ 154 DO_FIELD(DW2, MediaSoftResetCounterPer1000Clocks, params.mediaSoftResetCounterValue); 155 156 #include "mhw_hwcmd_process_cmdfields.h" 157 } 158 _MHW_SETCMD_OVERRIDE_DECL(HUC_IND_OBJ_BASE_ADDR_STATE)159 _MHW_SETCMD_OVERRIDE_DECL(HUC_IND_OBJ_BASE_ADDR_STATE) 160 { 161 _MHW_SETCMD_CALLBASE(HUC_IND_OBJ_BASE_ADDR_STATE); 162 163 MHW_RESOURCE_PARAMS resourceParams = {}; 164 165 resourceParams.dwLsbNum = MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT; 166 resourceParams.dwUpperBoundLocationOffsetFromCmd = 3; 167 resourceParams.HwCommandType = MOS_HUC_IND_OBJ_BASE_ADDR; 168 169 if (!Mos_ResourceIsNull(params.DataBuffer)) 170 { 171 resourceParams.presResource = params.DataBuffer; 172 resourceParams.dwOffset = params.DataOffset; 173 resourceParams.pdwCmd = cmd.HucIndirectStreamInObjectbaseAddress.DW0_1.Value; 174 resourceParams.dwLocationInCmd = 1; 175 resourceParams.bIsWritable = false; 176 resourceParams.dwSize = params.DataSize; 177 178 InitMocsParams(resourceParams, &cmd.HucIndirectStreamInObjectbaseAttributes.DW0.Value, 1, 6); 179 180 MHW_MI_CHK_STATUS(AddResourceToCmd( 181 this->m_osItf, 182 this->m_currentCmdBuf, 183 &resourceParams)); 184 } 185 186 if (!Mos_ResourceIsNull(params.StreamOutObjectBuffer)) 187 { 188 resourceParams.presResource = params.StreamOutObjectBuffer; 189 resourceParams.dwOffset = params.StreamOutObjectOffset; 190 resourceParams.pdwCmd = cmd.HucIndirectStreamOutObjectbaseAddress.DW0_1.Value; 191 resourceParams.dwLocationInCmd = 6; 192 resourceParams.bIsWritable = true; 193 resourceParams.dwSize = params.StreamOutObjectSize; 194 195 InitMocsParams(resourceParams, &cmd.HucIndirectStreamOutObjectbaseAttributes.DW0.Value, 1, 6); 196 197 MHW_MI_CHK_STATUS(AddResourceToCmd( 198 this->m_osItf, 199 this->m_currentCmdBuf, 200 &resourceParams)); 201 } 202 203 return MOS_STATUS_SUCCESS; 204 } 205 _MHW_SETCMD_OVERRIDE_DECL(HUC_STREAM_OBJECT)206 _MHW_SETCMD_OVERRIDE_DECL(HUC_STREAM_OBJECT) 207 { 208 _MHW_SETCMD_CALLBASE(HUC_STREAM_OBJECT); 209 #define DO_FIELDS() \ 210 DO_FIELD(DW1, IndirectStreamInDataLength, params.IndirectStreamInDataLength); \ 211 DO_FIELD(DW2, IndirectStreamInStartAddress, params.IndirectStreamInStartAddress); \ 212 DO_FIELD(DW2, HucProcessing, params.HucProcessing); \ 213 DO_FIELD(DW3, IndirectStreamOutStartAddress, params.IndirectStreamOutStartAddress); \ 214 DO_FIELD(DW4, HucBitstreamEnable, params.HucBitstreamEnable); \ 215 DO_FIELD(DW4, StreamOut, params.StreamOut); \ 216 DO_FIELD(DW4, EmulationPreventionByteRemoval, params.EmulationPreventionByteRemoval); \ 217 DO_FIELD(DW4, StartCodeSearchEngine, params.StartCodeSearchEngine); \ 218 DO_FIELD(DW4, Drmlengthmode, params.Drmlengthmode); \ 219 DO_FIELD(DW4, StartCodeByte2, params.StartCodeByte2); \ 220 DO_FIELD(DW4, StartCodeByte1, params.StartCodeByte1); \ 221 DO_FIELD(DW4, StartCodeByte0, params.StartCodeByte0); 222 223 #include "mhw_hwcmd_process_cmdfields.h" 224 } 225 _MHW_SETCMD_OVERRIDE_DECL(HUC_IMEM_STATE)226 _MHW_SETCMD_OVERRIDE_DECL(HUC_IMEM_STATE) 227 { 228 _MHW_SETCMD_CALLBASE(HUC_IMEM_STATE); 229 230 #define DO_FIELDS() \ 231 DO_FIELD(DW4, HucFirmwareDescriptor, params.kernelDescriptor); 232 233 #include "mhw_hwcmd_process_cmdfields.h" 234 } 235 _MHW_SETCMD_OVERRIDE_DECL(HUC_DMEM_STATE)236 _MHW_SETCMD_OVERRIDE_DECL(HUC_DMEM_STATE) 237 { 238 _MHW_SETCMD_CALLBASE(HUC_DMEM_STATE); 239 240 MHW_RESOURCE_PARAMS resourceParams = {}; 241 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 242 resourceParams.dwLsbNum = MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 243 resourceParams.HwCommandType = MOS_HUC_DMEM; 244 245 if (!Mos_ResourceIsNull(params.hucDataSource)) 246 { 247 resourceParams.presResource = params.hucDataSource; 248 resourceParams.dwOffset = 0; 249 resourceParams.pdwCmd = (cmd.HucDataSourceBaseAddress.DW0_1.Value); 250 resourceParams.dwLocationInCmd = _MHW_CMD_DW_LOCATION(HucDataSourceBaseAddress); 251 resourceParams.bIsWritable = false; 252 253 InitMocsParams(resourceParams, &cmd.HucDataSourceAttributes.DW0.Value, 1, 6); 254 255 MHW_MI_CHK_STATUS(AddResourceToCmd( 256 this->m_osItf, 257 this->m_currentCmdBuf, 258 &resourceParams)); 259 260 // set HuC data destination address 261 cmd.DW4.HucDataDestinationBaseAddress = params.dmemOffset >> MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 262 263 // set data length 264 cmd.DW5.HucDataLength = params.dataLength >> MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 265 } 266 return MOS_STATUS_SUCCESS; 267 } 268 _MHW_SETCMD_OVERRIDE_DECL(HUC_VIRTUAL_ADDR_STATE)269 _MHW_SETCMD_OVERRIDE_DECL(HUC_VIRTUAL_ADDR_STATE) 270 { 271 _MHW_SETCMD_CALLBASE(HUC_VIRTUAL_ADDR_STATE); 272 273 MHW_RESOURCE_PARAMS resourceParams = {}; 274 275 // set up surface 0~15 276 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 277 resourceParams.dwLsbNum = MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT; 278 resourceParams.HwCommandType = MOS_HUC_VIRTUAL_ADDR; 279 280 for (int i = 0; i < 16; i++) 281 { 282 if (params.regionParams[i].presRegion) 283 { 284 resourceParams.presResource = params.regionParams[i].presRegion; 285 resourceParams.dwOffset = params.regionParams[i].dwOffset; 286 resourceParams.bIsWritable = params.regionParams[i].isWritable; 287 resourceParams.pdwCmd = cmd.HucVirtualAddressRegion[i].HucSurfaceBaseAddressVirtualaddrregion015.DW0_1.Value; 288 resourceParams.dwLocationInCmd = _MHW_CMD_DW_LOCATION(HucVirtualAddressRegion[i].HucSurfaceBaseAddressVirtualaddrregion015); 289 290 InitMocsParams(resourceParams, &cmd.HucVirtualAddressRegion[i].HucSurfaceVirtualaddrregion015.DW0.Value, 1, 6); 291 292 MHW_MI_CHK_STATUS(AddResourceToCmd( 293 this->m_osItf, 294 this->m_currentCmdBuf, 295 &resourceParams)); 296 } 297 } 298 return MOS_STATUS_SUCCESS; 299 } 300 _MHW_SETCMD_OVERRIDE_DECL(HUC_START)301 _MHW_SETCMD_OVERRIDE_DECL(HUC_START) 302 { 303 _MHW_SETCMD_CALLBASE(HUC_START); 304 305 #define DO_FIELDS() \ 306 DO_FIELD(DW1, Laststreamobject, params.lastStreamObject ? 1 : 0); 307 308 #include "mhw_hwcmd_process_cmdfields.h" 309 } 310 MEDIA_CLASS_DEFINE_END(mhw__vdbox__huc__Impl) 311 }; 312 } // namespace huc 313 } // namespace vdbox 314 } // namespace mhw 315 316 #endif // __MHW_VDBOX_HUC_IMPL_H__ 317