1 2 /*===================== begin_copyright_notice ================================== 3 4 # Copyright (c) 2024, Intel Corporation 5 # 6 # Permission is hereby granted, free of charge, to any person obtaining a 7 # copy of this software and associated documentation files (the "Software"), 8 # to deal in the Software without restriction, including without limitation 9 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 # and/or sell copies of the Software, and to permit persons to whom the 11 # Software is furnished to do so, subject to the following conditions: 12 # 13 # The above copyright notice and this permission notice shall be included 14 # in all copies or substantial portions of the Software. 15 # 16 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 # OTHER DEALINGS IN THE SOFTWARE. 23 24 ======================= end_copyright_notice ==================================*/ 25 //! 26 //! \file mhw_vdbox_mfx_hwcmd_xe2_lpm.h 27 //! \brief Auto-generated constructors for MHW and states. 28 //! \details This file may not be included outside of Xe2_LPM+ as other components 29 //! should use MHW interface to interact with MHW commands and states. 30 //! 31 32 // DO NOT EDIT 33 34 #ifndef __MHW_VDBOX_MFX_HWCMD_XE2_LPM_H__ 35 #define __MHW_VDBOX_MFX_HWCMD_XE2_LPM_H__ 36 37 #pragma once 38 #pragma pack(1) 39 40 #include "mhw_hwcmd.h" 41 #include <cstdint> 42 #include <cstddef> 43 #include "media_class_trace.h" 44 45 namespace mhw 46 { 47 namespace vdbox 48 { 49 namespace mfx 50 { 51 namespace xe2_lpm_base 52 { 53 namespace xe2_lpm 54 { 55 class Cmd 56 { 57 public: 58 virtual ~Cmd() = default; 59 GetOpLength(uint32_t uiLength)60 static uint32_t GetOpLength(uint32_t uiLength) 61 { 62 return __CODEGEN_OP_LENGTH(uiLength); 63 } 64 65 //! 66 //! \brief MEMORYADDRESSATTRIBUTES 67 //! \details 68 //! This field controls the priority of arbitration used in the GAC/GAM 69 //! pipeline for this surface. It defines the attributes for VDBOX addresses 70 //! on BDW+. 71 //! 72 struct MEMORYADDRESSATTRIBUTES_CMD 73 { 74 union 75 { 76 struct 77 { 78 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 79 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< Base Address - Index to Memory Object Control State (MOCS) Tables 80 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Base Address - Arbitration Priority Control 81 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Base Address - Memory Compression Enable 82 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10); //!< COMPRESSION_TYPE 83 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 84 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 85 uint32_t Tilemode : __CODEGEN_BITFIELD(13, 14); //!< TILEMODE 86 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 87 }; 88 uint32_t Value; 89 } DW0; 90 91 //! \name Local enumerations 92 93 //! \brief COMPRESSION_TYPE 94 //! \details 95 //! Indicates if buffer is render/media compressed. 96 enum COMPRESSION_TYPE 97 { 98 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 99 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< Only support rendered compression with unified memory 100 }; 101 102 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 103 //! \details 104 //! This field controls if the Row Store is going to store inside Media 105 //! Cache (rowstore cache) or to LLC. 106 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 107 { 108 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 109 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 110 }; 111 112 enum TILEMODE 113 { 114 TILEMODE_LINEAR = 0, //!< No additional details 115 TILEMODE_TILES_64K = 1, //!< No additional details 116 TILEMODE_TILEX = 2, //!< No additional details 117 TILEMODE_TILEF = 3, //!< No additional details 118 }; 119 120 //! \name Initializations 121 122 //! \brief Explicit member initialization function 123 MEMORYADDRESSATTRIBUTES_CMD(); 124 125 static const size_t dwSize = 1; 126 static const size_t byteSize = 4; 127 }; 128 129 //! 130 //! \brief SPLITBASEADDRESS64BYTEALIGNED 131 //! \details 132 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 133 //! address. 134 //! 135 //! Bits 63:48 must be zero. 136 //! 137 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 138 { 139 union 140 { 141 struct 142 { 143 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 144 uint64_t BaseAddress : __CODEGEN_BITFIELD(6, 56); //!< Base Address 145 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63); //!< Reserved 146 }; 147 uint32_t Value[2]; 148 } DW0_1; 149 150 //! \name Local enumerations 151 152 //! \name Initializations 153 154 //! \brief Explicit member initialization function 155 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 156 157 static const size_t dwSize = 2; 158 static const size_t byteSize = 8; 159 }; 160 161 //! 162 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 163 //! \details 164 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 165 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 166 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 167 //! 168 //! Bits 63:48 must be zero. 169 //! 170 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 171 { 172 union 173 { 174 struct 175 { 176 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 177 uint64_t BaseAddress : __CODEGEN_BITFIELD(12, 56); //!< Base Address 178 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63); //!< Reserved 179 }; 180 uint32_t Value[2]; 181 } DW0_1; 182 183 //! \name Local enumerations 184 185 //! \name Initializations 186 187 //! \brief Explicit member initialization function 188 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 189 190 static const size_t dwSize = 2; 191 static const size_t byteSize = 8; 192 }; 193 194 //! 195 //! \brief MFX_QM_STATE 196 //! \details 197 //! This is a common state command for AVC encoder modes. For encoder, it 198 //! represents both the forward QM matrices as well as the decoding QM 199 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 200 //! application are being sent to the hardware. The driver is responsible 201 //! for determining the final set of scaling lists to be used for decoding 202 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 203 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 204 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 205 //! order. But the Forward Q scaling lists are sent in column-wise raster 206 //! order (column-by-column) to simplify the H/W. Driver will perform all 207 //! the scan order conversion for both ForwardQ and IQ. 208 //! 209 struct MFX_QM_STATE_CMD 210 { 211 union 212 { 213 struct 214 { 215 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 216 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 217 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 218 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 219 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 220 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 221 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 222 }; 223 uint32_t Value; 224 } DW0; 225 union 226 { 227 struct 228 { 229 uint32_t Mpeg2 : __CODEGEN_BITFIELD(0, 1); //!< MPEG2, MPEG2- Decoder Only 230 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, MPEG2- Decoder Only 231 } Obj0; 232 struct 233 { 234 uint32_t Jpeg : __CODEGEN_BITFIELD(0, 1); //!< JPEG, JPEG- Encoder Only 235 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, JPEG- Encoder Only 236 } Obj1; 237 struct 238 { 239 uint32_t Avc : __CODEGEN_BITFIELD(0, 1); //!< AVC, AVC- Decoder Only 240 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, AVC- Decoder Only 241 } Obj2; 242 uint32_t Value; 243 } DW1; 244 uint32_t ForwardQuantizerMatrix[16]; //!< Forward Quantizer Matrix 245 246 //! \name Local enumerations 247 248 enum SUBOPCODE_B 249 { 250 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 251 }; 252 253 enum SUBOPCODE_A 254 { 255 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 256 }; 257 258 enum MEDIA_COMMAND_OPCODE 259 { 260 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 261 }; 262 263 enum PIPELINE 264 { 265 PIPELINE_MFXMULTIDW = 2, //!< No additional details 266 }; 267 268 enum COMMAND_TYPE 269 { 270 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 271 }; 272 273 //! \brief MPEG2 274 //! \details 275 //! For MPEG2 QM Type: This field specifies which Quantizer Matrix is 276 //! loaded. 277 enum MPEG2 278 { 279 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 280 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 281 }; 282 283 //! \brief JPEG 284 //! \details 285 //! For JPEG QM Type:This field specifies which Quantizer Matrix is 286 //! loaded. 287 enum JPEG 288 { 289 JPEG_JPEGLUMAYQUANTIZERMATRIX_ORR = 0, //!< No additional details 290 JPEG_JPEGCHROMACBQUANTIZERMATRIX_ORG = 1, //!< No additional details 291 JPEG_JPEGCHROMACRQUANTIZERMATRIX_ORB = 2, //!< No additional details 292 }; 293 294 //! \brief AVC 295 //! \details 296 //! For AVC QM Type: This field specifies which Quantizer Matrix is 297 //! loaded. 298 enum AVC 299 { 300 AVC_AVC4X4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 301 AVC_AVC4X4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 302 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 303 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 304 }; 305 306 //! \name Initializations 307 308 //! \brief Explicit member initialization function 309 MFX_QM_STATE_CMD(); 310 311 static const size_t dwSize = 18; 312 static const size_t byteSize = 72; 313 }; 314 315 //! 316 //! \brief MFX_FQM_STATE 317 //! \details 318 //! This is a common state command for AVC encoder modes. For encoder, it 319 //! represents both the forward QM matrices as well as the decoding QM 320 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 321 //! application are being sent to the hardware. The driver is responsible 322 //! for determining the final set of scaling lists to be used for decoding 323 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 324 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 325 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 326 //! order. But the Forward Q scaling lists are sent in column-wise raster 327 //! order (column-by-column) to simplify the H/W. Driver will perform all 328 //! the scan order conversion for both ForwardQ and IQ. 329 //! 330 struct MFX_FQM_STATE_CMD 331 { 332 union 333 { 334 struct 335 { 336 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 337 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 338 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 339 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 340 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 341 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 342 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 343 }; 344 uint32_t Value; 345 } DW0; 346 union 347 { 348 struct 349 { 350 uint32_t Mpeg2 : __CODEGEN_BITFIELD(0, 1); //!< MPEG2, MPEG2- Decoder Only 351 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, MPEG2- Decoder Only 352 } Obj0; 353 struct 354 { 355 uint32_t Jpeg : __CODEGEN_BITFIELD(0, 1); //!< JPEG, JPEG- Encoder Only 356 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, JPEG- Encoder Only 357 } Obj1; 358 struct 359 { 360 uint32_t Avc : __CODEGEN_BITFIELD(0, 1); //!< AVC, AVC- Decoder Only 361 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, AVC- Decoder Only 362 } Obj2; 363 uint32_t Value; 364 } DW1; 365 uint32_t ForwardQuantizerMatrix[32]; //!< Forward Quantizer Matrix 366 367 //! \name Local enumerations 368 369 enum SUBOPCODE_B 370 { 371 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 372 }; 373 374 enum SUBOPCODE_A 375 { 376 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 377 }; 378 379 enum MEDIA_COMMAND_OPCODE 380 { 381 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 382 }; 383 384 enum PIPELINE 385 { 386 PIPELINE_MFXMULTIDW = 2, //!< No additional details 387 }; 388 389 enum COMMAND_TYPE 390 { 391 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 392 }; 393 394 //! \brief MPEG2 395 //! \details 396 //! For MPEG2 QM Type: This field specifies which Quantizer Matrix is 397 //! loaded. 398 enum MPEG2 399 { 400 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 401 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 402 }; 403 404 //! \brief JPEG 405 //! \details 406 //! For JPEG QM Type:This field specifies which Quantizer Matrix is 407 //! loaded. 408 enum JPEG 409 { 410 JPEG_JPEGLUMAYQUANTIZERMATRIX_ORR = 0, //!< No additional details 411 JPEG_JPEGCHROMACBQUANTIZERMATRIX_ORG = 1, //!< No additional details 412 JPEG_JPEGCHROMACRQUANTIZERMATRIX_ORB = 2, //!< No additional details 413 }; 414 415 //! \brief AVC 416 //! \details 417 //! For AVC QM Type: This field specifies which Quantizer Matrix is 418 //! loaded. 419 enum AVC 420 { 421 AVC_AVC4X4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 422 AVC_AVC4X4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 423 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 424 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 425 }; 426 427 //! \name Initializations 428 429 //! \brief Explicit member initialization function 430 MFX_FQM_STATE_CMD(); 431 432 static const size_t dwSize = 34; 433 static const size_t byteSize = 136; 434 }; 435 436 //! 437 //! \brief MFX_PIPE_MODE_SELECT 438 //! \details 439 //! Specifies which codec and hardware module is being used toencode/decode 440 //! the video data, on a per-frame basis. The MFX_PIPE_MODE_SELECT 441 //! commandspecifies which codec and hardware module is being used to 442 //! encode/decode the video data,on a per-frame basis. It also configures 443 //! the hardware pipeline according to the activeencoder/decoder operating 444 //! mode for encoding/decoding the current picture. Commandsissued 445 //! specifically for AVC and MPEG2 are ignored when VC1 is the activecodec. 446 //! 447 struct MFX_PIPE_MODE_SELECT_CMD 448 { 449 union 450 { 451 struct 452 { 453 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 454 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 455 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 456 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23); //!< SUBOPA 457 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26); //!< OPCODE 458 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 459 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 460 }; 461 uint32_t Value; 462 } DW0; 463 union 464 { 465 struct 466 { 467 uint32_t StandardSelect : __CODEGEN_BITFIELD(0, 3); //!< STANDARD_SELECT 468 uint32_t CodecSelect : __CODEGEN_BITFIELD(4, 4); //!< CODEC_SELECT 469 uint32_t StitchMode : __CODEGEN_BITFIELD(5, 5); //!< STITCH_MODE 470 uint32_t FrameStatisticsStreamoutEnable : __CODEGEN_BITFIELD(6, 6); //!< FRAME_STATISTICS_STREAMOUT_ENABLE 471 uint32_t ScaledSurfaceEnable : __CODEGEN_BITFIELD(7, 7); //!< SCALED_SURFACE_ENABLE 472 uint32_t PreDeblockingOutputEnablePredeblockoutenable : __CODEGEN_BITFIELD(8, 8); //!< PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 473 uint32_t PostDeblockingOutputEnablePostdeblockoutenable : __CODEGEN_BITFIELD(9, 9); //!< POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 474 uint32_t StreamOutEnable : __CODEGEN_BITFIELD(10, 10); //!< STREAM_OUT_ENABLE 475 uint32_t PicErrorStatusReportEnable : __CODEGEN_BITFIELD(11, 11); //!< PIC_ERRORSTATUS_REPORT_ENABLE 476 uint32_t DeblockerStreamOutEnable : __CODEGEN_BITFIELD(12, 12); //!< DEBLOCKER_STREAM_OUT_ENABLE 477 uint32_t VdencMode : __CODEGEN_BITFIELD(13, 13); //!< VDENC_MODE 478 uint32_t StandaloneVdencModeEnable : __CODEGEN_BITFIELD(14, 14); //!< STANDALONE_VDENC_MODE_ENABLE 479 uint32_t DecoderModeSelect : __CODEGEN_BITFIELD(15, 16); //!< DECODER_MODE_SELECT 480 uint32_t DecoderShortFormatMode : __CODEGEN_BITFIELD(17, 17); //!< DECODER_SHORT_FORMAT_MODE 481 uint32_t ExtendedStreamOutEnable : __CODEGEN_BITFIELD(18, 18); //!< Extended stream out enable 482 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 23); //!< Reserved 483 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 484 }; 485 uint32_t Value; 486 } DW1; 487 union 488 { 489 struct 490 { 491 uint32_t PerformanceCounterEnableVmxVmcVadVdsBsp : __CODEGEN_BITFIELD(0, 0); //!< PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP 492 uint32_t VmxRowStoreCounterOutputSelect : __CODEGEN_BITFIELD(1, 2); //!< VMX_ROW_STORE_COUNTER_OUTPUT_SELECT 493 uint32_t VdsIldbCalculation : __CODEGEN_BITFIELD(3, 3); //!< VDS_ILDB_CALCULATION 494 uint32_t Reserved68 : __CODEGEN_BITFIELD(4, 4); //!< Reserved 495 uint32_t Reserved69 : __CODEGEN_BITFIELD(5, 5); //!< Reserved 496 uint32_t ClockGateEnableAtSliceLevel : __CODEGEN_BITFIELD(6, 6); //!< CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 497 uint32_t Reserved71 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 498 uint32_t VmxDummyFetchControl : __CODEGEN_BITFIELD(8, 8); //!< VMX_DUMMY_FETCH_CONTROL 499 uint32_t Reserved73 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 500 uint32_t MpcPref08X8DisableFlagDefault0 : __CODEGEN_BITFIELD(10, 10); //!< MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 501 uint32_t VinClockGatingCmclkDisable : __CODEGEN_BITFIELD(11, 11); //!< VIN_CLOCK_GATING_CMCLK_DISABLE_ 502 uint32_t VlfMbaffOsStorageForSvcDisable : __CODEGEN_BITFIELD(12, 12); //!< VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ 503 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 504 uint32_t Vlf720IOddHeightInVc1Mode : __CODEGEN_BITFIELD(14, 14); //!< VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 505 uint32_t VinClockGatingCuclkDisable : __CODEGEN_BITFIELD(15, 15); //!< VIN_CLOCK_GATING_CUCLK_DISABLE 506 uint32_t VinSliceStartGenerationForItMode : __CODEGEN_BITFIELD(16, 16); //!< VIN_SLICE_START_GENERATION_FOR_IT_MODE 507 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 508 uint32_t Reserved82 : __CODEGEN_BITFIELD(18, 20); //!< Reserved 509 uint32_t Reserved83 : __CODEGEN_BITFIELD(21, 22); //!< Reserved 510 uint32_t VhrReferenceListGenerationAdjustmentUsingCurrentPocForBFrame : __CODEGEN_BITFIELD(23, 23); //!< VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME 511 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 24); //!< Reserved 512 uint32_t VamErrorHandlingForReferenceIndexInSvcAvcDisable : __CODEGEN_BITFIELD(25, 25); //!< VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE 513 uint32_t VadSvcDecodeErrorHandlingDisable : __CODEGEN_BITFIELD(26, 26); //!< VAD_SVC_DECODE_ERROR_HANDLING_DISABLE 514 uint32_t VmbSvcTlbDummyFetchDisableForPerformance : __CODEGEN_BITFIELD(27, 27); //!< VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 515 uint32_t VmbSvcMvReplicationFor8X8EnableErrorHandling : __CODEGEN_BITFIELD(28, 28); //!< VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 516 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 29); //!< Reserved 517 uint32_t VdsSvcSvcBlktypeEquationAdjustment : __CODEGEN_BITFIELD(30, 30); //!< VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT 518 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 519 }; 520 uint32_t Value; 521 } DW2; 522 union 523 { 524 struct 525 { 526 uint32_t PicStatusErrorReportId; //!< PIC_STATUSERROR_REPORT_ID 527 }; 528 uint32_t Value; 529 } DW3; 530 union 531 { 532 struct 533 { 534 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 15); //!< Reserved 535 uint32_t SliceSizeStreamout32bit : __CODEGEN_BITFIELD(16, 16); //!< Enable 32-bit report for SliceSizeStreamout 536 uint32_t Reserved129 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 537 }; 538 uint32_t Value; 539 } DW4; 540 541 //! \name Local enumerations 542 543 enum SUBOPB 544 { 545 SUBOPB_MFXPIPEMODESELECT = 0, //!< No additional details 546 }; 547 548 enum SUBOPA 549 { 550 SUBOPA_UNNAMED0 = 0, //!< No additional details 551 }; 552 553 enum OPCODE 554 { 555 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 556 }; 557 558 enum PIPELINE 559 { 560 PIPELINE_MFXCOMMON = 2, //!< No additional details 561 }; 562 563 enum COMMAND_TYPE 564 { 565 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 566 }; 567 568 enum STANDARD_SELECT 569 { 570 STANDARD_SELECT_MPEG2 = 0, //!< No additional details 571 STANDARD_SELECT_VC1 = 1, //!< No additional details 572 STANDARD_SELECT_AVC = 2, //!< Covers both AVC and MVC 573 STANDARD_SELECT_JPEG = 3, //!< No additional details 574 STANDARD_SELECT_SVC = 4, //!< No additional details 575 STANDARD_SELECT_VP8 = 5, //!< Decoder starting from BDW, Encoder starting from CHV 576 STANDARD_SELECT_UVLD = 15, //!< SW decoder w/ embedded micro-controller and co-processor 577 }; 578 579 enum CODEC_SELECT 580 { 581 CODEC_SELECT_DECODE = 0, //!< No additional details 582 CODEC_SELECT_ENCODE = 1, //!< Valid only if StandardSel is AVC, MPEG2 and SVC) 583 }; 584 585 enum STITCH_MODE 586 { 587 STITCH_MODE_NOTINSTITCHMODE = 0, //!< No additional details 588 STITCH_MODE_INTHESPECIALSTITCHMODE = 1, //!< This mode can be used for any Codec as long as bitfield conditions are met. 589 }; 590 591 //! \brief FRAME_STATISTICS_STREAMOUT_ENABLE 592 //! \details 593 //! This field controls the frame level statistics streamout from the PAK. 594 //! Note: This field needs to be always "Enabled" in VD_Enc mode. 595 //! In case of non-VDEnc mode,this can be used to control the frame 596 //! statistics output from the PAK. 597 enum FRAME_STATISTICS_STREAMOUT_ENABLE 598 { 599 FRAME_STATISTICS_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 600 FRAME_STATISTICS_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 601 }; 602 603 //! \brief SCALED_SURFACE_ENABLE 604 //! \details 605 //! This field indicates if the scaled surface is enabled. This fieldenables 606 //! the 4x HME downscalar of the reconstructed image. Only supported for AVC 607 //! and VP8 formats. 608 enum SCALED_SURFACE_ENABLE 609 { 610 SCALED_SURFACE_ENABLE_DISABLE = 0, //!< No additional details 611 SCALED_SURFACE_ENABLE_ENABLE = 1, //!< No additional details 612 }; 613 614 //! \brief PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 615 //! \details 616 //! This field controls the output write for the reconstructed pixels BEFORE 617 //! the deblocking filter. 618 enum PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 619 { 620 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 621 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 622 }; 623 624 //! \brief POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 625 //! \details 626 //! This field controls the output write for the reconstructed pixels AFTER 627 //! the deblocking filter.In MPEG2 decoding mode, if this is enabled, VC1 628 //! deblocking filter is used. 629 enum POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 630 { 631 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 632 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 633 }; 634 635 //! \brief STREAM_OUT_ENABLE 636 //! \details 637 //! This field controls whether the macroblock parameter stream-out is 638 //! enabled during VLD decoding for transcoding purpose. 639 enum STREAM_OUT_ENABLE 640 { 641 STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 642 STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 643 }; 644 645 //! \brief PIC_ERRORSTATUS_REPORT_ENABLE 646 //! \details 647 //! This field control whether the error/status reporting is enable or 648 //! not.0: Disable1: EnableIn decoder modes: Error reporting is written out 649 //! once per frame. The Error Report frame ID listed in DW3 along with the 650 //! VLD/IT error status bits are packed into one cache and written to the 651 //! "Decoded Picture Error/Status Buffer address" listed in the 652 //! MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall program different 653 //! error buffer addresses between pictrues; otherwise, hardware might 654 //! overwrite previous written data if driver does not read it fast 655 //! enough.In encoder modes: Not used Please refer to "Media 656 //! VDBOX -> Video Codec -> Other Codec Functions -> MFX Error 657 //! Handling -> Decoder" session for the output format. 658 enum PIC_ERRORSTATUS_REPORT_ENABLE 659 { 660 PIC_ERRORSTATUS_REPORT_ENABLE_DISABLE = 0, //!< No additional details 661 PIC_ERRORSTATUS_REPORT_ENABLE_ENABLE = 1, //!< No additional details 662 }; 663 664 //! \brief DEBLOCKER_STREAM_OUT_ENABLE 665 //! \details 666 //! This field indicates if Deblocker information is going to be streamout 667 //! during VLD decoding.For AVC, it is needed to enable the deblocker 668 //! streamout as the AVC Disable_DLKFilterIdc is a slice level parameters. 669 //! Driver needs to determine ahead of time if at least one slice of the 670 //! current frame/ has deblocker ON. For SVC, there are two deblocking 671 //! control streamout buffers (specified in MFX_BUF_ADDR State Command). 672 //! This field is still associated with the slice level SVC 673 //! Disable.DLK_Filter_Idc. 674 enum DEBLOCKER_STREAM_OUT_ENABLE 675 { 676 DEBLOCKER_STREAM_OUT_ENABLE_DISABLE = 0, //!< Disable streamout of deblocking control information for standalone deblocker operation.It needs other fields to determine one or two SVC deblocking surface streamout (Post Deblocking Output Enable, Pre Deblocking Output Enable, interlayer idc and regular deblock idc). 677 DEBLOCKER_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 678 }; 679 680 //! \brief VDENC_MODE 681 //! \details 682 //! This field indicates if PAK is working in legacy MBEnc mode or the VDEnc 683 //! mode. 684 enum VDENC_MODE 685 { 686 VDENC_MODE_MBENCMODE = 0, //!< PAK is working in legacy mode 687 VDENC_MODE_VDENCMODE = 1, //!< PAK is working in VDEnc mode 688 }; 689 690 //! \brief STANDALONE_VDENC_MODE_ENABLE 691 //! \details 692 //! This field indicates to PAK if this is standalone VDEnc mode. This is 693 //! primarily a validation mode. 694 enum STANDALONE_VDENC_MODE_ENABLE 695 { 696 STANDALONE_VDENC_MODE_ENABLE_VDENCPAK = 0, //!< No additional details 697 STANDALONE_VDENC_MODE_ENABLE_PAKONLY = 1, //!< No additional details 698 }; 699 700 //! \brief DECODER_MODE_SELECT 701 //! \details 702 //! Each coding standard supports two entry points: VLD entry point and IT 703 //! (IDCT) entry point. This field selects which one is in use.This field is 704 //! only valid if Codec Select is 0 (decoder). 705 enum DECODER_MODE_SELECT 706 { 707 DECODER_MODE_SELECT_VLDMODE = 0, //!< All codec minimum must support this mode 708 DECODER_MODE_SELECT_ITMODE = 1, //!< Configure the MFD Engine for IT ModeNote: Only VC1 and MPEG2 support this mode 709 DECODER_MODE_SELECT_DEBLOCKERMODE = 2, //!< Configure the MFD Engine for Standalone Deblocker Mode. Require streamout AVC edge control information from preceeding decoding pass.Note: [HSW, EXCLUDE(HSW:GT3:A, HSW:GT3:B, HSW:GT2:B)] Only AVC, MPEG2 and SVC are supported. 710 DECODER_MODE_SELECT_INTERLAYERMODE = 3, //!< Configure the MFX Engine for standalone SVC interlayer upsampling for motion info, residual and reconstructed pixel. Require information being streamout from the preceding encoding and decoding pass of a reference layer.> 711 }; 712 713 //! \brief DECODER_SHORT_FORMAT_MODE 714 //! \details 715 //! For IT mode, this bit must be 0. 716 enum DECODER_SHORT_FORMAT_MODE 717 { 718 DECODER_SHORT_FORMAT_MODE_SHORTFORMATDRIVERINTERFACE = 0, //!< AVC/VC1/MVC/SVC/VP8 Short Format Mode is in use Note: There is no Short Format for SVC and VP8 yet, so this field must be set to 1 for SVC and VP8. 719 DECODER_SHORT_FORMAT_MODE_LONGFORMATDRIVERINTERFACE = 1, //!< AVC/VC1/MVC/SVC/VP8 Long Format Mode is in use. 720 }; 721 722 //! \brief PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP 723 //! \details 724 //! This bit enables all performance counters in MFX hardware. 725 enum PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP 726 { 727 PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP_DISABLE = 0, //!< No additional details 728 PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP_ENABLE = 1, //!< No additional details 729 }; 730 731 //! \brief VMX_ROW_STORE_COUNTER_OUTPUT_SELECT 732 //! \details 733 //! This indicates which rowstore counter is going to be visable. 734 enum VMX_ROW_STORE_COUNTER_OUTPUT_SELECT 735 { 736 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED0 = 0, //!< Default Set of Counters 737 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED1 = 1, //!< Counter Set #1 738 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED2 = 2, //!< Counter Set #2 739 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED3 = 3, //!< Counter Set #3 740 }; 741 742 //! \brief VDS_ILDB_CALCULATION 743 //! \details 744 //! This bit forces all MB into INTRA MBs before doing ILDB control 745 //! generation in VDS. 746 enum VDS_ILDB_CALCULATION 747 { 748 VDS_ILDB_CALCULATION_DISABLE = 0, //!< Use original definition for ILDB calculation. 749 VDS_ILDB_CALCULATION_ENABLE = 1, //!< Force neighbor Intra MB = 1 on ILDB BS calculation. 750 }; 751 752 //! \brief CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 753 //! \details 754 //! BitFieldDesc: 755 enum CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 756 { 757 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_DISABLE = 0, //!< Disable Slice-level Clock gating, Unit-level Clock gating will apply 758 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_ENABLE = 1, //!< Enable Slice-level Clock gating, overrides any Unit level Clock gating 759 }; 760 761 //! \brief VMX_DUMMY_FETCH_CONTROL 762 //! \details 763 //! This control if VMX is going to accept the dummy fetch. 764 enum VMX_DUMMY_FETCH_CONTROL 765 { 766 VMX_DUMMY_FETCH_CONTROL_ENABLE = 0, //!< Allow SVC Dummy Fetch to go to GAC (Better Performance) 767 VMX_DUMMY_FETCH_CONTROL_DISABLE = 1, //!< Drops SVC Dummy Fetch (It matches back the original design) 768 }; 769 770 enum MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 771 { 772 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_DISABLE = 0, //!< No additional details 773 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_ENABLE = 1, //!< No additional details 774 }; 775 776 //! \brief VIN_CLOCK_GATING_CMCLK_DISABLE_ 777 //! \details 778 //! This bit disable cmclk clock gate for VIN. 779 enum VIN_CLOCK_GATING_CMCLK_DISABLE_ 780 { 781 VIN_CLOCK_GATING_CMCLK_DISABLE_DISABLE = 0, //!< No additional details 782 VIN_CLOCK_GATING_CMCLK_DISABLE_ENABLE = 1, //!< Disable gcmclkvin 783 }; 784 785 //! \brief VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ 786 //! \details 787 //! This bit disables MBAFF storage for SVC use in VLF. 788 enum VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ 789 { 790 VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ENABLE = 0, //!< Enable MBAFF OS storage of storing VOP data for SVC 791 VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_DISABLE = 1, //!< Disable MBAFF OS storage of storign VOP data for SVC 792 }; 793 794 //! \brief VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 795 //! \details 796 //! This bit indicates VLF write out VC1 picture with odd height (in MBs). 797 enum VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 798 { 799 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_DISABLE = 0, //!< No additional details 800 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ENABLE = 1, //!< 720i Enable 801 }; 802 803 //! \brief VIN_CLOCK_GATING_CUCLK_DISABLE 804 //! \details 805 //! This bit disables gcuclk for VIN. 806 enum VIN_CLOCK_GATING_CUCLK_DISABLE 807 { 808 VIN_CLOCK_GATING_CUCLK_DISABLE_DISABLE = 0, //!< No additional details 809 VIN_CLOCK_GATING_CUCLK_DISABLE_ENABLE = 1, //!< Disbales gcuclkvin 810 }; 811 812 //! \brief VIN_SLICE_START_GENERATION_FOR_IT_MODE 813 //! \details 814 //! This bit changes the behavior how VIN generates slice start in IT mode. 815 enum VIN_SLICE_START_GENERATION_FOR_IT_MODE 816 { 817 VIN_SLICE_START_GENERATION_FOR_IT_MODE_FRAME = 0, //!< 1 slice start per frame only 818 VIN_SLICE_START_GENERATION_FOR_IT_MODE_OBJECT = 1, //!< 1 slice start per object (multiple objects per frame) 819 }; 820 821 //! \brief VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME 822 //! \details 823 //! This bit is added to handle the discrepancy between spec and reference 824 //! decoder. 825 enum VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME 826 { 827 VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME_UNNAMED0 = 0, //!< Use " less than or equal to" on POC for B Frame Generation.(Reference Entry POC) =< (Current POC) (during reference list generation) 828 VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME_UNNAMED1 = 1, //!< Use "=" on POC for B Frame Generation(Reference Entry POC) = (Current POC) (during reference list generation) 829 }; 830 831 //! \brief VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE 832 //! \details 833 //! This bit disables Error Handling Logic for Reference Index in SVC/AVC 834 //! mode. 835 enum VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE 836 { 837 VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE_ENABLE = 0, //!< Enable VAM Error Handling Logic for Reference Index in SVC/AVC mode 838 VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE_DISABLE = 1, //!< Disable VAM Error Handling Logic for Reference Index in SVC/AVC mode 839 }; 840 841 //! \brief VAD_SVC_DECODE_ERROR_HANDLING_DISABLE 842 //! \details 843 //! This bit disables SVC Decode Error Handling Logic for MBTYPE, 844 //! Tcoeff/TrailingOnes and Trans8x8Flag. 845 enum VAD_SVC_DECODE_ERROR_HANDLING_DISABLE 846 { 847 VAD_SVC_DECODE_ERROR_HANDLING_DISABLE_ENABLE = 0, //!< Enable SVC Decode Error Handling 848 VAD_SVC_DECODE_ERROR_HANDLING_DISABLE_DISABLE = 1, //!< Disable SVC Decode Error Handling 849 }; 850 851 //! \brief VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 852 //! \details 853 //! This bit disables TLB dummy fetch in SVC mode in VMB. 854 enum VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 855 { 856 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_ENABLE = 0, //!< Enable VMB TLB Dummy Fetch for Performance 857 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_DISABLE = 1, //!< Disable VMB TLB Dummy Fetch 858 }; 859 860 //! \brief VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 861 //! \details 862 //! This bit enables Motion Vector replication on 8x8 level during SVC mode 863 //! for error handling. 864 enum VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 865 { 866 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_DISABLE = 0, //!< Disable MV 8x8 replication in SVC mode 867 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_ENABLE = 1, //!< Enable MV 8x8 Replication in SVC Mode 868 }; 869 870 //! \brief VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT 871 //! \details 872 //! This bit adjusts the svc_blktype equation in VDS (whether to use target 873 //! layer flag to be part of equation). 874 enum VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT 875 { 876 VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT_ENABLE = 0, //!< Target Layer Flag is used for svc_blktype equation 877 VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT_DISABLE = 1, //!< Target Layer Flag not used for svc_blktype equation 878 }; 879 880 //! \brief PIC_STATUSERROR_REPORT_ID 881 //! \details 882 //! In decoder modes: Error reporting is written out once per frame. This 883 //! field along with the VLD error status bits are packed into one cache and 884 //! written to the memory location specified by "Decoded Picture 885 //! Error/Status Buffer address" listed in the MFX_PIPE_BUF_ADDR_STATE 886 //! Command. 887 enum PIC_STATUSERROR_REPORT_ID 888 { 889 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 890 }; 891 892 //! \name Initializations 893 894 //! \brief Explicit member initialization function 895 MFX_PIPE_MODE_SELECT_CMD(); 896 897 static const size_t dwSize = 5; 898 static const size_t byteSize = 20; 899 }; 900 901 //! 902 //! \brief MFX_SURFACE_STATE 903 //! \details 904 //! This command is common for all encoding/decoding modes, tospecify the 905 //! uncompressed YUV picture (i.e. destination surface) or intermediate 906 //! streamout in/out surface (e.g. coefficient/residual) (field, frame 907 //! orinterleaved frame) format for reading and writing: 908 //! Uncompressed, original input picture to be encoded 909 //! Reconstructed non-filtered/filtered display picturec(becoming reference 910 //! pictures as well for subsequent temporal inter-prediction) 911 //! Residual in SVC 912 //! Reconstructed Intra pixel in SVC 913 //! CoeffPred in SVC 914 //! 915 //! Since there is only one media surface state being active during the 916 //! entire encoding/decodingprocess, all the uncompressed/reconstructed 917 //! pictures are defined to have the samesurface state. For each media 918 //! object call (decoding or encoding), multiple SVC surfaces can be active 919 //! concurrently, to distinguish among them, a surfaceID is added to specify 920 //! for each type of surface. The primary difference among picture surface 921 //! states is their individual programmed base addresses, which are provided 922 //! by other state commands and not included in this command. MFX engine is 923 //! making the association of surface states and corresponding buffer base 924 //! addresses. 925 //! MFX engine currently supports only one media surface type for video 926 //! andthat is the NV12 (Planar YUV420 with interleaved U (Cb) and V (Cr). 927 //! For optimizingmemory efficiency based on access patterns, only TileY is 928 //! supported. For JPEG decoder,only IMC1 and IMC3 are supported. Pitch can 929 //! be wider than the Picture Width in pixelsand garbage will be there at 930 //! the end of each line. The following describes all thedifferent formats 931 //! that are supported and not supported in Gen7 MFX : 932 //! NV12 - 4:2:0 only;UV interleaved; Full Pitch, U and V offset is set to 933 //! 0 (the only format supported forvideo codec); vertical UV offset is MB 934 //! aligned; UV xoffsets = 0. JPEG does not supportNV12 format because 935 //! non-interleave JPEG has performance issue with partial write 936 //! (ininterleaved UV format) 937 //! IMC 1 & 3 - Full Pitch, U and V are separate plane; (JPEGonly; U 938 //! plane + garbage first in full pitch followed by V plane + garbage in 939 //! fullpitch). U and V vertical offsets are block aligned; U and V xoffset 940 //! = 0; there is no gapbetween Y, U and V planes. IMC1 and IMC3 are 941 //! different by a swap of U and V. This is theonly format supported in JPEG 942 //! for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) 943 //! We are not supporting IMC 2 & 4 - Full Pitch, U and V are separate 944 //! plane (JPEG only; Uplane first in full pitch followed by V plane in full 945 //! pitch - U and V plane areside-by-side). U and V vertical offsets are 946 //! 16-pixel aligned; V xoffset is half-pitchaligned; U xoffset is 0; there 947 //! is no gap between Y, U and V planes. IMC2 and IMC4 aredifferent by a 948 //! swap of U and V. 949 //! We are not supporting YV12 - half pitch for each U and Vplane, and 950 //! separate planes for Y, U and V (U plane first in half pitch followed by 951 //! Vplane in half pitch). For YV12, U and V vertical offsets are block 952 //! aligned; U and Vxoffset = 0; there is no gap between Y, U and V planes 953 //! 954 //! Note that the following datastructures are not specified through the 955 //! media surface state 956 //! 1D buffers for row-store and other miscellaneous information. 957 //! 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, 958 //! ILDB Control and Tcoeff/Stocoeff). 959 //! 960 //! This surface state here is identical to the Surface State for 961 //! deinterlace and sample_8x8messages described in the Shared Function 962 //! Volume and Sampler Chapter. 963 //! For non pixel data,such as row stores, indirect data (Compressed Slice 964 //! Data, AVC MV record, Coeff recordand AVC ILDB record) and streamin/out 965 //! and output compressed bitstream, a linear buffer isemployed. For row 966 //! stores, the H/W is designed to guarantee legal memory accesses (readand 967 //! write). For the remaining cases, indirect object base address, indirect 968 //! objectaddress upper bound, object data start address (offset) and object 969 //! data length are usedto fully specified their corresponding buffer. This 970 //! mechanism is chosen over the pixelsurface type because of their variable 971 //! record sizes. 972 //! All row store surfaces are linear surface.Their addresses are 973 //! programmed in Pipe_Buf_Base_State orBsp_Buf_Base_Addr_State 974 //! 975 //! VC1 I picture scaling: Even though VC1 allows I reconstructed picture 976 //! scaling (via RESPIC), as such scaling is only allowed at I picture. All 977 //! subsequent P (and B) pictures must have the same picture dimensions with 978 //! the preceding I picture. Therefore, all reference pictures for P or B 979 //! picture can share the same surface state with the current P and B 980 //! picture. Note : H/W is not processing RESPIC. Application is no longer 981 //! expecting intel decoder pipelineand kernel to perform this function, it 982 //! is going to be done in the video post-processing scaler or display 983 //! controller scale as a separate step and controller. 984 //! 985 //! All video codec surfaces must be NV12 Compliant, except JPEG. U/V 986 //! vertical must be MB aligned for all video codec (further contrained for 987 //! field picture), but JPEG can be block aligned. All video codec and JPEG 988 //! uses Tiled - Y format only, for uncompressed pixel surfaces. 989 //! 990 //! Even for JPEG planar 420 surface, application may provide only 1 991 //! buffers, but there is still only one single surface state for all of 992 //! them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. 993 //! And U and V will have different offset, each offset is block aligned. 994 //! 995 struct MFX_SURFACE_STATE_CMD 996 { 997 union 998 { 999 struct 1000 { 1001 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1002 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1003 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 1004 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23); //!< SUBOPA 1005 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26); //!< OPCODE 1006 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1007 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1008 }; 1009 uint32_t Value; 1010 } DW0; 1011 union 1012 { 1013 struct 1014 { 1015 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 3); //!< SURFACE_ID 1016 uint32_t Reserved36 : __CODEGEN_BITFIELD(4, 31); //!< Reserved 1017 }; 1018 uint32_t Value; 1019 } DW1; 1020 union 1021 { 1022 struct 1023 { 1024 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD(0, 1); //!< Cr(V)/Cb(U) Pixel Offset V Direction 1025 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 1026 uint32_t Width : __CODEGEN_BITFIELD(4, 17); //!< Width 1027 uint32_t Height : __CODEGEN_BITFIELD(18, 31); //!< Height 1028 }; 1029 uint32_t Value; 1030 } DW2; 1031 union 1032 { 1033 struct 1034 { 1035 uint32_t Tilemode : __CODEGEN_BITFIELD(0, 1); //!< TILEMODE 1036 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(2, 2); //!< Half Pitch for Chroma 1037 uint32_t SurfacePitch : __CODEGEN_BITFIELD(3, 19); //!< Surface Pitch 1038 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 21); //!< Reserved21_20 1039 uint32_t CompressionFormat : __CODEGEN_BITFIELD(22, 25); //!< COMPRESSION_FORMAT 1040 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 1041 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27); //!< INTERLEAVE_CHROMA_ 1042 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31); //!< SURFACE_FORMAT 1043 }; 1044 uint32_t Value; 1045 } DW3; 1046 union 1047 { 1048 struct 1049 { 1050 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD(0, 14); //!< Y Offset for U(Cb) 1051 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1052 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30); //!< X Offset for U(Cb) 1053 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 1054 }; 1055 uint32_t Value; 1056 } DW4; 1057 union 1058 { 1059 struct 1060 { 1061 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(0, 15); //!< Y Offset for V(Cr) 1062 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28); //!< X Offset for V(Cr) 1063 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 1064 }; 1065 uint32_t Value; 1066 } DW5; 1067 1068 //! \name Local enumerations 1069 1070 enum SUBOPB 1071 { 1072 SUBOPB_UNNAMED1 = 1, //!< No additional details 1073 }; 1074 1075 enum SUBOPA 1076 { 1077 SUBOPA_UNNAMED0 = 0, //!< No additional details 1078 }; 1079 1080 enum OPCODE 1081 { 1082 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1083 }; 1084 1085 enum PIPELINE 1086 { 1087 PIPELINE_MFXCOMMON = 2, //!< No additional details 1088 }; 1089 1090 enum COMMAND_TYPE 1091 { 1092 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1093 }; 1094 1095 enum SURFACE_ID 1096 { 1097 SURFACE_ID_DECODEDPICTUREANDREFERENCEPICTURES_SVCUPSAMPLINGSTREAMOUTRECONSTRUCTEDPIXELSCOEFFPRED_UPPERLAYERSIZE = 0, //!< 8-bit uncompressed data 1098 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMOUTSURFACE_UPPERLAYERSIZE = 1, //!< 16-bit uncompressed data 1099 SURFACE_ID_SVCRECONSTRUCTEDPIXELANDCOEFFPREDUPSAMPLINGSTREAMINSURFACE_LOWERLAYERSIZE = 2, //!< 8-bit uncompressed data. 1100 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMINSURFACE_LOWERLAYERSIZE = 3, //!< 16-bit uncompressed data 1101 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 4, //!< 8-bit uncompressed data 1102 SURFACE_ID_RECONSTRUCTEDSCALEDREFERENCEPICTURE = 5, //!< 8-bit data 1103 }; 1104 1105 enum TILEMODE 1106 { 1107 TILEMODE_LINEAR = 0, //!< No additional details 1108 TILEMODE_TILEYS_64K = 1, //!< No additional details 1109 TILEMODE_TILEX = 2, //!< No additional details 1110 TILEMODE_TILEF = 3, //!< No additional details 1111 }; 1112 1113 //! \brief COMPRESSION_FORMAT 1114 //! \details 1115 //! \Specifies the compression format. 1116 enum COMPRESSION_FORMAT 1117 { 1118 COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 1119 COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 1120 COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 1121 COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 1122 COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 1123 COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 1124 COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 1125 COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 1126 COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 1127 COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 1128 COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 1129 COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 1130 COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 1131 }; 1132 1133 //! \brief INTERLEAVE_CHROMA_ 1134 //! \details 1135 //! This field indicates that the chroma fields are interleaved in a single 1136 //! plane rather than stored as two separate planes. This field is only used 1137 //! for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT modes : set to 1138 //! Enable to support interleave U/V only.For JPEG : set to Disable for all 1139 //! formats (including 4:2:0) - because JPEG does not support NV12. (This 1140 //! field is needed only if JPEG will support NV12; otherwise is ignored.) 1141 enum INTERLEAVE_CHROMA_ 1142 { 1143 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 1144 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 1145 }; 1146 1147 //! \brief SURFACE_FORMAT 1148 //! \details 1149 //! Specifies the format of the surface. All of the Y and G channels will 1150 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1.Usage: 1151 //! For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. For 1152 //! monochrome surfaces, hardware ignores control fields for Chroma 1153 //! planes.This field must be set to 4 - PLANAR_420_8, or 12 - Y8_UNORMNot 1154 //! used for MFX, and is ignored. But for JPEG decoding, this field should 1155 //! be programmed to the same format as JPEG_PIC_STATE. For video codec, it 1156 //! should set to 4 always. 1157 enum SURFACE_FORMAT 1158 { 1159 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1160 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1161 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1162 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1163 SURFACE_FORMAT_PLANAR4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1164 SURFACE_FORMAT_PLANAR4118 = 5, //!< Deinterlace Only 1165 SURFACE_FORMAT_PLANAR4228 = 6, //!< Deinterlace Only 1166 SURFACE_FORMAT_STMMDNSTATISTICS = 7, //!< Deinterlace Only 1167 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 Only 1168 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 Only 1169 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 Only 1170 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 Only 1171 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 Only 1172 }; 1173 1174 //! \name Initializations 1175 1176 //! \brief Explicit member initialization function 1177 MFX_SURFACE_STATE_CMD(); 1178 1179 static const size_t dwSize = 6; 1180 static const size_t byteSize = 24; 1181 }; 1182 1183 //! 1184 //! \brief MFX_IND_OBJ_BASE_ADDR_STATE 1185 //! \details 1186 //! This state command provides the memory base addresses for all row 1187 //! stores, StreamOut buffer andreconstructed picture output buffers 1188 //! required by the MFD or MFC Engine (that are in addition tothe row stores 1189 //! of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the reference 1190 //! picture buffers).This is a picture level state command and is common 1191 //! among all codec standards and for both encoderand decoder operating 1192 //! modes. However, some fields may only applicable to a specific codec 1193 //! standard.All Pixel Surfaces (original, reference frame and reconstructed 1194 //! frame) in the Encoder are programmedwith the same surface state (NV12 1195 //! and TileY format), except each has its own frame buffer base address.In 1196 //! the tile format, there is no need to provide buffer offset for each 1197 //! slice; since from each MB address,the hardware can calculated the 1198 //! corresponding memory location within the frame buffer directly. 1199 //! 1200 //! OPEN ??? : ARE WE DOING PER SURFACE UPPERBOUND CHECK OR THE GLOBAL CHECK 1201 //! - YES upper bound check mustalways enabled and restricted to 2G. AR. Sam 1202 //! to confirm with Ricky and update the doc. For encoder,compressed 1203 //! bitstream WRITE, we need to use the linear surface destination buffer. 1204 //! There is no need tohave a global upper bound for linear buffer write, 1205 //! for each linear buffer, there is a size field tocontrol its valid range. 1206 //! 1207 //! The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers 1208 //! for the correspondingIndirect Object Data Start Addresses (Offsets) 1209 //! specified in each OBJECT commands. Thecharacteristic of these indirect 1210 //! object data is their variable size (per MB or per Slice).Hence, each 1211 //! OBJECT command must specify the indirect object data offset from the 1212 //! base addressto start fetching or writing object data. 1213 //! 1214 //! It is an API requirement to support the indirection of certain 1215 //! graphics memory accesses (GTT-mapped). 1216 //! 1217 //! While the use of base address is unconditional, the indirection can be 1218 //! effectively disabled by setting thebase address to zero. For decoder, 1219 //! there are: 1 read-only per-slice indirect object in the BSD_OBJECT 1220 //! Command, and 1221 //! 2 read-only per-MB indirect objects in the IT_OBJECT Command. 1222 //! For decoder: the Video Command Streamer (VCS) will perform the memory 1223 //! access bound check automatically using the corresponding MFC Indirect 1224 //! Object Access Upper Bound specification. If any access is at or 1225 //! beyondthe upper bound, zero value is returned. The request to memory is 1226 //! still being sent, but the corresponding codec's BSD unit will detect 1227 //! this condition and perform the zeroing return. If the Upper Bound is 1228 //! turned off,the beyond bound request will return whatever on the bus 1229 //! (invalid data). For encoder, there are: 1 read-only per-MB indirect 1230 //! object in the PAK_OBJECT Command, and 1231 //! 1 write-only per-slice indirect object in the PAK Slice_State Command 1232 //! For encoder: whenever an out of bound address accessing request is 1233 //! generated, VMX will detect such requests and snap theaddress to the 1234 //! corresponding [indirect object base address + indirect data start 1235 //! address]. VMX will returnall 0s as the data to the requestor. 1236 //! NotationDefinitionPhysicalAddress[n:m] Corresponding bits of a 1237 //! physicalgraphics memory byte address (not mapped by a GTT) 1238 //! GraphicsAddress[n:m] Corresponding bits of an absolute,virtual graphics 1239 //! memory byte address (mapped by a GTT). 1240 //! 1241 struct MFX_IND_OBJ_BASE_ADDR_STATE_CMD 1242 { 1243 union 1244 { 1245 struct 1246 { 1247 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1248 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1249 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 1250 uint32_t SubOpcodea : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODEA 1251 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMON_OPCODE 1252 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1253 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1254 }; 1255 uint32_t Value; 1256 } DW0; 1257 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectBitstreamObjectBaseAddress; //!< DW1..2, MFX Indirect Bitstream Object - Base Address 1258 MEMORYADDRESSATTRIBUTES_CMD MfxIndirectBitstreamObjectAttributes; //!< DW3, MFX Indirect Bitstream Object - Attributes 1259 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectBitstreamObjectUpperBound; //!< DW4..5, MFX Indirect Bitstream Object - Upper Bound 1260 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectMvObjectBaseAddress; //!< DW6..7, MFX Indirect MV Object - Base Address 1261 MEMORYADDRESSATTRIBUTES_CMD MfxIndirectMvObjectAttributes; //!< DW8, MFX Indirect MV Object - Attributes 1262 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectMvObjectUpperBound; //!< DW9..10, MFX Indirect MV Object - Upper Bound 1263 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItCoeffObjectBaseAddress; //!< DW11..12, MFD Indirect IT-COEFF Object - Base Address 1264 MEMORYADDRESSATTRIBUTES_CMD MfdIndirectItCoeffObjectAttributes; //!< DW13, MFD Indirect IT-COEFF Object - Attributes 1265 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItCoeffObjectUpperBound; //!< DW14..15, MFD Indirect IT-COEFF Object - Upper Bound 1266 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItDblkObjectBaseAddress; //!< DW16..17, MFD Indirect IT-DBLK Object - Base Address 1267 MEMORYADDRESSATTRIBUTES_CMD MfdIndirectItDblkObjectAttributes; //!< DW18, MFD Indirect IT-DBLK Object - Attributes 1268 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItDblkObjectUpperBound; //!< DW19..20, MFD Indirect IT-DBLK Object - Upper Bound 1269 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfcIndirectPakBseObjectBaseAddress; //!< DW21..22, MFC Indirect PAK-BSE Object - Base Address 1270 MEMORYADDRESSATTRIBUTES_CMD MfcIndirectPakBseObjectAttributes; //!< DW23, MFC Indirect PAK-BSE Object - Attributes 1271 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfcIndirectPakBseObjectUpperBound; //!< DW24..25, MFC Indirect PAK-BSE Object - Upper Bound 1272 1273 //! \name Local enumerations 1274 1275 enum SUBOPCODEB 1276 { 1277 SUBOPCODEB_MFXINDOBJBASEADDRSTATE = 3, //!< No additional details 1278 }; 1279 1280 enum SUB_OPCODEA 1281 { 1282 SUB_OPCODEA_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1283 }; 1284 1285 enum COMMON_OPCODE 1286 { 1287 COMMON_OPCODE_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1288 }; 1289 1290 enum PIPELINE 1291 { 1292 PIPELINE_MFXINDOBJBASEADDRSTATE = 2, //!< No additional details 1293 }; 1294 1295 enum COMMAND_TYPE 1296 { 1297 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1298 }; 1299 1300 //! \name Initializations 1301 1302 //! \brief Explicit member initialization function 1303 MFX_IND_OBJ_BASE_ADDR_STATE_CMD(); 1304 1305 static const size_t dwSize = 26; 1306 static const size_t byteSize = 104; 1307 }; 1308 1309 //! 1310 //! \brief MFX_BSP_BUF_BASE_ADDR_STATE 1311 //! \details 1312 //! This frame-level state command is used to specify all the buffer base 1313 //! addresses needed for the operation of the AVC Bit Stream Processing 1314 //! Units (for decoder, it is BSD Unit; for encoder, it is BSE Unit)For both 1315 //! encoder and decoder, currently it is assumed that all codec standards 1316 //! can share the same BSP_BUF_BASE_STATE. The simplicity of this command is 1317 //! the result of moving all the direct MV related processing into the ENC 1318 //! Subsystem. Since all implicit weight calculations and directMV 1319 //! calculations are done in ENC and all picture buffer management are done 1320 //! in the Host, there is no need to provide POC (POC List - 1321 //! FieldOrderCntList, CurrPic POC - CurrFieldOrderCnt) information to PAK. 1322 //! For decoder, all the direct mode information are sent in a separate 1323 //! slice-level command (AVC_DIRECTMODE_STATE command).In addition, in 1324 //! Encoder, the row stores for CABAC encoding and MB Parameters 1325 //! Construction (MPC) are combined into one single row store.The row stores 1326 //! specified in this command do not combine with those specified in the 1327 //! MFC_PIPE_BUF_ADDR_STATE command for hardware simplification reason. 1328 //! 1329 struct MFX_BSP_BUF_BASE_ADDR_STATE_CMD 1330 { 1331 union 1332 { 1333 struct 1334 { 1335 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1336 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1337 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 1338 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 1339 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 1340 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1341 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1342 }; 1343 uint32_t Value; 1344 } DW0; 1345 union 1346 { 1347 struct 1348 { 1349 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1350 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite : __CODEGEN_BITFIELD(6, 31); //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write 1351 }; 1352 uint32_t Value; 1353 } DW1; 1354 union 1355 { 1356 struct 1357 { 1358 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD(0, 15); //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write [47:32] 1359 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1360 }; 1361 uint32_t Value; 1362 } DW2; 1363 union 1364 { 1365 struct 1366 { 1367 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 1368 uint32_t BsdMpcRowStoreScratchBufferIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< BSD/MPC Row Store Scratch Buffer - Index to Memory Object Control State (MOCS) Tables 1369 uint32_t BsdMpcRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1370 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 11); //!< Reserved 1371 uint32_t BsdMpcRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1372 uint32_t BsdMpcRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1373 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1374 }; 1375 uint32_t Value; 1376 } DW3; 1377 union 1378 { 1379 struct 1380 { 1381 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1382 uint32_t MprRowStoreScratchBufferBaseAddressReadWriteDecoderOnly : __CODEGEN_BITFIELD(6, 31); //!< MPR Row Store Scratch Buffer Base Address - Read/Write (Decoder Only) 1383 }; 1384 uint32_t Value; 1385 } DW4; 1386 union 1387 { 1388 struct 1389 { 1390 uint32_t MprRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD(0, 15); //!< MPR Row Store Scratch Buffer Base Address - Read/Write [47:32] 1391 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1392 }; 1393 uint32_t Value; 1394 } DW5; 1395 union 1396 { 1397 struct 1398 { 1399 uint32_t Reserved192 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 1400 uint32_t MprRowStoreScratchBufferIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< MPR Row Store Scratch Buffer - Index to Memory Object Control State (MOCS) Tables 1401 uint32_t MprRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1402 uint32_t Reserved201 : __CODEGEN_BITFIELD(9, 11); //!< Reserved 1403 uint32_t MprRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1404 uint32_t MprRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1405 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1406 }; 1407 uint32_t Value; 1408 } DW6; 1409 union 1410 { 1411 struct 1412 { 1413 uint32_t Reserved224 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1414 uint32_t BitplaneReadBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Bitplane Read Buffer Base Address 1415 }; 1416 uint32_t Value; 1417 } DW7; 1418 union 1419 { 1420 struct 1421 { 1422 uint32_t BitplaneReadBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD(0, 15); //!< Bitplane Read Buffer Base Address - Read/Write [47:32] 1423 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1424 }; 1425 uint32_t Value; 1426 } DW8; 1427 union 1428 { 1429 struct 1430 { 1431 uint32_t Reserved288 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 1432 uint32_t BitplaneReadBufferIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< Bitplane Read Buffer - Index to Memory Object Control State (MOCS) Tables 1433 uint32_t BitplaneReadBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL 1434 uint32_t Reserved297 : __CODEGEN_BITFIELD(9, 12); //!< Reserved 1435 uint32_t BitplaneReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE 1436 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1437 }; 1438 uint32_t Value; 1439 } DW9; 1440 1441 //! \name Local enumerations 1442 1443 enum SUBOPCODE_B 1444 { 1445 SUBOPCODE_B_UNNAMED4 = 4, //!< No additional details 1446 }; 1447 1448 enum SUBOPCODE_A 1449 { 1450 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1451 }; 1452 1453 enum MEDIA_COMMAND_OPCODE 1454 { 1455 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1456 }; 1457 1458 enum PIPELINE 1459 { 1460 PIPELINE_PIPELINE = 2, //!< No additional details 1461 }; 1462 1463 enum COMMAND_TYPE 1464 { 1465 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1466 }; 1467 1468 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1469 //! \details 1470 //! This field controls the priority of arbitration used in the GAC/GAM 1471 //! pipeline for this surface. 1472 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1473 { 1474 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1475 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1476 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1477 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1478 }; 1479 1480 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1481 //! \details 1482 //! This field controls if Intra Row Store is going to store inside Media 1483 //! Internal Storage or to LLC. 1484 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1485 { 1486 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1487 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1488 }; 1489 1490 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1491 //! \details 1492 //! For Media Surfaces:This field specifies the tiled resource mode. 1493 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1494 { 1495 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1496 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1497 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1498 }; 1499 1500 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1501 //! \details 1502 //! This field controls the priority of arbitration used in the GAC/GAM 1503 //! pipeline for this surface. 1504 enum MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1505 { 1506 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1507 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1508 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1509 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1510 }; 1511 1512 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1513 //! \details 1514 //! This field controls if Intra Row Store is going to store inside Media 1515 //! Internal Storage or to LLC. 1516 enum MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1517 { 1518 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1519 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1520 }; 1521 1522 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1523 //! \details 1524 //! For Media Surfaces:This field specifies the tiled resource mode. 1525 enum MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1526 { 1527 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1528 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1529 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1530 }; 1531 1532 //! \brief BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL 1533 //! \details 1534 //! This field controls the priority of arbitration used in the GAC/GAM 1535 //! pipeline for this surface. 1536 enum BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL 1537 { 1538 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1539 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1540 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1541 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1542 }; 1543 1544 //! \brief BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE 1545 //! \details 1546 //! For Media Surfaces:This field specifies the tiled resource mode. 1547 enum BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE 1548 { 1549 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1550 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1551 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1552 }; 1553 1554 //! \name Initializations 1555 1556 //! \brief Explicit member initialization function 1557 MFX_BSP_BUF_BASE_ADDR_STATE_CMD(); 1558 1559 static const size_t dwSize = 10; 1560 static const size_t byteSize = 40; 1561 }; 1562 1563 //! 1564 //! \brief MFD_AVC_PICID_STATE 1565 //! \details 1566 //! This is a frame level state command used for both AVC Long and Short 1567 //! Format in VLD mode.PictureID[16] contains the pictureID of each 1568 //! reference picture (16 maximum) so hardware can uniquely identify the 1569 //! reference picture across frames (this will be used for DMV 1570 //! operation).This command will be needed for both short and long format. 1571 //! 1572 struct MFD_AVC_PICID_STATE_CMD 1573 { 1574 union 1575 { 1576 struct 1577 { 1578 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1579 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1580 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 1581 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 1582 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 1583 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1584 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1585 }; 1586 uint32_t Value; 1587 } DW0; 1588 union 1589 { 1590 struct 1591 { 1592 uint32_t PictureidRemappingDisable : __CODEGEN_BITFIELD(0, 0); //!< PICTUREID_REMAPPING_DISABLE 1593 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 1594 }; 1595 uint32_t Value; 1596 } DW1; 1597 uint32_t Pictureidlist1616Bits[8]; //!< PictureIDList[16][16 bits] 1598 1599 //! \name Local enumerations 1600 1601 enum SUBOPCODE_B 1602 { 1603 SUBOPCODE_B_MEDIA = 5, //!< No additional details 1604 }; 1605 1606 enum SUBOPCODE_A 1607 { 1608 SUBOPCODE_A_DEC = 1, //!< No additional details 1609 }; 1610 1611 enum MEDIA_COMMAND_OPCODE 1612 { 1613 MEDIA_COMMAND_OPCODE_MFDAVCDPBSTATE = 1, //!< No additional details 1614 }; 1615 1616 enum PIPELINE 1617 { 1618 PIPELINE_MFXMULTIDW = 2, //!< No additional details 1619 }; 1620 1621 enum COMMAND_TYPE 1622 { 1623 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1624 }; 1625 1626 //! \brief PICTUREID_REMAPPING_DISABLE 1627 //! \details 1628 //! If Picture ID Remapping Disable is "1", PictureIDList will not be used. 1629 enum PICTUREID_REMAPPING_DISABLE 1630 { 1631 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE16BITSPICTUREIDTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE = 0, //!< Desc 1632 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE4BITSFRAMESTOREID_INDEXTOREFFRAMELISTTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE_THISCAUSESDMVLOGICTOFUNCTIONTHESAMEINPROJECTIVBANDBEFORE = 1, //!< Desc 1633 }; 1634 1635 //! \name Initializations 1636 1637 //! \brief Explicit member initialization function 1638 MFD_AVC_PICID_STATE_CMD(); 1639 1640 static const size_t dwSize = 10; 1641 static const size_t byteSize = 40; 1642 }; 1643 1644 //! 1645 //! \brief MFX_AVC_IMG_STATE 1646 //! \details 1647 //! This must be the very first command to issue after the surface state, 1648 //! the pipe select and base address setting commands. This command supports 1649 //! both Long and Short VLD and IT AVC Decoding Interface. 1650 //! 1651 struct MFX_AVC_IMG_STATE_CMD 1652 { 1653 union 1654 { 1655 struct 1656 { 1657 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1658 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1659 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 1660 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 1661 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 1662 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1663 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1664 }; 1665 uint32_t Value; 1666 } DW0; 1667 union 1668 { 1669 struct 1670 { 1671 uint32_t FrameSize : __CODEGEN_BITFIELD(0, 15); //!< Frame Size 1672 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1673 }; 1674 uint32_t Value; 1675 } DW1; 1676 union 1677 { 1678 struct 1679 { 1680 uint32_t FrameWidth : __CODEGEN_BITFIELD(0, 7); //!< Frame Width 1681 uint32_t Reserved72 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 1682 uint32_t FrameHeight : __CODEGEN_BITFIELD(16, 23); //!< Frame Height 1683 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 1684 }; 1685 uint32_t Value; 1686 } DW2; 1687 union 1688 { 1689 struct 1690 { 1691 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 7); //!< Reserved 1692 uint32_t ImgstructImageStructureImgStructure10 : __CODEGEN_BITFIELD(8, 9); //!< IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10 1693 uint32_t WeightedBipredIdc : __CODEGEN_BITFIELD(10, 11); //!< WEIGHTED_BIPRED_IDC 1694 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(12, 12); //!< WEIGHTED_PRED_FLAG 1695 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD(13, 13); //!< RHODOMAIN_RATE_CONTROL_ENABLE 1696 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 1697 uint32_t FirstChromaQpOffset : __CODEGEN_BITFIELD(16, 20); //!< First Chroma QP Offset 1698 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 1699 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 1700 uint32_t SecondChromaQpOffset : __CODEGEN_BITFIELD(24, 28); //!< Second Chroma QP Offset 1701 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 1702 }; 1703 uint32_t Value; 1704 } DW3; 1705 union 1706 { 1707 struct 1708 { 1709 uint32_t Fieldpicflag : __CODEGEN_BITFIELD(0, 0); //!< FIELDPICFLAG 1710 uint32_t Mbaffflameflag : __CODEGEN_BITFIELD(1, 1); //!< MBAFFFLAMEFLAG 1711 uint32_t Framembonlyflag : __CODEGEN_BITFIELD(2, 2); //!< FRAMEMBONLYFLAG 1712 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD(3, 3); //!< TRANSFORM8X8FLAG 1713 uint32_t Direct8X8Infflag : __CODEGEN_BITFIELD(4, 4); //!< DIRECT8X8INFFLAG 1714 uint32_t Constrainedipredflag : __CODEGEN_BITFIELD(5, 5); //!< CONSTRAINEDIPREDFLAG 1715 uint32_t Imgdisposableflag : __CODEGEN_BITFIELD(6, 6); //!< IMGDISPOSABLEFLAG 1716 uint32_t Entropycodingflag : __CODEGEN_BITFIELD(7, 7); //!< ENTROPYCODINGFLAG 1717 uint32_t Mbmvformatflag : __CODEGEN_BITFIELD(8, 8); //!< MBMVFORMATFLAG 1718 uint32_t Reserved137 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 1719 uint32_t Chromaformatidc : __CODEGEN_BITFIELD(10, 11); //!< CHROMAFORMATIDC 1720 uint32_t Mvunpackedflag : __CODEGEN_BITFIELD(12, 12); //!< MVUNPACKEDFLAG 1721 uint32_t Inserttestflag : __CODEGEN_BITFIELD(13, 13); //!< INSERTTESTFLAG 1722 uint32_t Loadslicepointerflag : __CODEGEN_BITFIELD(14, 14); //!< LOADSLICEPOINTERFLAG 1723 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15); //!< MBSTATENABLED 1724 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31); //!< MINFRAMEWSIZE 1725 }; 1726 uint32_t Value; 1727 } DW4; 1728 union 1729 { 1730 struct 1731 { 1732 uint32_t IntrambmaxbitflagIntrambmaxsizereportmask : __CODEGEN_BITFIELD(0, 0); //!< INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK 1733 uint32_t IntermbmaxbitflagIntermbmaxsizereportmask : __CODEGEN_BITFIELD(1, 1); //!< INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK 1734 uint32_t FrameszoverflagFramebitratemaxreportmask : __CODEGEN_BITFIELD(2, 2); //!< FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK 1735 uint32_t FrameszunderflagFramebitrateminreportmask : __CODEGEN_BITFIELD(3, 3); //!< FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK 1736 uint32_t Reserved164 : __CODEGEN_BITFIELD(4, 6); //!< Reserved 1737 uint32_t IntraIntermbipcmflagForceipcmcontrolmask : __CODEGEN_BITFIELD(7, 7); //!< INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK 1738 uint32_t Reserved168 : __CODEGEN_BITFIELD(8, 8); //!< Reserved 1739 uint32_t MbratectrlflagMbLevelRateControlEnablingFlag : __CODEGEN_BITFIELD(9, 9); //!< MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 1740 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11); //!< MINFRAMEWSIZEUNITS 1741 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1742 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16); //!< NONFIRSTPASSFLAG 1743 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 26); //!< Reserved 1744 uint32_t TrellisQuantizationChromaDisableTqchromadisable : __CODEGEN_BITFIELD(27, 27); //!< TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 1745 uint32_t TrellisQuantizationRoundingTqr : __CODEGEN_BITFIELD(28, 30); //!< TRELLIS_QUANTIZATION_ROUNDING_TQR 1746 uint32_t TrellisQuantizationEnabledTqenb : __CODEGEN_BITFIELD(31, 31); //!< TRELLIS_QUANTIZATION_ENABLED_TQENB 1747 }; 1748 uint32_t Value; 1749 } DW5; 1750 union 1751 { 1752 struct 1753 { 1754 uint32_t Intrambmaxsz : __CODEGEN_BITFIELD(0, 11); //!< IntraMbMaxSz 1755 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1756 uint32_t Intermbmaxsz : __CODEGEN_BITFIELD(16, 27); //!< InterMbMaxSz 1757 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 1758 }; 1759 uint32_t Value; 1760 } DW6; 1761 union 1762 { 1763 struct 1764 { 1765 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD(0, 0); //!< VSL_TOP_MB_TRANS8X8FLAG 1766 uint32_t Reserved225 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 1767 }; 1768 uint32_t Value; 1769 } DW7; 1770 union 1771 { 1772 struct 1773 { 1774 uint32_t Slicedeltaqppmax0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQpPMax[0] 1775 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQpMax[1] 1776 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQpMax[2] 1777 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31); //!< SliceDeltaQpMax[3] 1778 }; 1779 uint32_t Value; 1780 } DW8; 1781 union 1782 { 1783 struct 1784 { 1785 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQpMin[0] 1786 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQpMin[1] 1787 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQpMin[2] 1788 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31); //!< SliceDeltaQpMin[3] 1789 }; 1790 uint32_t Value; 1791 } DW9; 1792 union 1793 { 1794 struct 1795 { 1796 uint32_t Framebitratemin : __CODEGEN_BITFIELD(0, 13); //!< FrameBitRateMin 1797 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14); //!< FRAMEBITRATEMINUNITMODE 1798 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15); //!< FRAMEBITRATEMINUNIT 1799 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29); //!< FrameBitRateMax 1800 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30); //!< FRAMEBITRATEMAXUNITMODE 1801 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31); //!< FRAMEBITRATEMAXUNIT_ 1802 }; 1803 uint32_t Value; 1804 } DW10; 1805 union 1806 { 1807 struct 1808 { 1809 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(0, 14); //!< FrameBitRateMinDelta 1810 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1811 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30); //!< FRAMEBITRATEMAXDELTA 1812 uint32_t SliceStatsStreamoutEnable : __CODEGEN_BITFIELD(31, 31); //!< Slice Stats Streamout Enable 1813 }; 1814 uint32_t Value; 1815 } DW11; 1816 union 1817 { 1818 struct 1819 { 1820 uint32_t Reserved384 : __CODEGEN_BITFIELD(0, 16); //!< Reserved 1821 uint32_t Reserved401 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 1822 uint32_t VadErrorLogic : __CODEGEN_BITFIELD(18, 18); //!< VAD_ERROR_LOGIC 1823 uint32_t Reserved403 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 1824 uint32_t VmdErrorLogic : __CODEGEN_BITFIELD(20, 20); //!< VMD_ERROR_LOGIC 1825 uint32_t Reserved405 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 1826 }; 1827 uint32_t Value; 1828 } DW12; 1829 union 1830 { 1831 struct 1832 { 1833 uint32_t InitialQpValue : __CODEGEN_BITFIELD(0, 7); //!< Initial QP Value 1834 uint32_t NumberOfActiveReferencePicturesFromL0 : __CODEGEN_BITFIELD(8, 13); //!< Number of Active Reference Pictures from L0 1835 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 1836 uint32_t NumberOfActiveReferencePicturesFromL1 : __CODEGEN_BITFIELD(16, 21); //!< Number of Active Reference Pictures from L1 1837 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 1838 uint32_t NumberOfReferenceFrames : __CODEGEN_BITFIELD(24, 28); //!< Number of Reference Frames 1839 uint32_t CurrentPictureHasPerformedMmco5 : __CODEGEN_BITFIELD(29, 29); //!< Current Picture Has Performed MMCO5 1840 uint32_t Reserved446 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 1841 }; 1842 uint32_t Value; 1843 } DW13; 1844 union 1845 { 1846 struct 1847 { 1848 uint32_t PicOrderPresentFlag : __CODEGEN_BITFIELD(0, 0); //!< Pic_order_present_flag 1849 uint32_t DeltaPicOrderAlwaysZeroFlag : __CODEGEN_BITFIELD(1, 1); //!< Delta_pic_order_always_zero_flag 1850 uint32_t PicOrderCntType : __CODEGEN_BITFIELD(2, 3); //!< Pic_order_cnt_type 1851 uint32_t Reserved452 : __CODEGEN_BITFIELD(4, 7); //!< Reserved 1852 uint32_t SliceGroupMapType : __CODEGEN_BITFIELD(8, 10); //!< slice_group_map_type 1853 uint32_t RedundantPicCntPresentFlag : __CODEGEN_BITFIELD(11, 11); //!< redundant_pic_cnt_present_flag 1854 uint32_t NumSliceGroupsMinus1 : __CODEGEN_BITFIELD(12, 14); //!< num_slice_groups_minus1 1855 uint32_t DeblockingFilterControlPresentFlag : __CODEGEN_BITFIELD(15, 15); //!< deblocking_filter_control_present_flag 1856 uint32_t Log2MaxFrameNumMinus4 : __CODEGEN_BITFIELD(16, 23); //!< Log2_max_frame_num_minus4 1857 uint32_t Log2MaxPicOrderCntLsbMinus4 : __CODEGEN_BITFIELD(24, 31); //!< Log2_max_pic_order_cnt_lsb_minus4 1858 }; 1859 uint32_t Value; 1860 } DW14; 1861 union 1862 { 1863 struct 1864 { 1865 uint32_t SliceGroupChangeRate : __CODEGEN_BITFIELD(0, 15); //!< Slice Group Change Rate 1866 uint32_t CurrPicFrameNum : __CODEGEN_BITFIELD(16, 31); //!< Curr Pic Frame Num 1867 }; 1868 uint32_t Value; 1869 } DW15; 1870 union 1871 { 1872 struct 1873 { 1874 uint32_t CurrentFrameViewId : __CODEGEN_BITFIELD(0, 9); //!< Current Frame View ID 1875 uint32_t Reserved522 : __CODEGEN_BITFIELD(10, 11); //!< Reserved 1876 uint32_t MaxViewIdxl0 : __CODEGEN_BITFIELD(12, 15); //!< Max View IDXL0 1877 uint32_t Reserved528 : __CODEGEN_BITFIELD(16, 17); //!< Reserved 1878 uint32_t MaxViewIdxl1 : __CODEGEN_BITFIELD(18, 21); //!< Max View IDXL1 1879 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 30); //!< Reserved 1880 uint32_t InterViewOrderDisable : __CODEGEN_BITFIELD(31, 31); //!< INTER_VIEW_ORDER_DISABLE 1881 }; 1882 uint32_t Value; 1883 } DW16; 1884 union 1885 { 1886 struct 1887 { 1888 uint32_t FractionalQpInput : __CODEGEN_BITFIELD(0, 2); //!< Fractional QP input 1889 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD(3, 5); //!< Fractional QP offset 1890 uint32_t Reserved550 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 1891 uint32_t ExtendedRhodomainStatisticsEnable : __CODEGEN_BITFIELD(8, 8); //!< Extended RhoDomain Statistics Enable 1892 uint32_t Reserved553 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 1893 uint32_t RhodomainAveragemacroblockqp : __CODEGEN_BITFIELD(16, 21); //!< RhoDomain AverageMacroblockQP 1894 uint32_t Reserved566 : __CODEGEN_BITFIELD(22, 31); //!< Reserved 1895 }; 1896 uint32_t Value; 1897 } DW17; 1898 union 1899 { 1900 struct 1901 { 1902 uint32_t Reserved576; //!< Reserved 1903 }; 1904 uint32_t Value; 1905 } DW18; 1906 union 1907 { 1908 struct 1909 { 1910 uint32_t ThresholdSizeInBytes; //!< Threshold Size in Bytes 1911 }; 1912 uint32_t Value; 1913 } DW19; 1914 union 1915 { 1916 struct 1917 { 1918 uint32_t TargetSliceSizeInBytes; //!< Target Slice Size in Bytes 1919 }; 1920 uint32_t Value; 1921 } DW20; 1922 1923 //! \name Local enumerations 1924 1925 enum SUBOPCODE_B 1926 { 1927 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 1928 }; 1929 1930 enum SUBOPCODE_A 1931 { 1932 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1933 }; 1934 1935 enum MEDIA_COMMAND_OPCODE 1936 { 1937 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 1938 }; 1939 1940 enum PIPELINE 1941 { 1942 PIPELINE_MFXAVCIMGSTATE = 2, //!< No additional details 1943 }; 1944 1945 enum COMMAND_TYPE 1946 { 1947 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1948 }; 1949 1950 //! \brief IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10 1951 //! \details 1952 //! The current encoding picture structure can only takes on 3 possible 1953 //! values 1954 enum IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10 1955 { 1956 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_FRAMEPICTURE = 0, //!< No additional details 1957 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_TOPFIELDPICTURE = 1, //!< No additional details 1958 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_INVALID_NOTALLOWED = 2, //!< No additional details 1959 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_BOTTOMFIELDPICTURE = 3, //!< No additional details 1960 }; 1961 1962 //! \brief WEIGHTED_BIPRED_IDC 1963 //! \details 1964 //! (This field is defined differently from DevSNB; DevIVB follows strictly 1965 //! AVC interface.) 1966 enum WEIGHTED_BIPRED_IDC 1967 { 1968 WEIGHTED_BIPRED_IDC_DEFAULT = 0, //!< Specifies that the default weighted prediction is used for B slices 1969 WEIGHTED_BIPRED_IDC_EXPLICIT = 1, //!< Specifies that explicit weighted prediction is used for B slices 1970 WEIGHTED_BIPRED_IDC_IMPLICIT = 2, //!< Specifies that implicit weighted prediction is used for B slices. 1971 }; 1972 1973 //! \brief WEIGHTED_PRED_FLAG 1974 //! \details 1975 //! (This field is defined differently from Gen6, Gen7 follows strictly AVC 1976 //! interface.) 1977 enum WEIGHTED_PRED_FLAG 1978 { 1979 WEIGHTED_PRED_FLAG_DISABLE = 0, //!< specifies that weighted prediction is not used for P and SP slices 1980 WEIGHTED_PRED_FLAG_ENABLE = 1, //!< specifies that weighted prediction is used for P and SP slices 1981 }; 1982 1983 //! \brief RHODOMAIN_RATE_CONTROL_ENABLE 1984 //! \details 1985 //! This field indicates if RhoDomain related parameters are present in the 1986 //! MFX_AVC_IMAGE_STATE. (AverageMacroblockQP). It enables the Rho Domain 1987 //! statistics collection. 1988 enum RHODOMAIN_RATE_CONTROL_ENABLE 1989 { 1990 RHODOMAIN_RATE_CONTROL_ENABLE_DISABLE = 0, //!< RhoDomain rate control parameters are not present in MFX_AVC_IMAGE_STATE 1991 RHODOMAIN_RATE_CONTROL_ENABLE_ENABLE = 1, //!< RhoDomain rate control parameters are present in MFX_AVC_IMAGE_STATE. 1992 }; 1993 1994 //! \brief FIELDPICFLAG 1995 //! \details 1996 //! Field picture flag, field_pic_flag, specifies the current slice is a 1997 //! coded field or not.It is set to the same value as the syntax element in 1998 //! the Slice Header. It must be consistent with the img_structure[1:0] and 1999 //! the frame_mbs_only_flag settings.Although field_pic_flag is a Slice 2000 //! Header parameter, its value is expected to be the same for all the 2001 //! slices of a picture. 2002 enum FIELDPICFLAG 2003 { 2004 FIELDPICFLAG_FRAME = 0, //!< a slice of a coded frame 2005 FIELDPICFLAG_FIELD = 1, //!< a slice of a coded field 2006 }; 2007 2008 //! \brief MBAFFFLAMEFLAG 2009 //! \details 2010 //! MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag 2011 //! = (mb_adaptive_frame_field_flag && ! field_pic_flag ). 2012 //! mb_adaptive_frame_field_flag is a syntax element in the current active 2013 //! SPS and field_pic_flag is a syntax element in the current Slice Header. 2014 //! They both are present only if frame_mbs_only_flag is 0. Although 2015 //! mbaff_frame_flag is a Slice Header parameter, its value is expected to 2016 //! be the same for all the slices of a picture.It must be consistent with 2017 //! the mb_adaptive_frame_field_flag, the field_pic_flag and the 2018 //! frame_mbs_only_flag settings.This bit is valid only when the 2019 //! img_structure[1:0] indicates the current picture is a frame. 2020 enum MBAFFFLAMEFLAG 2021 { 2022 MBAFFFLAMEFLAG_FALSE = 0, //!< not in MBAFF mode 2023 MBAFFFLAMEFLAG_TRUE = 1, //!< in MBAFF mode 2024 }; 2025 2026 //! \brief FRAMEMBONLYFLAG 2027 //! \details 2028 //! Frame MB only flag, frame_mbs_only_flagIt is set to the value of the 2029 //! syntax element in the current active SPS. 2030 enum FRAMEMBONLYFLAG 2031 { 2032 FRAMEMBONLYFLAG_FALSE = 0, //!< not true ; effectively enables the possibility of MBAFF mode. 2033 FRAMEMBONLYFLAG_TRUE = 1, //!< true, only frame MBs can occur in this sequence, hence disallows the MBAFF mode and field picture. 2034 }; 2035 2036 //! \brief TRANSFORM8X8FLAG 2037 //! \details 2038 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT 2039 //! transform may be used in this pictureIt is set to the value of the 2040 //! syntax element in the current active PPS. 2041 enum TRANSFORM8X8FLAG 2042 { 2043 TRANSFORM8X8FLAG_4X4 = 0, //!< no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present 2044 TRANSFORM8X8FLAG_8X8 = 1, //!< 8x8 Transform is allowed 2045 }; 2046 2047 //! \brief DIRECT8X8INFFLAG 2048 //! \details 2049 //! Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the 2050 //! value of the syntax element in the current active SPS.It specifies the 2051 //! derivation process for luma motion vectors in the Direct MV coding modes 2052 //! (B_Skip, B_Direct_16x16 and B_Direct_8x8). When frame_mbs_only_flag is 2053 //! equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be 2054 //! consistent with the frame_mbs_only_flag and transform_8x8_mode_flag 2055 //! settings. 2056 enum DIRECT8X8INFFLAG 2057 { 2058 DIRECT8X8INFFLAG_SUBBLOCK = 0, //!< allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or 4x8) 2059 DIRECT8X8INFFLAG_BLOCK = 1, //!< allows processing only at 8x8 block size. MB Info is stored for 8x8 block size. 2060 }; 2061 2062 //! \brief CONSTRAINEDIPREDFLAG 2063 //! \details 2064 //! Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to 2065 //! the value of the syntax element in the current active PPS. 2066 enum CONSTRAINEDIPREDFLAG 2067 { 2068 CONSTRAINEDIPREDFLAG_INTRAANDINTER = 0, //!< allows both intra and inter neighboring MB to be used in the intra-prediction encoding of the current MB. 2069 CONSTRAINEDIPREDFLAG_INTRAONLY = 1, //!< allows only to use neighboring Intra MBs in the intra-prediction encoding of the current MB. If the neighbor is an inter MB, it is considered as not available. 2070 }; 2071 2072 //! \brief IMGDISPOSABLEFLAG 2073 //! \details 2074 //! Current Img Disposable Flag or Non-Reference Picture Flag 2075 enum IMGDISPOSABLEFLAG 2076 { 2077 IMGDISPOSABLEFLAG_REFERENCE = 0, //!< the current decoding picture may be used as a reference picture for others 2078 IMGDISPOSABLEFLAG_DISPOSABLE = 1, //!< the current decoding picture is not used as a reference picture (e.g. a B-picture cannot be a reference picture for any subsequent decoding) 2079 }; 2080 2081 //! \brief ENTROPYCODINGFLAG 2082 //! \details 2083 //! Entropy Coding Flag, entropy_coding_flag 2084 enum ENTROPYCODINGFLAG 2085 { 2086 ENTROPYCODINGFLAG_CAVLCBIT_SERIALENCODINGMODE = 0, //!< Desc 2087 ENTROPYCODINGFLAG_CABACBIT_SERIALENCODINGMODE = 1, //!< Desc 2088 }; 2089 2090 //! \brief MBMVFORMATFLAG 2091 //! \details 2092 //! Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero 2093 //! in IVB:GT2:A0) 2094 enum MBMVFORMATFLAG 2095 { 2096 MBMVFORMATFLAG_IGNORE = 0, //!< HW PAK ignore MvFormat in the MB data. 2097 MBMVFORMATFLAG_FOLLOW = 1, //!< HW PAK will follow MvFormat value set within each MB data. 2098 }; 2099 2100 //! \brief CHROMAFORMATIDC 2101 //! \details 2102 //! Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of 2103 //! chroma component (Cb, Cr) in the current picture as follows : 2104 enum CHROMAFORMATIDC 2105 { 2106 CHROMAFORMATIDC_MONOCHROMEPICTURE = 0, //!< Desc 2107 CHROMAFORMATIDC_420PICTURE = 1, //!< Desc 2108 CHROMAFORMATIDC_422PICTURE_NOTSUPPORTED = 2, //!< No additional details 2109 CHROMAFORMATIDC_444PICTURE_NOTSUPPORTED = 3, //!< No additional details 2110 }; 2111 2112 //! \brief MVUNPACKEDFLAG 2113 //! \details 2114 //! MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. 2115 enum MVUNPACKEDFLAG 2116 { 2117 MVUNPACKEDFLAG_PACKED = 0, //!< use packed MV format 2118 MVUNPACKEDFLAG_UNPACKED = 1, //!< use unpacked 8MV/32MV format only 2119 }; 2120 2121 //! \brief INSERTTESTFLAG 2122 //! \details 2123 //! CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 2124 //! CABAC K equation so that a positive K value can be generated easily. 2125 //! This is done for validation purpose only. In normal usage this bit 2126 //! should be set to 0.Regular equation for generating 'K' value when CABAC 2127 //! 0 Word Insertion Test Enable is set to 0.K = { [ ((96 * pic_bin_count()) 2128 //! - (RawMbBits * PicSizeInMbs *3) + 1023) / 1024 ] - bytes_in_picture } / 2129 //! 3Modified equation when CABAC 0 Word Insertion Test Enable bit set to 2130 //! 1.K = { [ ((3072 * pic_bin_count()) - (RawMbBits * PicSizeInMbs *3) + 2131 //! 1023) / 1024 ] - bytes_in_picture } / 3 2132 enum INSERTTESTFLAG 2133 { 2134 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 2135 }; 2136 2137 //! \brief LOADSLICEPOINTERFLAG 2138 //! \details 2139 //! LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice 2140 //! picture and additional header/data insertion before and after an encoded 2141 //! slice.When this field is set to 0, bitstream pointer is only loaded once 2142 //! for the first slice of a frame. For subsequent slices in the frame, 2143 //! bitstream data are stitched together to form a single output data 2144 //! stream.When this field is set to 1, bitstream pointer is loaded for each 2145 //! slice of a frame. Basically bitstream data for different slices of a 2146 //! frame will be written to different memory locations. 2147 enum LOADSLICEPOINTERFLAG 2148 { 2149 LOADSLICEPOINTERFLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame 2150 LOADSLICEPOINTERFLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 2151 }; 2152 2153 //! \brief MBSTATENABLED 2154 //! \details 2155 //! Enable reading in MB status buffer (a.k.a. encoding stream-out 2156 //! buffer) Note: For multi-pass encoder, all passes except the first one 2157 //! need to set this value to 1. By setting the first pass to 0, it does 2158 //! save some memory bandwidth. <span 2159 //! style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; line-height: 2160 //! normal;">In VDenc mode this must be set to zero as no MB level rate 2161 //! control is used. 2162 enum MBSTATENABLED 2163 { 2164 MBSTATENABLED_DISABLE = 0, //!< Disable Reading of Macroblock Status Buffer 2165 MBSTATENABLED_ENABLE = 1, //!< Enable Reading of Macroblock Status Buffer 2166 }; 2167 2168 //! \brief MINFRAMEWSIZE 2169 //! \details 2170 //! Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder 2171 //! Only) Minimum Frame Size is specified to compensate for intel Rate 2172 //! Control Currently zero fill (no need to perform emulation byte 2173 //! insertion) is done only to the end of the CABAC_ZERO_WORD insertion (if 2174 //! any) at the last slice of a picture. Intel encoder parameter. The caller 2175 //! should always make sure that the value, represented by Minimum Frame 2176 //! Size, is always less than maximum frame size FrameBitRateMax (DWORD 2177 //! 10 bits 29:16). This field is reserved in Decode mode. 2178 //! The programmable range 02^18-1 When 2179 //! MinFrameWSizeUnits is 00. Programmable range is 02^20-1 2180 //! when MinFrameWSizeUnits is 01. Programmable range is 2181 //! 02^26-1 when MinFrameWSizeUnits is 10. Programmable 2182 //! range is 02^32-1 when MinFrameWSizeUnits is 11. 2183 enum MINFRAMEWSIZE 2184 { 2185 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 2186 }; 2187 2188 //! \brief INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK 2189 //! \details 2190 //! This is a mask bit controlling if the condition of any intra MB in the 2191 //! frame exceeds IntraMBMaxSize. 2192 enum INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK 2193 { 2194 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2195 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_ENABLE = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 2196 }; 2197 2198 //! \brief INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK 2199 //! \details 2200 //! This is a mask bit controlling if the condition of any inter MB in the 2201 //! frame exceeds InterMBMaxSize. 2202 enum INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK 2203 { 2204 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2205 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 2206 }; 2207 2208 //! \brief FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK 2209 //! \details 2210 //! This is a mask bit controlling if the condition of frame level bit count 2211 //! exceeds FrameBitRateMax. 2212 enum FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK 2213 { 2214 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2215 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 2216 }; 2217 2218 //! \brief FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK 2219 //! \details 2220 //! This is a mask bit controlling if the condition of frame level bit count 2221 //! is less than FrameBitRateMin 2222 enum FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK 2223 { 2224 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2225 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 2226 }; 2227 2228 //! \brief INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK 2229 //! \details 2230 //! This field is to Force IPCM for Intra or Inter Macroblock size 2231 //! conformance mask. 2232 enum INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK 2233 { 2234 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_DISABLE = 0, //!< Do not change intra or Inter macroblocks even 2235 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_ENABLE = 1, //!< Change intra or Inter macroblocks MB_type to IPCM 2236 }; 2237 2238 //! \brief MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2239 //! \details 2240 //! MB Rate Control conformance mask In VDenc mode, this 2241 //! field must be zero as frame level rate control is used. 2242 enum MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2243 { 2244 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_DISABLE = 0, //!< Apply accumulative delta QP for consecutive passes on top of the macroblock QP values in inline data 2245 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_ENABLE = 1, //!< Apply RC QP delta to suggested QP values in Macroblock Status Buffer except the first pass. 2246 }; 2247 2248 //! \brief MINFRAMEWSIZEUNITS 2249 //! \details 2250 //! This field is the Minimum Frame Size Units 2251 enum MINFRAMEWSIZEUNITS 2252 { 2253 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 2254 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 2255 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 2256 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 2257 }; 2258 2259 //! \brief NONFIRSTPASSFLAG 2260 //! \details 2261 //! This signals the current pass is not the first pass. It will imply 2262 //! designate HW behavior: e.g 2263 enum NONFIRSTPASSFLAG 2264 { 2265 NONFIRSTPASSFLAG_DISABLE = 0, //!< Always use the MbQpY from initial PAK inline object for all passes of PAK 2266 NONFIRSTPASSFLAG_ENABLE = 1, //!< Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 2267 }; 2268 2269 //! \brief TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2270 //! \details 2271 //! This signal is used to disable chroma TQ. To enable TQ for both luma and 2272 //! chroma, TQEnb=1, TQChromaDisable=0. To enable TQ only for luma, TQEnb=1, 2273 //! TQChromaDisable=1. 2274 enum TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2275 { 2276 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_UNNAMED0 = 0, //!< Enable Trellis Quantization chroma 2277 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_DEFAULT = 1, //!< Disable Trellis Quantization chroma 2278 }; 2279 2280 //! \brief TRELLIS_QUANTIZATION_ROUNDING_TQR 2281 //! \details 2282 //! This rounding scheme is only applied to the quantized coefficients 2283 //! ranging from 0 to 1 when TQEnb is set to 1 in AVC CABAC mode. One of the 2284 //! following values is added to quantized coefficients before truncating 2285 //! fractional part. 2286 enum TRELLIS_QUANTIZATION_ROUNDING_TQR 2287 { 2288 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED0 = 0, //!< Add 1/8 2289 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED1 = 1, //!< Add 2/8 2290 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED2 = 2, //!< Add 3/8 2291 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED3 = 3, //!< Add 4/8 (rounding 0.5) 2292 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED4 = 4, //!< Add 5/8 2293 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED5 = 5, //!< Add 6/8 2294 TRELLIS_QUANTIZATION_ROUNDING_TQR_DEFAULT = 6, //!< Add 7/8 (Default rounding 0.875) 2295 }; 2296 2297 //! \brief TRELLIS_QUANTIZATION_ENABLED_TQENB 2298 //! \details 2299 //! The TQ improves output video quality of AVC CABAC encoder by selecting 2300 //! quantized values for each non-zero coefficient so as to minimize the 2301 //! total R-D cost.This flag is only valid AVC CABAC mode. Otherwise, this 2302 //! flag should be disabled. 2303 enum TRELLIS_QUANTIZATION_ENABLED_TQENB 2304 { 2305 TRELLIS_QUANTIZATION_ENABLED_TQENB_DISABLE = 0, //!< Use Normal 2306 TRELLIS_QUANTIZATION_ENABLED_TQENB_ENABLE = 1, //!< Use Trellis quantization 2307 }; 2308 2309 enum VSL_TOP_MB_TRANS8X8FLAG 2310 { 2311 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 2312 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 2313 }; 2314 2315 //! \brief FRAMEBITRATEMINUNITMODE 2316 //! \details 2317 //! This field is the Frame Bitrate Minimum Limit Units. 2318 enum FRAMEBITRATEMINUNITMODE 2319 { 2320 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2321 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2322 }; 2323 2324 //! \brief FRAMEBITRATEMINUNIT 2325 //! \details 2326 //! This field is the Frame Bitrate Minimum Limit Units. 2327 enum FRAMEBITRATEMINUNIT 2328 { 2329 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 2330 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2331 }; 2332 2333 //! \brief FRAMEBITRATEMAXUNITMODE 2334 //! \details 2335 //! This field is the Frame Bitrate Maximum Limit Units. 2336 enum FRAMEBITRATEMAXUNITMODE 2337 { 2338 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2339 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2340 }; 2341 2342 //! \brief FRAMEBITRATEMAXUNIT_ 2343 //! \details 2344 //! This field is the Frame Bitrate Maximum Limit Units. 2345 enum FRAMEBITRATEMAXUNIT_ 2346 { 2347 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 2348 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2349 }; 2350 2351 //! \brief FRAMEBITRATEMAXDELTA 2352 //! \details 2353 //! This field is used to select the slice delta QP when FrameBitRateMax Is 2354 //! exceeded. It shares the same FrameBitrateMaxUnit. When 2355 //! FrameBitrateMaxUnitMode is 0(compatibility mode), only bits 16:27 should 2356 //! be used, bits 28, 29 and 30 should be 0. 2357 enum FRAMEBITRATEMAXDELTA 2358 { 2359 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 2360 }; 2361 2362 enum VAD_ERROR_LOGIC 2363 { 2364 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 2365 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 2366 }; 2367 2368 enum VMD_ERROR_LOGIC 2369 { 2370 VMD_ERROR_LOGIC_DISABLE = 0, //!< No additional details 2371 VMD_ERROR_LOGIC_ENABLE = 1, //!< Error Handling 2372 }; 2373 2374 //! \brief INTER_VIEW_ORDER_DISABLE 2375 //! \details 2376 //! It indicates how to append inter-view picture into initial sorted 2377 //! reference list. (due to ambiguity in the MVC Spec) 2378 enum INTER_VIEW_ORDER_DISABLE 2379 { 2380 INTER_VIEW_ORDER_DISABLE_DEFAULT = 0, //!< View Order Ascending 2381 INTER_VIEW_ORDER_DISABLE_DISABLE = 1, //!< View ID Ascending 2382 }; 2383 2384 //! \name Initializations 2385 2386 //! \brief Explicit member initialization function 2387 MFX_AVC_IMG_STATE_CMD(); 2388 2389 static const size_t dwSize = 21; 2390 static const size_t byteSize = 84; 2391 }; 2392 2393 //! 2394 //! \brief MFX_AVC_REF_IDX_STATE 2395 //! \details 2396 //! This is a slice level command and can be issued multiple times within a 2397 //! picture that is comprised of multiple slices. The same command is used 2398 //! for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in 2399 //! decoder IT mode. The inline data of this command is interpreted 2400 //! differently for encoder as for decoder. For decoder, it is interpreted 2401 //! as RefIdx List L0/L1 as in AVC spec., and it matches with the AVC API 2402 //! data structure for decoder in VLD mode : RefPicList[2][32] (L0:L1, 0:31 2403 //! RefPic). But for encoder, it is interpreted as a Reference Index 2404 //! Mapping Table for L0 and L1 reference pictures. For packing the bits at 2405 //! the output of PAK, the syntax elements must follow the definition of 2406 //! RefIdxL0/L1 list according to the AVC spec. However, the decoder 2407 //! pipeline was designed to use a variation of that standard definition, as 2408 //! such a conversion (mapping) is needed to support the hardware design.The 2409 //! Reference lists are needed in processing both P and B slice in AVC 2410 //! codec. For P-MB, only L0 list is used; for B-MB both L0 and L1 lists are 2411 //! needed. For a B-MB that is coded in L1-only Prediction, only L1 list is 2412 //! used. 2413 //! 2414 //! An application will create the RefPicList L0 and L1 and pass onto the 2415 //! driver. The content of each entry of RefPicList L0/L1[ ] is a 7-bit 2416 //! picture index. This picture index is the same as that of RefFrameList[ 2417 //! ] content. This picture index, however, is not defined the same as the 2418 //! frame store ID (0 to 16, 5-bits) we have implemented in H/W. Hence, 2419 //! driver is required to manage a table to convert between picture index 2420 //! and intel frame store ID. As such, the final RefPicList L0/L1[ ] that 2421 //! the driver passes onto the H/W is not the same as that defined. 2422 //! 2423 struct MFX_AVC_REF_IDX_STATE_CMD 2424 { 2425 union 2426 { 2427 struct 2428 { 2429 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 2430 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2431 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 2432 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 2433 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMAND_OPCODE 2434 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 2435 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 2436 }; 2437 uint32_t Value; 2438 } DW0; 2439 union 2440 { 2441 struct 2442 { 2443 uint32_t RefpiclistSelect : __CODEGEN_BITFIELD(0, 0); //!< REFPICLIST_SELECT 2444 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 2445 }; 2446 uint32_t Value; 2447 } DW1; 2448 uint32_t ReferenceListEntry[8]; //!< Reference List Entry 2449 2450 //! \name Local enumerations 2451 2452 enum SUBOPCODEB 2453 { 2454 SUBOPCODEB_MFXAVCREFIDXSTATE = 4, //!< No additional details 2455 }; 2456 2457 enum SUBOPCODEA 2458 { 2459 SUBOPCODEA_MFXAVCREFIDXSTATE = 0, //!< No additional details 2460 }; 2461 2462 enum COMMAND_OPCODE 2463 { 2464 COMMAND_OPCODE_AVC = 1, //!< No additional details 2465 }; 2466 2467 enum PIPELINE 2468 { 2469 PIPELINE_MFXAVCREFIDXSTATE = 2, //!< No additional details 2470 }; 2471 2472 enum COMMAND_TYPE 2473 { 2474 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2475 }; 2476 2477 //! \brief REFPICLIST_SELECT 2478 //! \details 2479 //! Num_ref_idx_l1_active is resulted from the specifications in both PPS 2480 //! and Slice Header for the current slice. However, since the full 2481 //! reference list L0 and/or L1 are always sent, only present flags are 2482 //! specified instead. This parameter is specified for Intel 2483 //! interface only. 2484 enum REFPICLIST_SELECT 2485 { 2486 REFPICLIST_SELECT_REFPICLIST0 = 0, //!< The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx Mapping Table L0 (Encoder PAK mode) 2487 REFPICLIST_SELECT_REFPICLIST1 = 1, //!< The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx Mapping Table L1 (Encoder PAK mode) 2488 }; 2489 2490 //! \name Initializations 2491 2492 //! \brief Explicit member initialization function 2493 MFX_AVC_REF_IDX_STATE_CMD(); 2494 2495 static const size_t dwSize = 10; 2496 static const size_t byteSize = 40; 2497 }; 2498 2499 //! 2500 //! \brief MFX_AVC_WEIGHTOFFSET_STATE 2501 //! \details 2502 //! This is a slice level command and can be issued multiple times within a 2503 //! picture that is comprised of multiple slices. The same command is used 2504 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, 2505 //! since for AVC decoder VLD and IT modes, and AVC encoder mode, the 2506 //! implicit weights are computed in hardware, this command is not issued. 2507 //! For encoder, regardless of the type of weight calculation is active for 2508 //! the current slice (default, implicit or explicit), they are all sent to 2509 //! the PAK as if they were all in explicit mode. However, for implicit 2510 //! weight and offset, each entry contains only a 16-bit weight and no 2511 //! offset (offset = 0 always in implicit mode and can be hard-coded inside 2512 //! the hardware).The weights (and offsets) are needed in processing both P 2513 //! and B slice in AVC codec. For P-MB, at most only L0 list is used; for 2514 //! B-MB both L0 and L1 lists may be needed. For a B-MB that is coded in 2515 //! L1-only Prediction, only L1 list is sent.The content of this command 2516 //! matches with the AVC API data structure for explicit prediction mode 2517 //! only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) 2518 //! 2519 struct MFX_AVC_WEIGHTOFFSET_STATE_CMD 2520 { 2521 union 2522 { 2523 struct 2524 { 2525 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 2526 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2527 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 2528 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 2529 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 2530 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 2531 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 2532 }; 2533 uint32_t Value; 2534 } DW0; 2535 union 2536 { 2537 struct 2538 { 2539 uint32_t WeightAndOffsetSelect : __CODEGEN_BITFIELD(0, 0); //!< WEIGHT_AND_OFFSET_SELECT 2540 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 2541 }; 2542 uint32_t Value; 2543 } DW1; 2544 uint32_t Weightoffset[96]; //!< WeightOffset 2545 2546 //! \name Local enumerations 2547 2548 enum SUBOPCODE_B 2549 { 2550 SUBOPCODE_B_UNNAMED5 = 5, //!< No additional details 2551 }; 2552 2553 enum SUBOPCODE_A 2554 { 2555 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2556 }; 2557 2558 enum MEDIA_COMMAND_OPCODE 2559 { 2560 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2561 }; 2562 2563 enum PIPELINE 2564 { 2565 PIPELINE_MFXAVCWEIGHTOFFSETSTATE = 2, //!< No additional details 2566 }; 2567 2568 enum COMMAND_TYPE 2569 { 2570 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2571 }; 2572 2573 //! \brief WEIGHT_AND_OFFSET_SELECT 2574 //! \details 2575 //! It must be set in consistent with the WeightedPredFlag and 2576 //! WeightedBiPredIdc in the Img_State command.This parameter is specified 2577 //! for Intel interface only. For implicit even though only one entry may be 2578 //! used, still loading the whole 32-entry table. 2579 enum WEIGHT_AND_OFFSET_SELECT 2580 { 2581 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL0TABLE = 0, //!< The list that followed is associated with the weight and offset for RefPicList L0 2582 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL1TABLE = 1, //!< The list that followed is associated with the weight and offset for RefPicList L1 2583 }; 2584 2585 //! \name Initializations 2586 2587 //! \brief Explicit member initialization function 2588 MFX_AVC_WEIGHTOFFSET_STATE_CMD(); 2589 2590 static const size_t dwSize = 98; 2591 static const size_t byteSize = 392; 2592 }; 2593 2594 //! 2595 //! \brief MFX_AVC_SLICE_STATE 2596 //! \details 2597 //! This is a slice level command and can be issued multiple times within a 2598 //! picture that is comprised of multiple slices. The same command is used 2599 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). 2600 //! 2601 //! In VDEnc mode, this command is programmed for every super-slice. However 2602 //! not all parameters are allowed to change across super-slices. 2603 //! 2604 //! MFX_AVC_SLICE_STATE command is not issued for AVC Short Format Bitstream 2605 //! decode, instead MFD_AVC_SLICEADDR command is executed to retrieve the 2606 //! next slice MB Start Address X and Y by H/W itself. 2607 //! 2608 struct MFX_AVC_SLICE_STATE_CMD 2609 { 2610 union 2611 { 2612 struct 2613 { 2614 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 2615 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2616 uint32_t CommandSubopcodeb : __CODEGEN_BITFIELD(16, 20); //!< COMMAND_SUBOPCODEB 2617 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 2618 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMAND_OPCODE 2619 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 2620 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 2621 }; 2622 uint32_t Value; 2623 } DW0; 2624 union 2625 { 2626 struct 2627 { 2628 uint32_t SliceType : __CODEGEN_BITFIELD(0, 3); //!< SLICE_TYPE 2629 uint32_t Reserved36 : __CODEGEN_BITFIELD(4, 31); //!< Reserved 2630 }; 2631 uint32_t Value; 2632 } DW1; 2633 union 2634 { 2635 struct 2636 { 2637 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD(0, 2); //!< Log 2 Weight Denom Luma 2638 uint32_t Reserved67 : __CODEGEN_BITFIELD(3, 7); //!< Reserved 2639 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD(8, 10); //!< Log 2 Weight Denom Chroma 2640 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15); //!< Reserved 2641 uint32_t NumberOfReferencePicturesInInterPredictionList0 : __CODEGEN_BITFIELD(16, 21); //!< Number of Reference Pictures in Inter-prediction List 0 2642 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 2643 uint32_t NumberOfReferencePicturesInInterPredictionList1 : __CODEGEN_BITFIELD(24, 29); //!< Number of Reference Pictures in Inter-prediction List 1 2644 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 2645 }; 2646 uint32_t Value; 2647 } DW2; 2648 union 2649 { 2650 struct 2651 { 2652 uint32_t SliceAlphaC0OffsetDiv2 : __CODEGEN_BITFIELD(0, 3); //!< Slice Alpha C0 Offset Div2 2653 uint32_t Reserved100 : __CODEGEN_BITFIELD(4, 7); //!< Reserved 2654 uint32_t SliceBetaOffsetDiv2 : __CODEGEN_BITFIELD(8, 11); //!< Slice Beta Offset Div2 2655 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2656 uint32_t SliceQuantizationParameter : __CODEGEN_BITFIELD(16, 21); //!< Slice Quantization Parameter 2657 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 2658 uint32_t CabacInitIdc10 : __CODEGEN_BITFIELD(24, 25); //!< Cabac Init Idc[1:0] 2659 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 2660 uint32_t DisableDeblockingFilterIndicator : __CODEGEN_BITFIELD(27, 28); //!< DISABLE_DEBLOCKING_FILTER_INDICATOR 2661 uint32_t DirectPredictionType : __CODEGEN_BITFIELD(29, 29); //!< DIRECT_PREDICTION_TYPE 2662 uint32_t WeightedPredictionIndicator : __CODEGEN_BITFIELD(30, 31); //!< Weighted Prediction Indicator 2663 }; 2664 uint32_t Value; 2665 } DW3; 2666 union 2667 { 2668 struct 2669 { 2670 uint32_t SliceStartMbNum : __CODEGEN_BITFIELD(0, 14); //!< Slice Start Mb Num 2671 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 2672 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(16, 23); //!< Slice Horizontal Position 2673 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(24, 31); //!< Slice Vertical Position 2674 }; 2675 uint32_t Value; 2676 } DW4; 2677 union 2678 { 2679 struct 2680 { 2681 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD(0, 7); //!< Next Slice Horizontal Position 2682 uint32_t Reserved168 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 2683 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(16, 23); //!< Next Slice Vertical Position 2684 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 2685 }; 2686 uint32_t Value; 2687 } DW5; 2688 union 2689 { 2690 struct 2691 { 2692 uint32_t StreamId10 : __CODEGEN_BITFIELD(0, 1); //!< Stream ID [1:0] 2693 uint32_t Reserved194 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 2694 uint32_t SliceId30 : __CODEGEN_BITFIELD(4, 7); //!< Slice ID [3:0] 2695 uint32_t Reserved200 : __CODEGEN_BITFIELD(8, 11); //!< Reserved 2696 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD(12, 12); //!< CABACZEROWORDINSERTIONENABLE 2697 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD(13, 13); //!< EMULATIONBYTESLICEINSERTENABLE 2698 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 14); //!< Reserved 2699 uint32_t TailInsertionPresentInBitstream : __CODEGEN_BITFIELD(15, 15); //!< TAIL_INSERTION_PRESENT_IN_BITSTREAM 2700 uint32_t SlicedataInsertionPresentInBitstream : __CODEGEN_BITFIELD(16, 16); //!< SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2701 uint32_t HeaderInsertionPresentInBitstream : __CODEGEN_BITFIELD(17, 17); //!< HEADER_INSERTION_PRESENT_IN_BITSTREAM 2702 uint32_t CompressedBitstreamOutputDisableFlag : __CODEGEN_BITFIELD(18, 18); //!< COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG 2703 uint32_t IsLastSlice : __CODEGEN_BITFIELD(19, 19); //!< IS_LAST_SLICE 2704 uint32_t MbTypeSkipConversionDisable : __CODEGEN_BITFIELD(20, 20); //!< MB_TYPE_SKIP_CONVERSION_DISABLE 2705 uint32_t MbTypeDirectConversionDisable : __CODEGEN_BITFIELD(21, 21); //!< MB_TYPE_DIRECT_CONVERSION_DISABLE 2706 uint32_t RcPanicType : __CODEGEN_BITFIELD(22, 22); //!< RC_PANIC_TYPE 2707 uint32_t RcPanicEnable : __CODEGEN_BITFIELD(23, 23); //!< RC_PANIC_ENABLE 2708 uint32_t RcStableTolerance : __CODEGEN_BITFIELD(24, 27); //!< RC Stable Tolerance 2709 uint32_t RcTriggleMode : __CODEGEN_BITFIELD(28, 29); //!< RC_TRIGGLE_MODE 2710 uint32_t Resetratecontrolcounter : __CODEGEN_BITFIELD(30, 30); //!< RESETRATECONTROLCOUNTER 2711 uint32_t RateControlCounterEnable : __CODEGEN_BITFIELD(31, 31); //!< RATE_CONTROL_COUNTER_ENABLE 2712 }; 2713 uint32_t Value; 2714 } DW6; 2715 union 2716 { 2717 struct 2718 { 2719 uint32_t IndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD(0, 28); //!< Indirect PAK-BSE Data Start Address (Write) 2720 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 2721 }; 2722 uint32_t Value; 2723 } DW7; 2724 union 2725 { 2726 struct 2727 { 2728 uint32_t GrowParamGrowInit : __CODEGEN_BITFIELD(0, 3); //!< Grow Param - Grow Init 2729 uint32_t GrowParamGrowResistance : __CODEGEN_BITFIELD(4, 7); //!< Grow Param - Grow Resistance 2730 uint32_t ShrinkParamShrinkInit : __CODEGEN_BITFIELD(8, 11); //!< Shrink Param - Shrink Init 2731 uint32_t ShrinkParamShrinkResistance : __CODEGEN_BITFIELD(12, 15); //!< Shrink Param - Shrink Resistance 2732 uint32_t MagnitudeOfQpMaxPositiveModifier : __CODEGEN_BITFIELD(16, 23); //!< Magnitude of QP Max Positive Modifier 2733 uint32_t MagnitudeOfQpMaxNegativeModifier : __CODEGEN_BITFIELD(24, 31); //!< Magnitude of QP Max Negative Modifier 2734 }; 2735 uint32_t Value; 2736 } DW8; 2737 union 2738 { 2739 struct 2740 { 2741 uint32_t Correct1 : __CODEGEN_BITFIELD(0, 3); //!< Correct 1 2742 uint32_t Correct2 : __CODEGEN_BITFIELD(4, 7); //!< Correct 2 2743 uint32_t Correct3 : __CODEGEN_BITFIELD(8, 11); //!< Correct 3 2744 uint32_t Correct4 : __CODEGEN_BITFIELD(12, 15); //!< Correct 4 2745 uint32_t Correct5 : __CODEGEN_BITFIELD(16, 19); //!< Correct 5 2746 uint32_t Correct6 : __CODEGEN_BITFIELD(20, 23); //!< Correct 6 2747 uint32_t Roundintra : __CODEGEN_BITFIELD(24, 26); //!< ROUNDINTRA 2748 uint32_t Roundintraenable : __CODEGEN_BITFIELD(27, 27); //!< RoundIntraEnable 2749 uint32_t Roundinter : __CODEGEN_BITFIELD(28, 30); //!< ROUNDINTER 2750 uint32_t Roundinterenable : __CODEGEN_BITFIELD(31, 31); //!< RoundInterEnable 2751 }; 2752 uint32_t Value; 2753 } DW9; 2754 union 2755 { 2756 struct 2757 { 2758 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD(0, 3); //!< CV0 - Clamp Value 0 2759 uint32_t Cv1 : __CODEGEN_BITFIELD(4, 7); //!< CV1 2760 uint32_t Cv2 : __CODEGEN_BITFIELD(8, 11); //!< CV2 2761 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15); //!< CV3 2762 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19); //!< CV4 2763 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23); //!< CV5 2764 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27); //!< CV6 2765 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31); //!< ClampValues - CV7 2766 }; 2767 uint32_t Value; 2768 } DW10; 2769 2770 //! \name Local enumerations 2771 2772 enum COMMAND_SUBOPCODEB 2773 { 2774 COMMAND_SUBOPCODEB_MFXAVCSLICESTATE = 3, //!< No additional details 2775 }; 2776 2777 enum SUBOPCODEA 2778 { 2779 SUBOPCODEA_MFXAVCSLICESTATE = 0, //!< No additional details 2780 }; 2781 2782 enum COMMAND_OPCODE 2783 { 2784 COMMAND_OPCODE_AVC = 1, //!< No additional details 2785 }; 2786 2787 enum PIPELINE 2788 { 2789 PIPELINE_MFXAVCSLICESTATE = 2, //!< No additional details 2790 }; 2791 2792 enum COMMAND_TYPE 2793 { 2794 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2795 }; 2796 2797 //! \brief SLICE_TYPE 2798 //! \details 2799 //! It is set to the value of the syntax element read from the Slice Header. 2800 enum SLICE_TYPE 2801 { 2802 SLICE_TYPE_PSLICE = 0, //!< No additional details 2803 SLICE_TYPE_BSLICE = 1, //!< No additional details 2804 SLICE_TYPE_ISLICE = 2, //!< No additional details 2805 }; 2806 2807 enum DISABLE_DEBLOCKING_FILTER_INDICATOR 2808 { 2809 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED0 = 0, //!< FilterInternalEdgesFlag is set equal to 1 2810 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED1 = 1, //!< Disable all deblocking operation, no deblocking parameter syntax element is read; filterInternalEdgesFlag is set equal to 0 2811 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED2 = 2, //!< Macroblocks in different slices are considered not available; filterInternalEdgesFlag is set equal to 1 2812 }; 2813 2814 //! \brief DIRECT_PREDICTION_TYPE 2815 //! \details 2816 //! Type of direct prediction used for B Slices. This field is valid only 2817 //! for Slice_Type = B Slice; otherwise, it must be set to 0. 2818 enum DIRECT_PREDICTION_TYPE 2819 { 2820 DIRECT_PREDICTION_TYPE_TEMPORAL = 0, //!< No additional details 2821 DIRECT_PREDICTION_TYPE_SPATIAL = 1, //!< No additional details 2822 }; 2823 2824 //! \brief CABACZEROWORDINSERTIONENABLE 2825 //! \details 2826 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2827 //! requirement. 2828 enum CABACZEROWORDINSERTIONENABLE 2829 { 2830 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion 2831 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP(effectively can be used as an indicator for last slice of a picture, if the assumption is only the last slice of a picture needs to insert CABAC_ZERO_WORDs. 2832 }; 2833 2834 //! \brief EMULATIONBYTESLICEINSERTENABLE 2835 //! \details 2836 //! To have PAK outputting SODB or EBSP to the output bitstream buffer 2837 enum EMULATIONBYTESLICEINSERTENABLE 2838 { 2839 EMULATIONBYTESLICEINSERTENABLE_UNNAMED0 = 0, //!< outputting RBSP 2840 EMULATIONBYTESLICEINSERTENABLE_UNNAMED1 = 1, //!< outputting EBSP 2841 }; 2842 2843 //! \brief TAIL_INSERTION_PRESENT_IN_BITSTREAM 2844 //! \details 2845 //! This bit should only be set for the last super slice. 2846 //! style="color: rgb(0, 0, 0); font-family: Arial, 2847 //! sans-serif; line-height: normal;">SKL Restriction: In VDENC mode, SW 2848 //! should insert 1000style="color: rgb(0, 0, 0); 2849 //! font-family: Arial, sans-serif; line-height: normal;">VD_PIPELINE_FLUSH 2850 //! commands with VDENC_pipeline_Done set to 1before inserting tail command. 2851 //! This is for delaying the tail insertion in HW. The HW recommendation is 2852 //! to insert tail only at the end of sequence to avoid performance loss 2853 //! since this restriction potentially cause performance degradation. 2854 //! 2855 enum TAIL_INSERTION_PRESENT_IN_BITSTREAM 2856 { 2857 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits 2858 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 2859 }; 2860 2861 //! \brief SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2862 //! \details 2863 //! This bit should be set for all super-slices. 2864 enum SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2865 { 2866 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No Slice Data insertion into the output bitstream buffer 2867 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Slice Data insertion into the output bitstream buffer is present. 2868 }; 2869 2870 //! \brief HEADER_INSERTION_PRESENT_IN_BITSTREAM 2871 //! \details 2872 //! Note: In VDEnc mode, the slice header PAK object maximum size is 25 DWs. 2873 enum HEADER_INSERTION_PRESENT_IN_BITSTREAM 2874 { 2875 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, in front of the current slice encoded bits. 2876 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 2877 }; 2878 2879 //! \brief COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG 2880 //! \details 2881 //! This field could be set to 1 only if LoadBitStreamPointerPerSlice is set 2882 //! to 1 as well, for debugging purpose. Otherwise when multiple slices are 2883 //! stitched together (with LoadBitStreamPointerPerSlice is set to 0), it 2884 //! doesn't make sense to disable bitstream output. 2885 enum COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG 2886 { 2887 COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENABLETHEWRITINGOFTHEOUTPUTCOMPRESSEDBITSTREAM = 0, //!< No additional details 2888 COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_DISABLETHEWRITINGOFTHEOUTPUTCOMPRESSEDBITSTREAM = 1, //!< See description above 2889 }; 2890 2891 //! \brief IS_LAST_SLICE 2892 //! \details 2893 //! It is used by the zero filling in the Minimum Frame Size test. 2894 enum IS_LAST_SLICE 2895 { 2896 IS_LAST_SLICE_UNNAMED0 = 0, //!< Current slice is NOT the last slice of a picture 2897 IS_LAST_SLICE_UNNAMED1 = 1, //!< Current slice is the last slice of a picture 2898 }; 2899 2900 //! \brief MB_TYPE_SKIP_CONVERSION_DISABLE 2901 //! \details 2902 //! For all Macroblock type conversions in different slices, refer to 2903 //! Section "Macroblock Type Conversion Rules" in the same volume. 2904 enum MB_TYPE_SKIP_CONVERSION_DISABLE 2905 { 2906 MB_TYPE_SKIP_CONVERSION_DISABLE_ENABLESKIPTYPECONVERSION = 0, //!< No additional details 2907 MB_TYPE_SKIP_CONVERSION_DISABLE_DISABLESKIPTYPECONVERSION = 1, //!< No additional details 2908 }; 2909 2910 //! \brief MB_TYPE_DIRECT_CONVERSION_DISABLE 2911 //! \details 2912 //! For all Macroblock type conversions in different slices, refer to 2913 //! Section "Macroblock Type Conversion Rules" in the same volume. 2914 enum MB_TYPE_DIRECT_CONVERSION_DISABLE 2915 { 2916 MB_TYPE_DIRECT_CONVERSION_DISABLE_ENABLEDIRECTMODECONVERSION = 0, //!< No additional details 2917 MB_TYPE_DIRECT_CONVERSION_DISABLE_DISABLEDIRECTMODECONVERSION = 1, //!< No additional details 2918 }; 2919 2920 //! \brief RC_PANIC_TYPE 2921 //! \details 2922 //! This field selects between two RC Panic methods 2923 enum RC_PANIC_TYPE 2924 { 2925 RC_PANIC_TYPE_QPPANIC = 0, //!< No additional details 2926 RC_PANIC_TYPE_CBPPANIC = 1, //!< No additional details 2927 }; 2928 2929 //! \brief RC_PANIC_ENABLE 2930 //! \details 2931 //! If this field is set to 1, RC enters panic mode when sum_act > 2932 //! sum_max. RC Panic Type field controls what type of panic behavior is 2933 //! invoked. 2934 enum RC_PANIC_ENABLE 2935 { 2936 RC_PANIC_ENABLE_DISABLE = 0, //!< No additional details 2937 RC_PANIC_ENABLE_ENABLE = 1, //!< No additional details 2938 }; 2939 2940 enum RC_TRIGGLE_MODE 2941 { 2942 RC_TRIGGLE_MODE_ALWAYSRATECONTROL = 0, //!< Whereas RC becomes active if sum_act > sum_target or sum_act < sum_target 2943 RC_TRIGGLE_MODE_GENTLERATECONTROL = 1, //!< whereas RC becomes active if sum_act > upper_midpt or sum_act < lower_midpt 2944 RC_TRIGGLE_MODE_LOOSERATECONTROL = 2, //!< whereas RC becomes active if sum_act > sum_max or sum_act < sum_min 2945 }; 2946 2947 //! \brief RESETRATECONTROLCOUNTER 2948 //! \details 2949 //! To reset the bit allocation accumulation counter to 0 to restart the 2950 //! rate control. 2951 enum RESETRATECONTROLCOUNTER 2952 { 2953 RESETRATECONTROLCOUNTER_NOTRESET = 0, //!< No additional details 2954 RESETRATECONTROLCOUNTER_RESET = 1, //!< No additional details 2955 }; 2956 2957 //! \brief RATE_CONTROL_COUNTER_ENABLE 2958 //! \details 2959 //! To enable the accumulation of bit allocation for rate controlThis field 2960 //! enables hardware Rate Control logic. The rest of the RC control fields 2961 //! are only valid when this field is set to 1. Otherwise, hardware ignores 2962 //! these fields. 2963 enum RATE_CONTROL_COUNTER_ENABLE 2964 { 2965 RATE_CONTROL_COUNTER_ENABLE_DISABLE = 0, //!< No additional details 2966 RATE_CONTROL_COUNTER_ENABLE_ENABLE = 1, //!< No additional details 2967 }; 2968 2969 //! \brief ROUNDINTRA 2970 //! \details 2971 //! Rounding precision for Intra quantized coefficients 2972 enum ROUNDINTRA 2973 { 2974 ROUNDINTRA_116 = 0, //!< No additional details 2975 ROUNDINTRA_216 = 1, //!< No additional details 2976 ROUNDINTRA_316 = 2, //!< No additional details 2977 ROUNDINTRA_416 = 3, //!< No additional details 2978 ROUNDINTRA_516 = 4, //!< No additional details 2979 ROUNDINTRA_616 = 5, //!< No additional details 2980 ROUNDINTRA_716 = 6, //!< No additional details 2981 ROUNDINTRA_816 = 7, //!< No additional details 2982 }; 2983 2984 //! \brief ROUNDINTER 2985 //! \details 2986 //! Rounding precision for Inter quantized coefficients 2987 enum ROUNDINTER 2988 { 2989 ROUNDINTER_116 = 0, //!< No additional details 2990 ROUNDINTER_216 = 1, //!< No additional details 2991 ROUNDINTER_316 = 2, //!< No additional details 2992 ROUNDINTER_416 = 3, //!< No additional details 2993 ROUNDINTER_516 = 4, //!< No additional details 2994 ROUNDINTER_616 = 5, //!< No additional details 2995 ROUNDINTER_716 = 6, //!< No additional details 2996 ROUNDINTER_816 = 7, //!< No additional details 2997 }; 2998 2999 //! \name Initializations 3000 3001 //! \brief Explicit member initialization function 3002 MFX_AVC_SLICE_STATE_CMD(); 3003 3004 static const size_t dwSize = 11; 3005 static const size_t byteSize = 44; 3006 }; 3007 3008 //! 3009 //! \brief MFD_AVC_DPB_STATE 3010 //! \details 3011 //! This is a frame level state command used only in AVC Short Slice 3012 //! Bitstream Format VLD mode.RefFrameList[16] of interface is replaced with 3013 //! intel Reference Picture Addresses[16] of MFX_PIPE_BUF_ADDR_STATE 3014 //! command. The LongTerm Picture flag indicator of all reference pictures 3015 //! are collected into LongTermPic_Flag[16].FieldOrderCntList[16][2] and 3016 //! CurrFieldOrderCnt[2] of interface are replaced with intel POCList[34] of 3017 //! MFX_AVC_DIRECTMODE_STATE command. 3018 //! 3019 struct MFD_AVC_DPB_STATE_CMD 3020 { 3021 union 3022 { 3023 struct 3024 { 3025 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3026 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3027 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3028 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3029 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3030 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3031 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3032 }; 3033 uint32_t Value; 3034 } DW0; 3035 union 3036 { 3037 struct 3038 { 3039 uint32_t NonExistingframeFlag161Bit : __CODEGEN_BITFIELD(0, 15); //!< NON_EXISTINGFRAME_FLAG161_BIT 3040 uint32_t LongtermframeFlag161Bit : __CODEGEN_BITFIELD(16, 31); //!< LONGTERMFRAME_FLAG161_BIT 3041 }; 3042 uint32_t Value; 3043 } DW1; 3044 union 3045 { 3046 struct 3047 { 3048 uint32_t UsedforreferenceFlag162Bits; //!< USEDFORREFERENCE_FLAG162_BITS 3049 }; 3050 uint32_t Value; 3051 } DW2; 3052 uint32_t Ltstframenumlist1616Bits[8]; //!< LTSTFRAMENUMLIST1616_BITS 3053 uint32_t Viewidlist1616Bits[8]; //!< ViewIDList[16][16 bits] 3054 uint32_t Vieworderlistl0168Bits[4]; //!< ViewOrderListL0[16][8 bits] 3055 uint32_t Vieworderlistl1168Bits[4]; //!< ViewOrderListL1[16][8 bits] 3056 3057 //! \name Local enumerations 3058 3059 enum SUBOPCODE_B 3060 { 3061 SUBOPCODE_B_UNNAMED6 = 6, //!< No additional details 3062 }; 3063 3064 enum SUBOPCODE_A 3065 { 3066 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3067 }; 3068 3069 enum MEDIA_COMMAND_OPCODE 3070 { 3071 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3072 }; 3073 3074 enum PIPELINE 3075 { 3076 PIPELINE_MFXMULTIDW = 2, //!< No additional details 3077 }; 3078 3079 enum COMMAND_TYPE 3080 { 3081 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3082 }; 3083 3084 //! \brief NON_EXISTINGFRAME_FLAG161_BIT 3085 //! \details 3086 //! One-to-one correspondence with the entries of the Intel 3087 //! RefFrameList[16]. 1 bit per reference frame. 3088 enum NON_EXISTINGFRAME_FLAG161_BIT 3089 { 3090 NON_EXISTINGFRAME_FLAG161_BIT_VALID = 0, //!< the reference picture in that entry of RefFrameList[] is a valid reference 3091 NON_EXISTINGFRAME_FLAG161_BIT_INVALID = 1, //!< the reference picture in that entry of RefFrameList[] does not exist anymore. 3092 }; 3093 3094 //! \brief LONGTERMFRAME_FLAG161_BIT 3095 //! \details 3096 //! One-to-one correspondence with the entries of the Intel 3097 //! RefFrameList[16]. 1 bit per reference frame. 3098 enum LONGTERMFRAME_FLAG161_BIT 3099 { 3100 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISASHORTTERMREFERENCEPICTURE = 0, //!< No additional details 3101 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISALONGTERMREFERENCEPICTURE = 1, //!< No additional details 3102 }; 3103 3104 //! \brief USEDFORREFERENCE_FLAG162_BITS 3105 //! \details 3106 //! One-to-one correspondence with the entries of the Intel 3107 //! RefFrameList[16]. 2 bits per reference frame. 3108 enum USEDFORREFERENCE_FLAG162_BITS 3109 { 3110 USEDFORREFERENCE_FLAG162_BITS_NOTREFERENCE = 0, //!< indicates a frame is "not used for reference". 3111 USEDFORREFERENCE_FLAG162_BITS_TOPFIELD = 1, //!< bit[0] indicates that the top field of a frame is marked as "used for reference". 3112 USEDFORREFERENCE_FLAG162_BITS_BOTTOMFIELD = 2, //!< bit[1] indicates that the bottom field of a frame is marked as "used for reference". 3113 USEDFORREFERENCE_FLAG162_BITS_FRAME = 3, //!< bit[1:0] indicates that a frame (or field pair) is marked as "used for reference". 3114 }; 3115 3116 //! \brief LTSTFRAMENUMLIST1616_BITS 3117 //! \details 3118 //! One-to-one correspondence with the entries of the Intel 3119 //! RefFrameList[16]. 16 bits per reference frame.Depending on the 3120 //! corresponding LongTermFrame_Flag[], the content of this field is 3121 //! interpreted differently. 3122 enum LTSTFRAMENUMLIST1616_BITS 3123 { 3124 LTSTFRAMENUMLIST1616_BITS_SHORTTERMFRAMEFLAGI = 0, //!< LTSTFrameNumList[i]represent Short Term Picture FrameNum. 3125 LTSTFRAMENUMLIST1616_BITS_LONGTERMFRAMEFLAGI = 1, //!< LTSTFrameNumList[i] represent LongTermFrameIdx. 3126 }; 3127 3128 //! \name Initializations 3129 3130 //! \brief Explicit member initialization function 3131 MFD_AVC_DPB_STATE_CMD(); 3132 3133 static const size_t dwSize = 27; 3134 static const size_t byteSize = 108; 3135 }; 3136 3137 //! 3138 //! \brief MFD_AVC_SLICEADDR 3139 //! \details 3140 //! This is a Slice level command used only for AVC Short Slice Bitstream 3141 //! Format VLD mode.When decoding a slice, H/W needs to know the last MB of 3142 //! the slice has reached in order to start decoding the next slice. It also 3143 //! needs to know if a slice is terminated but the last MB has not reached, 3144 //! error conealment should be invoked to generate those missing MBs. For 3145 //! AVC Short Format, the only way to know the last MB position of the 3146 //! current slice, H/W needs to snoop into the next slice's start MB address 3147 //! (a linear address encoded in the Slice Header). Since each BSD Object 3148 //! command can have only one indirect bitstream buffer address, this 3149 //! command is added to help H/W to snoop into the next slice's slice header 3150 //! and retrieve its Start MB Address. This command will take the next 3151 //! slice's bitstream buffer address as input (exactly the same way as a BSD 3152 //! Object command), and parse only the first_mb_in_slice syntax element. 3153 //! The result will stored inside the H/W, and will be used to decode the 3154 //! current slice specified in the BSD Object command.Only the very first 3155 //! few bytes (max 5 bytes for a max 4K picture) of the Slice Header will be 3156 //! decoded, the rest of the bitstream are don't care. This is because the 3157 //! first_mb_in_slice is encoded in Exponential Golomb, and will take 33 3158 //! bits to represent the max 256 x 256 = 64K-1 value. The indirect data of 3159 //! MFD_AVC_SLICEADDR is a valid BSD object and is decoded as in BSD OBJECT 3160 //! command.The next Slice Start MB Address is also exposed to the MMIO 3161 //! interface.The Slice Start MB Address (first_mb_in_slice) is a linear MB 3162 //! address count; but it is translated into the corresponding 2D MB X and Y 3163 //! raster position, and are stored internally as NextSliceMbY and 3164 //! NextSliceMbX. 3165 //! 3166 struct MFD_AVC_SLICEADDR_CMD 3167 { 3168 union 3169 { 3170 struct 3171 { 3172 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3173 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3174 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3175 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3176 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3177 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3178 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3179 }; 3180 uint32_t Value; 3181 } DW0; 3182 union 3183 { 3184 struct 3185 { 3186 uint32_t IndirectBsdDataLength; //!< Indirect BSD Data Length 3187 }; 3188 uint32_t Value; 3189 } DW1; 3190 union 3191 { 3192 struct 3193 { 3194 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_BSD_DATA_START_ADDRESS 3195 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 3196 }; 3197 uint32_t Value; 3198 } DW2; 3199 union 3200 { 3201 struct 3202 { 3203 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD(0, 7); //!< Driver Provided NAL Type Value 3204 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD(8, 8); //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3205 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 12); //!< Reserved 3206 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 31); //!< Reserved 3207 }; 3208 uint32_t Value; 3209 } DW3; 3210 3211 //! \name Local enumerations 3212 3213 enum SUBOPCODE_B 3214 { 3215 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 3216 }; 3217 3218 enum SUBOPCODE_A 3219 { 3220 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3221 }; 3222 3223 enum MEDIA_COMMAND_OPCODE 3224 { 3225 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3226 }; 3227 3228 enum PIPELINE 3229 { 3230 PIPELINE_MFDAVCSLICEADDR = 2, //!< No additional details 3231 }; 3232 3233 enum COMMAND_TYPE 3234 { 3235 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3236 }; 3237 3238 //! \brief INDIRECT_BSD_DATA_START_ADDRESS 3239 //! \details 3240 //! This field specifies the Graphics Memory starting address of the data 3241 //! to be fetched into BSD Unit for processing. This pointer is relative to 3242 //! the MFD Indirect Object Base Address.Hardware ignores this field if 3243 //! indirect data is not present. It is a byte-aligned address for the AVC 3244 //! bitstream data in both CABAC/CAVLD Modes.In implementing a phantom slice 3245 //! at the end of a picture for automatic error concealment, this field 3246 //! should set to 0.It includes the NAL Header Byte. (but does not perform 3247 //! EMU detection).Must provide a valid MB address, even if error. MB must 3248 //! be clamped to within a pic boundary. 3249 enum INDIRECT_BSD_DATA_START_ADDRESS 3250 { 3251 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED0 = 0, //!< No additional details 3252 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED512 = 512, //!< No additional details 3253 }; 3254 3255 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3256 //! \details 3257 //! This bit indicates hardware should use the NAL Type (provided below) 3258 //! programmed by driver instead of using the one from bitstream. The NAL 3259 //! byte from bitstream will not be correct. 3260 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3261 { 3262 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from first byte of decoded bitstream. 3263 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided NAL Type Values" programmed by driver. 3264 }; 3265 3266 //! \name Initializations 3267 3268 //! \brief Explicit member initialization function 3269 MFD_AVC_SLICEADDR_CMD(); 3270 3271 static const size_t dwSize = 4; 3272 static const size_t byteSize = 16; 3273 }; 3274 3275 //! 3276 //! \brief MFD_AVC_BSD_OBJECT 3277 //! \details 3278 //! The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC 3279 //! Decoding Pipeline. The same command is used for both CABAC and CAVLD 3280 //! modes. The Slice Data portion of the bitstream is loaded as indirect 3281 //! data object.Before issuing a MFD_AVC_BSD_OBJECT command, all AVC states 3282 //! of the MFD Engine need to be valid. Therefore the commands used to set 3283 //! these states need to have been issued prior to the issue of a 3284 //! MFD_AVC_BSD_OBJECT command. 3285 //! 3286 //! Context switch interrupt is not supported by this command. 3287 //! 3288 struct MFD_AVC_BSD_OBJECT_CMD 3289 { 3290 union 3291 { 3292 struct 3293 { 3294 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3295 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3296 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3297 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3298 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3299 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3300 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3301 }; 3302 uint32_t Value; 3303 } DW0; 3304 union 3305 { 3306 struct 3307 { 3308 uint32_t IndirectBsdDataLength; //!< Indirect BSD Data Length 3309 }; 3310 uint32_t Value; 3311 } DW1; 3312 union 3313 { 3314 struct 3315 { 3316 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_BSD_DATA_START_ADDRESS 3317 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 3318 }; 3319 uint32_t Value; 3320 } DW2; 3321 union 3322 { 3323 struct 3324 { 3325 uint32_t MbErrorConcealmentPSliceWeightPredictionDisableFlag : __CODEGEN_BITFIELD(0, 0); //!< MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3326 uint32_t MbErrorConcealmentPSliceMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD(1, 1); //!< MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3327 uint32_t Reserved98 : __CODEGEN_BITFIELD(2, 2); //!< Reserved 3328 uint32_t MbErrorConcealmentBSpatialWeightPredictionDisableFlag : __CODEGEN_BITFIELD(3, 3); //!< MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3329 uint32_t MbErrorConcealmentBSpatialMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD(4, 4); //!< MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3330 uint32_t Reserved101 : __CODEGEN_BITFIELD(5, 5); //!< Reserved 3331 uint32_t MbErrorConcealmentBSpatialPredictionMode : __CODEGEN_BITFIELD(6, 7); //!< MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3332 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD(8, 8); //!< MB_HEADER_ERROR_HANDLING_ 3333 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 3334 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10); //!< ENTROPY_ERROR_HANDLING 3335 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 3336 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12); //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3337 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 3338 uint32_t BsdPrematureCompleteErrorHandling : __CODEGEN_BITFIELD(14, 14); //!< BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3339 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 3340 uint32_t ConcealmentPictureId : __CODEGEN_BITFIELD(16, 21); //!< Concealment Picture ID 3341 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 3342 uint32_t MbErrorConcealmentBTemporalWeightPredictionDisableFlag : __CODEGEN_BITFIELD(24, 24); //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3343 uint32_t MbErrorConcealmentBTemporalMotionVectorsOverrideEnableFlag : __CODEGEN_BITFIELD(25, 25); //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3344 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 3345 uint32_t MbErrorConcealmentBTemporalPredictionMode : __CODEGEN_BITFIELD(27, 28); //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3346 uint32_t IntraPredmode4X48X8LumaErrorControlBit : __CODEGEN_BITFIELD(29, 29); //!< INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3347 uint32_t InitCurrentMbNumber : __CODEGEN_BITFIELD(30, 30); //!< Init Current MB Number 3348 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31); //!< CONCEALMENT_METHOD 3349 }; 3350 uint32_t Value; 3351 } DW3; 3352 union 3353 { 3354 struct 3355 { 3356 uint32_t FirstMacroblockMbBitOffset : __CODEGEN_BITFIELD(0, 2); //!< First Macroblock (MB)Bit Offset 3357 uint32_t LastsliceFlag : __CODEGEN_BITFIELD(3, 3); //!< LASTSLICE_FLAG 3358 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD(4, 4); //!< EMULATION_PREVENTION_BYTE_PRESENT 3359 uint32_t Reserved133 : __CODEGEN_BITFIELD(5, 6); //!< Reserved 3360 uint32_t FixPrevMbSkipped : __CODEGEN_BITFIELD(7, 7); //!< Fix Prev Mb Skipped 3361 uint32_t Reserved136 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 3362 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31); //!< First MB Byte Offset of Slice Data or Slice Header 3363 }; 3364 uint32_t Value; 3365 } DW4; 3366 union 3367 { 3368 struct 3369 { 3370 uint32_t IntraPredictionErrorControlBitAppliedToIntra16X16Intra8X8Intra4X4LumaAndChroma : __CODEGEN_BITFIELD(0, 0); //!< INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3371 uint32_t Intra8X84X4PredictionErrorConcealmentControlBit : __CODEGEN_BITFIELD(1, 1); //!< INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3372 uint32_t Reserved162 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 3373 uint32_t BSliceTemporalInterConcealmentMode : __CODEGEN_BITFIELD(4, 6); //!< B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3374 uint32_t Reserved167 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 3375 uint32_t BSliceSpatialInterConcealmentMode : __CODEGEN_BITFIELD(8, 10); //!< B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3376 uint32_t Reserved171 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 3377 uint32_t BSliceInterDirectTypeConcealmentMode : __CODEGEN_BITFIELD(12, 13); //!< B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3378 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 14); //!< Reserved 3379 uint32_t BSliceConcealmentMode : __CODEGEN_BITFIELD(15, 15); //!< B_SLICE_CONCEALMENT_MODE 3380 uint32_t PSliceInterConcealmentMode : __CODEGEN_BITFIELD(16, 18); //!< P_SLICE_INTER_CONCEALMENT_MODE 3381 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 22); //!< Reserved 3382 uint32_t PSliceConcealmentMode : __CODEGEN_BITFIELD(23, 23); //!< P_SLICE_CONCEALMENT_MODE 3383 uint32_t ConcealmentReferencePictureFieldBit : __CODEGEN_BITFIELD(24, 29); //!< Concealment Reference Picture + Field Bit 3384 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30); //!< Reserved 3385 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31); //!< I_SLICE_CONCEALMENT_MODE 3386 }; 3387 uint32_t Value; 3388 } DW5; 3389 union 3390 { 3391 struct 3392 { 3393 uint32_t Reserved192; //!< Reserved 3394 }; 3395 uint32_t Value; 3396 } DW6; 3397 3398 //! \name Local enumerations 3399 3400 enum SUBOPCODE_B 3401 { 3402 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3403 }; 3404 3405 enum SUBOPCODE_A 3406 { 3407 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3408 }; 3409 3410 enum MEDIA_COMMAND_OPCODE 3411 { 3412 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3413 }; 3414 3415 enum PIPELINE 3416 { 3417 PIPELINE_MFDAVCBSDOBJECT = 2, //!< No additional details 3418 }; 3419 3420 enum COMMAND_TYPE 3421 { 3422 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3423 }; 3424 3425 //! \brief INDIRECT_BSD_DATA_START_ADDRESS 3426 //! \details 3427 //! This field specifies the Graphics Memory starting address of the data 3428 //! to be fetched into BSD Unit for processing. This pointer is relative to 3429 //! the MFD Indirect Object Base Address. Hardware ignores this 3430 //! field if indirect data is not present. It is a byte-aligned address for 3431 //! the AVC bitstream data in both CABAC/CAVLD Modes. In implementing a 3432 //! phantom slice at the end of a picture for automatic error concealment, 3433 //! this field should set to 0. It includes the NAL Header (the NAL Header 3434 //! does not need to perform EMU detection). For AVC and SVC Base Layer, it 3435 //! is a single byte. But for SVC and MVC, the NAL Header is 4 Bytes long. 3436 //! These NAL Header Unit must be passed to HW in the compressed bitstream 3437 //! buffer. 3438 enum INDIRECT_BSD_DATA_START_ADDRESS 3439 { 3440 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED0 = 0, //!< No additional details 3441 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED512 = 512, //!< No additional details 3442 }; 3443 3444 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3445 //! \details 3446 //! During MB Error Concealment on P slice, weight prediction is disabled to 3447 //! improve image quality.This bit can be set to preserve the original 3448 //! weight prediction. This bit does not affect normal decoded MB. 3449 enum MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3450 { 3451 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3452 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3453 }; 3454 3455 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3456 //! \details 3457 //! During MB Error Concealment on P slice, motion vectors are forced to 0 3458 //! to improve image quality. This bit can be set to use the predicted 3459 //! motion vectors instead. This bit does not affect normal decoded MB. 3460 enum MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3461 { 3462 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3463 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3464 }; 3465 3466 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3467 //! \details 3468 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3469 //! weight prediction is disabled to improve image quality.This bit can be 3470 //! set to preserve the original weight prediction. This bit does not 3471 //! affect normal decoded MB. 3472 enum MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3473 { 3474 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3475 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3476 }; 3477 3478 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3479 //! \details 3480 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3481 //! motion vectors are forced to 0 to improve image quality. This bit can be 3482 //! set to use the predicted motion vectors instead. This bit does not 3483 //! affect normal decoded MB. 3484 enum MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3485 { 3486 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3487 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3488 }; 3489 3490 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3491 //! \details 3492 //! These two bits control how the reference L0/L1 are overridden in B 3493 //! spatial slice. 3494 enum MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3495 { 3496 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3497 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3498 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3499 }; 3500 3501 //! \brief MB_HEADER_ERROR_HANDLING_ 3502 //! \details 3503 //! Software must follow the action for each Value as follow: 3504 enum MB_HEADER_ERROR_HANDLING_ 3505 { 3506 MB_HEADER_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error concealment. 3507 MB_HEADER_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3508 }; 3509 3510 //! \brief ENTROPY_ERROR_HANDLING 3511 //! \details 3512 //! Software must follow the action for each Value as follow: 3513 enum ENTROPY_ERROR_HANDLING 3514 { 3515 ENTROPY_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error handling. 3516 ENTROPY_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3517 }; 3518 3519 //! \brief MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3520 //! \details 3521 //! Software must follow the action for each Value as follow: 3522 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3523 { 3524 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3525 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3526 }; 3527 3528 //! \brief BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3529 //! \details 3530 //! BSD Premature Complete Error occurs in situation where the Slice decode 3531 //! is completed but there are still data in the bitstream. 3532 enum BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3533 { 3534 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3535 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3536 }; 3537 3538 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3539 //! \details 3540 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3541 //! weight prediction is disabled to improve image quality.This bit can be 3542 //! set to preserve the original weight prediction. 3543 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3544 { 3545 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment 3546 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment 3547 }; 3548 3549 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3550 //! \details 3551 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3552 //! motion vectors are forced to 0 to improve image quality.This bit can be 3553 //! set to preserve the original weight prediction. 3554 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3555 { 3556 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED0 = 0, //!< Predicted Motion Vectors are used during MB Concealment 3557 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED1 = 1, //!< Motion Vectors are Overridden to 0 during MB Concealment 3558 }; 3559 3560 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3561 //! \details 3562 //! These two bits control how the reference L0/L1 are overridden in B 3563 //! temporal slice. 3564 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3565 { 3566 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3567 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3568 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3569 }; 3570 3571 //! \brief INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3572 //! \details 3573 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3574 //! decoded value is incorrect according to MB position 3575 enum INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3576 { 3577 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will detect and fix IntraPredMode (4x4/8x8 Luma) Errors. 3578 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will NOT detect IntraPredMode (4x4/8x8 Luma) Errors. The wrong IntraPredMode value will be retaind. 3579 }; 3580 3581 //! \brief CONCEALMENT_METHOD 3582 //! \details 3583 //! This field specifies the method used for concealment when error is 3584 //! detected. If set, a copy from collocated macroblock location is 3585 //! performed from the concealment reference indicated by the ConCeal_Pic_Id 3586 //! field. If it is not set, a copy from the current picture is performed 3587 //! using Intra 16x16 Prediction method. 3588 enum CONCEALMENT_METHOD 3589 { 3590 CONCEALMENT_METHOD_UNNAMED0 = 0, //!< Intra 16x16 Prediction 3591 CONCEALMENT_METHOD_UNNAMED1 = 1, //!< Inter P Copy 3592 }; 3593 3594 //! \brief LASTSLICE_FLAG 3595 //! \details 3596 //! It is needed for both error concealment at the end of a picture (so, no 3597 //! more phantom slice as in DevSNB). It is also needed to know to set the 3598 //! last MB in a picture correctly. 3599 enum LASTSLICE_FLAG 3600 { 3601 LASTSLICE_FLAG_UNNAMED0 = 0, //!< If the current Slice to be decoded is any slice other than the very last slice of the current picture 3602 LASTSLICE_FLAG_UNNAMED1 = 1, //!< If the current Slice to be decoded is the very last slice of the current picture. 3603 }; 3604 3605 enum EMULATION_PREVENTION_BYTE_PRESENT 3606 { 3607 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 3608 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 3609 }; 3610 3611 //! \brief INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3612 //! \details 3613 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3614 //! decoded value is incorrect according to MB position. 3615 enum INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3616 { 3617 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED0 = 0, //!< AVC decoder will detect and fix Intra Prediction Mode Errors. 3618 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED1 = 1, //!< AVC decoder will retain the Intra Prediction value decoded from bitstream. 3619 }; 3620 3621 //! \brief INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3622 //! \details 3623 //! This field controls if AVC goes into MB concealment mode (next MB) when 3624 //! an error is detected on Intra8x8/4x4 Prediction Mode (these 2 modes have 3625 //! fixed coding so it may not affect the bitstream. 3626 enum INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3627 { 3628 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will NOT go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3629 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3630 }; 3631 3632 //! \brief B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3633 //! \details 3634 //! This field controls how AVC decoder select reference picture for 3635 //! Temporal Inter Concealment in B Slice 3636 enum B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3637 { 3638 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1) 3639 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3640 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using B-Skip Algorithm) 3641 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< " Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3642 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED4 = 4, //!< First Long Term Picture in Reference List L0/L1(If no long term picture available, use Temporal Closest Picture) 3643 }; 3644 3645 //! \brief B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3646 //! \details 3647 //! This field controls how AVC decoder select reference picture for Spatial 3648 //! Inter Concealment in B Slice. 3649 enum B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3650 { 3651 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1). 3652 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3653 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3654 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED4 = 4, //!< " First Long Term Picture in Reference List L0/L1 (If no long term picture available, use Temporal Closest Picture) 3655 }; 3656 3657 //! \brief B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3658 //! \details 3659 //! AVC decoder can use Spatial or Temporal Direct for B Skip/Direct. This 3660 //! field determine can override the mode on how AVC decoder handles MB 3661 //! concealment in B slice. 3662 enum B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3663 { 3664 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Use Default Direct Type (slice programmed direct type) 3665 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Forced to Spatial Direct Only 3666 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Forced to Temporal Direct Only 3667 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Spatial Direct without Temporal Componenet (MovingBlock information) 3668 }; 3669 3670 //! \brief B_SLICE_CONCEALMENT_MODE 3671 //! \details 3672 //! This field controls how AVC decoder handle MB concealment in B Slice 3673 enum B_SLICE_CONCEALMENT_MODE 3674 { 3675 B_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3676 B_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3677 }; 3678 3679 //! \brief P_SLICE_INTER_CONCEALMENT_MODE 3680 //! \details 3681 //! This field controls how AVC decoder select reference picture for 3682 //! Concealment in P Slice. 3683 enum P_SLICE_INTER_CONCEALMENT_MODE 3684 { 3685 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0 (Use top entry of Reference List L0) 3686 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3687 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using P-Skip Algorithm) 3688 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC] 3689 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED4 = 4, //!< First Long Term Picture in Reference List L0 (If no long term picture available, use Temporal Closest Picture) 3690 }; 3691 3692 //! \brief P_SLICE_CONCEALMENT_MODE 3693 //! \details 3694 //! This field controls how AVC decoder handle MB concealment in P Slice 3695 enum P_SLICE_CONCEALMENT_MODE 3696 { 3697 P_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3698 P_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3699 }; 3700 3701 //! \brief I_SLICE_CONCEALMENT_MODE 3702 //! \details 3703 //! This field controls how AVC decoder handle MB concealment in I Slice 3704 enum I_SLICE_CONCEALMENT_MODE 3705 { 3706 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3707 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3708 }; 3709 3710 //! \name Initializations 3711 3712 //! \brief Explicit member initialization function 3713 MFD_AVC_BSD_OBJECT_CMD(); 3714 3715 static const size_t dwSize = 7; 3716 static const size_t byteSize = 28; 3717 }; 3718 3719 //! 3720 //! \brief MFX_PAK_INSERT_OBJECT 3721 //! \details 3722 //! The MFX_PAK_INSERT_OBJECT command is the first primitive command for the 3723 //! AVC, MPEG2, JPEG, SVC and VP8 Encoding Pipeline. 3724 //! 3725 //! This command is issued to setup the control and parameters of inserting 3726 //! a chunk of compressed/encoded bits into the current bitstream output 3727 //! buffer starting at the specified bit locationto perform the actual 3728 //! insertion by transferring the command inline data to the output buffer 3729 //! max, 32 bits at a time.It is a variable length command as the data to be 3730 //! inserted are presented as inline data of this command. It is a multiple 3731 //! of 32-bit (1 DW), as the data bus to the bitstream buffer is 32-bit 3732 //! wide.Multiple insertion commands can be issued back to back in a series. 3733 //! It is host software's responsibility to make sure their corresponding 3734 //! data will properly stitch together to form a valid H.264 3735 //! bitstream.Internally, MFX hardware will keep track of the very last two 3736 //! bytes' (the very last byte can be a partial byte) values of the previous 3737 //! insertion. It is required that the next Insertion Object Command or the 3738 //! next PAK Object Command to perform the start code emulation sequence 3739 //! check and prevention 0x03 byte insertion with this end condition of the 3740 //! previous insertion.Hardware will keep track of an output bitstream 3741 //! buffer current byte position and the associated next bit insertion 3742 //! position index. Data to be inserted can be a valid H.264 NAL units or a 3743 //! partial NAL unit. Certain NAL unit has a minimum byte size requirement. 3744 //! As such the hardware will optionally (enabled by STATE Command) 3745 //! determines the number of CABAC_ZERO_WORD to be inserted to the end of 3746 //! the current NAL, based on the minimum byte size of a NAL and the actual 3747 //! bin count of the encoded Slice. Since prior to the CABAC_ZERO_WORD 3748 //! insertion, the RBSP or EBSP is already byte-aligned, so each 3749 //! CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The 3750 //! inline data may have already been processed for start code emulation 3751 //! byte insertion, except the possibility of the last 2 bytes plus the very 3752 //! last partial byte (if any). Hence, when hardware performing the 3753 //! concatenation of multiple consecutive insertion commands, or 3754 //! concatenation of an insertion command and a PAK object command, it must 3755 //! check and perform the necessary start code emulation byte insert at the 3756 //! junction.The inline data is required to be byte aligned on the left 3757 //! (first transmitted bit order) and may or may not be byte aligned on the 3758 //! right (last transmitted bits). The command will specify the bit offset 3759 //! of the last valid DW.Each insertion state command defines a chunk of 3760 //! bits (compressed data) to be inserted at a specific location of the 3761 //! output compressed bitstream in the output buffer.Depend on CABAC or 3762 //! CAVLC encoding mode (from Slice State), PAK Object Command is always 3763 //! ended in byte aligned output bitstream except for CABAC header insertion 3764 //! which is bit aligned. In the aligned cases, PAK will perform 0 filling 3765 //! in CAVLC mode, and 1 filling in CABAC mode.Insertion data can 3766 //! include:any encoded syntax elements bit data before the encoded Slice 3767 //! Data (PAK Object Command) of the current SliceSPS NALPPS NALSEI NALOther 3768 //! Non-Slice NALLeading_Zero_8_bits (as many bytes as there is)Start Code 3769 //! PrefixNAL Header ByteSlice HeaderAny encoded syntax elements bit data 3770 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3771 //! and prior to the next encoded Slice Data of the next Slice or prior to 3772 //! the end of the bistream, whichever comes firstCabac_Zero_Word or 3773 //! Trailing_Zero_8bits (as many bytes as there is).Anything listed above 3774 //! before a Slice DataContext switch interrupt is not supported by this 3775 //! command. 3776 //! 3777 struct MFX_PAK_INSERT_OBJECT_CMD 3778 { 3779 union 3780 { 3781 struct 3782 { 3783 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWord Length 3784 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3785 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3786 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3787 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3788 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3789 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3790 }; 3791 uint32_t Value; 3792 } DW0; 3793 union 3794 { 3795 struct 3796 { 3797 uint32_t BitstreamstartresetResetbitstreamstartingpos : __CODEGEN_BITFIELD(0, 0); //!< BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS 3798 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD(1, 1); //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3799 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD(2, 2); //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3800 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD(3, 3); //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3801 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD(4, 7); //!< SkipEmulByteCnt - Skip Emulation Byte Count 3802 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD(8, 13); //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3803 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14); //!< SLICE_HEADER_INDICATOR 3804 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15); //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3805 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17); //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3806 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 31); //!< Reserved 3807 }; 3808 uint32_t Value; 3809 } DW1; 3810 3811 //! \name Local enumerations 3812 3813 enum SUBOPCODE_B 3814 { 3815 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3816 }; 3817 3818 enum SUBOPCODE_A 3819 { 3820 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 3821 }; 3822 3823 enum MEDIA_COMMAND_OPCODE 3824 { 3825 MEDIA_COMMAND_OPCODE_MFXCOMMON = 0, //!< No additional details 3826 }; 3827 3828 enum PIPELINE 3829 { 3830 PIPELINE_MFXPAKINSERTOBJECT = 2, //!< No additional details 3831 }; 3832 3833 enum COMMAND_TYPE 3834 { 3835 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3836 }; 3837 3838 //! \brief BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS 3839 //! \details 3840 //! OPEN: This bit is redundant, the control is already in the Slice State 3841 //! command 3842 enum BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS 3843 { 3844 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_INSERT = 0, //!< Insert the current command inline data starting at the current bitstream buffer insertion position 3845 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_RESET = 1, //!< Reset the bitstream buffer insertion position to the bitstream buffer starting position. 3846 }; 3847 3848 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3849 //! \details 3850 //! Must be set to 0 for JPEG encoder 3851 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3852 { 3853 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_NONE = 0, //!< No emulation 3854 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_EMULATE = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between insertion commands, or an insertion command followed by a PAK Object command. 3855 }; 3856 3857 //! \brief SLICE_HEADER_INDICATOR 3858 //! \details 3859 //! This bit indicates if the insert object is a slice header. In the VDEnc 3860 //! mode, PAK only gets this command at the beginning of the frame for slice 3861 //! position X=0, Y=0. It internally generates the header that needs to be 3862 //! inserted per slice. For VDEnc mode, this bit should always be set. 3863 enum SLICE_HEADER_INDICATOR 3864 { 3865 SLICE_HEADER_INDICATOR_LEGACY = 0, //!< Legacy Insertion Object command. The PAK Insertion Object command is not stored in HW. 3866 SLICE_HEADER_INDICATOR_SLICEHEADER = 1, //!< Insertion Object is a Slice Header. The command is stored internally by HW and is used for inserting slice headers. 3867 }; 3868 3869 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3870 //! \details 3871 //! In case this flag is on, bits are NOT accumulated during current access 3872 //! unit coding neither for Cabac Zero Word insertion bits counting or for 3873 //! output in MMIO register MFC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER. When 3874 //! using HeaderLenghtExcludeFrmSize for header insertion, the software 3875 //! needs to make sure that data comes already with inserted start code 3876 //! emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of DWORD1 of 3877 //! MFX_PAK_INSERT_OBJECT). 3878 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3879 { 3880 HEADERLENGTHEXCLUDEFRMSIZE_ACCUMULATE = 0, //!< All bits accumulated 3881 HEADERLENGTHEXCLUDEFRMSIZE_NOACCUMULATION = 1, //!< Bits during current call are not accumulated 3882 }; 3883 3884 //! \name Initializations 3885 3886 //! \brief Explicit member initialization function 3887 MFX_PAK_INSERT_OBJECT_CMD(); 3888 3889 static const size_t dwSize = 2; 3890 static const size_t byteSize = 8; 3891 }; 3892 3893 //! 3894 //! \brief MFX_MPEG2_PIC_STATE 3895 //! \details 3896 //! This must be the very first command to issue after the surface state, 3897 //! the pipe select and base address setting commands. For MPEG-2 the 3898 //! encoder is called per slice-group, however the picture state is called 3899 //! per picture.Notice that a slice-group is a group of consecutive slices 3900 //! that no non-trivial slice headers are inserted in between. 3901 //! 3902 struct MFX_MPEG2_PIC_STATE_CMD 3903 { 3904 union 3905 { 3906 struct 3907 { 3908 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3909 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3910 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3911 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3912 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3913 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3914 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3915 }; 3916 uint32_t Value; 3917 } DW0; 3918 union 3919 { 3920 struct 3921 { 3922 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 3923 uint32_t ScanOrder : __CODEGEN_BITFIELD(6, 6); //!< SCAN_ORDER 3924 uint32_t IntraVlcFormat : __CODEGEN_BITFIELD(7, 7); //!< Intra VLC Format 3925 uint32_t QuantizerScaleType : __CODEGEN_BITFIELD(8, 8); //!< QUANTIZER_SCALE_TYPE 3926 uint32_t ConcealmentMotionVectorFlag : __CODEGEN_BITFIELD(9, 9); //!< Concealment Motion Vector Flag 3927 uint32_t FramePredictionFrameDct : __CODEGEN_BITFIELD(10, 10); //!< Frame Prediction Frame DCT 3928 uint32_t TffTopFieldFirst : __CODEGEN_BITFIELD(11, 11); //!< TFF (Top Field First) 3929 uint32_t PictureStructure : __CODEGEN_BITFIELD(12, 13); //!< Picture Structure 3930 uint32_t IntraDcPrecision : __CODEGEN_BITFIELD(14, 15); //!< Intra DC Precision 3931 uint32_t FCode00 : __CODEGEN_BITFIELD(16, 19); //!< f_code[0][0] 3932 uint32_t FCode01 : __CODEGEN_BITFIELD(20, 23); //!< f_code[0][1] 3933 uint32_t FCode10 : __CODEGEN_BITFIELD(24, 27); //!< f_code[1][0]. 3934 uint32_t FCode11 : __CODEGEN_BITFIELD(28, 31); //!< f_code[1][1]. 3935 }; 3936 uint32_t Value; 3937 } DW1; 3938 union 3939 { 3940 struct 3941 { 3942 uint32_t Mismatchcontroldisabled : __CODEGEN_BITFIELD(0, 1); //!< MISMATCHCONTROLDISABLED 3943 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 8); //!< Reserved 3944 uint32_t PictureCodingType : __CODEGEN_BITFIELD(9, 10); //!< PICTURE_CODING_TYPE 3945 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13); //!< Reserved 3946 uint32_t LoadslicepointerflagLoadbitstreampointerperslice : __CODEGEN_BITFIELD(14, 14); //!< LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE 3947 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 23); //!< Reserved 3948 uint32_t PBSlicePredictedMotionVectorOverrideFinalMvValueOverride : __CODEGEN_BITFIELD(24, 24); //!< PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 3949 uint32_t PBSlicePredictedBidirMotionTypeOverrideBiDirectionMvTypeOverride : __CODEGEN_BITFIELD(25, 26); //!< PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE 3950 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 27); //!< Reserved 3951 uint32_t PBSliceConcealmentMode : __CODEGEN_BITFIELD(28, 29); //!< PB_SLICE_CONCEALMENT_MODE_ 3952 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30); //!< Reserved 3953 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31); //!< I_SLICE_CONCEALMENT_MODE_ 3954 }; 3955 uint32_t Value; 3956 } DW2; 3957 union 3958 { 3959 struct 3960 { 3961 uint32_t Framewidthinmbsminus170PictureWidthInMacroblocks : __CODEGEN_BITFIELD(0, 7); //!< FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) 3962 uint32_t Reserved104 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 3963 uint32_t Frameheightinmbsminus170PictureHeightInMacroblocks : __CODEGEN_BITFIELD(16, 23); //!< FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) 3964 uint32_t MFX_MPEG2_PIC_STATE_CMD_DW3_BIT24_28 : __CODEGEN_BITFIELD(24, 28); //!< Reserved 3965 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 30); //!< Reserved 3966 uint32_t SliceConcealmentDisableBit : __CODEGEN_BITFIELD(31, 31); //!< SLICE_CONCEALMENT_DISABLE_BIT 3967 }; 3968 uint32_t Value; 3969 } DW3; 3970 union 3971 { 3972 struct 3973 { 3974 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 3975 uint32_t Roundintradc : __CODEGEN_BITFIELD(1, 2); //!< RoundIntraDC 3976 uint32_t Reserved131 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 3977 uint32_t Roundinterdc : __CODEGEN_BITFIELD(4, 6); //!< RoundInterDC 3978 uint32_t Reserved135 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 3979 uint32_t Roundintraac : __CODEGEN_BITFIELD(8, 10); //!< RoundIntraAC 3980 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 3981 uint32_t Roundinterac : __CODEGEN_BITFIELD(12, 14); //!< RoundInterAC, 3982 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 3983 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31); //!< MinFrameWSize 3984 }; 3985 uint32_t Value; 3986 } DW4; 3987 union 3988 { 3989 struct 3990 { 3991 uint32_t Intrambmaxsizereportmask : __CODEGEN_BITFIELD(0, 0); //!< INTRAMBMAXSIZEREPORTMASK 3992 uint32_t Intermbmaxsizereportmask : __CODEGEN_BITFIELD(1, 1); //!< INTERMBMAXSIZEREPORTMASK 3993 uint32_t Framebitratemaxreportmask : __CODEGEN_BITFIELD(2, 2); //!< FRAMEBITRATEMAXREPORTMASK_ 3994 uint32_t Framebitrateminreportmask : __CODEGEN_BITFIELD(3, 3); //!< FRAMEBITRATEMINREPORTMASK 3995 uint32_t Reserved164 : __CODEGEN_BITFIELD(4, 8); //!< Reserved 3996 uint32_t Mbratecontrolmask : __CODEGEN_BITFIELD(9, 9); //!< MBRATECONTROLMASK 3997 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11); //!< MINFRAMEWSIZEUNITS 3998 uint32_t Intermbforcecbpzerocontrolmask : __CODEGEN_BITFIELD(12, 12); //!< INTERMBFORCECBPZEROCONTROLMASK 3999 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15); //!< Reserved 4000 uint32_t Framesizecontrolmask : __CODEGEN_BITFIELD(16, 16); //!< FRAMESIZECONTROLMASK 4001 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 4002 }; 4003 uint32_t Value; 4004 } DW5; 4005 union 4006 { 4007 struct 4008 { 4009 uint32_t Intrambmaxsize : __CODEGEN_BITFIELD(0, 11); //!< INTRAMBMAXSIZE 4010 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4011 uint32_t Intermbmaxsize : __CODEGEN_BITFIELD(16, 27); //!< INTERMBMAXSIZE 4012 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 4013 }; 4014 uint32_t Value; 4015 } DW6; 4016 union 4017 { 4018 struct 4019 { 4020 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD(0, 0); //!< VSL_TOP_MB_TRANS8X8FLAG 4021 uint32_t Reserved225 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 4022 }; 4023 uint32_t Value; 4024 } DW7; 4025 union 4026 { 4027 struct 4028 { 4029 uint32_t Slicedeltaqpmax0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQPMax[0] 4030 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQPMax[1] 4031 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQPMax[2] 4032 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31); //!< SLICEDELTAQPMAX3 4033 }; 4034 uint32_t Value; 4035 } DW8; 4036 union 4037 { 4038 struct 4039 { 4040 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQPMin[0] 4041 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQPMin[1] 4042 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQPMin[2] 4043 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31); //!< SliceDeltaQPMin[3] 4044 }; 4045 uint32_t Value; 4046 } DW9; 4047 union 4048 { 4049 struct 4050 { 4051 uint32_t Framebitratemin : __CODEGEN_BITFIELD(0, 13); //!< FrameBitRateMin 4052 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14); //!< FRAMEBITRATEMINUNITMODE 4053 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15); //!< FRAMEBITRATEMINUNIT 4054 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29); //!< FrameBitRateMax 4055 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30); //!< FRAMEBITRATEMAXUNITMODE 4056 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31); //!< FRAMEBITRATEMAXUNIT_ 4057 }; 4058 uint32_t Value; 4059 } DW10; 4060 union 4061 { 4062 struct 4063 { 4064 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(0, 14); //!< FrameBitRateMinDelta 4065 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 4066 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30); //!< FRAMEBITRATEMAXDELTA 4067 uint32_t Reserved383 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 4068 }; 4069 uint32_t Value; 4070 } DW11; 4071 union 4072 { 4073 struct 4074 { 4075 uint32_t Reserved384 : __CODEGEN_BITFIELD(0, 16); //!< Reserved 4076 uint32_t Reserved401 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 4077 uint32_t VadErrorLogic : __CODEGEN_BITFIELD(18, 18); //!< VAD_ERROR_LOGIC 4078 uint32_t Reserved403 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 4079 uint32_t VmdErrorLogic : __CODEGEN_BITFIELD(20, 20); //!< VMD_ERROR_LOGIC 4080 uint32_t Reserved405 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 4081 }; 4082 uint32_t Value; 4083 } DW12; 4084 4085 //! \name Local enumerations 4086 4087 enum SUBOPCODE_B 4088 { 4089 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 4090 }; 4091 4092 enum SUBOPCODE_A 4093 { 4094 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4095 }; 4096 4097 enum MEDIA_COMMAND_OPCODE 4098 { 4099 MEDIA_COMMAND_OPCODE_MPEG2COMMON = 3, //!< No additional details 4100 }; 4101 4102 enum PIPELINE 4103 { 4104 PIPELINE_MFXMPEG2PICSTATE = 2, //!< No additional details 4105 }; 4106 4107 enum COMMAND_TYPE 4108 { 4109 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4110 }; 4111 4112 //! \brief SCAN_ORDER 4113 //! \details 4114 //! This field specifies the Inverse Scan method for the DCT-domain 4115 //! coefficients in the blocks of the current picture. 4116 enum SCAN_ORDER 4117 { 4118 SCAN_ORDER_UNNAMED0 = 0, //!< MPEG_ZIGZAG_SCAN 4119 SCAN_ORDER_UNNAMED1 = 1, //!< MPEG_ALTERNATE_VERTICAL_SCAN 4120 }; 4121 4122 //! \brief QUANTIZER_SCALE_TYPE 4123 //! \details 4124 //! This field specifies the quantizer scaling type. 4125 enum QUANTIZER_SCALE_TYPE 4126 { 4127 QUANTIZER_SCALE_TYPE_UNNAMED0 = 0, //!< MPEG_QSCALE_LINEAR 4128 QUANTIZER_SCALE_TYPE_UNNAMED1 = 1, //!< D MPEG_QSCALE_NONLINEAR esc 4129 }; 4130 4131 //! \brief MISMATCHCONTROLDISABLED 4132 //! \details 4133 //! These 2 bits flag disables mismatch control of the inverse 4134 //! transformation for some specific cases during reference 4135 //! reconstruction.To disable MPEG2 IDCT fixed point arithmetic correction. 4136 enum MISMATCHCONTROLDISABLED 4137 { 4138 MISMATCHCONTROLDISABLED_UNNAMED0 = 0, //!< Mismatch control applies to all MBs 4139 MISMATCHCONTROLDISABLED_UNNAMED1 = 1, //!< Disable mismatch control to all intra MBs whose all AC-coefficients are zero. 4140 MISMATCHCONTROLDISABLED_UNNAMED2 = 2, //!< Disable mismatch control to all MBs whose all AC-coefficients are zero. 4141 MISMATCHCONTROLDISABLED_UNNAMED3 = 3, //!< Disable mismatch control to all MBs. 4142 }; 4143 4144 //! \brief PICTURE_CODING_TYPE 4145 //! \details 4146 //! This field identifies whether the picture is an intra-coded picture (I), 4147 //! predictive-coded picture (P) or bi-directionally predictive-coded 4148 //! picture (B). See ISO/IEC 13818-2 6.3.9 for details. 4149 enum PICTURE_CODING_TYPE 4150 { 4151 PICTURE_CODING_TYPE_MPEGIPICTURE = 1, //!< No additional details 4152 PICTURE_CODING_TYPE_10MPEGPPICTURE = 2, //!< No additional details 4153 PICTURE_CODING_TYPE_MPEGBPICTURE = 3, //!< No additional details 4154 }; 4155 4156 //! \brief LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE 4157 //! \details 4158 //! To support multiple slice picture and additional header/data insertion 4159 //! before and after an encoded slice.When this field is set to 0, bitstream 4160 //! pointer is only loaded once for the first slice of a frame. For 4161 //! subsequent slices in the frame, bitstream data are stitched together to 4162 //! form a single output data stream.When this field is set to 1, bitstream 4163 //! pointer is loaded for each slice of a frame. Basically bitstream data 4164 //! for different slices of a frame will be written to different memory 4165 //! locations. 4166 enum LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE 4167 { 4168 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED0 = 0, //!< Load BitStream Pointer only once for the first slice of a frame 4169 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED1 = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 4170 }; 4171 4172 //! \brief PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4173 //! \details 4174 //! This field is only applicable if the Concealment Motion Vectors are 4175 //! non-zero.It is only possible if "P/B Slice Concealment Mode" is set to 4176 //! "00" or "01" and left MB has non-zero motion vectors). 4177 enum PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4178 { 4179 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_PREDICTED = 0, //!< Motion Vectors use predicted values 4180 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_ZERO = 1, //!< Motion Vectors force to 0 4181 }; 4182 4183 //! \brief PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE 4184 //! \details 4185 //! This field is only applicable if the Concealment Motion Type is 4186 //! predicted to be Bi-directional. (It is only possible if "P/B Slice 4187 //! Concealment Mode" is set to "00" or "01" and left MB is a bi-directional 4188 //! MB). 4189 enum PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE 4190 { 4191 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BID = 0, //!< Keep Bi-direction Prediction 4192 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_FWD = 2, //!< Only use Forward Prediction (Backward MV is forced to invalid 4193 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BWD = 3, //!< Only use Backward Prediction (Forward MV is forced to invalid) 4194 }; 4195 4196 //! \brief PB_SLICE_CONCEALMENT_MODE_ 4197 //! \details 4198 //! This field controls how MPEG decoder handles MB concealment in P/B 4199 //! Slice. 4200 enum PB_SLICE_CONCEALMENT_MODE_ 4201 { 4202 PB_SLICE_CONCEALMENT_MODE_INTER = 0, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use forward reference (same polarity for field pic) with MV final values set to 0. 4203 PB_SLICE_CONCEALMENT_MODE_LEFT = 1, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data) 4204 PB_SLICE_CONCEALMENT_MODE_ZERO = 2, //!< Always use forward reference (same polarity for field pic) with MV final values set to 0 (Macroblock is concealed as INTER coded) 4205 PB_SLICE_CONCEALMENT_MODE_INTRA = 3, //!< Use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data 4206 }; 4207 4208 //! \brief I_SLICE_CONCEALMENT_MODE_ 4209 //! \details 4210 //! This field controls how MPEG decoder handles MB concealment in I Slice 4211 enum I_SLICE_CONCEALMENT_MODE_ 4212 { 4213 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< Using Coefficient values to handle MB concealment 4214 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< Using Motion Vectors to handle MB concealment 4215 }; 4216 4217 //! \brief SLICE_CONCEALMENT_DISABLE_BIT 4218 //! \details 4219 //! If VINunit detects the next slice starting position is either 4220 //! out-of-bound or smaller than or equal to the current slice starting 4221 //! position, VIN will set the current slice to be 1 MB and force VMDunit to 4222 //! do slice concealment on the next slice.This bit will disable this 4223 //! feature and the MB data from the next slice will be decoded from 4224 //! bitstream. 4225 enum SLICE_CONCEALMENT_DISABLE_BIT 4226 { 4227 SLICE_CONCEALMENT_DISABLE_BIT_ENABLE = 0, //!< VIN will force next slice to be concealment if detects slice boundary error 4228 SLICE_CONCEALMENT_DISABLE_BIT_DISABLE = 1, //!< VIN will not force next slice to be in concealment 4229 }; 4230 4231 //! \brief INTRAMBMAXSIZEREPORTMASK 4232 //! \details 4233 //! This is a mask bit controlling if the condition of any intra MB in the 4234 //! frame exceeds IntraMBMaxSize. 4235 enum INTRAMBMAXSIZEREPORTMASK 4236 { 4237 INTRAMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4238 INTRAMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 4239 }; 4240 4241 //! \brief INTERMBMAXSIZEREPORTMASK 4242 //! \details 4243 //! This is a mask bit controlling if the condition of any inter MB in the 4244 //! frame exceeds InterMBMaxSize. 4245 enum INTERMBMAXSIZEREPORTMASK 4246 { 4247 INTERMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4248 INTERMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 4249 }; 4250 4251 //! \brief FRAMEBITRATEMAXREPORTMASK_ 4252 //! \details 4253 //! This is a mask bit controlling if the condition of frame level bit count 4254 //! exceeds FrameBitRateMax. 4255 enum FRAMEBITRATEMAXREPORTMASK_ 4256 { 4257 FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4258 FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 4259 }; 4260 4261 //! \brief FRAMEBITRATEMINREPORTMASK 4262 //! \details 4263 //! This is a mask bit controlling if the condition of frame level bit count 4264 //! is less than FrameBitRateMin. 4265 enum FRAMEBITRATEMINREPORTMASK 4266 { 4267 FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4268 FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 4269 }; 4270 4271 //! \brief MBRATECONTROLMASK 4272 //! \details 4273 //! MB Rate Control conformance maskThis field is ignored when 4274 //! MacroblockStatEnable is disabled or MB level Rate control flag for the 4275 //! current MB is disable in Macroblock Status Buffer. 4276 enum MBRATECONTROLMASK 4277 { 4278 MBRATECONTROLMASK_UNNAMED0 = 0, //!< Do not change QP values of inter macroblock with suggested QP values in Macroblock Status Buffer 4279 MBRATECONTROLMASK_UNNAMED1 = 1, //!< Apply RC QP delta for all macroblock 4280 }; 4281 4282 //! \brief MINFRAMEWSIZEUNITS 4283 //! \details 4284 //! This field is the Minimum Frame Size Units 4285 enum MINFRAMEWSIZEUNITS 4286 { 4287 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 4288 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 4289 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 4290 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 4291 }; 4292 4293 //! \brief INTERMBFORCECBPZEROCONTROLMASK 4294 //! \details 4295 //! Inter MB Force CBP ZERO mask. 4296 enum INTERMBFORCECBPZEROCONTROLMASK 4297 { 4298 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED0 = 0, //!< No effect 4299 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED1 = 1, //!< Zero out all A/C coefficients for the inter MB violating Inter Confirmance 4300 }; 4301 4302 //! \brief FRAMESIZECONTROLMASK 4303 //! \details 4304 //! Frame size conformance maskThis field is used when MacroblockStatEnable 4305 //! is set to 1. 4306 enum FRAMESIZECONTROLMASK 4307 { 4308 FRAMESIZECONTROLMASK_UNNAMED0 = 0, //!< Do not change Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control 4309 FRAMESIZECONTROLMASK_UNNAMED1 = 1, //!< Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control values in MFC_IMAGE_STATUS control register. 4310 }; 4311 4312 //! \brief INTRAMBMAXSIZE 4313 //! \details 4314 //! This field, Intra MB Conformance Max size limit,indicates the allowed 4315 //! max bit count size for Intra MB 4316 enum INTRAMBMAXSIZE 4317 { 4318 INTRAMBMAXSIZE_UNNAMED4095 = 4095, //!< No additional details 4319 }; 4320 4321 //! \brief INTERMBMAXSIZE 4322 //! \details 4323 //! This field, Inter MB Conformance Max size limit,indicates the allowed 4324 //! max bit count size for Inter MB 4325 enum INTERMBMAXSIZE 4326 { 4327 INTERMBMAXSIZE_UNNAMED4095 = 4095, //!< No additional details 4328 }; 4329 4330 enum VSL_TOP_MB_TRANS8X8FLAG 4331 { 4332 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 4333 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 4334 }; 4335 4336 //! \brief SLICEDELTAQPMAX3 4337 //! \details 4338 //! This field is the Slice level delta QP for totalbit-count above 4339 //! FrameBitRateMax - first 1/8 regionThis field is used tocalculate the 4340 //! suggested slice QP into the MFC_IMAGE_STATUS control register whentotal 4341 //! bit count for the entire frame exceeds FrameBitRateMax but is within 4342 //! 1/8of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range 4343 //! of(FrameBitRateMax, (FrameBitRateMax+FrameBitRateMaxDelta>>3). 4344 enum SLICEDELTAQPMAX3 4345 { 4346 SLICEDELTAQPMAX3_DISABLE = 0, //!< No additional details 4347 SLICEDELTAQPMAX3_ENABLE = 1, //!< No additional details 4348 }; 4349 4350 //! \brief FRAMEBITRATEMINUNITMODE 4351 //! \details 4352 //! This field is the Frame Bitrate Minimum Limit 4353 //! Units.ValueNameDescriptionProject 4354 enum FRAMEBITRATEMINUNITMODE 4355 { 4356 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4357 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4358 }; 4359 4360 //! \brief FRAMEBITRATEMINUNIT 4361 //! \details 4362 //! This field is the Frame Bitrate Minimum Limit Units. 4363 enum FRAMEBITRATEMINUNIT 4364 { 4365 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 4366 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4367 }; 4368 4369 //! \brief FRAMEBITRATEMAXUNITMODE 4370 //! \details 4371 //! BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc 4372 enum FRAMEBITRATEMAXUNITMODE 4373 { 4374 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4375 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4376 }; 4377 4378 //! \brief FRAMEBITRATEMAXUNIT_ 4379 //! \details 4380 //! This field is the Frame Bitrate Maximum Limit Units. 4381 enum FRAMEBITRATEMAXUNIT_ 4382 { 4383 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 4384 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4385 }; 4386 4387 //! \brief FRAMEBITRATEMAXDELTA 4388 //! \details 4389 //! This field is used to select the slice delta QP when FrameBitRateMax Is 4390 //! exceeded. It shares the same FrameBitrateMaxUnit. When 4391 //! FrameBitrateMaxUnitMode is 0(compatibility mode), only bits 16:27 should 4392 //! be used, bits 28, 29 and 30 should be 0. 4393 enum FRAMEBITRATEMAXDELTA 4394 { 4395 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 4396 }; 4397 4398 enum VAD_ERROR_LOGIC 4399 { 4400 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 4401 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 4402 }; 4403 4404 enum VMD_ERROR_LOGIC 4405 { 4406 VMD_ERROR_LOGIC_DISABLE = 0, //!< No additional details 4407 VMD_ERROR_LOGIC_ENABLE = 1, //!< Error Handling 4408 }; 4409 4410 //! \name Initializations 4411 4412 //! \brief Explicit member initialization function 4413 MFX_MPEG2_PIC_STATE_CMD(); 4414 4415 static const size_t dwSize = 13; 4416 static const size_t byteSize = 52; 4417 }; 4418 4419 //! 4420 //! \brief MFD_MPEG2_BSD_OBJECT 4421 //! \details 4422 //! Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. 4423 //! This is for performance purpose as in MPEG2 a slice is defined as a 4424 //! group of MBs of any size that must be within a macroblock row.Slice 4425 //! header parameters are passed in as inline data and the bitstream data 4426 //! for the slice is passed in as indirect data. Of the inline data, 4427 //! slice_horizontal_position and slice_vertical_position determines the 4428 //! location within the destination picture of the first macroblock in the 4429 //! slice. The content in this command is identical to that in the 4430 //! MEDIA_OBJECT command in VLD mode described in the Media Chapter. 4431 //! 4432 struct MFD_MPEG2_BSD_OBJECT_CMD 4433 { 4434 union 4435 { 4436 struct 4437 { 4438 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4439 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4440 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 4441 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 4442 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 4443 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4444 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4445 }; 4446 uint32_t Value; 4447 } DW0; 4448 union 4449 { 4450 struct 4451 { 4452 uint32_t IndirectBsdDataLength; //!< Indirect BSD Data Length 4453 }; 4454 uint32_t Value; 4455 } DW1; 4456 union 4457 { 4458 struct 4459 { 4460 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Data Start Address 4461 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4462 }; 4463 uint32_t Value; 4464 } DW2; 4465 union 4466 { 4467 struct 4468 { 4469 uint32_t FirstMacroblockBitOffset : __CODEGEN_BITFIELD(0, 2); //!< First Macroblock Bit Offset 4470 uint32_t IsLastMb : __CODEGEN_BITFIELD(3, 3); //!< IS_LAST_MB 4471 uint32_t MbRowLastSlice : __CODEGEN_BITFIELD(4, 4); //!< MB_ROW_LAST_SLICE 4472 uint32_t LastPicSlice : __CODEGEN_BITFIELD(5, 5); //!< LAST_PIC_SLICE 4473 uint32_t SliceConcealmentTypeBit : __CODEGEN_BITFIELD(6, 6); //!< SLICE_CONCEALMENT_TYPE_BIT 4474 uint32_t SliceConcealmentOverrideBit : __CODEGEN_BITFIELD(7, 7); //!< SLICE_CONCEALMENT_OVERRIDE_BIT 4475 uint32_t MacroblockCount : __CODEGEN_BITFIELD(8, 15); //!< Macroblock Count 4476 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(16, 23); //!< Slice Vertical Position 4477 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(24, 31); //!< Slice Horizontal Position 4478 }; 4479 uint32_t Value; 4480 } DW3; 4481 union 4482 { 4483 struct 4484 { 4485 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD(0, 7); //!< Next Slice Horizontal Position 4486 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(8, 16); //!< Next Slice Vertical Position 4487 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 23); //!< Reserved 4488 uint32_t QuantizerScaleCode : __CODEGEN_BITFIELD(24, 28); //!< Quantizer Scale Code 4489 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4490 }; 4491 uint32_t Value; 4492 } DW4; 4493 4494 //! \name Local enumerations 4495 4496 enum SUBOPCODE_B 4497 { 4498 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 4499 }; 4500 4501 enum SUBOPCODE_A 4502 { 4503 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4504 }; 4505 4506 enum MEDIA_COMMAND_OPCODE 4507 { 4508 MEDIA_COMMAND_OPCODE_MPEG2DEC = 3, //!< No additional details 4509 }; 4510 4511 enum PIPELINE 4512 { 4513 PIPELINE_MFDMPEG2BSDOBJECT = 2, //!< No additional details 4514 }; 4515 4516 enum COMMAND_TYPE 4517 { 4518 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4519 }; 4520 4521 enum IS_LAST_MB 4522 { 4523 IS_LAST_MB_UNNAMED0 = 0, //!< The current MB is not the last MB in the current Slice 4524 IS_LAST_MB_UNNAMED1 = 1, //!< The current MB is the last MB in the current Slice 4525 }; 4526 4527 //! \brief MB_ROW_LAST_SLICE 4528 //! \details 4529 //! This bit is added to support error concealment when Context Switch at 4530 //! row boundary in debugging mode is active. 4531 enum MB_ROW_LAST_SLICE 4532 { 4533 MB_ROW_LAST_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of MB row 4534 MB_ROW_LAST_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the current MB row 4535 }; 4536 4537 //! \brief LAST_PIC_SLICE 4538 //! \details 4539 //! This bit is added to support error concealment at the end of a picture. 4540 enum LAST_PIC_SLICE 4541 { 4542 LAST_PIC_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of current picture 4543 LAST_PIC_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the entire picture 4544 }; 4545 4546 //! \brief SLICE_CONCEALMENT_TYPE_BIT 4547 //! \details 4548 //! This bit can be forced by driver ("Slice Concealment Override Bit") or 4549 //! set by VINunit depending on slice boundary errors. 4550 enum SLICE_CONCEALMENT_TYPE_BIT 4551 { 4552 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED0 = 0, //!< VMD will decode MBs from the bitstream until the bitstream is run-out. Then VMD will conceal the remaining MBs. 4553 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED1 = 1, //!< VMD will conceal all MBs of the slice regardless of bitstream. (If driver does not force the value of this bit, VIN will set this bit depending on slice boundary error. If the next slice position of the current slice is out-of-bound or the same or earlier than the current slice start position, VIN will set this bit for the next slice) 4554 }; 4555 4556 //! \brief SLICE_CONCEALMENT_OVERRIDE_BIT 4557 //! \details 4558 //! This bit forces hardware to handle the current slice in Conceal or 4559 //! Deocde Mode. If this bit is set to one, VIN will force the current 4560 //! slice to do concealment or to decode from bitstream regardless if the 4561 //! slice boundary has errors or not. 4562 enum SLICE_CONCEALMENT_OVERRIDE_BIT 4563 { 4564 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED0 = 0, //!< Driver must program "Slice Concealment Type" to '0'. VIN will set "Slice Concealment Type" depending if the slice boundary has error or not 4565 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED1 = 1, //!< VIN will use driver-provided "Slice Concealment Type" regardless of valid slice boundary 4566 }; 4567 4568 //! \name Initializations 4569 4570 //! \brief Explicit member initialization function 4571 MFD_MPEG2_BSD_OBJECT_CMD(); 4572 4573 static const size_t dwSize = 5; 4574 static const size_t byteSize = 20; 4575 }; 4576 4577 //! 4578 //! \brief MFD_IT_OBJECT_MPEG2_INLINE_DATA 4579 //! \details 4580 //! The content in this command is similar to that in the MEDIA_OBJECT 4581 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4582 //! command corresponds to the processing of one macroblock. Macroblock 4583 //! parameters are passed in as inline data and the non-zero DCT coefficient 4584 //! data for the macroblock is passed in as indirect data. Inline data 4585 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4586 //! 4587 struct MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD 4588 { 4589 union 4590 { 4591 struct 4592 { 4593 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 4594 uint32_t Lastmbinrow : __CODEGEN_BITFIELD(3, 3); //!< LastMBInRow 4595 uint32_t Reserved4 : __CODEGEN_BITFIELD(4, 5); //!< Reserved 4596 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD(6, 11); //!< Coded Block Pattern 4597 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4598 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16); //!< MACROBLOCK_INTRA_TYPE 4599 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17); //!< MACROBLOCK_MOTION_FORWARD 4600 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18); //!< MACROBLOCK_MOTION_BACKWARD 4601 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20); //!< Reserved 4602 uint32_t DctType : __CODEGEN_BITFIELD(21, 21); //!< DCT_TYPE 4603 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 4604 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25); //!< Motion Type 4605 uint32_t Reserved26 : __CODEGEN_BITFIELD(26, 27); //!< Reserved 4606 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31); //!< MOTION_VERTICAL_FIELD_SELECT 4607 }; 4608 uint32_t Value; 4609 } DW0; 4610 union 4611 { 4612 struct 4613 { 4614 uint32_t Horzorigin : __CODEGEN_BITFIELD(0, 7); //!< HorzOrigin 4615 uint32_t Vertorigin : __CODEGEN_BITFIELD(8, 15); //!< VertOrigin 4616 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 4617 }; 4618 uint32_t Value; 4619 } DW1; 4620 union 4621 { 4622 struct 4623 { 4624 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Forward, Horizontal Component 4625 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Forward, Vertical Component 4626 }; 4627 uint32_t Value; 4628 } DW2; 4629 union 4630 { 4631 struct 4632 { 4633 uint32_t MotionVectorsField0BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Backward, Horizontal Component 4634 uint32_t MotionVectorsField0BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Backward, Vertical Component 4635 }; 4636 uint32_t Value; 4637 } DW3; 4638 union 4639 { 4640 struct 4641 { 4642 uint32_t MotionVectorsField1ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Forward, Horizontal Component 4643 uint32_t MotionVectorsField1ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Forward, Vertical Component 4644 }; 4645 uint32_t Value; 4646 } DW4; 4647 union 4648 { 4649 struct 4650 { 4651 uint32_t MotionVectorsField1BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Backward, Horizontal Component 4652 uint32_t MotionVectorsField1BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Backward, Vertical Component 4653 }; 4654 uint32_t Value; 4655 } DW5; 4656 4657 //! \name Local enumerations 4658 4659 //! \brief MACROBLOCK_INTRA_TYPE 4660 //! \details 4661 //! This field specifies if the current macroblock is intra-coded. When set, 4662 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4663 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4664 enum MACROBLOCK_INTRA_TYPE 4665 { 4666 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4667 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4668 }; 4669 4670 //! \brief MACROBLOCK_MOTION_FORWARD 4671 //! \details 4672 //! This field specifies if the forward motion vector is active. See ISO/IEC 4673 //! 13818-2 Tables B-2 through B-4. 4674 enum MACROBLOCK_MOTION_FORWARD 4675 { 4676 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4677 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTOR_S = 1, //!< No additional details 4678 }; 4679 4680 //! \brief MACROBLOCK_MOTION_BACKWARD 4681 //! \details 4682 //! This field specifies if the backward motion vector is active. See 4683 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4684 enum MACROBLOCK_MOTION_BACKWARD 4685 { 4686 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4687 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTOR_S = 1, //!< No additional details 4688 }; 4689 4690 //! \brief DCT_TYPE 4691 //! \details 4692 //! This field specifies the DCT type of the current macroblock. The kernel 4693 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 4694 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 4695 //! (no coded blocks present). 4696 enum DCT_TYPE 4697 { 4698 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 4699 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 4700 }; 4701 4702 //! \brief MOTION_VERTICAL_FIELD_SELECT 4703 //! \details 4704 //! A bit-wise representation of a long [2][2] array as defined in 4705 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also 4706 //! #167;7.6.4).<table><thead><tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 4707 //! Index</td></tr></thead><tbody><tr><td>28</td><td>0</td><td>0</td><td>0</td></tr><tr><td>29</td><td>0</td><td>1</td><td>1</td></tr><tr><td>30</td><td>1</td><td>0</td><td>2</td></tr><tr><td>31</td><td>1</td><td>1</td><td>3</td></tr></tbody></table> 4708 enum MOTION_VERTICAL_FIELD_SELECT 4709 { 4710 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field 4711 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 4712 }; 4713 4714 //! \name Initializations 4715 4716 //! \brief Explicit member initialization function 4717 MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD(); 4718 4719 static const size_t dwSize = 6; 4720 static const size_t byteSize = 24; 4721 }; 4722 4723 //! 4724 //! \brief MFD_IT_OBJECT 4725 //! \details 4726 //! All weight mode (default and implicit) are mapped to explicit mode. But 4727 //! the weights come in either as explicit or implicit. 4728 //! 4729 struct MFD_IT_OBJECT_CMD 4730 { 4731 union 4732 { 4733 struct 4734 { 4735 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4736 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4737 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 4738 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 4739 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 4740 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4741 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4742 }; 4743 uint32_t Value; 4744 } DW0; 4745 union 4746 { 4747 struct 4748 { 4749 uint32_t IndirectItMvDataLength : __CODEGEN_BITFIELD(0, 9); //!< Indirect IT-MV Data Length 4750 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 4751 }; 4752 uint32_t Value; 4753 } DW1; 4754 union 4755 { 4756 struct 4757 { 4758 uint32_t IndirectItMvDataStartAddressOffset : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET 4759 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4760 }; 4761 uint32_t Value; 4762 } DW2; 4763 union 4764 { 4765 struct 4766 { 4767 uint32_t IndirectItCoeffDataLength : __CODEGEN_BITFIELD(0, 11); //!< Indirect IT-COEFF Data Length 4768 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31); //!< Reserved 4769 }; 4770 uint32_t Value; 4771 } DW3; 4772 union 4773 { 4774 struct 4775 { 4776 uint32_t IndirectItCoeffDataStartAddressOffset : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET 4777 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4778 }; 4779 uint32_t Value; 4780 } DW4; 4781 union 4782 { 4783 struct 4784 { 4785 uint32_t IndirectItDblkControlDataLength : __CODEGEN_BITFIELD(0, 5); //!< Indirect IT-DBLK Control Data Length 4786 uint32_t Reserved166 : __CODEGEN_BITFIELD(6, 31); //!< Reserved 4787 }; 4788 uint32_t Value; 4789 } DW5; 4790 union 4791 { 4792 struct 4793 { 4794 uint32_t IndirectItDblkControlDataStartAddressOffset : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET 4795 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4796 }; 4797 uint32_t Value; 4798 } DW6; 4799 4800 //! \name Local enumerations 4801 4802 enum SUBOPCODE_B 4803 { 4804 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 4805 }; 4806 4807 enum SUBOPCODE_A 4808 { 4809 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4810 }; 4811 4812 enum MEDIA_COMMAND_OPCODE 4813 { 4814 MEDIA_COMMAND_OPCODE_MFXCOMMONDEC = 0, //!< No additional details 4815 }; 4816 4817 enum PIPELINE 4818 { 4819 PIPELINE_MFDITOBJECT = 2, //!< No additional details 4820 }; 4821 4822 enum COMMAND_TYPE 4823 { 4824 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4825 }; 4826 4827 //! \brief INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET 4828 //! \details 4829 //! This field specifies the memory starting address (offset) of the MV data 4830 //! to be fetched into the IT pipeline for processing. This pointer is 4831 //! relative to the Indirect IT-MV Object Base Address.Hardware ignores this 4832 //! field if indirect data is not present, i.e. the Indirect MV Data Length 4833 //! is set to 0. Alignment of this address depends on the mode of 4834 //! operation.AVC-IT Mode: It must be DWord aligned (since each MV is 4 4835 //! bytes in size). This field is only valid in AVC decoder IT mode (VC1 and 4836 //! MPEG uses inline MV data). 4837 enum INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET 4838 { 4839 INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET_UNNAMED0 = 0, //!< No additional details 4840 INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET_UNNAMED512 = 512, //!< No additional details 4841 }; 4842 4843 //! \brief INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET 4844 //! \details 4845 //! This field specifies the memory starting address (offset) of the coeff 4846 //! data to be loaded into the IT pipeline for processing. This pointer is 4847 //! relative to the Indirect IT-COEFF Object Base Address.Hardware ignores 4848 //! this field if indirect IT-COEFF data is not present, i.e. the Indirect 4849 //! IT-COEFF Data Length is set to 0.This field must be DW aligned, since 4850 //! each coeff icient is 4 bytes in size.Driver will determine the Num of 4851 //! EOB 4x4/8x8 must match the block cbp flags, if not match, hardware 4852 //! cannot hang - add error handling.This field is only valid in AVC, VC1, 4853 //! MPEG2 decoder IT mode. 4854 enum INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET 4855 { 4856 INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET_UNNAMED0 = 0, //!< No additional details 4857 INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET_UNNAMED512 = 512, //!< No additional details 4858 }; 4859 4860 //! \brief INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET 4861 //! \details 4862 //! This field specifies the memory starting address (offset) of the 4863 //! Deblocker control data to be fetched into the IT Pipeline for 4864 //! processing. This pointer is relative to the Indirect IT-DBLK Object Base 4865 //! Address.Hardware ignores this field if indirect data is not present, ie. 4866 //! The indirect IT-DBLK Control Data Length is set to 0.It must be DWord 4867 //! aligned. Each Deblock Control Data record is 48 bytes or 12 DWords in 4868 //! size.This field is only valid in AVC decoder IT mode. 4869 enum INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET 4870 { 4871 INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET_UNNAMED0 = 0, //!< No additional details 4872 INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET_UNNAMED512 = 512, //!< No additional details 4873 }; 4874 4875 //! \name Initializations 4876 4877 //! \brief Explicit member initialization function 4878 MFD_IT_OBJECT_CMD(); 4879 4880 static const size_t dwSize = 7; 4881 static const size_t byteSize = 28; 4882 }; 4883 4884 //! 4885 //! \brief MFC_MPEG2_SLICEGROUP_STATE 4886 //! \details 4887 //! This is a slice group level command and can be issued multiple times 4888 //! within a picture that is comprised of multiple slice groups. The same 4889 //! command is used for AVC encoder (PAK mode) and decoder (VLD and IT 4890 //! modes). 4891 //! 4892 struct MFC_MPEG2_SLICEGROUP_STATE_CMD 4893 { 4894 union 4895 { 4896 struct 4897 { 4898 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4899 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4900 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 4901 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 4902 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 4903 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4904 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4905 }; 4906 uint32_t Value; 4907 } DW0; 4908 union 4909 { 4910 struct 4911 { 4912 uint32_t Streamid10EncoderOnly : __CODEGEN_BITFIELD(0, 1); //!< StreamID[1:0] (Encoder-only) 4913 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 4914 uint32_t Sliceid30EncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< SliceID[3:0] (Encoder-only) 4915 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 11); //!< Reserved 4916 uint32_t Intrasliceflag : __CODEGEN_BITFIELD(12, 12); //!< IntraSliceFlag 4917 uint32_t Intraslice : __CODEGEN_BITFIELD(13, 13); //!< IntraSlice 4918 uint32_t Firstslicehdrdisabled : __CODEGEN_BITFIELD(14, 14); //!< FirstSliceHdrDisabled 4919 uint32_t TailpresentflagTailInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(15, 15); //!< TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 4920 uint32_t SlicedataPresentflagSlicedataInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(16, 16); //!< SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 4921 uint32_t HeaderpresentflagHeaderInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(17, 17); //!< HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 4922 uint32_t BitstreamoutputflagCompressedBitstreamOutputDisableFlagEncoderOnly : __CODEGEN_BITFIELD(18, 18); //!< BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 4923 uint32_t Islastslicegrp : __CODEGEN_BITFIELD(19, 19); //!< IsLastSliceGrp 4924 uint32_t SkipconvdisabledMbTypeSkipConversionDisableEncoderOnly : __CODEGEN_BITFIELD(20, 20); //!< SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 4925 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 4926 uint32_t RatectrlpanictypeRcPanicTypeEncoderOnly : __CODEGEN_BITFIELD(22, 22); //!< RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY 4927 uint32_t RatectrlpanicflagRcPanicEnableEncoderOnly : __CODEGEN_BITFIELD(23, 23); //!< RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY 4928 uint32_t MbratectrlparamRcStableToleranceEncoderOnly : __CODEGEN_BITFIELD(24, 27); //!< MbRateCtrlParam- RC Stable Tolerance (Encoder-only) 4929 uint32_t MbratectrlmodeRcTriggleModeEncoderOnly : __CODEGEN_BITFIELD(28, 29); //!< MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 4930 uint32_t MbratectrlresetResetratecontrolcounterEncoderOnly : __CODEGEN_BITFIELD(30, 30); //!< MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 4931 uint32_t MbratectrlflagRatecontrolcounterenableEncoderOnly : __CODEGEN_BITFIELD(31, 31); //!< MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 4932 }; 4933 uint32_t Value; 4934 } DW1; 4935 union 4936 { 4937 struct 4938 { 4939 uint32_t FirstmbxcntAlsoCurrstarthorzpos : __CODEGEN_BITFIELD(0, 7); //!< FirstMbXcnt - also CurrStartHorzPos 4940 uint32_t FirstmbycntAlsoCurrstartvertpos : __CODEGEN_BITFIELD(8, 15); //!< FirstMbYcnt - also CurrStartVertPos 4941 uint32_t NextsgmbxcntAlsoNextstarthorzpos : __CODEGEN_BITFIELD(16, 23); //!< NextSgMbXcnt - also NextStartHorzPos 4942 uint32_t NextsgmbycntAlsoNextstartvertpos : __CODEGEN_BITFIELD(24, 31); //!< NextSgMbYcnt - also NextStartVertPos 4943 }; 4944 uint32_t Value; 4945 } DW2; 4946 union 4947 { 4948 struct 4949 { 4950 uint32_t Slicegroupqp : __CODEGEN_BITFIELD(0, 5); //!< SliceGroupQp 4951 uint32_t Reserved102 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 4952 uint32_t Slicegroupskip : __CODEGEN_BITFIELD(8, 8); //!< SliceGroupSkip 4953 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 31); //!< Reserved 4954 }; 4955 uint32_t Value; 4956 } DW3; 4957 union 4958 { 4959 struct 4960 { 4961 uint32_t BitstreamoffsetIndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD(0, 28); //!< BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE 4962 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4963 }; 4964 uint32_t Value; 4965 } DW4; 4966 union 4967 { 4968 struct 4969 { 4970 uint32_t GrowparamGrowInitEncoderOnly : __CODEGEN_BITFIELD(0, 3); //!< GrowParam - Grow Init (Encoder-only) 4971 uint32_t GrowparamGrowResistanceEncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< GrowParam - Grow Resistance (Encoder-only) 4972 uint32_t ShrinkaramShrinkInitEncoderOnly : __CODEGEN_BITFIELD(8, 11); //!< Shrinkaram - Shrink Init (Encoder-only) 4973 uint32_t ShrinkparamShrinkResistanceEncoderOnly : __CODEGEN_BITFIELD(12, 15); //!< ShrinkParam - Shrink Resistance (Encoder-only) 4974 uint32_t MaxqpposmodifierMagnitudeOfQpMaxPositiveModifierEncoderOnly : __CODEGEN_BITFIELD(16, 23); //!< MaxQpPosModifier - Magnitude of QP Max Positive Modifier (Encoder-only) 4975 uint32_t MaxqpnegmodifierMagnitudeOfQpMaxNegativeModifierEncoderOnly : __CODEGEN_BITFIELD(24, 31); //!< MaxQpNegModifier - Magnitude of QP Max Negative Modifier (Encoder-only) 4976 }; 4977 uint32_t Value; 4978 } DW5; 4979 union 4980 { 4981 struct 4982 { 4983 uint32_t CorrectpointsCorrect1EncoderOnly : __CODEGEN_BITFIELD(0, 3); //!< CorrectPoints - Correct 1 (Encoder-only) 4984 uint32_t CorrectpointsCorrect2EncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< CorrectPoints - Correct 2 (Encoder-only) 4985 uint32_t CorrectpointsCorrect3EncoderOnly : __CODEGEN_BITFIELD(8, 11); //!< CorrectPoints - Correct 3 (Encoder-only) 4986 uint32_t CorrectpointsCorrect4EncoderOnly : __CODEGEN_BITFIELD(12, 15); //!< CorrectPoints - Correct 4 (Encoder-only) 4987 uint32_t CorrectpointsCorrect5EncoderOnly : __CODEGEN_BITFIELD(16, 19); //!< CorrectPoints - Correct 5 (Encoder-only) 4988 uint32_t CorrectpointsCorrect6EncoderOnly : __CODEGEN_BITFIELD(20, 23); //!< CorrectPoints - Correct 6 (Encoder-only) 4989 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 4990 }; 4991 uint32_t Value; 4992 } DW6; 4993 union 4994 { 4995 struct 4996 { 4997 uint32_t Cv0ClampValue0EncoderOnly : __CODEGEN_BITFIELD(0, 3); //!< CV0 - Clamp Value 0 (Encoder-only) 4998 uint32_t Cv1ClampValue1EncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< CV1 - Clamp Value 1 (Encoder-only) 4999 uint32_t Cv2ClampValue2EncoderOnly : __CODEGEN_BITFIELD(8, 11); //!< CV2 - Clamp Value 2 (Encoder-only) 5000 uint32_t Cv3ClampValue3EncoderOnly : __CODEGEN_BITFIELD(12, 15); //!< CV3 - Clamp Value 3 (Encoder-only) 5001 uint32_t Cv4ClampValue4EncoderOnly : __CODEGEN_BITFIELD(16, 19); //!< CV4 - Clamp Value 4 (Encoder-only) 5002 uint32_t Cv5ClampValue5EncoderOnly : __CODEGEN_BITFIELD(20, 23); //!< CV5 - Clamp Value 5 (Encoder-only) 5003 uint32_t Cv6ClampValue6EncoderOnly : __CODEGEN_BITFIELD(24, 27); //!< CV6 - Clamp Value 6 (Encoder-only) 5004 uint32_t Cv7ClampValue7EncoderOnly : __CODEGEN_BITFIELD(28, 31); //!< CV7 - Clamp Value 7 (Encoder-only) 5005 }; 5006 uint32_t Value; 5007 } DW7; 5008 5009 //! \name Local enumerations 5010 5011 enum SUBOPCODE_B 5012 { 5013 SUBOPCODE_B_MEDIA = 3, //!< No additional details 5014 }; 5015 5016 enum SUBOPCODE_A 5017 { 5018 SUBOPCODE_A_MEDIA = 2, //!< No additional details 5019 }; 5020 5021 enum MEDIA_COMMAND_OPCODE 5022 { 5023 MEDIA_COMMAND_OPCODE_MPEG2 = 3, //!< No additional details 5024 }; 5025 5026 enum PIPELINE 5027 { 5028 PIPELINE_MFXMPEG2SLICEGROUPSTATE = 2, //!< No additional details 5029 }; 5030 5031 enum COMMAND_TYPE 5032 { 5033 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5034 }; 5035 5036 enum TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5037 { 5038 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED0 = 0, //!< no tail insertion into the output bitstream buffer, after the current slice encoded bits 5039 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED1 = 1, //!< tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 5040 }; 5041 5042 enum SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5043 { 5044 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no Slice Data insertion into the output bitstream buffer 5045 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< Slice Data insertion into the output bitstream buffer is present. 5046 }; 5047 5048 enum HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5049 { 5050 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no header insertion into the output bitstream buffer, in front of the current slice encoded bits 5051 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 5052 }; 5053 5054 //! \brief BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5055 //! \details 5056 //! This field could be set to 1 only if LoadBitStreamPointerPerSlice is set 5057 //! to 1 as well, for debugging purpose. Otherwise whenmultiple slices are 5058 //! stitched together (with LoadBitStreamPointerPerSlice is set to 0), it 5059 //! doesn't make sense to disable bitstream output. 5060 enum BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5061 { 5062 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_ENABLE = 0, //!< enable the writing of the output compressed bitstream 5063 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_DISABLE = 1, //!< disable the writing of the output compressed bitstream 5064 }; 5065 5066 //! \brief SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5067 //! \details 5068 //! This field is only valid for a P or B slice. It must be zero for other 5069 //! slice types. Rules are provided in Section 2.3.3.1.6 5070 enum SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5071 { 5072 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_ENABLE = 0, //!< Enable skip type conversion 5073 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_DISABLE = 1, //!< Disable skip type conversion 5074 }; 5075 5076 //! \brief RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY 5077 //! \details 5078 //! This field selects between two RC Panic methods. If it is set to 0, in 5079 //! panic mode, the macroblock QP is maxed out, setting to requested QP + 5080 //! QP_max_pos_mod. If it is set to 1, for an intra macroblock, AC CBPs are 5081 //! set to zero (note that DC CBPs are not modified). For inter macroblocks, 5082 //! AC and DC CBPs are forced to zero. 5083 enum RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY 5084 { 5085 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED0 = 0, //!< QP Panic 5086 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED1 = 1, //!< CBP Panic 5087 }; 5088 5089 //! \brief RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY 5090 //! \details 5091 //! If this field is set to 1, RC enters panic modewhen sum_act > 5092 //! sum_max. RC Panic Type field controls what type of panicbehavior is 5093 //! invoked. 5094 enum RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY 5095 { 5096 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5097 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5098 }; 5099 5100 enum MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5101 { 5102 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED0 = 0, //!< Always Rate Control, whereas RC becomes activeif sum_act > sum_target or sum_act < sum_target 5103 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED1 = 1, //!< Gentle Rate Control, whereas RC becomes activeif sum_act > upper_midpt or sum_act < lower_midpt 5104 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED2 = 2, //!< Loose Rate Control, whereas RC becomes activeif sum_act > sum_max or sum_act < sum_min 5105 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED3 = 3, //!< Reserved 5106 }; 5107 5108 //! \brief MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5109 //! \details 5110 //! To reset the bit allocation accumulation counter to 0 to restart the 5111 //! rate control. 5112 enum MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5113 { 5114 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_DISABLE = 0, //!< Not reset 5115 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_ENABLE = 1, //!< reset 5116 }; 5117 5118 //! \brief MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5119 //! \details 5120 //! To enable the accumulation of bit allocation for rate controlThis field 5121 //! enables hardware Rate Control logic. The rest of the RC control fields 5122 //! are only valid when this field is set to 1. Otherwise, hardware ignores 5123 //! these fields.Note: To reset MB level rate control (QRC), we need to set 5124 //! both bits MbRateCtrlFlag and MbRateCtrlReset to 1 in the new slice 5125 enum MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5126 { 5127 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5128 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5129 }; 5130 5131 //! \brief BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE 5132 //! \details 5133 //! This field specifies the memory starting address (offset) to write out 5134 //! the compressed bitstream data from the BSE processing. This pointer is 5135 //! relative to the MFC Indirect PAK-BSE Object Base Address.It is a 5136 //! byte-aligned address for the AVC bitstream data in both CABAC/CAVLC 5137 //! Modes.For Write, there is no need to have a data length field. It is 5138 //! assumed the global memory bound check specified in the 5139 //! IND_OBJ_BASE_ADDRESS command (Indirect PAK-BSE Object Access Upper 5140 //! Bound) will take care of any illegal write access.This field is only 5141 //! valid for AVC encode mode. 5142 enum BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE 5143 { 5144 BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE_UNNAMED0 = 0, //!< No additional details 5145 BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE_UNNAMED512 = 512, //!< No additional details 5146 }; 5147 5148 //! \name Initializations 5149 5150 //! \brief Explicit member initialization function 5151 MFC_MPEG2_SLICEGROUP_STATE_CMD(); 5152 5153 static const size_t dwSize = 8; 5154 static const size_t byteSize = 32; 5155 }; 5156 5157 //! 5158 //! \brief MFX_VC1_PRED_PIPE_STATE 5159 //! \details 5160 //! This command is used to set the operating states of the MFD Engine 5161 //! beyond the BSD unit. It is used with both VC1 Long and Short 5162 //! format.Driver is responsible to take the intensity compensation enable 5163 //! signal, the LumScale and the LumShift provided from the VC1 interface, 5164 //! and maintain a history of these values for reference pictures. Together 5165 //! with these three parameters specified for the current picture being 5166 //! decoded, driver will derive and supply the above sets of LumScaleX, 5167 //! LumShiftX and intensity compensation enable (single or double, forward 5168 //! or backward) signals. H/W is responsible to take these state values, and 5169 //! use them to build the lookup table (including the derivation of iScale 5170 //! and iShift) for remapping the reference frame pixels, as well as 5171 //! perfoming the actual pixel remapping calculations/process. 5172 //! 5173 struct MFX_VC1_PRED_PIPE_STATE_CMD 5174 { 5175 union 5176 { 5177 struct 5178 { 5179 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 5180 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5181 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 5182 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 5183 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 5184 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 5185 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 5186 }; 5187 uint32_t Value; 5188 } DW0; 5189 union 5190 { 5191 struct 5192 { 5193 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 3); //!< Reserved 5194 uint32_t ReferenceFrameBoundaryReplicationMode : __CODEGEN_BITFIELD(4, 7); //!< Reference Frame Boundary Replication Mode 5195 uint32_t VinIntensitycompSingleBwden : __CODEGEN_BITFIELD(8, 9); //!< vin_intensitycomp_Single_BWDen 5196 uint32_t VinIntensitycompSingleFwden : __CODEGEN_BITFIELD(10, 11); //!< vin_intensitycomp_Single_FWDen 5197 uint32_t VinIntensitycompDoubleBwden : __CODEGEN_BITFIELD(12, 13); //!< vin_intensitycomp_Double_BWDen 5198 uint32_t VinIntensitycompDoubleFwden : __CODEGEN_BITFIELD(14, 15); //!< vin_intensitycomp_Double_FWDen 5199 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 5200 }; 5201 uint32_t Value; 5202 } DW1; 5203 union 5204 { 5205 struct 5206 { 5207 uint32_t Lumscale1SingleFwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - Single - FWD 5208 uint32_t Reserved70 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5209 uint32_t Lumscale2SingleFwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - single - FWD 5210 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5211 uint32_t Lumshift1SingleFwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - single - FWD 5212 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5213 uint32_t Lumshift2SingleFwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- single - FWD 5214 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5215 }; 5216 uint32_t Value; 5217 } DW2; 5218 union 5219 { 5220 struct 5221 { 5222 uint32_t Lumscale1DoubleFwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - double - FWD 5223 uint32_t Reserved102 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5224 uint32_t Lumscale2DoubleFwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - double - FWD 5225 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5226 uint32_t Lumshift1DoubleFwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - double -FWD 5227 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5228 uint32_t Lumshift2DoubleFwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- double - FWD 5229 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5230 }; 5231 uint32_t Value; 5232 } DW3; 5233 union 5234 { 5235 struct 5236 { 5237 uint32_t Lumscale1SingleBwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - Single - BWD 5238 uint32_t Reserved134 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5239 uint32_t Lumscale2SingleBwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - single - BWD 5240 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5241 uint32_t Lumshift1SingleBwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - single - BWD 5242 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5243 uint32_t Lumshift2SingleBwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- single - BWD 5244 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5245 }; 5246 uint32_t Value; 5247 } DW4; 5248 union 5249 { 5250 struct 5251 { 5252 uint32_t Lumscale1DoubleBwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - double - BWD 5253 uint32_t Reserved166 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5254 uint32_t Lumscale2DoubleBwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - double - BWD 5255 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5256 uint32_t Lumshift1DoubleBwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - double -BWD 5257 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5258 uint32_t Lumshift2DoubleBwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- double - BWD 5259 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5260 }; 5261 uint32_t Value; 5262 } DW5; 5263 5264 //! \name Local enumerations 5265 5266 enum SUBOPCODE_B 5267 { 5268 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5269 }; 5270 5271 enum SUBOPCODE_A 5272 { 5273 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 5274 }; 5275 5276 enum MEDIA_COMMAND_OPCODE 5277 { 5278 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 5279 }; 5280 5281 enum PIPELINE 5282 { 5283 PIPELINE_MFXVC1PREDPIPESTATE = 2, //!< No additional details 5284 }; 5285 5286 enum COMMAND_TYPE 5287 { 5288 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5289 }; 5290 5291 //! \name Initializations 5292 5293 //! \brief Explicit member initialization function 5294 MFX_VC1_PRED_PIPE_STATE_CMD(); 5295 5296 static const size_t dwSize = 6; 5297 static const size_t byteSize = 24; 5298 }; 5299 5300 //! 5301 //! \brief MFD_VC1_LONG_PIC_STATE 5302 //! \details 5303 //! MFX_VC1_LONG PIC_STATE command encapsulates the decoding parameters that 5304 //! are read or derived from bitstream syntax elements above (inclusive) 5305 //! picture header layer. These parameters are static for a picture and when 5306 //! slice structure is present, these parameters are not changed from slice 5307 //! to slice of the same picture. Hence, this command is only issued at the 5308 //! beginning of processing a new picture and prior to the VC1_*_OBJECT 5309 //! command. The values set for these state variables are retained 5310 //! internally across slices.Only the parameters needed by hardware (BSD 5311 //! unit) to decode bit sequence for the macroblocks in a picture layer or a 5312 //! slice layer are presented in this command. Other parameters such as the 5313 //! ones used for inverse transform or motion compensation are provided in 5314 //! MFX_VC1_PRED_PIPE_STATE command.This Long interface format is intel 5315 //! proprietary interface. Driver will need to perform addition operations 5316 //! to generate all the fields in this command. 5317 //! 5318 struct MFD_VC1_LONG_PIC_STATE_CMD 5319 { 5320 union 5321 { 5322 struct 5323 { 5324 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 5325 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5326 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 5327 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 5328 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 5329 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 5330 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 5331 }; 5332 uint32_t Value; 5333 } DW0; 5334 union 5335 { 5336 struct 5337 { 5338 uint32_t Picturewidthinmbsminus1PictureWidthMinus1InMacroblocks : __CODEGEN_BITFIELD(0, 7); //!< PictureWidthInMBsMinus1 (Picture Width Minus 1 in Macroblocks) 5339 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 5340 uint32_t Pictureheightinmbsminus1PictureHeightMinus1InMacroblocks : __CODEGEN_BITFIELD(16, 23); //!< PictureHeightInMBsMinus1 (Picture Height Minus 1 in Macroblocks) 5341 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 5342 }; 5343 uint32_t Value; 5344 } DW1; 5345 union 5346 { 5347 struct 5348 { 5349 uint32_t Vc1Profile : __CODEGEN_BITFIELD(0, 0); //!< VC1_PROFILE 5350 uint32_t Reserved65 : __CODEGEN_BITFIELD(1, 2); //!< Reserved 5351 uint32_t Secondfield : __CODEGEN_BITFIELD(3, 3); //!< Secondfield 5352 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(4, 4); //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5353 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD(5, 5); //!< LOOPFILTER_ENABLE_FLAG 5354 uint32_t RangereductionEnable : __CODEGEN_BITFIELD(6, 6); //!< RANGEREDUCTION_ENABLE 5355 uint32_t Rangereductionscale : __CODEGEN_BITFIELD(7, 7); //!< RANGEREDUCTIONSCALE 5356 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(8, 11); //!< MOTION_VECTOR_MODE 5357 uint32_t Syncmarker : __CODEGEN_BITFIELD(12, 12); //!< SYNCMARKER 5358 uint32_t InterpolationRounderContro : __CODEGEN_BITFIELD(13, 13); //!< Interpolation Rounder Contro 5359 uint32_t Implicitquantizer : __CODEGEN_BITFIELD(14, 14); //!< ImplicitQuantizer 5360 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15); //!< DmvSurfaceValid 5361 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 23); //!< Reserved 5362 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31); //!< Bitplane Buffer Pitch Minus 1 5363 }; 5364 uint32_t Value; 5365 } DW2; 5366 union 5367 { 5368 struct 5369 { 5370 uint32_t Bscalefactor : __CODEGEN_BITFIELD(0, 7); //!< BScaleFactor 5371 uint32_t PquantPictureQuantizationValue : __CODEGEN_BITFIELD(8, 12); //!< PQuant (Picture Quantization Value) 5372 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15); //!< Reserved 5373 uint32_t AltpquantAlternativePictureQuantizationValue : __CODEGEN_BITFIELD(16, 20); //!< AltPQuant (Alternative Picture Quantization Value) 5374 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23); //!< Reserved 5375 uint32_t FcmFrameCodingMode : __CODEGEN_BITFIELD(24, 25); //!< FCM_FRAME_CODING_MODE 5376 uint32_t PictypePictureType : __CODEGEN_BITFIELD(26, 28); //!< PicType (Picture Type) 5377 uint32_t Condover : __CODEGEN_BITFIELD(29, 30); //!< CONDOVER 5378 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 5379 }; 5380 uint32_t Value; 5381 } DW3; 5382 union 5383 { 5384 struct 5385 { 5386 uint32_t Pquantuniform : __CODEGEN_BITFIELD(0, 0); //!< PQUANTUNIFORM 5387 uint32_t Halfqp : __CODEGEN_BITFIELD(1, 1); //!< HalfQP 5388 uint32_t AltpquantconfigAlternativePictureQuantizationConfiguration : __CODEGEN_BITFIELD(2, 3); //!< ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5389 uint32_t AltpquantedgemaskAlternativePictureQuantizationEdgeMask : __CODEGEN_BITFIELD(4, 7); //!< AltPQuantEdgeMask (Alternative Picture Quantization Edge Mask) 5390 uint32_t ExtendedmvrangeExtendedMotionVectorRangeFlag : __CODEGEN_BITFIELD(8, 9); //!< EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5391 uint32_t ExtendeddmvrangeExtendedDifferentialMotionVectorRangeFlag : __CODEGEN_BITFIELD(10, 11); //!< EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5392 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5393 uint32_t FwdrefdistReferenceDistance : __CODEGEN_BITFIELD(16, 19); //!< FwdRefDist (Reference Distance) 5394 uint32_t BwdrefdistReferenceDistance : __CODEGEN_BITFIELD(20, 23); //!< BwdRefDist (Reference Distance) 5395 uint32_t NumrefNumberOfReferences : __CODEGEN_BITFIELD(24, 24); //!< NUMREF_NUMBER_OF_REFERENCES 5396 uint32_t ReffieldpicpolarityReferenceFieldPicturePolarity : __CODEGEN_BITFIELD(25, 25); //!< REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5397 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(26, 26); //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5398 uint32_t FourmvswitchFourMotionVectorSwitch : __CODEGEN_BITFIELD(27, 27); //!< FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5399 uint32_t UnifiedmvmodeUnifiedMotionVectorMode : __CODEGEN_BITFIELD(28, 29); //!< UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5400 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5401 }; 5402 uint32_t Value; 5403 } DW4; 5404 union 5405 { 5406 struct 5407 { 5408 uint32_t CbptabCodedBlockPatternTable : __CODEGEN_BITFIELD(0, 2); //!< CbpTab (Coded Block Pattern Table) 5409 uint32_t TransdctabIntraTransformDcTable : __CODEGEN_BITFIELD(3, 3); //!< TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5410 uint32_t TransacuvPictureLevelTransformChromaAcCodingSetIndexTransactable : __CODEGEN_BITFIELD(4, 5); //!< TransAcUV (Picture-level Transform Chroma AC Coding Set Index, TRANSACTABLE) 5411 uint32_t TransacyPictureLevelTransformLumaAcCodingSetIndexTransactable2 : __CODEGEN_BITFIELD(6, 7); //!< TransAcY (Picture-level Transform Luma AC Coding Set Index, TRANSACTABLE2 5412 uint32_t MbmodetabMacroblockModeTable : __CODEGEN_BITFIELD(8, 10); //!< MbModeTab (Macroblock Mode Table) 5413 uint32_t TranstypembflagMacroblockTransformTypeFlag : __CODEGEN_BITFIELD(11, 11); //!< TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5414 uint32_t TranstypePictureLevelTransformType : __CODEGEN_BITFIELD(12, 13); //!< TransType (Picture-level Transform Type) 5415 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5416 uint32_t Twomvbptab2MvBlockPatternTable : __CODEGEN_BITFIELD(16, 17); //!< TwoMvBpTab (2MV Block Pattern Table) 5417 uint32_t Fourmvbptab4MvBlockPatternTable : __CODEGEN_BITFIELD(18, 19); //!< FourMvBpTab (4-MV Block Pattern Table) 5418 uint32_t MvtabMotionVectorTable : __CODEGEN_BITFIELD(20, 22); //!< MvTab (Motion Vector Table) 5419 uint32_t Reserved183 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 5420 uint32_t Fieldtxraw : __CODEGEN_BITFIELD(24, 24); //!< FIELDTXRAW 5421 uint32_t Acpredraw : __CODEGEN_BITFIELD(25, 25); //!< ACPREDRAW 5422 uint32_t Overflagsraw : __CODEGEN_BITFIELD(26, 26); //!< OVERFLAGSRAW 5423 uint32_t Directmbraw : __CODEGEN_BITFIELD(27, 27); //!< DIRECTMBRAW 5424 uint32_t Skipmbraw : __CODEGEN_BITFIELD(28, 28); //!< SKIPMBRAW 5425 uint32_t Mvtypembraw : __CODEGEN_BITFIELD(29, 29); //!< MVTYPEMBRAW 5426 uint32_t Forwardmbraw : __CODEGEN_BITFIELD(30, 30); //!< FORWARDMBRAW 5427 uint32_t BitplanepresentflagBitplaneBufferPresentFlag : __CODEGEN_BITFIELD(31, 31); //!< BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5428 }; 5429 uint32_t Value; 5430 } DW5; 5431 5432 //! \name Local enumerations 5433 5434 enum SUBOPCODE_B 5435 { 5436 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5437 }; 5438 5439 enum SUBOPCODE_A 5440 { 5441 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5442 }; 5443 5444 enum MEDIA_COMMAND_OPCODE 5445 { 5446 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5447 }; 5448 5449 enum PIPELINE 5450 { 5451 PIPELINE_MFDVC1LONGPICSTATE = 2, //!< No additional details 5452 }; 5453 5454 enum COMMAND_TYPE 5455 { 5456 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5457 }; 5458 5459 //! \brief VC1_PROFILE 5460 //! \details 5461 //! specifies the bitstream profile.This field is used in both VLD and IT 5462 //! modes. 5463 enum VC1_PROFILE 5464 { 5465 VC1_PROFILE_DISABLE = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 5466 VC1_PROFILE_ENABLE = 1, //!< current picture is in Advanced Profile 5467 }; 5468 5469 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 5470 //! \details 5471 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 5472 //! if Overlap smoothing is ON at the picture levelThis field is used in 5473 //! both VLD and IT modes. 5474 enum OVERLAP_SMOOTHING_ENABLE_FLAG 5475 { 5476 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 5477 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 5478 }; 5479 5480 //! \brief LOOPFILTER_ENABLE_FLAG 5481 //! \details 5482 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 5483 //! indicates if In-loop Deblocking is ON according to picture level 5484 //! bitstream syntax control. This bit affects BSD unit and also the loop 5485 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 5486 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 5487 //! in-loop deblocking operation follows the VC1 standard - deblocking 5488 //! doesn't cross slice boundary.When this bit is set to 0, but 5489 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 5490 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 5491 //! this case, deblocking operation does cross slice boundary.This field is 5492 //! used in VLD mode only, not in IT mode. 5493 enum LOOPFILTER_ENABLE_FLAG 5494 { 5495 LOOPFILTER_ENABLE_FLAG_DISABLE = 0, //!< Disables loop filter 5496 LOOPFILTER_ENABLE_FLAG_ENABLE = 1, //!< Enables loop filter 5497 }; 5498 5499 //! \brief RANGEREDUCTION_ENABLE 5500 //! \details 5501 //! This field specifies whether on-the-fly pixel value range reduction 5502 //! should be performed for the preceding (or forward) reference picture. 5503 //! Along with RangeReductionScale to specify whether scale up or down 5504 //! should be performed. It is not the same value as RANGEREDFRM Syntax 5505 //! Element (PictureParameters bPicDeblocked bit 5) in the Picture Header. 5506 enum RANGEREDUCTION_ENABLE 5507 { 5508 RANGEREDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 5509 RANGEREDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 5510 }; 5511 5512 //! \brief RANGEREDUCTIONSCALE 5513 //! \details 5514 //! This field specifies whether the reference picture pixel values should 5515 //! be scaled up or scaled down on-the-fly, if RangeReduction is Enabled. 5516 enum RANGEREDUCTIONSCALE 5517 { 5518 RANGEREDUCTIONSCALE_UNNAMED0 = 0, //!< Scale down reference picture by factor of 2 5519 RANGEREDUCTIONSCALE_UNNAMED1 = 1, //!< Scale up reference picture by factor of 2 5520 }; 5521 5522 //! \brief MOTION_VECTOR_MODE 5523 //! \details 5524 //! This field indicates one of the following motion compensation 5525 //! interpolation modes for P and B pictures. The MC interpolation modes 5526 //! apply to prediction values of luminance blocks and are always in 5527 //! quarter-sample. For chrominance blocks, it always performs bilinear 5528 //! interpolation with either half-pel or quarter-pel precision.Before the 5529 //! polarity of Chroma Half-pel or Q-pel is reversed from Spec, now I have 5530 //! fixed it to match with VC1 Spec. 5531 enum MOTION_VECTOR_MODE 5532 { 5533 MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Chroma Quarter -pel + Luma bicubic. (can only be 1MV) 5534 MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< Chroma Half-pel + Luma bicubic. (can be 1MV or 4MV) 5535 MOTION_VECTOR_MODE_UNNAMED8 = 8, //!< Chroma Quarter -pel + Luma bilinear. (can only be 1MV) 5536 MOTION_VECTOR_MODE_UNNAMED9 = 9, //!< Chroma Half-pel + Luma bilinear 5537 }; 5538 5539 //! \brief SYNCMARKER 5540 //! \details 5541 //! Indicates whether sync markers are enabled/disabled. If enable, sync 5542 //! markers "may be" present in the current video sequence being decoded. It 5543 //! is a sequence level syntax element and is valid only for Simple and Main 5544 //! Profiles. 5545 enum SYNCMARKER 5546 { 5547 SYNCMARKER_NOTPRESENT = 0, //!< Sync Marker is not present in the bitstream 5548 SYNCMARKER_MAYBEPRESENT = 1, //!< Sync Marker maybe present in the bitstream 5549 }; 5550 5551 //! \brief FCM_FRAME_CODING_MODE 5552 //! \details 5553 //! This is the same as the variable FCM defined in VC1.This field must be 5554 //! set to 0 for Simple and Main ProfilesThis field is unique to intel VC1 5555 //! VLD Long format, and is used in IT mode as well. For VC1 IT mode, driver 5556 //! needs to convert the interface to intel HW VLD Long Format interface. 5557 enum FCM_FRAME_CODING_MODE 5558 { 5559 FCM_FRAME_CODING_MODE_DISABLE = 0, //!< Progressive Frame Picture 5560 FCM_FRAME_CODING_MODE_ENABLE = 1, //!< Interlaced Frame Picture 5561 FCM_FRAME_CODING_MODE_UNNAMED2 = 2, //!< Field Picture with Top Field First 5562 FCM_FRAME_CODING_MODE_UNNAMED3 = 3, //!< Field Picture with Bottom Field First 5563 }; 5564 5565 //! \brief CONDOVER 5566 //! \details 5567 //! This field is the decoded syntax element CONDOVER in a bitstream of 5568 //! advanced profile. It controls the overlap smoothing filter operation for 5569 //! an I frame or an BI frame when the picture level qualization step size 5570 //! PQUANT is 8 or lower.This field is used in intel VC1 VLD mode only, not 5571 //! in VC1 and IT modes. 5572 enum CONDOVER 5573 { 5574 CONDOVER_UNNAMED0 = 0, //!< No overlap smoothing 5575 CONDOVER_UNNAMED1 = 1, //!< Reserved 5576 CONDOVER_UNNAMED2 = 2, //!< Always perform overlap smoothing filter 5577 CONDOVER_UNNAMED3 = 3, //!< Overlap smoothing on a per macroblock basis based on OVERFLAGS 5578 }; 5579 5580 //! \brief PQUANTUNIFORM 5581 //! \details 5582 //! Indicating if uniform quantization applies to thepicture. It is used for 5583 //! inverse quantization of the AC coefficients.QUANTIZER001123PQUANTIZER 5584 //! --01--PQINDEX>=9<=8----PQuantUniform010201ImplicitQuantizer = 0, 5585 //! andPQuantUniform = 0 is used to represent 2 cases : 1) QUANTIZER=01 5586 //! andPQUANTIZER=0; and 2) QUANTIZER = 10b.ImplicitQuantizer = 0, and 5587 //! PQuantUniform =1 is used to represent 2 cases : 1) QUANTIZER=01 and 5588 //! PQUANTIZER=1; and 2)QUANTIZER = 11bThis field is unique to intel VC1 VLD 5589 //! Long format mode, and isnot used in IT and VC1 modes. 5590 enum PQUANTUNIFORM 5591 { 5592 PQUANTUNIFORM_UNNAMED0 = 0, //!< Non-uniform 5593 PQUANTUNIFORM_UNNAMED1 = 1, //!< Uniform 5594 }; 5595 5596 //! \brief ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5597 //! \details 5598 //! This field specifies the way AltPQuant is used in the picture. It 5599 //! determines how to compute the macroblock quantizer step size, MQUANT. It 5600 //! is derived based on the following variables DQUANT, DQUANTFRM, 5601 //! DQPROFILE, DQSBEDGE, DQDBEDGE, and DQBILEVEL defined in the VC1 5602 //! standard, as shown in Error! Reference source not found..This field is 5603 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 5604 //! modes. 5605 enum ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5606 { 5607 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED0 = 0, //!< AltPQuant not used 5608 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED1 = 1, //!< AltPQuant is used and applied to edge macroblocks only 5609 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED2 = 2, //!< MQUANT is encoded in macroblock layer 5610 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED3 = 3, //!< AltPQuant and PQuant are selected on macroblock basis 5611 }; 5612 5613 //! \brief EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5614 //! \details 5615 //! This field specifies the motion vector range in quarter-pel or half-pel 5616 //! modes. It is equivalent to the variable MVRANGE in the VC1 standard. 5617 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5618 //! in IT and VC1 modes 5619 enum EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5620 { 5621 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< [-256, 255] x [-128, 127] 5622 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< 512, 511] x [-256, 255] 5623 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< [-2048, 2047] x [-1024, 1023] 5624 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< [-4096, 4095] x [-2048, 2047] 5625 }; 5626 5627 //! \brief EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5628 //! \details 5629 //! This field specifies the differential motion vector range in interlaced 5630 //! pictures. It is equivalent to the variable DMVRANGE in the VC1 standard. 5631 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5632 //! in IT and VC1 modes. 5633 enum EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5634 { 5635 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< No extended range 5636 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< Extended horizontally 5637 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< Extended vertically 5638 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< Extended in both directions 5639 }; 5640 5641 //! \brief NUMREF_NUMBER_OF_REFERENCES 5642 //! \details 5643 //! This field indicates how many reference fields are referenced by the 5644 //! current (field) picture. It is identical to the variable NUMREF in the 5645 //! VC1 standard. This field is only valid for field P picture (FCM = 10 | 5646 //! 11).This field is unique to intel VC1 VLD Long format mode, and is not 5647 //! used in IT and VC1 modes. 5648 enum NUMREF_NUMBER_OF_REFERENCES 5649 { 5650 NUMREF_NUMBER_OF_REFERENCES_UNNAMED0 = 0, //!< One field referenced 5651 NUMREF_NUMBER_OF_REFERENCES_UNNAMED1 = 1, //!< Two fields referenced 5652 }; 5653 5654 //! \brief REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5655 //! \details 5656 //! This field specifies the polarity of the one reference field picture 5657 //! used for a field P picture. It is derived from the variable REFFIELD 5658 //! defined in VC1 standard and is only valid when one field is referenced 5659 //! (NUMREF = 0) for a field P picture.When NUMREF = 0 and REFFIELD = 0, 5660 //! this field is the polarity of the reference I/P field that is temporally 5661 //! closest; When NUMREF = 0 and REFFIELD = 1, this field is the polarity of 5662 //! the reference I/P field that is the second most temporally closest. The 5663 //! distance is measured based on display order but ignoring the repeated 5664 //! field if present (due to RFF = 1).This field is unique to intel VC1 VLD 5665 //! Long format mode, and is not used in IT and VC1 modes. 5666 enum REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5667 { 5668 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED0 = 0, //!< Top (even) field 5669 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED1 = 1, //!< Bottom (odd) field 5670 }; 5671 5672 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5673 //! \details 5674 //! This field specifies whether the motion vectors forUV is rounded to half 5675 //! or full pel position. It is identical to the variableFASTUVMC in VC1 5676 //! standard.This field is used in both VLD and IT modes.It isderived from 5677 //! FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in both VLD andIT 5678 //! modes, and should have the same value as Motion Vector ModeLSBit. 5679 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5680 { 5681 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 5682 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 5683 }; 5684 5685 //! \brief FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5686 //! \details 5687 //! This field indicates if 4-MV is present for an interlaced frame P 5688 //! picture. It is identical to the variable 4MVSWITCH (4 Motion Vector 5689 //! Switch) in VC1 standard.This field is used in intel VC1 VLD Long Format 5690 //! mode only, it is not used in VC1 VLD and IT modes. 5691 enum FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5692 { 5693 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_DISABLE = 0, //!< only 1-MV 5694 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_ENABLE = 1, //!< 1, 2, or 4 Motion Vectors 5695 }; 5696 5697 //! \brief UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5698 //! \details 5699 //! This field is a combination of the variables MVMODE and MVMODE2 in the 5700 //! VC1 standard, for parsing Luma MVD from the bitstream. This field is 5701 //! used to signal 1MV vs 4MVallowed (Mixed Mode). This field is also used 5702 //! to signal Q-pel or Half-pel MVD read from the bitstream. The bicubic or 5703 //! bilinear Luma MC interpolation mode is duplicate information from Motion 5704 //! Vector Mode field, and is ignored here.This field is used in intel VC1 5705 //! VLD Long Format mode only, it is not used in VC1 VLD and IT modes. 5706 enum UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5707 { 5708 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Mixed MV, Q-pel bicubic 5709 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< 1-MV, Q-pel bicubic 5710 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED2 = 2, //!< 1-MV half-pel bicubic 5711 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED3 = 3, //!< 1-MV half-pel bilinear 5712 }; 5713 5714 //! \brief TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5715 //! \details 5716 //! This field specifies whether the low motion tables or the high motion 5717 //! tables are used to decode the Transform DC coefficients in intra-coded 5718 //! blocks. This field is identical to the variable TRANSDCTAB in the VC1 5719 //! standard, section 8.1.1.2.This field is valid for all picture types.This 5720 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5721 //! and VC1 modes. 5722 enum TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5723 { 5724 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED0 = 0, //!< The high motion tables 5725 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED1 = 1, //!< The low motion tables 5726 }; 5727 5728 //! \brief TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5729 //! \details 5730 //! This field indicates whether Transform Type is fixed at picture level or 5731 //! variable at macroblock level. It is identical to the variable TTMBF in 5732 //! the VC1 standard, section 7.1.1.40.This field is set to 1 when 5733 //! VSTRANSFORM is 0 in the entry point layer.This field is unique to intel 5734 //! VC1 VLD Long format mode, and is not used in IT and VC1 modes. 5735 enum TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5736 { 5737 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED0 = 0, //!< variable transform type in macroblock layer 5738 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED1 = 1, //!< use picture level transform type TransType 5739 }; 5740 5741 //! \brief FIELDTXRAW 5742 //! \details 5743 //! This field indicates whether the FIELDTX field is coded in raw or 5744 //! non-raw mode.This field is only valid when PictureType is I or BI.This 5745 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5746 //! and VC1 modes. 5747 enum FIELDTXRAW 5748 { 5749 FIELDTXRAW_DISABLE = 0, //!< Non-Raw Mode 5750 FIELDTXRAW_ENABLE = 1, //!< Raw Mode 5751 }; 5752 5753 //! \brief ACPREDRAW 5754 //! \details 5755 //! This field indicates whether the ACPRED field is coded in raw or non-raw 5756 //! mode.This field is only valid when PictureType is I or BI.This field is 5757 //! unique to intel VC1 VLD Long format mode, and is not used in IT and VC1 5758 //! modes. 5759 enum ACPREDRAW 5760 { 5761 ACPREDRAW_DISABLE = 0, //!< Non-Raw Mode 5762 ACPREDRAW_ENABLE = 1, //!< Raw Mode 5763 }; 5764 5765 //! \brief OVERFLAGSRAW 5766 //! \details 5767 //! This field indicates whether the OVERFLAGS field is coded in raw or 5768 //! non-raw mode.This field is only valid when PictureType is I or BI.This 5769 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5770 //! and VC1 modes. 5771 enum OVERFLAGSRAW 5772 { 5773 OVERFLAGSRAW_UNNAMED0 = 0, //!< Non-Raw Mode 5774 OVERFLAGSRAW_UNNAMED1 = 1, //!< Raw Mode 5775 }; 5776 5777 //! \brief DIRECTMBRAW 5778 //! \details 5779 //! This field indicates whether the DIRECTMB field is coded in raw or 5780 //! non-raw mode.This field is only valid when PictureType is P or B.This 5781 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5782 //! and VC1 modes. 5783 enum DIRECTMBRAW 5784 { 5785 DIRECTMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 5786 DIRECTMBRAW_UNNAMED1 = 1, //!< Raw Mode 5787 }; 5788 5789 //! \brief SKIPMBRAW 5790 //! \details 5791 //! This field indicates whether the SKIPMB field is coded in raw or non-raw 5792 //! mode.This field is only valid when PictureType is P or B.0 = non-raw 5793 //! mode1 = raw modeThis field is unique to intel VC1 VLD Long format mode, 5794 //! and is not used in IT and VC1 modes. 5795 enum SKIPMBRAW 5796 { 5797 SKIPMBRAW_DISABLE = 0, //!< Non-Raw Mode 5798 SKIPMBRAW_ENABLE = 1, //!< Raw Mode 5799 }; 5800 5801 //! \brief MVTYPEMBRAW 5802 //! \details 5803 //! This field indicates whether the MVTYPREMB field is coded in raw or 5804 //! non-raw mode.This field is only valid when PictureType is P.This field 5805 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 5806 //! VC1 modes. 5807 enum MVTYPEMBRAW 5808 { 5809 MVTYPEMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 5810 MVTYPEMBRAW_UNNAMED1 = 1, //!< Raw Mode 5811 }; 5812 5813 //! \brief FORWARDMBRAW 5814 //! \details 5815 //! This field indicates whether the FORWARDMB field is coded in raw or 5816 //! non-raw mode.This field is only valid when PictureType is B.This field 5817 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 5818 //! VC1 modes. 5819 enum FORWARDMBRAW 5820 { 5821 FORWARDMBRAW_UNNAMED0 = 0, //!< non-raw mode 5822 FORWARDMBRAW_UNNAMED1 = 1, //!< raw mode 5823 }; 5824 5825 //! \brief BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5826 //! \details 5827 //! This field indicates whether the bitplane buffer is present for the 5828 //! picture. If set, at least one of the fields listed in bits 22:16 is 5829 //! coded in non-raw mode, and Bitplane Buffer Base Address field in the 5830 //! VC1_BSD_BUF_BASE_STATE command points to the bitplane buffer. Otherwise, 5831 //! all the fields that are applicable for the current picture in bits 22:16 5832 //! must be coded in raw mode.This field is unique to intel VC1 VLD Long 5833 //! format mode, and is not used in IT and VC1 modes. 5834 enum BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5835 { 5836 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED0 = 0, //!< bitplane buffer is not present 5837 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED1 = 1, //!< bitplane buffer is present 5838 }; 5839 5840 //! \name Initializations 5841 5842 //! \brief Explicit member initialization function 5843 MFD_VC1_LONG_PIC_STATE_CMD(); 5844 5845 static const size_t dwSize = 6; 5846 static const size_t byteSize = 24; 5847 }; 5848 5849 //! 5850 //! \brief MFD_VC1_SHORT_PIC_STATE 5851 //! \details 5852 //! 5853 //! 5854 struct MFD_VC1_SHORT_PIC_STATE_CMD 5855 { 5856 union 5857 { 5858 struct 5859 { 5860 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 5861 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5862 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 5863 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 5864 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 5865 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 5866 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 5867 }; 5868 uint32_t Value; 5869 } DW0; 5870 union 5871 { 5872 struct 5873 { 5874 uint32_t PictureWidth : __CODEGEN_BITFIELD(0, 7); //!< Picture Width 5875 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 5876 uint32_t PictureHeight : __CODEGEN_BITFIELD(16, 23); //!< Picture Height 5877 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 5878 }; 5879 uint32_t Value; 5880 } DW1; 5881 union 5882 { 5883 struct 5884 { 5885 uint32_t PictureStructure : __CODEGEN_BITFIELD(0, 1); //!< PICTURE_STRUCTURE 5886 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 2); //!< Reserved 5887 uint32_t Secondfield : __CODEGEN_BITFIELD(3, 3); //!< SecondField 5888 uint32_t IntraPictureFlag : __CODEGEN_BITFIELD(4, 4); //!< INTRA_PICTURE_FLAG 5889 uint32_t BackwardPredictionPresentFlag : __CODEGEN_BITFIELD(5, 5); //!< Backward Prediction Present Flag 5890 uint32_t Reserved70 : __CODEGEN_BITFIELD(6, 10); //!< Reserved 5891 uint32_t Vc1Profile : __CODEGEN_BITFIELD(11, 11); //!< VC1_PROFILE 5892 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 14); //!< Reserved 5893 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15); //!< DmvSurfaceValid 5894 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(16, 19); //!< Motion Vector Mode 5895 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 22); //!< Reserved 5896 uint32_t InterpolationRounderControl : __CODEGEN_BITFIELD(23, 23); //!< Interpolation Rounder Control 5897 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31); //!< Bitplane Buffer Pitch Minus 1 5898 }; 5899 uint32_t Value; 5900 } DW2; 5901 union 5902 { 5903 struct 5904 { 5905 uint32_t VstransformFlag : __CODEGEN_BITFIELD(0, 0); //!< VSTRANSFORM_FLAG 5906 uint32_t Dquant : __CODEGEN_BITFIELD(1, 2); //!< DQUANT 5907 uint32_t ExtendedMvPresentFlag : __CODEGEN_BITFIELD(3, 3); //!< EXTENDED_MV_PRESENT_FLAG 5908 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(4, 4); //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5909 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD(5, 5); //!< LOOPFILTER_ENABLE_FLAG 5910 uint32_t RefdistFlag : __CODEGEN_BITFIELD(6, 6); //!< REFDIST_FLAG 5911 uint32_t PanscanPresentFlag : __CODEGEN_BITFIELD(7, 7); //!< PANSCAN_PRESENT_FLAG 5912 uint32_t Maxbframes : __CODEGEN_BITFIELD(8, 10); //!< MAXBFRAMES 5913 uint32_t RangeredPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(11, 11); //!< RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 5914 uint32_t SyncmarkerPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(12, 12); //!< SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 5915 uint32_t MultiresPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(13, 13); //!< MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 5916 uint32_t Quantizer : __CODEGEN_BITFIELD(14, 15); //!< QUANTIZER 5917 uint32_t PPicRefDistance : __CODEGEN_BITFIELD(16, 20); //!< P_PIC_REF_DISTANCE 5918 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 5919 uint32_t ProgressivePicType : __CODEGEN_BITFIELD(22, 23); //!< PROGRESSIVE_PIC_TYPE 5920 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 27); //!< Reserved 5921 uint32_t RangeReductionEnable : __CODEGEN_BITFIELD(28, 28); //!< RANGE_REDUCTION_ENABLE 5922 uint32_t RangeReductionScale : __CODEGEN_BITFIELD(29, 29); //!< RANGE_REDUCTION_SCALE 5923 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(30, 30); //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5924 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 5925 }; 5926 uint32_t Value; 5927 } DW3; 5928 union 5929 { 5930 struct 5931 { 5932 uint32_t ExtendedDmvPresentFlag : __CODEGEN_BITFIELD(0, 0); //!< EXTENDED_DMV_PRESENT_FLAG 5933 uint32_t Psf : __CODEGEN_BITFIELD(1, 1); //!< PSF 5934 uint32_t RefpicFlag : __CODEGEN_BITFIELD(2, 2); //!< REFPIC_FLAG 5935 uint32_t Finterflag : __CODEGEN_BITFIELD(3, 3); //!< FINTERFLAG 5936 uint32_t Tfcntrflag : __CODEGEN_BITFIELD(4, 4); //!< TFCNTRFLAG 5937 uint32_t Interlace : __CODEGEN_BITFIELD(5, 5); //!< INTERLACE 5938 uint32_t Pulldown : __CODEGEN_BITFIELD(6, 6); //!< PULLDOWN 5939 uint32_t PostprocFlag : __CODEGEN_BITFIELD(7, 7); //!< POSTPROC Flag 5940 uint32_t _4MvAllowedFlag : __CODEGEN_BITFIELD(8, 8); //!< 4MV Allowed Flag 5941 uint32_t Reserved137 : __CODEGEN_BITFIELD(9, 23); //!< Reserved 5942 uint32_t BfractionEnumeration : __CODEGEN_BITFIELD(24, 28); //!< BFraction Enumeration 5943 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 5944 }; 5945 uint32_t Value; 5946 } DW4; 5947 5948 //! \name Local enumerations 5949 5950 enum SUBOPCODE_B 5951 { 5952 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 5953 }; 5954 5955 enum SUBOPCODE_A 5956 { 5957 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5958 }; 5959 5960 enum MEDIA_COMMAND_OPCODE 5961 { 5962 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5963 }; 5964 5965 enum PIPELINE 5966 { 5967 PIPELINE_MFDVC1SHORTPICSTATE = 2, //!< No additional details 5968 }; 5969 5970 enum COMMAND_TYPE 5971 { 5972 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5973 }; 5974 5975 //! \brief PICTURE_STRUCTURE 5976 //! \details 5977 //! This field is used in both VC1 VLD mode and IT mode. It is the same 5978 //! parameter as bPicStructure in VC1 spec.The Picture Structure and 5979 //! Progressive Pic Type are used to derive the picture structure as 5980 //! specified in FCM, in VC1 VLD and IT mode. 5981 enum PICTURE_STRUCTURE 5982 { 5983 PICTURE_STRUCTURE_UNNAMED0 = 0, //!< illegal 5984 PICTURE_STRUCTURE_UNNAMED1 = 1, //!< top field (bit 0) 5985 PICTURE_STRUCTURE_UNNAMED2 = 2, //!< bottom field (bit 1) 5986 PICTURE_STRUCTURE_UNNAMED3 = 3, //!< frame (both fields are present) 5987 }; 5988 5989 //! \brief INTRA_PICTURE_FLAG 5990 //! \details 5991 //! This field is used in both VC1 VLD mode and IT mode. It is the same 5992 //! parameter as bPicIntra in VC1 spec. The Intra Picture Flag, Backward 5993 //! Prediction Present Flag and RefPicFlag are used to derive the picture 5994 //! type, as specified in PTYPE for a frame, and in FPTYPE for a field, in 5995 //! VC1 VLD and IT mode. 5996 enum INTRA_PICTURE_FLAG 5997 { 5998 INTRA_PICTURE_FLAG_UNNAMED0 = 0, //!< entire picture can have a mixture of intra and inter MB type or just inter MB type. 5999 INTRA_PICTURE_FLAG_UNNAMED1 = 1, //!< entire picture is coded in intra MB type 6000 }; 6001 6002 //! \brief VC1_PROFILE 6003 //! \details 6004 //! specifies the bitstream profile.Note: This is required because 128 is 6005 //! added for intra blocks post inverse transform in advanced profile and 6006 //! also to find out if Motion vectors are adjusted or not.This field is 6007 //! used in both VLD and IT modes. 6008 enum VC1_PROFILE 6009 { 6010 VC1_PROFILE_UNNAMED0 = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 6011 VC1_PROFILE_UNNAMED1 = 1, //!< current picture is in Advanced Profile 6012 }; 6013 6014 enum VSTRANSFORM_FLAG 6015 { 6016 VSTRANSFORM_FLAG_DISABLE = 0, //!< variable-sized transform coding is not enabled 6017 VSTRANSFORM_FLAG_ENABLE = 1, //!< variable-sized transform coding is enabled 6018 }; 6019 6020 //! \brief DQUANT 6021 //! \details 6022 //! Use for Picture Header Parsing of VOPDUANT elements 6023 enum DQUANT 6024 { 6025 DQUANT_UNNAMED0 = 0, //!< no VOPDQUANT elements; Quantizer cannot vary in frame, same quantization step size PQUANT is used for all MBs in the frame 6026 DQUANT_UNNAMED1 = 1, //!< refer to VC1 Spec. for all the MB position dependent quantizer selection 6027 DQUANT_UNNAMED2 = 2, //!< The macroblocks located on the picture edge boundary shall be quantized with ALTPQUANT while the rest of the macroblocks shall be quantized with PQUANT. 6028 }; 6029 6030 //! \brief EXTENDED_MV_PRESENT_FLAG 6031 //! \details 6032 //! BitFieldDesc 6033 enum EXTENDED_MV_PRESENT_FLAG 6034 { 6035 EXTENDED_MV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_MV is not present in the picture header 6036 EXTENDED_MV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_MV is present in the picture header 6037 }; 6038 6039 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6040 //! \details 6041 //! This field specifies whether the motion vectors forUV is rounded to half 6042 //! or full pel position. It is identical to the variableFASTUVMC in VC1 6043 //! standard.This field is used in both VLD and IT modes.It isderived from 6044 //! FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in both VLD andIT 6045 //! modes, and should have the same value as Motion Vector ModeLSBit. 6046 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6047 { 6048 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6049 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6050 }; 6051 6052 //! \brief LOOPFILTER_ENABLE_FLAG 6053 //! \details 6054 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 6055 //! indicates if In-loop Deblocking is ON according to picture level 6056 //! bitstream syntax control. This bit affects BSD unit and also the loop 6057 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 6058 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 6059 //! in-loop deblocking operation follows the VC1 standard - deblocking 6060 //! doesn't cross slice boundary.When this bit is set to 0, but 6061 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 6062 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 6063 //! this case, deblocking operation does cross slice boundary.This field is 6064 //! used in VLD mode only, not in IT mode. 6065 enum LOOPFILTER_ENABLE_FLAG 6066 { 6067 LOOPFILTER_ENABLE_FLAG_UNNAMED0 = 0, //!< In-Loop-Deblocking-Filter is disabled 6068 LOOPFILTER_ENABLE_FLAG_UNNAMED1 = 1, //!< In-Loop-Deblocking-Filter is enabled 6069 }; 6070 6071 enum PANSCAN_PRESENT_FLAG 6072 { 6073 PANSCAN_PRESENT_FLAG_UNNAMED0 = 0, //!< Pan Scan Parameters are not present in the picture header 6074 PANSCAN_PRESENT_FLAG_UNNAMED1 = 1, //!< Pan Scan Parameters are present in the picture header 6075 }; 6076 6077 //! \brief RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6078 //! \details 6079 //! It is needed for Picture Header Parsing.Driver is responsible to keep 6080 //! RangeReductionScale, RangeReduction Enable and RANGERED Present Flag of 6081 //! current picture coherent. 6082 enum RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6083 { 6084 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Range Reduction Parameter (RANGEREDFRM) is not present in the picture header 6085 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Range Reduction Parameter (RANGEREDFRM) is present in the picture header. 6086 }; 6087 6088 enum SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6089 { 6090 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Bitstream for Simple and Main Profile has no sync marker 6091 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Bitstream for Simple and Main Profile may have sync marker(s) 6092 }; 6093 6094 enum MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6095 { 6096 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< RESPIC Parameter is present in the picture header 6097 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< RESPIC Parameter is present in the picture header 6098 }; 6099 6100 enum QUANTIZER 6101 { 6102 QUANTIZER_UNNAMED0 = 0, //!< implicit quantizer at frame leve 6103 QUANTIZER_UNNAMED1 = 1, //!< explicit quantizer at frame level, and use PQUANTIZER SE to specify uniform or non-uniform 6104 QUANTIZER_UNNAMED2 = 2, //!< explicit quantizer, and non-uniform quantizer for all frames 6105 QUANTIZER_UNNAMED3 = 3, //!< explicit quantizer, and uniform quantizer for all frames 6106 }; 6107 6108 //! \brief P_PIC_REF_DISTANCE 6109 //! \details 6110 //! This element defines the number of frames between the current frame and 6111 //! the reference frame. It is the same as the REFDIST SE in VC1 interlaced 6112 //! field picture header. It is present if the entry-level flag REFDIST_FLAG 6113 //! == 1, and if the picture type is not one of the following types: B/B, 6114 //! B/BI, BI/B, BI/BI. If the entry level flag REFDIST_FLAG == 0, REFDIST 6115 //! shall be set to the default value of 0.This field is used in VC1 VLD 6116 //! mode only, not used in IT and intel VC1 VLD Long Format modes. 6117 enum P_PIC_REF_DISTANCE 6118 { 6119 P_PIC_REF_DISTANCE_UNNAMED0 = 0, //!< No additional details 6120 }; 6121 6122 //! \brief PROGRESSIVE_PIC_TYPE 6123 //! \details 6124 //! This field is used in both VC1 VLD mode and IT mode. It is the same 6125 //! parameter as bPicExtrapolation in VC1 spec.The Picture Structure and 6126 //! Progressive Pic Type are used to derive the picture structure as 6127 //! specified in FCM, in VC1 VLD and IT mode. 6128 enum PROGRESSIVE_PIC_TYPE 6129 { 6130 PROGRESSIVE_PIC_TYPE_UNNAMED0 = 0, //!< progressive only picture 6131 PROGRESSIVE_PIC_TYPE_UNNAMED1 = 1, //!< progressive only picture 6132 PROGRESSIVE_PIC_TYPE_UNNAMED2 = 2, //!< interlace picture (frame-interlace or field-interlace) 6133 PROGRESSIVE_PIC_TYPE_UNNAMED3 = 3, //!< illegal 6134 }; 6135 6136 //! \brief RANGE_REDUCTION_ENABLE 6137 //! \details 6138 //! This field specifies whether on-the-fly pixel valuerange reduction 6139 //! should be performed for the preceding (or forward) referencepicture. 6140 //! Along with RangeReductionScale to specify whether scale up or downshould 6141 //! be performed. It is not the same value as RANGEREDFRM Syntax 6142 //! Element(PictureParameters bPicDeblocked bit 5) in the Picture 6143 //! Header.This field isfor Main Profile only. Simple Profile is always 6144 //! disable, and not applicable toAdvanced Profile. This field is used in 6145 //! both VLD and IT modes.This is derived bydriver from the history of 6146 //! RANGERED and RANGEREDFRM syntax elements (i.e. offorward/preceding 6147 //! reference picture) and those of the current picture.RANGEREDis the same 6148 //! as (bPicOverflowBlocks >> 3) & 1. RANGEREDFRM is the sameas 6149 //! (bPicDeblocked >> 5) & 1.For the current picture is a B 6150 //! picture,this field represents the state of the forward/preceding 6151 //! reference pictureonlyDriver is responsible to keep RangeReductionScale, 6152 //! RangeReduction Enable andRANGERED Present Flag of current picture 6153 //! coherent. 6154 enum RANGE_REDUCTION_ENABLE 6155 { 6156 RANGE_REDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 6157 RANGE_REDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 6158 }; 6159 6160 //! \brief RANGE_REDUCTION_SCALE 6161 //! \details 6162 //! This field specifies whether the reference picturepixel values should be 6163 //! scaled up or scaled down on-the-fly, if RangeReduction isEnabled.NOTE: 6164 //! This bit is derived by driver for Main Profile only. Ignored inSimple 6165 //! and Advanced Profiles. This field is used in both VLD and IT 6166 //! modes.Thisis derived by driver from the history of RANGERED and 6167 //! RANGEREDFRM syntaxelements (i.e. of forward/preceding reference picture) 6168 //! and those of the currentpicture. RANGERED is the same as 6169 //! (bPicOverflowBlocks >> 3) & 1.RANGEREDFRM is the same as 6170 //! (bPicDeblocked >> 5) & 1. For the currentpicture is a B 6171 //! picture, this field represents the state of the 6172 //! forward/precedingreference picture onlyDriver is responsible to keep 6173 //! RangeReductionScale,RangeReduction Enable and RANGERED Present Flag of 6174 //! current picturecoherent. 6175 enum RANGE_REDUCTION_SCALE 6176 { 6177 RANGE_REDUCTION_SCALE_DISABLE = 0, //!< Scale down reference picture by factor of 2 6178 RANGE_REDUCTION_SCALE_ENABLE = 1, //!< Scale up reference picture by factor of 2 6179 }; 6180 6181 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 6182 //! \details 6183 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 6184 //! if Overlap smoothing is ON at the picture levelThis field is used in 6185 //! both VLD and IT modes 6186 enum OVERLAP_SMOOTHING_ENABLE_FLAG 6187 { 6188 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 6189 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 6190 }; 6191 6192 enum EXTENDED_DMV_PRESENT_FLAG 6193 { 6194 EXTENDED_DMV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_DMV is not present in the picture header 6195 EXTENDED_DMV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_DMV is present in the picture header 6196 }; 6197 6198 //! \brief REFPIC_FLAG 6199 //! \details 6200 //! For a BI picture, REFPIC flag must set to 0For I and P picture, REFPIC 6201 //! flag must set to 0.For a B picture, REFPIC flag must set to 0, except 6202 //! for a B-field in interlaced field mode which can be 0 or 1 (e.g. the top 6203 //! B field can be used as a reference for decoding its corresponding bottom 6204 //! B-field in a field pair).In VLD mode, this flag cannot be used as an 6205 //! optimization signaling for an I or P picture that is not used as a 6206 //! reference picture.This field is used in both VC1 VLD mode and IT mode. 6207 //! It is the same parameter as bPicDeblockConfined[bit2] in VC1 spec.The 6208 //! Intra Picture Flag, Backward Prediction Present Flag and RefPicFlag are 6209 //! used to derive the picture type, as specified in PTYPE for a frame, and 6210 //! in FPTYPE for a field, in VC1 VLD and IT mode. 6211 enum REFPIC_FLAG 6212 { 6213 REFPIC_FLAG_UNNAMED0 = 0, //!< the current picture after decoded, will never used as a reference picture 6214 REFPIC_FLAG_UNNAMED1 = 1, //!< the current picture after decoded, will be used as a reference picture later 6215 }; 6216 6217 //! \name Initializations 6218 6219 //! \brief Explicit member initialization function 6220 MFD_VC1_SHORT_PIC_STATE_CMD(); 6221 6222 static const size_t dwSize = 5; 6223 static const size_t byteSize = 20; 6224 }; 6225 6226 //! 6227 //! \brief MFX_VC1_DIRECTMODE_STATE 6228 //! \details 6229 //! This is a picture level command and should be issued only once, even for 6230 //! a multi-slices picture. There is only one DMV buffer for read (when 6231 //! processing a B-picture) and one for write (when processing a P-Picture). 6232 //! Each DMV record is 64 bits per MB, to store the top and bottom field 6233 //! Motion Vectors (32-bit MVx,y each). 6234 //! 6235 struct MFX_VC1_DIRECTMODE_STATE_CMD 6236 { 6237 union 6238 { 6239 struct 6240 { 6241 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6242 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6243 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6244 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6245 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6246 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6247 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6248 }; 6249 uint32_t Value; 6250 } DW0; 6251 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvWriteBufferBaseAddress; //!< DW1..2, Direct MV Write Buffer - Base Address 6252 MEMORYADDRESSATTRIBUTES_CMD DirectMvWriteBufferAttributes; //!< DW3, Direct MV Write Buffer - Attributes 6253 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvReferenceBufferBaseAddress; //!< DW4..5, Direct MV Reference Buffer - Base Address 6254 MEMORYADDRESSATTRIBUTES_CMD DirectMvReferenceBufferAttributes; //!< DW6, Direct MV Reference Buffer - Attributes 6255 6256 //! \name Local enumerations 6257 6258 enum SUBOPCODE_B 6259 { 6260 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 6261 }; 6262 6263 enum SUBOPCODE_A 6264 { 6265 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 6266 }; 6267 6268 enum MEDIA_COMMAND_OPCODE 6269 { 6270 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 6271 }; 6272 6273 enum PIPELINE 6274 { 6275 PIPELINE_MFXVC1DIRECTMODESTATE = 2, //!< No additional details 6276 }; 6277 6278 enum COMMAND_TYPE 6279 { 6280 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6281 }; 6282 6283 //! \name Initializations 6284 6285 //! \brief Explicit member initialization function 6286 MFX_VC1_DIRECTMODE_STATE_CMD(); 6287 6288 static const size_t dwSize = 7; 6289 static const size_t byteSize = 28; 6290 }; 6291 6292 //! 6293 //! \brief MFD_VC1_BSD_OBJECT 6294 //! \details 6295 //! The MFD_VC1_BSD_OBJECT command is the only primitive command for the VC1 6296 //! Decoding Pipeline. The macroblock data portion of the bitstream is 6297 //! loaded as indirect data object.Before issuing a MFD_VC1_BSD_OBJECT 6298 //! command, all VC1 states of the MFD Engine need to be valid. Therefore 6299 //! the commands used to set these states need to have been issued prior to 6300 //! the issue of a MFD_VC1_BSD_OBJECT command.VC1 deblock filter kernel 6301 //! cross the slice boundary if in the last MB row of a slice, so need to 6302 //! know the last MB row of a slice to disable the edge mask. There is why 6303 //! VC1 BSD hardware need to know the end of MB address for the current 6304 //! slice. As such no more phantom slice is needed for VC1, as long as the 6305 //! driver will program both start MB address in the current slice and the 6306 //! start MB address of the next slice. As a result, we can also support 6307 //! multiple picture state commands in between slices. 6308 //! 6309 struct MFD_VC1_BSD_OBJECT_CMD 6310 { 6311 union 6312 { 6313 struct 6314 { 6315 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6316 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6317 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6318 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6319 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6320 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6321 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6322 }; 6323 uint32_t Value; 6324 } DW0; 6325 union 6326 { 6327 struct 6328 { 6329 uint32_t IndirectBsdDataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect BSD Data Length 6330 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 6331 }; 6332 uint32_t Value; 6333 } DW1; 6334 union 6335 { 6336 struct 6337 { 6338 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_DATA_START_ADDRESS 6339 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 6340 }; 6341 uint32_t Value; 6342 } DW2; 6343 union 6344 { 6345 struct 6346 { 6347 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(0, 8); //!< Next Slice Vertical Position 6348 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 6349 uint32_t SliceStartVerticalPosition : __CODEGEN_BITFIELD(16, 23); //!< Slice Start Vertical Position 6350 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 6351 }; 6352 uint32_t Value; 6353 } DW3; 6354 union 6355 { 6356 struct 6357 { 6358 uint32_t FirstmbbitoffsetFirstMacroblockBitOffset : __CODEGEN_BITFIELD(0, 2); //!< FirstMbBitOffset (First Macroblock Bit Offset ) 6359 uint32_t Reserved131 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 6360 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD(4, 4); //!< EMULATION_PREVENTION_BYTE_PRESENT 6361 uint32_t Reserved133 : __CODEGEN_BITFIELD(5, 15); //!< Reserved 6362 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31); //!< First_MB_Byte_Offset of Slice Data or Slice Header 6363 }; 6364 uint32_t Value; 6365 } DW4; 6366 6367 //! \name Local enumerations 6368 6369 enum SUBOPCODE_B 6370 { 6371 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6372 }; 6373 6374 enum SUBOPCODE_A 6375 { 6376 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6377 }; 6378 6379 enum MEDIA_COMMAND_OPCODE 6380 { 6381 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6382 }; 6383 6384 enum PIPELINE 6385 { 6386 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6387 }; 6388 6389 enum COMMAND_TYPE 6390 { 6391 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6392 }; 6393 6394 //! \brief INDIRECT_DATA_START_ADDRESS 6395 //! \details 6396 //! This field specifies the Graphics Memory starting address of the data to 6397 //! be fetched into BSD Unit for processing. This pointer is relative to the 6398 //! MFD Indirect Object Base Address.Hardware ignores this field if indirect 6399 //! data is not present. It is a byte-aligned address for the VC1 bitstream 6400 //! data. 6401 enum INDIRECT_DATA_START_ADDRESS 6402 { 6403 INDIRECT_DATA_START_ADDRESS_UNNAMED0 = 0, //!< No additional details 6404 INDIRECT_DATA_START_ADDRESS_UNNAMED512 = 512, //!< No additional details 6405 }; 6406 6407 enum EMULATION_PREVENTION_BYTE_PRESENT 6408 { 6409 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 6410 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 6411 }; 6412 6413 //! \name Initializations 6414 6415 //! \brief Explicit member initialization function 6416 MFD_VC1_BSD_OBJECT_CMD(); 6417 6418 static const size_t dwSize = 5; 6419 static const size_t byteSize = 20; 6420 }; 6421 6422 //! 6423 //! \brief MFX_JPEG_PIC_STATE 6424 //! \details 6425 //! 6426 //! 6427 struct MFX_JPEG_PIC_STATE_CMD 6428 { 6429 union 6430 { 6431 struct 6432 { 6433 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6434 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6435 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6436 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6437 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6438 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6439 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6440 }; 6441 uint32_t Value; 6442 } DW0; 6443 union 6444 { 6445 struct 6446 { 6447 uint32_t OutputMcuStructure : __CODEGEN_BITFIELD(0, 2); //!< OUTPUT_MCU_STRUCTURE, Encoder Only 6448 uint32_t Reserved35 : __CODEGEN_BITFIELD(3, 7); //!< Reserved, Encoder Only 6449 uint32_t InputSurfaceFormatYuv : __CODEGEN_BITFIELD(8, 11); //!< INPUT_SURFACE_FORMAT_YUV, Encoder Only 6450 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 20); //!< Reserved, Encoder Only 6451 uint32_t PixelsInVerticalLastMcu : __CODEGEN_BITFIELD(21, 25); //!< Pixels In Vertical Last MCU, Encoder Only 6452 uint32_t PixelsInHorizontalLastMcu : __CODEGEN_BITFIELD(26, 30); //!< Pixels In Horizontal Last MCU, Encoder Only 6453 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31); //!< Reserved, Encoder Only 6454 } Obj0; 6455 struct 6456 { 6457 uint32_t InputFormatYuv : __CODEGEN_BITFIELD(0, 2); //!< INPUT_FORMAT_YUV, Decoder Only 6458 uint32_t Reserved35 : __CODEGEN_BITFIELD(3, 3); //!< Reserved, Decoder Only 6459 uint32_t Rotation : __CODEGEN_BITFIELD(4, 5); //!< ROTATION, Decoder Only 6460 uint32_t Reserved38 : __CODEGEN_BITFIELD(6, 7); //!< Reserved, Decoder Only 6461 uint32_t OutputFormatYuv : __CODEGEN_BITFIELD(8, 11); //!< OUTPUT_FORMAT_YUV, Decoder Only 6462 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 15); //!< Reserved, Decoder Only 6463 uint32_t AverageDownSampling : __CODEGEN_BITFIELD(16, 16); //!< AVERAGE_DOWN_SAMPLING, Decoder Only 6464 uint32_t VerticalDownSamplingEnable : __CODEGEN_BITFIELD(17, 17); //!< VERTICAL_DOWN_SAMPLING_ENABLE, Decoder Only 6465 uint32_t HorizontalDownSamplingEnable : __CODEGEN_BITFIELD(18, 18); //!< HORIZONTAL_DOWN_SAMPLING_ENABLE, Decoder Only 6466 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19); //!< Reserved, Decoder Only 6467 uint32_t VerticalUpSamplingEnable : __CODEGEN_BITFIELD(20, 20); //!< VERTICAL_UP_SAMPLING_ENABLE, Decoder Only 6468 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31); //!< Reserved, Decoder Only 6469 } Obj1; 6470 uint32_t Value; 6471 } DW1; 6472 union 6473 { 6474 struct 6475 { 6476 uint32_t FrameWidthInBlocksMinus1 : __CODEGEN_BITFIELD(0, 12); //!< Frame Width In Blocks Minus 1, Decoder Only 6477 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 15); //!< Reserved, Decoder Only 6478 uint32_t FrameHeightInBlocksMinus1 : __CODEGEN_BITFIELD(16, 28); //!< Frame Height In Blocks Minus 1, Decoder Only 6479 uint32_t OutputPixelNormalize : __CODEGEN_BITFIELD(29, 29); //!< OUTPUT_PIXEL_NORMALIZE, Decoder Only 6480 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31); //!< Reserved, Decoder Only 6481 } Obj0; 6482 struct 6483 { 6484 uint32_t FrameWidthInBlksMinus1 : __CODEGEN_BITFIELD(0, 12); //!< Frame Width In Blks Minus 1, Encoder Only 6485 uint32_t Roundingquant : __CODEGEN_BITFIELD(13, 15); //!< ROUNDINGQUANT, Encoder Only 6486 uint32_t FrameHeightInBlksMinus1 : __CODEGEN_BITFIELD(16, 28); //!< Frame Height In Blks Minus 1, Encoder Only 6487 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved, Encoder Only 6488 } Obj1; 6489 uint32_t Value; 6490 } DW2; 6491 6492 //! \name Local enumerations 6493 6494 enum SUBOPCODE_B 6495 { 6496 SUBOPCODE_B_MEDIA = 0, //!< No additional details 6497 }; 6498 6499 enum SUBOPCODE_A 6500 { 6501 SUBOPCODE_A_COMMON = 0, //!< No additional details 6502 }; 6503 6504 enum MEDIA_COMMAND_OPCODE 6505 { 6506 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 6507 }; 6508 6509 enum PIPELINE 6510 { 6511 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6512 }; 6513 6514 enum COMMAND_TYPE 6515 { 6516 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6517 }; 6518 6519 //! \brief OUTPUT_MCU_STRUCTURE 6520 //! \details 6521 //! />Output MCU Structure(OutputMcuStructure) should be set 6522 //! accordingly for each Input Surface Format 6523 //! YUV(InputSurfaceFormatYUV):If 6524 //! InputSurfaceFormatYUV is set to NV12, OutputMCUStructure 6525 //! is set to YUV420. 6526 //If InputSurfaceFormatYUV is set to UYVY 6527 //! or YUY2, OutputMCUStructure is set to YUV422H_2Y. 6528 //If 6529 //! InputSurfaceFormatYUV is set to Y8, OutputMCuStructure is 6530 //! set to YUV400. 6531 //If InputSurfaceFormatYUV is set to RGB (or 6532 //! GBR, BGR, YUV), OutputMCuStructure is set to RGB. 6533 //If 6534 //! InputSurfaceFormatYUV is set to RGB, the order of encoded blocks 6535 //! in MCU will be same as the order of input image components. If the order 6536 //! of input image components is RGB (or GBR, BGR, YUV), then the order of 6537 //! blocks will be RGB (or GBR, BGR, YUV respectively). 6538 /// > 6539 enum OUTPUT_MCU_STRUCTURE 6540 { 6541 OUTPUT_MCU_STRUCTURE_YUV400 = 0, //!< Grayscale Image 6542 OUTPUT_MCU_STRUCTURE_YUV420 = 1, //!< Both horizontally and vertically chroma 2:1 subsampled 6543 OUTPUT_MCU_STRUCTURE_YUV422H2Y = 2, //!< Horizontally chroma 2:1 subsampled - horizontal 2 Y-blocks, 1 U and 1 V block 6544 OUTPUT_MCU_STRUCTURE_RGB = 3, //!< RGB or YUV444: No subsample 6545 OUTPUT_MCU_STRUCTURE_UNNAMED4 = 4, //!< Reserved for YUV411: Horizontally chroma 4:1 subsampled -- horizontal 4 Y-block, 1U and 1V 6546 OUTPUT_MCU_STRUCTURE_UNNAMED5 = 5, //!< Reserved for YUV422V_2Y: Vertically chroma 2:1 subsampled - vertical 2 Y-blocks, 1U and 1V 6547 OUTPUT_MCU_STRUCTURE_UNNAMED6 = 6, //!< Reserved for YUV422H_4Y: Horizontally chroma 2:1 subsampled - 2x2 Y-blocks, vertical 2U and 2V 6548 OUTPUT_MCU_STRUCTURE_UNNAMED7 = 7, //!< Reserved for YUV422V_4Y: Vertically chroma 2:1 subsampled - 2x2 Y-blocks, horizontal 2U and 2V 6549 }; 6550 6551 enum INPUT_FORMAT_YUV 6552 { 6553 INPUT_FORMAT_YUV_UNNAMED0 = 0, //!< YUV400 (grayscale image) 6554 INPUT_FORMAT_YUV_UNNAMED1 = 1, //!< YUV420 6555 INPUT_FORMAT_YUV_UNNAMED2 = 2, //!< YUV422H_2Y (Horizontally chroma 2:1 subsampled) - horizontal 2 Y-block, 1U and 1V 6556 INPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUV444 6557 INPUT_FORMAT_YUV_UNNAMED4 = 4, //!< YUV411 6558 INPUT_FORMAT_YUV_UNNAMED5 = 5, //!< YUV422V_2Y (Vertically chroma 2:1 subsampled) - vertical 2 Y-blocks, 1U and 1V 6559 INPUT_FORMAT_YUV_UNNAMED6 = 6, //!< YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V 6560 INPUT_FORMAT_YUV_UNNAMED7 = 7, //!< YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V 6561 }; 6562 6563 //! \brief ROTATION 6564 //! \details 6565 //! Rotation can be set to 01b, 10b, or 11b when OutputFormatYUV is set to 6566 //! 0000b. For other OutputFormatYUV, Rotation is not allowed. 6567 enum ROTATION 6568 { 6569 ROTATION_UNNAMED0 = 0, //!< no rotation 6570 ROTATION_UNNAMED1 = 1, //!< rotate clockwise 90 degree 6571 ROTATION_UNNAMED2 = 2, //!< rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) 6572 ROTATION_UNNAMED3 = 3, //!< rotate 180 degree (NOT the same as flipped on the x-axis) 6573 }; 6574 6575 //! \brief OUTPUT_FORMAT_YUV 6576 //! \details 6577 //! This field specifies the surface format to write the decoded JPEG 6578 //! image.Note that any non-interleaved JPEG input should be set to "0000". 6579 //! For the interleaved input Scan data, it can be set either "0000" or the 6580 //! corresponding format. 6581 enum OUTPUT_FORMAT_YUV 6582 { 6583 OUTPUT_FORMAT_YUV_UNNAMED0 = 0, //!< 3 separate plane for Y, U, and V respectively 6584 OUTPUT_FORMAT_YUV_UNNAMED1 = 1, //!< NV12 for chroma 4:2:0 6585 OUTPUT_FORMAT_YUV_UNNAMED2 = 2, //!< UYVY for chroma 4:2:2 6586 OUTPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUY2 for chroma 4:2:2 6587 }; 6588 6589 //! \brief INPUT_SURFACE_FORMAT_YUV 6590 //! \details 6591 //! This field specifies the surface format to read a YUV image data 6592 enum INPUT_SURFACE_FORMAT_YUV 6593 { 6594 INPUT_SURFACE_FORMAT_YUV_UNNAMED0 = 0, //!< Reserved 6595 INPUT_SURFACE_FORMAT_YUV_NV12 = 1, //!< NV12 for chroma 4:2:0 6596 INPUT_SURFACE_FORMAT_YUV_UYVY = 2, //!< UYVY for chroma 4:2:2 6597 INPUT_SURFACE_FORMAT_YUV_YUY2 = 3, //!< YUY2 for chroma 4:2:2 6598 INPUT_SURFACE_FORMAT_YUV_Y8 = 4, //!< Y8 for chroma400 Y-only image 6599 INPUT_SURFACE_FORMAT_YUV_RGB = 5, //!< RGB or YUV for chroma 4:4:4 6600 }; 6601 6602 //! \brief AVERAGE_DOWN_SAMPLING 6603 //! \details 6604 //! This flag is used to select a down-sampling method when 6605 //! VertDownSamplingEnb or HoriDownSamplingEnb is set to 1. 6606 enum AVERAGE_DOWN_SAMPLING 6607 { 6608 AVERAGE_DOWN_SAMPLING_UNNAMED0 = 0, //!< Drop every other line (or column) pixels 6609 AVERAGE_DOWN_SAMPLING_UNNAMED1 = 1, //!< Average neighboring two pixels 6610 }; 6611 6612 //! \brief VERTICAL_DOWN_SAMPLING_ENABLE 6613 //! \details 6614 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 6615 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 6616 //! enable this flag, the input should be interleaved Scan, 6617 //! InputFormatYUV should be set to YUV422H_2Y or YUV422H_4Y, and 6618 //! OutputFormatYUV should be set to NV12. 6619 enum VERTICAL_DOWN_SAMPLING_ENABLE 6620 { 6621 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 6622 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical down-sampling 6623 }; 6624 6625 //! \brief HORIZONTAL_DOWN_SAMPLING_ENABLE 6626 //! \details 6627 //! Only applied to chroma blocks. This flag is used for 2:1 horizontal 6628 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 6629 //! enable this flag, the input should be interleaved Scan, 6630 //! InputFormatYUV should be set to YUV422V_2Y or YUV422V_4Y, and 6631 //! OutputFormatYUV should be set to NV12. 6632 enum HORIZONTAL_DOWN_SAMPLING_ENABLE 6633 { 6634 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 6635 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 horizonatl down-sampling 6636 }; 6637 6638 //! \brief VERTICAL_UP_SAMPLING_ENABLE 6639 //! \details 6640 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 6641 //! up-sampling for chroma 420 and outputting chroma422 YUY2 or UYVY format. 6642 //! To enable this flag, the input should be interleaved Scan, 6643 //! InputFormatYUV should be set to YUV420, and 6644 //! OutputFormatYUV should be set to YUY2 or UYVY. 6645 enum VERTICAL_UP_SAMPLING_ENABLE 6646 { 6647 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no up-sampling 6648 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical up-sampling 6649 }; 6650 6651 //! \brief ROUNDINGQUANT 6652 //! \details 6653 //! Rounding value applied to quantization output 6654 enum ROUNDINGQUANT 6655 { 6656 ROUNDINGQUANT_UNNAMED0 = 0, //!< 1/2 6657 ROUNDINGQUANT_UNNAMED1 = 1, //!< (1/2 - 1/128) 6658 ROUNDINGQUANT_UNNAMED2 = 2, //!< (1/2 + 1/128) 6659 ROUNDINGQUANT_UNNAMED3 = 3, //!< (1/2 - 1/64) 6660 ROUNDINGQUANT_UNNAMED4 = 4, //!< (1/2 + 1/64) 6661 ROUNDINGQUANT_UNNAMED5 = 5, //!< (1/2 - 1/32) 6662 ROUNDINGQUANT_UNNAMED6 = 6, //!< (1/2 - 1/16) 6663 ROUNDINGQUANT_UNNAMED7 = 7, //!< (1/2 - 1/8) 6664 }; 6665 6666 //! \brief OUTPUT_PIXEL_NORMALIZE 6667 //! \details 6668 //! JPEG decoded output pixels for Y and U/V in order to adjust display YUV 6669 //! range. 6670 enum OUTPUT_PIXEL_NORMALIZE 6671 { 6672 OUTPUT_PIXEL_NORMALIZE_UNNAMED0 = 0, //!< No Normalization 6673 OUTPUT_PIXEL_NORMALIZE_UNNAMED1 = 1, //!< Normalize output pixels from [0,255] to [16,239] 6674 }; 6675 6676 //! \name Initializations 6677 6678 //! \brief Explicit member initialization function 6679 MFX_JPEG_PIC_STATE_CMD(); 6680 6681 static const size_t dwSize = 3; 6682 static const size_t byteSize = 12; 6683 }; 6684 6685 //! 6686 //! \brief MFC_JPEG_HUFF_TABLE_STATE 6687 //! \details 6688 //! This Huffman table commands contains both DC and AC tables for either 6689 //! luma or chroma. Once a Huffman table has been defined for a particular 6690 //! destination, it replaces the previous tables stored in that destination 6691 //! and shall be used in the remaining Scans of the current image. Two 6692 //! Huffman tables for luma and chroma will be sent to H/W, and chroma table 6693 //! is used for both U and V. 6694 //! 6695 struct MFC_JPEG_HUFF_TABLE_STATE_CMD 6696 { 6697 union 6698 { 6699 struct 6700 { 6701 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6702 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6703 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6704 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6705 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6706 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6707 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6708 }; 6709 uint32_t Value; 6710 } DW0; 6711 union 6712 { 6713 struct 6714 { 6715 uint32_t HuffTableId : __CODEGEN_BITFIELD(0, 0); //!< HUFF_TABLE_ID 6716 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 6717 }; 6718 uint32_t Value; 6719 } DW1; 6720 uint32_t DcTable[12]; //!< DC_TABLE 6721 uint32_t AcTable[162]; //!< AC_TABLE 6722 6723 //! \name Local enumerations 6724 6725 enum SUBOPCODE_B 6726 { 6727 SUBOPCODE_B_MEDIA = 3, //!< No additional details 6728 }; 6729 6730 enum SUBOPCODE_A 6731 { 6732 SUBOPCODE_A_COMMON = 2, //!< No additional details 6733 }; 6734 6735 enum MEDIA_COMMAND_OPCODE 6736 { 6737 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 6738 }; 6739 6740 enum PIPELINE 6741 { 6742 PIPELINE_MFCJPEGHUFFTABLESTATE = 2, //!< No additional details 6743 }; 6744 6745 enum COMMAND_TYPE 6746 { 6747 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6748 }; 6749 6750 //! \brief HUFF_TABLE_ID 6751 //! \details 6752 //! Huffman table destination identifier will specify one of two 6753 //! destinations at the encoder into which the Huffman table must be stored. 6754 enum HUFF_TABLE_ID 6755 { 6756 HUFF_TABLE_ID_UNNAMED0 = 0, //!< Huffman table 0 6757 HUFF_TABLE_ID_UNNAMED1 = 1, //!< Huffman table 1 6758 }; 6759 6760 //! \name Initializations 6761 6762 //! \brief Explicit member initialization function 6763 MFC_JPEG_HUFF_TABLE_STATE_CMD(); 6764 6765 static const size_t dwSize = 176; 6766 static const size_t byteSize = 704; 6767 }; 6768 6769 //! 6770 //! \brief MFD_JPEG_BSD_OBJECT 6771 //! \details 6772 //! 6773 //! 6774 struct MFD_JPEG_BSD_OBJECT_CMD 6775 { 6776 union 6777 { 6778 struct 6779 { 6780 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6781 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6782 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6783 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6784 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6785 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6786 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6787 }; 6788 uint32_t Value; 6789 } DW0; 6790 union 6791 { 6792 struct 6793 { 6794 uint32_t IndirectDataLength; //!< Indirect Data Length 6795 }; 6796 uint32_t Value; 6797 } DW1; 6798 union 6799 { 6800 struct 6801 { 6802 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Data Start Address 6803 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 6804 }; 6805 uint32_t Value; 6806 } DW2; 6807 union 6808 { 6809 struct 6810 { 6811 uint32_t ScanVerticalPosition : __CODEGEN_BITFIELD(0, 12); //!< Scan Vertical Position 6812 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15); //!< Reserved 6813 uint32_t ScanHorizontalPosition : __CODEGEN_BITFIELD(16, 28); //!< Scan Horizontal Position 6814 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 6815 }; 6816 uint32_t Value; 6817 } DW3; 6818 union 6819 { 6820 struct 6821 { 6822 uint32_t McuCount : __CODEGEN_BITFIELD(0, 25); //!< MCU Count 6823 uint32_t Reserved154 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 6824 uint32_t ScanComponents : __CODEGEN_BITFIELD(27, 29); //!< Scan Components 6825 uint32_t Interleaved : __CODEGEN_BITFIELD(30, 30); //!< INTERLEAVED 6826 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 6827 }; 6828 uint32_t Value; 6829 } DW4; 6830 union 6831 { 6832 struct 6833 { 6834 uint32_t Restartinterval16Bit : __CODEGEN_BITFIELD(0, 15); //!< RestartInterval(16 bit) 6835 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 6836 }; 6837 uint32_t Value; 6838 } DW5; 6839 6840 //! \name Local enumerations 6841 6842 enum SUBOPCODE_B 6843 { 6844 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6845 }; 6846 6847 enum SUBOPCODE_A 6848 { 6849 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6850 }; 6851 6852 enum MEDIA_COMMAND_OPCODE 6853 { 6854 MEDIA_COMMAND_OPCODE_JPEGDEC = 7, //!< No additional details 6855 }; 6856 6857 enum PIPELINE 6858 { 6859 PIPELINE_MFDJPEGBSDOBJECT = 2, //!< No additional details 6860 }; 6861 6862 enum COMMAND_TYPE 6863 { 6864 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6865 }; 6866 6867 enum INTERLEAVED 6868 { 6869 INTERLEAVED_NON_INTERLEAVED = 0, //!< one component in the Scan 6870 INTERLEAVED_INTERLEAVED = 1, //!< multiple components in the Scan 6871 }; 6872 6873 //! \name Initializations 6874 6875 //! \brief Explicit member initialization function 6876 MFD_JPEG_BSD_OBJECT_CMD(); 6877 6878 static const size_t dwSize = 6; 6879 static const size_t byteSize = 24; 6880 }; 6881 6882 //! 6883 //! \brief MFC_JPEG_SCAN_OBJECT 6884 //! \details 6885 //! Encoder Only 6886 //! 6887 struct MFC_JPEG_SCAN_OBJECT_CMD 6888 { 6889 union 6890 { 6891 struct 6892 { 6893 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6894 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6895 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6896 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6897 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6898 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6899 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6900 }; 6901 uint32_t Value; 6902 } DW0; 6903 union 6904 { 6905 struct 6906 { 6907 uint32_t McuCount : __CODEGEN_BITFIELD(0, 25); //!< MCU Count 6908 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 6909 }; 6910 uint32_t Value; 6911 } DW1; 6912 union 6913 { 6914 struct 6915 { 6916 uint32_t RestartInterval : __CODEGEN_BITFIELD(0, 15); //!< Restart Interval 6917 uint32_t IsLastScan : __CODEGEN_BITFIELD(16, 16); //!< IS_LAST_SCAN 6918 uint32_t HeadPresentFlag : __CODEGEN_BITFIELD(17, 17); //!< HEAD_PRESENT_FLAG 6919 uint32_t HuffmanDcTable : __CODEGEN_BITFIELD(18, 20); //!< HUFFMAN_DC_TABLE 6920 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 6921 uint32_t HuffmanAcTable : __CODEGEN_BITFIELD(22, 24); //!< HUFFMAN_AC_TABLE 6922 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 6923 }; 6924 uint32_t Value; 6925 } DW2; 6926 6927 //! \name Local enumerations 6928 6929 enum SUBOPCODE_B 6930 { 6931 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 6932 }; 6933 6934 enum SUBOPCODE_A 6935 { 6936 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 6937 }; 6938 6939 enum MEDIA_COMMAND_OPCODE 6940 { 6941 MEDIA_COMMAND_OPCODE_JPEGENC = 7, //!< No additional details 6942 }; 6943 6944 enum PIPELINE 6945 { 6946 PIPELINE_MFCJPEGSCANOBJECT = 2, //!< No additional details 6947 }; 6948 6949 enum COMMAND_TYPE 6950 { 6951 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6952 }; 6953 6954 //! \brief IS_LAST_SCAN 6955 //! \details 6956 //! If this flag is set, then HW will insert EOI (0xFFD9) to the end of Scan 6957 //! encoded bitstream. 6958 enum IS_LAST_SCAN 6959 { 6960 IS_LAST_SCAN_UNNAMED0 = 0, //!< Not the last Scan. 6961 IS_LAST_SCAN_UNNAMED1 = 1, //!< Indicates that the current Scan is the last one. 6962 }; 6963 6964 //! \brief HEAD_PRESENT_FLAG 6965 //! \details 6966 //! If this flag is set to 0, then no MFC_JPEG_PAK_INSERT_OBJECT commands 6967 //! will be sent. If this flag is set to 1, then one or more 6968 //! MFC_JPEG_PAK_INSERT_OBJECT commands will be sent after 6969 //! MFC_JPEG_SCAN_OBJECT command. 6970 enum HEAD_PRESENT_FLAG 6971 { 6972 HEAD_PRESENT_FLAG_UNNAMED0 = 0, //!< No insertion into the output bitstream buffer before Scan encoded bitstream 6973 HEAD_PRESENT_FLAG_UNNAMED1 = 1, //!< Headers, tables, App data insertion into the output bitstream buffer. HW will insert the insertion data before the Scan encoded bitstream. 6974 }; 6975 6976 //! \brief HUFFMAN_DC_TABLE 6977 //! \details 6978 //! DC Huffman table destination selector specifies one of two possible DC 6979 //! table destinations for each Y, U, V, or R, G, B.The DC Huffman tables 6980 //! shall have been loaded in destination 0 and 1 by the time of issuing 6981 //! MFC_JPEG_HUFF_TABLE_STATE Command. 6982 enum HUFFMAN_DC_TABLE 6983 { 6984 HUFFMAN_DC_TABLE_BIT20_V0 = 0, //!< The third image component must use the DC table 0. 6985 HUFFMAN_DC_TABLE_BIT19_U0 = 0, //!< The second image component must use the DC table 0. 6986 HUFFMAN_DC_TABLE_BIT18_Y0 = 0, //!< The first image component must use the DC table 0. 6987 HUFFMAN_DC_TABLE_BIT18_Y1 = 1, //!< The first image component must use the DC table 1. 6988 HUFFMAN_DC_TABLE_BIT19_U1 = 2, //!< The second image component must use the DC table 1. 6989 HUFFMAN_DC_TABLE_BIT20_V1 = 4, //!< The third image component must use the DC table 1. 6990 }; 6991 6992 //! \brief HUFFMAN_AC_TABLE 6993 //! \details 6994 //! AC Huffman table destination selector specifies one of two possible AC 6995 //! table destinations for each Y, U, V, or R, G, B.The AC Huffman tables 6996 //! must have been loaded in destination 0 and 1 by the time of issuing 6997 //! MFC_JPEG_HUFF_TABLE_STATE Command. 6998 enum HUFFMAN_AC_TABLE 6999 { 7000 HUFFMAN_AC_TABLE_BIT24_V0 = 0, //!< The third image component must use the AC table 0. 7001 HUFFMAN_AC_TABLE_BIT23_U0 = 0, //!< The second image component must use the AC table 0. 7002 HUFFMAN_AC_TABLE_BIT22_Y0 = 0, //!< The first image component must use the AC table 0. 7003 HUFFMAN_AC_TABLE_BIT22_Y1 = 1, //!< The first image component must use the AC table 1. 7004 HUFFMAN_AC_TABLE_BIT23_U1 = 2, //!< The second image component must use the AC table 1. 7005 HUFFMAN_AC_TABLE_BIT24_V1 = 4, //!< The third image component must use the AC table 1. 7006 }; 7007 7008 //! \name Initializations 7009 7010 //! \brief Explicit member initialization function 7011 MFC_JPEG_SCAN_OBJECT_CMD(); 7012 7013 static const size_t dwSize = 3; 7014 static const size_t byteSize = 12; 7015 }; 7016 7017 //! 7018 //! \brief MFX_VP8_Encoder_CFG 7019 //! \details 7020 //! This must be the very first command to issue after the surface state, 7021 //! the pipe select and base address setting commands and must be issued 7022 //! before MFX_VP8_PIC_STATE. 7023 //! 7024 struct MFX_VP8_Encoder_CFG_CMD 7025 { 7026 union 7027 { 7028 struct 7029 { 7030 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7031 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7032 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUB_OPCODE_B 7033 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODE_A 7034 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7035 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7036 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7037 }; 7038 uint32_t Value; 7039 } DW0; 7040 union 7041 { 7042 struct 7043 { 7044 uint32_t PerformanceCounterEnable : __CODEGEN_BITFIELD(0, 0); //!< Performance Counter Enable 7045 uint32_t FinalBitstreamOutputDisable : __CODEGEN_BITFIELD(1, 1); //!< Final Bitstream Output Disable 7046 uint32_t TokenStatisticsOutputEnable : __CODEGEN_BITFIELD(2, 2); //!< Token Statistics Output Enable 7047 uint32_t BitstreamStatisticsOutputEnable : __CODEGEN_BITFIELD(3, 3); //!< Bitstream Statistics Output Enable 7048 uint32_t UpdateSegmentFeatureDataFlag : __CODEGEN_BITFIELD(4, 4); //!< Update Segment Feature Data Flag 7049 uint32_t SkipFinalBitstreamWhenOverUnderFlow : __CODEGEN_BITFIELD(5, 5); //!< Skip Final Bitstream when Over / Under flow 7050 uint32_t RateControlInitialPass : __CODEGEN_BITFIELD(6, 6); //!< RATE_CONTROL_INITIAL_PASS 7051 uint32_t PerSegmentDeltaQindexLoopfilterDisable : __CODEGEN_BITFIELD(7, 7); //!< Per Segment Delta Qindex / LoopFilter Disable 7052 uint32_t FinerBrcEnable : __CODEGEN_BITFIELD(8, 8); //!< Finer BRC Enable 7053 uint32_t CompressedBitstreamOutputDisable : __CODEGEN_BITFIELD(9, 9); //!< Compressed Bitstream Output Disable 7054 uint32_t VbspunitpowerclockGatingDisable : __CODEGEN_BITFIELD(10, 10); //!< VBSPunitPowerClock Gating Disable 7055 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 7056 }; 7057 uint32_t Value; 7058 } DW1; 7059 union 7060 { 7061 struct 7062 { 7063 uint32_t MaxFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD(0, 0); //!< MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7064 uint32_t MinFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD(1, 1); //!< MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7065 uint32_t MaxInterMbBitCountCheckEnableMask : __CODEGEN_BITFIELD(2, 2); //!< Max Inter MB Bit Count Check Enable Mask 7066 uint32_t MaxIntraMbBitCountCheckEnableMask : __CODEGEN_BITFIELD(3, 3); //!< Max Intra MB Bit Count Check Enable Mask 7067 uint32_t IntermediateBitBufferOverrunEnableMask : __CODEGEN_BITFIELD(4, 4); //!< Intermediate Bit Buffer Overrun Enable Mask 7068 uint32_t FinalBistreamBufferOverrunEnableMask : __CODEGEN_BITFIELD(5, 5); //!< Final Bistream Buffer Overrun Enable Mask 7069 uint32_t QindexClampHighMaskForUnderflow : __CODEGEN_BITFIELD(6, 6); //!< Qindex_Clamp_High_mask for underflow 7070 uint32_t QindexClampHighMaskForOverflow : __CODEGEN_BITFIELD(7, 7); //!< Qindex_Clamp_High_mask for overflow 7071 uint32_t Reserved72 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 7072 }; 7073 uint32_t Value; 7074 } DW2; 7075 union 7076 { 7077 struct 7078 { 7079 uint32_t MaxInterMbBitCount : __CODEGEN_BITFIELD(0, 11); //!< Max Inter MB bit count 7080 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7081 uint32_t MaxIntraMbBitCountLimit : __CODEGEN_BITFIELD(16, 27); //!< Max Intra MB Bit Count Limit 7082 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 7083 }; 7084 uint32_t Value; 7085 } DW3; 7086 union 7087 { 7088 struct 7089 { 7090 uint32_t FrameBitRateMax : __CODEGEN_BITFIELD(0, 13); //!< Frame Bit Rate Max 7091 uint32_t FrameBitRateMaxUnit : __CODEGEN_BITFIELD(14, 14); //!< FRAME_BIT_RATE_MAX_UNIT 7092 uint32_t FrameBitrateMaxUnitMode : __CODEGEN_BITFIELD(15, 15); //!< FRAME_BITRATE_MAX_UNIT_MODE 7093 uint32_t FrameBitRateMin : __CODEGEN_BITFIELD(16, 29); //!< Frame Bit Rate Min 7094 uint32_t FrameBitRateMinUnit : __CODEGEN_BITFIELD(30, 30); //!< FRAME_BIT_RATE_MIN_UNIT 7095 uint32_t FrameBitrateMinUnitMode : __CODEGEN_BITFIELD(31, 31); //!< FRAME_BITRATE_MIN_UNIT_MODE 7096 }; 7097 uint32_t Value; 7098 } DW4; 7099 union 7100 { 7101 struct 7102 { 7103 uint32_t FrameDeltaQindexMax0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta QIndex Max [0] 7104 uint32_t FrameDeltaQindexMax1 : __CODEGEN_BITFIELD(8, 15); //!< Frame Delta QIndex Max[1] 7105 uint32_t FrameDeltaqIndexMax2 : __CODEGEN_BITFIELD(16, 23); //!< Frame DeltaQ Index Max[2] 7106 uint32_t FrameDeltaQindexMax3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta QIndex Max[3] 7107 }; 7108 uint32_t Value; 7109 } DW5; 7110 union 7111 { 7112 struct 7113 { 7114 uint32_t FrameDeltaQindexMin0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta QIndex Min[0] 7115 uint32_t FrameDeltaQindexMin1 : __CODEGEN_BITFIELD(8, 15); //!< Frame Delta QIndex Min[1] 7116 uint32_t FrameDeltaQindexMin2 : __CODEGEN_BITFIELD(16, 23); //!< Frame Delta QIndex Min[2] 7117 uint32_t FrameDeltaQindexMin3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta QIndex Min[3] 7118 }; 7119 uint32_t Value; 7120 } DW6; 7121 union 7122 { 7123 struct 7124 { 7125 uint32_t PerSegmentFrameDeltaQindexMax1; //!< Per Segment Frame Delta QIndex Max[1] 7126 }; 7127 uint32_t Value; 7128 } DW7; 7129 union 7130 { 7131 struct 7132 { 7133 uint32_t PerSegmentFrameDeltaQindexMin1; //!< Per Segment Frame Delta QIndex Min[1] 7134 }; 7135 uint32_t Value; 7136 } DW8; 7137 union 7138 { 7139 struct 7140 { 7141 uint32_t PerSegmentFrameDeltaQindexMax2; //!< Per Segment Frame Delta QIndex Max[2] 7142 }; 7143 uint32_t Value; 7144 } DW9; 7145 union 7146 { 7147 struct 7148 { 7149 uint32_t PerSegmentFrameDeltaQindexMin2; //!< Per Segment Frame Delta QIndex Min[2] 7150 }; 7151 uint32_t Value; 7152 } DW10; 7153 union 7154 { 7155 struct 7156 { 7157 uint32_t PerSegmentFrameDeltaQindexMax3; //!< Per Segment Frame Delta QIndex Max[3] 7158 }; 7159 uint32_t Value; 7160 } DW11; 7161 union 7162 { 7163 struct 7164 { 7165 uint32_t PerSegmentFrameDeltaQindexMin3; //!< Per Segment Frame Delta QIndex Min[3] 7166 }; 7167 uint32_t Value; 7168 } DW12; 7169 union 7170 { 7171 struct 7172 { 7173 uint32_t FrameDeltaLoopFilterMax0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta Loop Filter Max[0] 7174 uint32_t FramEdeltaLoopFilterMax1 : __CODEGEN_BITFIELD(8, 15); //!< Fram eDelta Loop Filter Max[1] 7175 uint32_t FrameDeltaLoopFilterMax2 : __CODEGEN_BITFIELD(16, 23); //!< Frame Delta Loop Filter Max[2] 7176 uint32_t FrameDeltaLoopFilterMax3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta Loop Filter Max[3] 7177 }; 7178 uint32_t Value; 7179 } DW13; 7180 union 7181 { 7182 struct 7183 { 7184 uint32_t FrameDeltaLoopFilterMin0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta Loop Filter Min[0] 7185 uint32_t FrameDeltaLoopFilterMin1 : __CODEGEN_BITFIELD(8, 15); //!< Frame Delta Loop Filter Min[1] 7186 uint32_t FrameDeltaLoopFilterMin2 : __CODEGEN_BITFIELD(16, 23); //!< Frame Delta Loop Filter Min[2] 7187 uint32_t FrameDeltaLoopFilterMin3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta Loop Filter Min[3] 7188 }; 7189 uint32_t Value; 7190 } DW14; 7191 union 7192 { 7193 struct 7194 { 7195 uint32_t PerSegmentFrameDeltaLoopfilterMax1; //!< Per Segment Frame Delta LoopFilter Max[1] 7196 }; 7197 uint32_t Value; 7198 } DW15; 7199 union 7200 { 7201 struct 7202 { 7203 uint32_t PerSegmentFrameDeltaLoopfilterMin1; //!< Per Segment Frame Delta LoopFilter Min[1] 7204 }; 7205 uint32_t Value; 7206 } DW16; 7207 union 7208 { 7209 struct 7210 { 7211 uint32_t PerSegmentFrameDeltaLoopfilterMax2; //!< Per Segment Frame Delta LoopFilter Max[2] 7212 }; 7213 uint32_t Value; 7214 } DW17; 7215 union 7216 { 7217 struct 7218 { 7219 uint32_t PerSegmentFrameDeltaLoopfilterMin2; //!< Per Segment Frame Delta LoopFilter Min[2] 7220 }; 7221 uint32_t Value; 7222 } DW18; 7223 union 7224 { 7225 struct 7226 { 7227 uint32_t PerSegmentFrameDeltaLoopfilterMax3; //!< Per Segment Frame Delta LoopFilter Max[3] 7228 }; 7229 uint32_t Value; 7230 } DW19; 7231 union 7232 { 7233 struct 7234 { 7235 uint32_t PerSegmentFrameDeltaLoopfilterMin3; //!< Per Segment Frame Delta LoopFilter Min[3] 7236 }; 7237 uint32_t Value; 7238 } DW20; 7239 union 7240 { 7241 struct 7242 { 7243 uint32_t FrameBitRateMaxDelta : __CODEGEN_BITFIELD(0, 14); //!< Frame Bit Rate Max Delta 7244 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 7245 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(16, 30); //!< FrameBitRateMinDelta 7246 uint32_t Reserved703 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 7247 }; 7248 uint32_t Value; 7249 } DW21; 7250 union 7251 { 7252 struct 7253 { 7254 uint32_t MinFrameWsize : __CODEGEN_BITFIELD(0, 15); //!< Min Frame WSize 7255 uint32_t MinFrameWsizeUnit : __CODEGEN_BITFIELD(16, 17); //!< MIN_FRAME_WSIZE_UNIT 7256 uint32_t Reserved722 : __CODEGEN_BITFIELD(18, 19); //!< Reserved 7257 uint32_t BitstreamFormatVersion : __CODEGEN_BITFIELD(20, 22); //!< Bitstream Format Version 7258 uint32_t ShowFrame : __CODEGEN_BITFIELD(23, 23); //!< Show Frame 7259 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7260 }; 7261 uint32_t Value; 7262 } DW22; 7263 union 7264 { 7265 struct 7266 { 7267 uint32_t HorizontalSizeCode : __CODEGEN_BITFIELD(0, 15); //!< Horizontal_Size_Code 7268 uint32_t VerticalSizeCode : __CODEGEN_BITFIELD(16, 31); //!< Vertical_Size_Code 7269 }; 7270 uint32_t Value; 7271 } DW23; 7272 union 7273 { 7274 struct 7275 { 7276 uint32_t FrameHeaderBitCount; //!< Frame Header Bit Count 7277 }; 7278 uint32_t Value; 7279 } DW24; 7280 union 7281 { 7282 struct 7283 { 7284 uint32_t FrameHeaderBinBufferQindexUpdatePointer; //!< Frame Header Bin Buffer Qindex Update Pointer 7285 }; 7286 uint32_t Value; 7287 } DW25; 7288 union 7289 { 7290 struct 7291 { 7292 uint32_t FrameHeaderBinBufferLoopfilterUpdatePointer; //!< Frame Header Bin Buffer LoopFilter Update Pointer 7293 }; 7294 uint32_t Value; 7295 } DW26; 7296 union 7297 { 7298 struct 7299 { 7300 uint32_t FrameHeaderBinBufferTokenUpdatePointer; //!< Frame Header Bin Buffer Token Update Pointer 7301 }; 7302 uint32_t Value; 7303 } DW27; 7304 union 7305 { 7306 struct 7307 { 7308 uint32_t FrameHeaderBinBufferMvupdatePointer; //!< Frame Header Bin Buffer MVUpdate Pointer 7309 }; 7310 uint32_t Value; 7311 } DW28; 7312 union 7313 { 7314 struct 7315 { 7316 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD(0, 3); //!< CV0 - Clamp Value 0 7317 uint32_t Cv1 : __CODEGEN_BITFIELD(4, 7); //!< CV1 7318 uint32_t Cv2 : __CODEGEN_BITFIELD(8, 11); //!< CV2 7319 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15); //!< CV3 7320 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19); //!< CV4 7321 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23); //!< CV5 7322 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27); //!< CV6 7323 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31); //!< ClampValues - CV7 7324 }; 7325 uint32_t Value; 7326 } DW29; 7327 7328 //! \name Local enumerations 7329 7330 enum SUB_OPCODE_B 7331 { 7332 SUB_OPCODE_B_MFXVP8ENCODERCFG = 1, //!< No additional details 7333 }; 7334 7335 enum SUB_OPCODE_A 7336 { 7337 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7338 }; 7339 7340 enum MEDIA_COMMAND_OPCODE 7341 { 7342 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7343 }; 7344 7345 enum PIPELINE 7346 { 7347 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7348 }; 7349 7350 enum COMMAND_TYPE 7351 { 7352 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7353 }; 7354 7355 enum RATE_CONTROL_INITIAL_PASS 7356 { 7357 RATE_CONTROL_INITIAL_PASS_SUBSEQUENCEPASS_ES = 0, //!< No additional details 7358 RATE_CONTROL_INITIAL_PASS_INITIALPASS = 1, //!< No additional details 7359 }; 7360 7361 //! \brief MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7362 //! \details 7363 //! Enable Max. Frame Rate Control.This is a mask bit controlling if the 7364 //! condition of frame level bit count is greater than or equal to 7365 //! FrameBitRateMax. 7366 enum MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7367 { 7368 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS control register. 7369 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) >= (Frame Bit Rate Maximum Limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS control register. 7370 }; 7371 7372 //! \brief MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7373 //! \details 7374 //! Enable Min. Frame Rate Control. This is a mask bit controlling if the 7375 //! condition of frame level bit count is less than or equal to 7376 //! FrameBitRateMin. 7377 enum MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7378 { 7379 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS Control Register. 7380 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) =< (Frame Bit Rate Minimum limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS Control Register. 7381 }; 7382 7383 //! \brief FRAME_BIT_RATE_MAX_UNIT 7384 //! \details 7385 //! This field is Frame Bitrate Maximum Mode 7386 enum FRAME_BIT_RATE_MAX_UNIT 7387 { 7388 FRAME_BIT_RATE_MAX_UNIT_32_B = 0, //!< No additional details 7389 FRAME_BIT_RATE_MAX_UNIT_4_KB = 1, //!< No additional details 7390 }; 7391 7392 //! \brief FRAME_BITRATE_MAX_UNIT_MODE 7393 //! \details 7394 //! This field is the Frame Bitrate Maximum Limit Units. 7395 enum FRAME_BITRATE_MAX_UNIT_MODE 7396 { 7397 FRAME_BITRATE_MAX_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Max Unit is in old mode (128b/16Kb) 7398 FRAME_BITRATE_MAX_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Max Unit is in new mode (32byte/4Kb) 7399 }; 7400 7401 //! \brief FRAME_BIT_RATE_MIN_UNIT 7402 //! \details 7403 //! This field is Frame Bitrate Minimum Mode. 7404 enum FRAME_BIT_RATE_MIN_UNIT 7405 { 7406 FRAME_BIT_RATE_MIN_UNIT_32_B = 0, //!< No additional details 7407 FRAME_BIT_RATE_MIN_UNIT_4_KB = 1, //!< No additional details 7408 }; 7409 7410 //! \brief FRAME_BITRATE_MIN_UNIT_MODE 7411 //! \details 7412 //! This field is the Frame Bitrate Minimum Limit Units. 7413 enum FRAME_BITRATE_MIN_UNIT_MODE 7414 { 7415 FRAME_BITRATE_MIN_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Min Unit is in old mode (128b/16Kb) 7416 FRAME_BITRATE_MIN_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Min Unit is in new mode (32byte/4Kb) 7417 }; 7418 7419 enum MIN_FRAME_WSIZE_UNIT 7420 { 7421 MIN_FRAME_WSIZE_UNIT_COMPATIBILITYMODE = 0, //!< MinFrameWSizeUnit is in old mode (128b/16Kb) 7422 MIN_FRAME_WSIZE_UNIT_NEWMODE = 1, //!< MinFrameWSizeUnit is in new mode (32byte/4Kb) 7423 }; 7424 7425 //! \name Initializations 7426 7427 //! \brief Explicit member initialization function 7428 MFX_VP8_Encoder_CFG_CMD(); 7429 7430 static const size_t dwSize = 30; 7431 static const size_t byteSize = 120; 7432 }; 7433 7434 //! 7435 //! \brief MFX_VP8_BSP_BUF_BASE_ADDR_STATE 7436 //! \details 7437 //! 7438 //! 7439 struct MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD 7440 { 7441 union 7442 { 7443 struct 7444 { 7445 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7446 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7447 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUB_OPCODE_B 7448 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODE_A 7449 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7450 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7451 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7452 }; 7453 uint32_t Value; 7454 } DW0; 7455 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameHeaderBaseAddress; //!< DW1..2, Frame Header - Base Address 7456 MEMORYADDRESSATTRIBUTES_CMD FrameHeaderAttributes; //!< DW3, Frame Header - Attributes 7457 SPLITBASEADDRESS64BYTEALIGNED_CMD IntermediateBufferBaseAddress; //!< DW4..5, Intermediate Buffer - Base Address 7458 MEMORYADDRESSATTRIBUTES_CMD IntermediateBufferAttributes; //!< DW6, Intermediate Buffer - Attributes 7459 uint32_t IntermediateBufferPartitionOffset[8]; //!< Intermediate Buffer Partition Offset 7460 union 7461 { 7462 struct 7463 { 7464 uint32_t IntermediateBufferMaxSize; //!< Intermediate Buffer Max Size 7465 }; 7466 uint32_t Value; 7467 } DW15; 7468 SPLITBASEADDRESS64BYTEALIGNED_CMD FinalFrameBaseAddress; //!< DW16..17, Final Frame - Base Address 7469 MEMORYADDRESSATTRIBUTES_CMD FinalFrameAttributes; //!< DW18, Final Frame - Attributes 7470 union 7471 { 7472 struct 7473 { 7474 uint32_t FinalFrameByteOffset : __CODEGEN_BITFIELD(0, 5); //!< Final Frame Byte Offset 7475 uint32_t Reserved614 : __CODEGEN_BITFIELD(6, 31); //!< Reserved 7476 }; 7477 uint32_t Value; 7478 } DW19; 7479 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutBaseAddress; //!< DW20..21, Streamout - Base Address 7480 MEMORYADDRESSATTRIBUTES_CMD StreamoutAttributes; //!< DW22, Streamout - Attributes 7481 SPLITBASEADDRESS64BYTEALIGNED_CMD CoeffProbsStreaminSurfaceBaseAddress; //!< DW23..24, Coeff Probs StreamIn Surface - Base Address 7482 MEMORYADDRESSATTRIBUTES_CMD CoeffProbsStreaminSurfaceAttributes; //!< DW25, Coeff Probs StreamIn Surface - Attributes 7483 SPLITBASEADDRESS64BYTEALIGNED_CMD TokenStatisticsSurfaceBaseAddress; //!< DW26..27, Token Statistics Surface - Base Address 7484 MEMORYADDRESSATTRIBUTES_CMD TokenStatisticsSurfaceAttributes; //!< DW28, Token Statistics Surface - Attributes 7485 SPLITBASEADDRESS64BYTEALIGNED_CMD MpcRowstoreSurfaceBaseAddress; //!< DW29..30, MPC RowStore Surface - Base Address 7486 MEMORYADDRESSATTRIBUTES_CMD MpcRowstoreSurfaceAttributes; //!< DW31, MPC RowStore Surface - Attributes 7487 7488 //! \name Local enumerations 7489 7490 enum SUB_OPCODE_B 7491 { 7492 SUB_OPCODE_B_MFXVP8BSPBUFBASEADDRSTATE = 3, //!< No additional details 7493 }; 7494 7495 enum SUB_OPCODE_A 7496 { 7497 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7498 }; 7499 7500 enum MEDIA_COMMAND_OPCODE 7501 { 7502 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7503 }; 7504 7505 enum PIPELINE 7506 { 7507 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7508 }; 7509 7510 enum COMMAND_TYPE 7511 { 7512 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7513 }; 7514 7515 //! \name Initializations 7516 7517 //! \brief Explicit member initialization function 7518 MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD(); 7519 7520 static const size_t dwSize = 32; 7521 static const size_t byteSize = 128; 7522 }; 7523 7524 //! 7525 //! \brief MFD_VP8_BSD_OBJECT 7526 //! \details 7527 //! The MFD_VP8_BSD_OBJECT command is the only primitive command for the VP8 7528 //! Decoding Pipeline. The Partitions of the bitstream is loaded as indirect 7529 //! data object. Before issuing a MFD_VP8_BSD_OBJECT command, all VP8 frame 7530 //! level states of the MFD Engine need to be valid. Therefore the commands 7531 //! used to set these states need to have been issued prior to the issue of 7532 //! a MFD_VP8_BSD_OBJECT command.Context switch interrupt is not supported 7533 //! by this command. 7534 //! 7535 struct MFD_VP8_BSD_OBJECT_CMD 7536 { 7537 union 7538 { 7539 struct 7540 { 7541 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7542 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7543 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 7544 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 7545 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7546 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7547 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7548 }; 7549 uint32_t Value; 7550 } DW0; 7551 union 7552 { 7553 struct 7554 { 7555 uint32_t Partition0FirstmbbitoffsetFromFrameHeader : __CODEGEN_BITFIELD(0, 2); //!< Partition0 FirstMBBitOffset from Frame Header 7556 uint32_t Reserved35 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 7557 uint32_t CodedNumOfCoeffTokenPartitions : __CODEGEN_BITFIELD(4, 5); //!< Coded Num of Coeff Token Partitions 7558 uint32_t Reserved38 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 7559 uint32_t Partition0CpbacEntropyRange : __CODEGEN_BITFIELD(8, 15); //!< Partition0 CPBAC Entropy Range 7560 uint32_t Partition0CpbacEntropyCount : __CODEGEN_BITFIELD(16, 20); //!< Partition0 CPBAC Entropy Count 7561 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 7562 }; 7563 uint32_t Value; 7564 } DW1; 7565 union 7566 { 7567 struct 7568 { 7569 uint32_t Reserved64 : __CODEGEN_BITFIELD(0, 23); //!< Reserved 7570 uint32_t Partition0CpbacEntropyValue : __CODEGEN_BITFIELD(24, 31); //!< Partition0 CPBAC Entropy Value 7571 }; 7572 uint32_t Value; 7573 } DW2; 7574 union 7575 { 7576 struct 7577 { 7578 uint32_t IndirectPartition0DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition0 Data Length 7579 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7580 }; 7581 uint32_t Value; 7582 } DW3; 7583 union 7584 { 7585 struct 7586 { 7587 uint32_t IndirectPartition0DataStartOffset; //!< Indirect Partition0 Data Start Offset 7588 }; 7589 uint32_t Value; 7590 } DW4; 7591 union 7592 { 7593 struct 7594 { 7595 uint32_t IndirectPartition1DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition1 Data Length 7596 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7597 }; 7598 uint32_t Value; 7599 } DW5; 7600 union 7601 { 7602 struct 7603 { 7604 uint32_t IndirectPartition1DataStartOffset; //!< Indirect Partition1 Data Start Offset 7605 }; 7606 uint32_t Value; 7607 } DW6; 7608 union 7609 { 7610 struct 7611 { 7612 uint32_t IndirectPartition2DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition2 Data Length 7613 uint32_t Reserved248 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7614 }; 7615 uint32_t Value; 7616 } DW7; 7617 union 7618 { 7619 struct 7620 { 7621 uint32_t IndirectPartition2DataStartOffset; //!< Indirect Partition2 Data Start Offset 7622 }; 7623 uint32_t Value; 7624 } DW8; 7625 union 7626 { 7627 struct 7628 { 7629 uint32_t IndirectPartition3DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition3 Data Length 7630 uint32_t Reserved312 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7631 }; 7632 uint32_t Value; 7633 } DW9; 7634 union 7635 { 7636 struct 7637 { 7638 uint32_t IndirectPartition3DataStartOffset; //!< Indirect Partition3 Data Start Offset 7639 }; 7640 uint32_t Value; 7641 } DW10; 7642 union 7643 { 7644 struct 7645 { 7646 uint32_t IndirectPartition4DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition4 Data Length 7647 uint32_t Reserved376 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7648 }; 7649 uint32_t Value; 7650 } DW11; 7651 union 7652 { 7653 struct 7654 { 7655 uint32_t IndirectPartition4DataStartOffset; //!< Indirect Partition4 Data Start Offset 7656 }; 7657 uint32_t Value; 7658 } DW12; 7659 union 7660 { 7661 struct 7662 { 7663 uint32_t IndirectPartition5DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition5 Data Length 7664 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7665 }; 7666 uint32_t Value; 7667 } DW13; 7668 union 7669 { 7670 struct 7671 { 7672 uint32_t IndirectPartition5DataStartOffset; //!< Indirect Partition5 Data Start Offset 7673 }; 7674 uint32_t Value; 7675 } DW14; 7676 union 7677 { 7678 struct 7679 { 7680 uint32_t IndirectPartition6DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition6 Data Length 7681 uint32_t Reserved504 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7682 }; 7683 uint32_t Value; 7684 } DW15; 7685 union 7686 { 7687 struct 7688 { 7689 uint32_t IndirectPartition6DataStartOffset; //!< Indirect Partition6 Data Start Offset 7690 }; 7691 uint32_t Value; 7692 } DW16; 7693 union 7694 { 7695 struct 7696 { 7697 uint32_t IndirectPartition7DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition7 Data Length 7698 uint32_t Reserved568 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7699 }; 7700 uint32_t Value; 7701 } DW17; 7702 union 7703 { 7704 struct 7705 { 7706 uint32_t IndirectPartition7DataStartOffset; //!< Indirect Partition7 Data Start Offset 7707 }; 7708 uint32_t Value; 7709 } DW18; 7710 union 7711 { 7712 struct 7713 { 7714 uint32_t IndirectPartition8DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition8 Data Length 7715 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7716 }; 7717 uint32_t Value; 7718 } DW19; 7719 union 7720 { 7721 struct 7722 { 7723 uint32_t IndirectPartition8DataStartOffset; //!< Indirect Partition8 Data Start Offset 7724 }; 7725 uint32_t Value; 7726 } DW20; 7727 union 7728 { 7729 struct 7730 { 7731 uint32_t Reserved672 : __CODEGEN_BITFIELD(0, 7); //!< Reserved 7732 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD(8, 8); //!< MB_HEADER_ERROR_HANDLING 7733 uint32_t Reserved681 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 7734 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10); //!< ENTROPY_ERROR_HANDLING 7735 uint32_t Reserved683 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 7736 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12); //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 7737 uint32_t Reserved685 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 7738 uint32_t BsdprematurecompleteErrorHandling : __CODEGEN_BITFIELD(14, 14); //!< BSDPREMATURECOMPLETE_ERROR_HANDLING 7739 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 7740 uint32_t ConcealPicIdConcealmentPictureId : __CODEGEN_BITFIELD(16, 17); //!< Conceal_Pic_Id (Concealment Picture ID) 7741 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 30); //!< Reserved 7742 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31); //!< CONCEALMENT_METHOD 7743 }; 7744 uint32_t Value; 7745 } DW21; 7746 7747 //! \name Local enumerations 7748 7749 enum SUBOPCODEB 7750 { 7751 SUBOPCODEB_UNNAMED8 = 8, //!< No additional details 7752 }; 7753 7754 enum SUBOPCODEA 7755 { 7756 SUBOPCODEA_UNNAMED1 = 1, //!< No additional details 7757 }; 7758 7759 enum MEDIA_COMMAND_OPCODE 7760 { 7761 MEDIA_COMMAND_OPCODE_VP8DEC = 4, //!< No additional details 7762 }; 7763 7764 enum PIPELINE 7765 { 7766 PIPELINE_MFDVP8BSDOBJECT = 2, //!< No additional details 7767 }; 7768 7769 enum COMMAND_TYPE 7770 { 7771 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7772 }; 7773 7774 enum MB_HEADER_ERROR_HANDLING 7775 { 7776 MB_HEADER_ERROR_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7777 MB_HEADER_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7778 }; 7779 7780 enum ENTROPY_ERROR_HANDLING 7781 { 7782 ENTROPY_ERROR_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7783 ENTROPY_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7784 }; 7785 7786 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 7787 { 7788 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7789 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7790 }; 7791 7792 //! \brief BSDPREMATURECOMPLETE_ERROR_HANDLING 7793 //! \details 7794 //! It occurs in situation where the decode is completed but there are still 7795 //! data in the bitstream. 7796 enum BSDPREMATURECOMPLETE_ERROR_HANDLING 7797 { 7798 BSDPREMATURECOMPLETE_ERROR_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7799 BSDPREMATURECOMPLETE_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7800 }; 7801 7802 //! \brief CONCEALMENT_METHOD 7803 //! \details 7804 //! This field specifies the method used for concealment when error is 7805 //! detected. 7806 enum CONCEALMENT_METHOD 7807 { 7808 CONCEALMENT_METHOD_INTRA16X16PREDICTION = 0, //!< A copy from the current picture is performed using Intra 16x16 Prediction method. 7809 CONCEALMENT_METHOD_INTERPCOPY = 1, //!< A copy from collocated macroblock location is performed from the concealment reference indicated by the ConCeal_Pic_Id field. 7810 }; 7811 7812 //! \name Initializations 7813 7814 //! \brief Explicit member initialization function 7815 MFD_VP8_BSD_OBJECT_CMD(); 7816 7817 static const size_t dwSize = 22; 7818 static const size_t byteSize = 88; 7819 }; 7820 7821 //! 7822 //! \brief MFX_VP8_PIC_STATE 7823 //! \details 7824 //! This must be the very first command to issue after the surface state, 7825 //! the pipe select and base address setting commands and must be issued 7826 //! before MFX_VP8_IMG_STATE. 7827 //! 7828 struct MFX_VP8_PIC_STATE_CMD 7829 { 7830 union 7831 { 7832 struct 7833 { 7834 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7835 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7836 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUB_OPCODE_B 7837 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODE_A 7838 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7839 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7840 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7841 }; 7842 uint32_t Value; 7843 } DW0; 7844 union 7845 { 7846 struct 7847 { 7848 uint32_t FrameWidthMinus1 : __CODEGEN_BITFIELD(0, 7); //!< Frame Width Minus 1 7849 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 7850 uint32_t FrameHeightMinus1 : __CODEGEN_BITFIELD(16, 23); //!< Frame Height Minus 1 7851 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7852 }; 7853 uint32_t Value; 7854 } DW1; 7855 union 7856 { 7857 struct 7858 { 7859 uint32_t McFilterSelect : __CODEGEN_BITFIELD(0, 0); //!< MC_FILTER_SELECT 7860 uint32_t ChromaFullPixelMcFilterMode : __CODEGEN_BITFIELD(1, 1); //!< CHROMA_FULL_PIXEL_MC_FILTER_MODE 7861 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 7862 uint32_t Dblkfiltertype : __CODEGEN_BITFIELD(4, 4); //!< DBLKFILTERTYPE 7863 uint32_t Skeyframeflag : __CODEGEN_BITFIELD(5, 5); //!< SKEYFRAMEFLAG 7864 uint32_t SegmentationIdStreamoutEnable : __CODEGEN_BITFIELD(6, 6); //!< SEGMENTATION_ID_STREAMOUT_ENABLE 7865 uint32_t SegmentationIdStreaminEnable : __CODEGEN_BITFIELD(7, 7); //!< SEGMENTATION_ID_STREAMIN_ENABLE 7866 uint32_t SegmentEnableFlag : __CODEGEN_BITFIELD(8, 8); //!< SEGMENT_ENABLE_FLAG 7867 uint32_t UpdateMbsegmentMapFlag : __CODEGEN_BITFIELD(9, 9); //!< UPDATE_MBSEGMENT_MAP_FLAG 7868 uint32_t MbNocoeffSkipflag : __CODEGEN_BITFIELD(10, 10); //!< MB_NOCOEFF_SKIPFLAG 7869 uint32_t ModeReferenceLoopFilterDeltaEnabled : __CODEGEN_BITFIELD(11, 11); //!< MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 7870 uint32_t GoldenRefPictureMvSignbiasFlag : __CODEGEN_BITFIELD(12, 12); //!< Golden Ref Picture MV SignBias Flag 7871 uint32_t AlternateRefPicMvSignbiasFlag : __CODEGEN_BITFIELD(13, 13); //!< Alternate Ref Pic MV SignBias Flag 7872 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 7873 uint32_t DeblockSharpnessLevel : __CODEGEN_BITFIELD(16, 18); //!< Deblock Sharpness Level 7874 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 23); //!< Reserved 7875 uint32_t Log2NumOfPartition : __CODEGEN_BITFIELD(24, 25); //!< LOG2_NUM_OF_PARTITION 7876 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 7877 }; 7878 uint32_t Value; 7879 } DW2; 7880 union 7881 { 7882 struct 7883 { 7884 uint32_t DblkfilterlevelForSegment0 : __CODEGEN_BITFIELD(0, 5); //!< DBLKFILTERLEVEL_FOR_SEGMENT0 7885 uint32_t Reserved102 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 7886 uint32_t DblkfilterlevelForSegment1 : __CODEGEN_BITFIELD(8, 13); //!< DBLKFILTERLEVEL_FOR_SEGMENT1 7887 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 7888 uint32_t DblkfilterlevelForSegment2 : __CODEGEN_BITFIELD(16, 21); //!< DBLKFILTERLEVEL_FOR_SEGMENT2 7889 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 7890 uint32_t DblkfilterlevelForSegment3 : __CODEGEN_BITFIELD(24, 29); //!< DBLKFILTERLEVEL_FOR_SEGMENT3 7891 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 7892 }; 7893 uint32_t Value; 7894 } DW3; 7895 union 7896 { 7897 struct 7898 { 7899 uint32_t QuantizerValue0Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [0][BlockType0=Y1DC], Decoder Only 7900 uint32_t Reserved137 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7901 uint32_t QuantizerValue0Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [0][BlockType1=Y1AC], Decoder Only 7902 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7903 } dec; 7904 struct 7905 { 7906 uint32_t Seg0Qindex : __CODEGEN_BITFIELD(0, 6); //!< Seg 0 Qindex, Encoder Only 7907 uint32_t Reserved135 : __CODEGEN_BITFIELD(7, 7); //!< Reserved, Encoder Only 7908 uint32_t Seg1Qindex : __CODEGEN_BITFIELD(8, 14); //!< Seg 1 Qindex, Encoder Only 7909 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved, Encoder Only 7910 uint32_t Seg2Qindex : __CODEGEN_BITFIELD(16, 22); //!< Seg 2 Qindex, Encoder Only 7911 uint32_t Reserved151 : __CODEGEN_BITFIELD(23, 23); //!< Reserved, Encoder Only 7912 uint32_t Seg3Qindex : __CODEGEN_BITFIELD(24, 30); //!< Seg 3 Qindex, Encoder Only 7913 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 7914 } enc; 7915 uint32_t Value; 7916 } DW4; 7917 union 7918 { 7919 struct 7920 { 7921 uint32_t QuantizerValue0Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [0][BlockType2=UVDC], Decoder Only 7922 uint32_t Reserved169 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7923 uint32_t QuantizerValue0Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [0][BlockType3=UVAC], Decoder Only 7924 uint32_t Reserved185 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7925 } dec; 7926 struct 7927 { 7928 uint32_t Y2DcQindexDelta : __CODEGEN_BITFIELD(0, 3); //!< Y2dc Qindex Delta, Encoder Only 7929 uint32_t Y2AcQindexDeltaSign : __CODEGEN_BITFIELD(4, 4); //!< Y2ac Qindex Delta Sign , Encoder Only 7930 uint32_t Reserved165 : __CODEGEN_BITFIELD(5, 7); //!< Reserved, Encoder Only 7931 uint32_t Y2AcQindexDelta : __CODEGEN_BITFIELD(8, 11); //!< Y2ac Qindex Delta , Encoder Only 7932 uint32_t Y2AcQindexSign : __CODEGEN_BITFIELD(12, 12); //!< Y2ac Qindex Sign, Encoder Only 7933 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15); //!< Reserved, Encoder Only 7934 uint32_t UvdcQindexDelta : __CODEGEN_BITFIELD(16, 19); //!< UVdc Qindex Delta, Encoder Only 7935 uint32_t UvdcQindexDeltaSign : __CODEGEN_BITFIELD(20, 20); //!< UVdc Qindex Delta Sign, Encoder Only 7936 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 23); //!< Reserved, Encoder Only 7937 uint32_t UvacQindexdelta : __CODEGEN_BITFIELD(24, 27); //!< UVac QindexDelta, Encoder Only 7938 uint32_t UvacQindexDeltaSign : __CODEGEN_BITFIELD(28, 28); //!< UVac Qindex Delta Sign, Encoder Only 7939 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 7940 } enc; 7941 uint32_t Value; 7942 } DW5; 7943 union 7944 { 7945 struct 7946 { 7947 uint32_t QuantizerValue0Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [0][BlockType4=Y2DC], Decoder Only 7948 uint32_t Reserved201 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7949 uint32_t QuantizerValue0Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [0][BlockType5=Y2AC], Decoder Only 7950 uint32_t Reserved217 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7951 } dec; 7952 struct 7953 { 7954 uint32_t Y1DcQindexDelta : __CODEGEN_BITFIELD(0, 3); //!< Y1dc Qindex Delta, Encoder Only 7955 uint32_t Y1DcQindexDeltaSign : __CODEGEN_BITFIELD(4, 4); //!< Y1dc Qindex Delta Sign , Encoder Only 7956 uint32_t Reserved197 : __CODEGEN_BITFIELD(5, 31); //!< Reserved 7957 } enc; 7958 uint32_t Value; 7959 } DW6; 7960 union 7961 { 7962 struct 7963 { 7964 uint32_t QuantizerValue1Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [1][BlockType0=Y1DC], Decoder Only 7965 uint32_t Reserved233 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7966 uint32_t QuantizerValue1Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [1][BlockType1=Y1AC], Decoder Only 7967 uint32_t Reserved249 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7968 } dec; 7969 struct 7970 { 7971 uint32_t ClampQindexLow : __CODEGEN_BITFIELD(0, 6); //!< Clamp Qindex Low, Encoder Only 7972 uint32_t Reserved231 : __CODEGEN_BITFIELD(7, 7); //!< Reserved, Encoder Only 7973 uint32_t ClampQindexHigh : __CODEGEN_BITFIELD(8, 14); //!< Clamp Qindex high, Encoder Only 7974 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 7975 } enc; 7976 uint32_t Value; 7977 } DW7; 7978 union 7979 { 7980 struct 7981 { 7982 uint32_t QuantizerValue1Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [1][BlockType2=UVDC] 7983 uint32_t Reserved265 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 7984 uint32_t QuantizerValue1Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [1][BlockType3=UVAC] 7985 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7986 }; 7987 uint32_t Value; 7988 } DW8; 7989 union 7990 { 7991 struct 7992 { 7993 uint32_t QuantizerValue1Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [1][BlockType4=Y2DC] 7994 uint32_t Reserved297 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 7995 uint32_t QuantizerValue1Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [1][BlockType5=Y2AC] 7996 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7997 }; 7998 uint32_t Value; 7999 } DW9; 8000 union 8001 { 8002 struct 8003 { 8004 uint32_t QuantizerValue2Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [2][BlockType0=Y1DC] 8005 uint32_t Reserved329 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8006 uint32_t QuantizerValue2Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [2][BlockType1=Y1AC] 8007 uint32_t Reserved345 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8008 }; 8009 uint32_t Value; 8010 } DW10; 8011 union 8012 { 8013 struct 8014 { 8015 uint32_t QuantizerValue2Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [2][BlockType2=UVDC] 8016 uint32_t Reserved361 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8017 uint32_t QuantizerValue2Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [2][BlockType3=UVAC] 8018 uint32_t Reserved377 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8019 }; 8020 uint32_t Value; 8021 } DW11; 8022 union 8023 { 8024 struct 8025 { 8026 uint32_t QuantizerValue2Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [2][BlockType4=Y2DC] 8027 uint32_t Reserved393 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8028 uint32_t QuantizerValue2Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [2][BlockType5=Y2AC] 8029 uint32_t Reserved409 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8030 }; 8031 uint32_t Value; 8032 } DW12; 8033 union 8034 { 8035 struct 8036 { 8037 uint32_t QuantizerValue3Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [3][BlockType0=Y1DC] 8038 uint32_t Reserved425 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8039 uint32_t QuantizerValue3Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [3][BlockType1=Y1AC] 8040 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8041 }; 8042 uint32_t Value; 8043 } DW13; 8044 union 8045 { 8046 struct 8047 { 8048 uint32_t QuantizerValue3Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [3][BlockType2=UVDC] 8049 uint32_t Reserved457 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8050 uint32_t QuantizerValue3Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [3][BlockType3=UVAC] 8051 uint32_t Reserved473 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8052 }; 8053 uint32_t Value; 8054 } DW14; 8055 union 8056 { 8057 struct 8058 { 8059 uint32_t QuantizerValue3Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [3][BlockType4=Y2DC] 8060 uint32_t Reserved489 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8061 uint32_t QuantizerValue3Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [3][BlockType5=Y2AC] 8062 uint32_t Reserved505 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8063 }; 8064 uint32_t Value; 8065 } DW15; 8066 SPLITBASEADDRESS4KBYTEALIGNED_CMD CoeffprobabilityStreaminBaseAddress; //!< DW16..17, CoeffProbability StreamIn Base Address 8067 union 8068 { 8069 struct 8070 { 8071 uint32_t Reserved576 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 8072 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 8073 uint32_t CoeffprobabilityStreaminArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL 8074 uint32_t CoeffprobabilityStreaminMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< CoeffProbability StreamIn - Memory Compression Enable 8075 uint32_t CoeffprobabilityStreaminMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE 8076 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 12); //!< Reserved 8077 uint32_t CoeffprobabilityStreaminTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE 8078 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 8079 }; 8080 uint32_t Value; 8081 } DW18; 8082 union 8083 { 8084 struct 8085 { 8086 uint32_t Mbsegmentidtreeprobs0 : __CODEGEN_BITFIELD(0, 7); //!< MBSegmentIDTreeProbs[0] 8087 uint32_t Mbsegmentidtreeprobs1 : __CODEGEN_BITFIELD(8, 15); //!< MBSegmentIDTreeProbs[1] 8088 uint32_t Mbsegmentidtreeprobs2 : __CODEGEN_BITFIELD(16, 23); //!< MBSegmentIDTreeProbs[2] 8089 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8090 }; 8091 uint32_t Value; 8092 } DW19; 8093 union 8094 { 8095 struct 8096 { 8097 uint32_t Interpredfromgrefrefprob : __CODEGEN_BITFIELD(0, 7); //!< InterPredFromGRefRefProb 8098 uint32_t Interpredfromlastrefprob : __CODEGEN_BITFIELD(8, 15); //!< InterPredFromLastRefProb 8099 uint32_t Intrambprob : __CODEGEN_BITFIELD(16, 23); //!< IntraMBProb 8100 uint32_t Mbnocoeffskipfalseprob : __CODEGEN_BITFIELD(24, 31); //!< MBNoCoeffSkipFalseProb 8101 }; 8102 uint32_t Value; 8103 } DW20; 8104 union 8105 { 8106 struct 8107 { 8108 uint32_t Ymodeprob0 : __CODEGEN_BITFIELD(0, 7); //!< YModeProb[0] 8109 uint32_t Ymodeprob1 : __CODEGEN_BITFIELD(8, 15); //!< YModeProb[1] 8110 uint32_t Ymodeprob2 : __CODEGEN_BITFIELD(16, 23); //!< YModeProb[2] 8111 uint32_t Ymodeprob3 : __CODEGEN_BITFIELD(24, 31); //!< YModeProb[3] 8112 }; 8113 uint32_t Value; 8114 } DW21; 8115 union 8116 { 8117 struct 8118 { 8119 uint32_t Uvmodeprob0 : __CODEGEN_BITFIELD(0, 7); //!< UVModeProb[0] 8120 uint32_t Uvmodeprob1 : __CODEGEN_BITFIELD(8, 15); //!< UVModeProb[1] 8121 uint32_t Uvmodeprob2 : __CODEGEN_BITFIELD(16, 23); //!< UVModeProb[2] 8122 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8123 }; 8124 uint32_t Value; 8125 } DW22; 8126 union 8127 { 8128 struct 8129 { 8130 uint32_t Mvupdateprobs00 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][0] 8131 uint32_t Mvupdateprobs01 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][1] 8132 uint32_t Mvupdateprobs02 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][2] 8133 uint32_t Mvupdateprobs03 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][3] 8134 }; 8135 uint32_t Value; 8136 } DW23; 8137 union 8138 { 8139 struct 8140 { 8141 uint32_t Mvupdateprobs04 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][4] 8142 uint32_t Mvupdateprobs05 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][5] 8143 uint32_t Mvupdateprobs06 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][6] 8144 uint32_t Mvupdateprobs07 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][7] 8145 }; 8146 uint32_t Value; 8147 } DW24; 8148 union 8149 { 8150 struct 8151 { 8152 uint32_t Mvupdateprobs08 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][8] 8153 uint32_t Mvupdateprobs09 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][9] 8154 uint32_t Mvupdateprobs010 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][10] 8155 uint32_t Mvupdateprobs011 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][11] 8156 }; 8157 uint32_t Value; 8158 } DW25; 8159 union 8160 { 8161 struct 8162 { 8163 uint32_t Mvupdateprobs012 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][12] 8164 uint32_t Mvupdateprobs013 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][13] 8165 uint32_t Mvupdateprobs014 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][14] 8166 uint32_t Mvupdateprobs015 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][15] 8167 }; 8168 uint32_t Value; 8169 } DW26; 8170 union 8171 { 8172 struct 8173 { 8174 uint32_t Mvupdateprobs016 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][16] 8175 uint32_t Mvupdateprobs017 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][17] 8176 uint32_t Mvupdateprobs018 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][18] 8177 uint32_t Reserved888 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8178 }; 8179 uint32_t Value; 8180 } DW27; 8181 union 8182 { 8183 struct 8184 { 8185 uint32_t Mvupdateprobs10 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][0] 8186 uint32_t Mvupdateprobs11 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][1] 8187 uint32_t Mvupdateprobs12 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][2] 8188 uint32_t Mvupdateprobs13 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][3] 8189 }; 8190 uint32_t Value; 8191 } DW28; 8192 union 8193 { 8194 struct 8195 { 8196 uint32_t Mvupdateprobs14 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][4] 8197 uint32_t Mvupdateprobs15 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][5] 8198 uint32_t Mvupdateprobs16 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][6] 8199 uint32_t Mvupdateprobs17 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][7] 8200 }; 8201 uint32_t Value; 8202 } DW29; 8203 union 8204 { 8205 struct 8206 { 8207 uint32_t Mvupdateprobs18 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][8] 8208 uint32_t Mvupdateprobs19 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][9] 8209 uint32_t Mvupdateprobs110 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][10] 8210 uint32_t Mvupdateprobs111 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][11] 8211 }; 8212 uint32_t Value; 8213 } DW30; 8214 union 8215 { 8216 struct 8217 { 8218 uint32_t Mvupdateprobs112 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][12] 8219 uint32_t Mvupdateprobs113 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][13] 8220 uint32_t Mvupdateprobs114 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][14] 8221 uint32_t Mvupdateprobs115 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][15] 8222 }; 8223 uint32_t Value; 8224 } DW31; 8225 union 8226 { 8227 struct 8228 { 8229 uint32_t Mvupdateprobs116 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][16] 8230 uint32_t Mvupdateprobs117 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][17] 8231 uint32_t Mvupdateprobs118 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][18] 8232 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8233 }; 8234 uint32_t Value; 8235 } DW32; 8236 union 8237 { 8238 struct 8239 { 8240 uint32_t Reflfdelta0ForIntraFrame : __CODEGEN_BITFIELD(0, 6); //!< RefLFDelta0 (for INTRA FRAME) 8241 uint32_t Reserved1063 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 8242 uint32_t Reflfdelta1ForLastFrame : __CODEGEN_BITFIELD(8, 14); //!< RefLFDelta1 (for LAST FRAME) 8243 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 8244 uint32_t Reflfdelta2ForGoldenFrame : __CODEGEN_BITFIELD(16, 22); //!< RefLFDelta2 (for GOLDEN FRAME) 8245 uint32_t Reserved1079 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 8246 uint32_t Reflfdelta3ForAltrefFrame : __CODEGEN_BITFIELD(24, 30); //!< RefLFDelta3 (for ALTREF FRAME) 8247 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 8248 }; 8249 uint32_t Value; 8250 } DW33; 8251 union 8252 { 8253 struct 8254 { 8255 uint32_t Modelfdelta0ForBPredMode : __CODEGEN_BITFIELD(0, 6); //!< ModeLFDelta0 (for B_PRED mode) 8256 uint32_t Reserved1095 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 8257 uint32_t Modelfdelta1ForZeromvMode : __CODEGEN_BITFIELD(8, 14); //!< ModeLFDelta1(for ZEROMV mode) 8258 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 8259 uint32_t Modelfdelta2ForNearestNearAndNewMode : __CODEGEN_BITFIELD(16, 22); //!< ModeLFDelta2 (for Nearest, Near and New mode) 8260 uint32_t Reserved1111 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 8261 uint32_t Modelfdelta3ForSplitmvMode : __CODEGEN_BITFIELD(24, 30); //!< ModeLFDelta3 (for SPLITMV mode) 8262 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 8263 }; 8264 uint32_t Value; 8265 } DW34; 8266 SPLITBASEADDRESS4KBYTEALIGNED_CMD SegmentationIdStreamBaseAddress; //!< DW35..36, Segmentation ID Stream Base Address 8267 union 8268 { 8269 struct 8270 { 8271 uint32_t Reserved1184 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 8272 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 8273 uint32_t SegmentationIdStreamArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL 8274 uint32_t SegmentationIdStreamMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Segmentation ID Stream - Memory Compression Enable 8275 uint32_t SegmentationIdStreamMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE 8276 uint32_t Reserved1195 : __CODEGEN_BITFIELD(11, 12); //!< Reserved 8277 uint32_t SegmentationIdStreamTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE 8278 uint32_t Reserved1199 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 8279 }; 8280 uint32_t Value; 8281 } DW37; 8282 8283 //! \name Local enumerations 8284 8285 enum SUB_OPCODE_B 8286 { 8287 SUB_OPCODE_B_MFXVP8PICSTATE = 0, //!< No additional details 8288 }; 8289 8290 enum SUB_OPCODE_A 8291 { 8292 SUB_OPCODE_A_VP8COMMON = 0, //!< No additional details 8293 }; 8294 8295 enum MEDIA_COMMAND_OPCODE 8296 { 8297 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 8298 }; 8299 8300 enum PIPELINE 8301 { 8302 PIPELINE_VIDEOCODEC = 2, //!< No additional details 8303 }; 8304 8305 enum COMMAND_TYPE 8306 { 8307 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8308 }; 8309 8310 //! \brief MC_FILTER_SELECT 8311 //! \details 8312 //! To specify VP8 Profile of operation. 8313 enum MC_FILTER_SELECT 8314 { 8315 MC_FILTER_SELECT_UNNAMED0 = 0, //!< 6-tap filter (regular filter mode) 8316 MC_FILTER_SELECT_UNNAMED1 = 1, //!< 2-tap bilinear filter (simple profile/version mode) 8317 }; 8318 8319 //! \brief CHROMA_FULL_PIXEL_MC_FILTER_MODE 8320 //! \details 8321 //! To specify VP8 Profile of operation. 8322 enum CHROMA_FULL_PIXEL_MC_FILTER_MODE 8323 { 8324 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED0 = 0, //!< Chroma MC filter operates in sub-pixel mode 8325 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED1 = 1, //!< Chroma MC filter only operates in full pixel position, i.e. no sub-pixel interpolation. 8326 }; 8327 8328 //! \brief DBLKFILTERTYPE 8329 //! \details 8330 //! To specify VP8 Profile of operation. 8331 enum DBLKFILTERTYPE 8332 { 8333 DBLKFILTERTYPE_UNNAMED0 = 0, //!< Use a full feature normal deblocking filter 8334 DBLKFILTERTYPE_UNNAMED1 = 1, //!< Use a simple filter for deblocking 8335 }; 8336 8337 enum SKEYFRAMEFLAG 8338 { 8339 SKEYFRAMEFLAG_NON_KEYFRAME_P_FRAME = 0, //!< No additional details 8340 SKEYFRAMEFLAG_KEYFRAME_I_FRAME = 1, //!< No additional details 8341 }; 8342 8343 //! \brief SEGMENTATION_ID_STREAMOUT_ENABLE 8344 //! \details 8345 //! When 0, no output needed. 8346 enum SEGMENTATION_ID_STREAMOUT_ENABLE 8347 { 8348 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTDISABLED = 0, //!< No additional details 8349 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTENABLED = 1, //!< No additional details 8350 }; 8351 8352 //! \brief SEGMENTATION_ID_STREAMIN_ENABLE 8353 //! \details 8354 //! When 0, no input needed. 8355 enum SEGMENTATION_ID_STREAMIN_ENABLE 8356 { 8357 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINDISABLED = 0, //!< No additional details 8358 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINENABLED = 1, //!< No additional details 8359 }; 8360 8361 enum SEGMENT_ENABLE_FLAG 8362 { 8363 SEGMENT_ENABLE_FLAG_UNNAMED0 = 0, //!< Disable Segmentation processing in the current frame 8364 SEGMENT_ENABLE_FLAG_UNNAMED1 = 1, //!< Enable Segmentation processing in the current frame 8365 }; 8366 8367 enum UPDATE_MBSEGMENT_MAP_FLAG 8368 { 8369 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED0 = 0, //!< Disable segmentation update 8370 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED1 = 1, //!< Enable segmentation update, and to enable reading segment_id for each MB. 8371 }; 8372 8373 //! \brief MB_NOCOEFF_SKIPFLAG 8374 //! \details 8375 //! Frame level control if Skip MB (with no non-zero coefficient) is allowed 8376 //! or not. 8377 enum MB_NOCOEFF_SKIPFLAG 8378 { 8379 MB_NOCOEFF_SKIPFLAG_UNNAMED0 = 0, //!< All MBs will have its MB level signaling mb_skip_coeff forced to 0. That is, no skip of coefficient record in the bitstream (even their values are all 0s) 8380 MB_NOCOEFF_SKIPFLAG_UNNAMED1 = 1, //!< Skip MB is enabled in the per MB record. 8381 }; 8382 8383 enum MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 8384 { 8385 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED0 = 0, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is disabled. 8386 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED1 = 1, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is enabled. 8387 }; 8388 8389 enum LOG2_NUM_OF_PARTITION 8390 { 8391 LOG2_NUM_OF_PARTITION_1TOKENPARTITION = 0, //!< No additional details 8392 LOG2_NUM_OF_PARTITION_2TOKENPARTITION = 1, //!< No additional details 8393 LOG2_NUM_OF_PARTITION_4TOKENPARTITION = 2, //!< No additional details 8394 LOG2_NUM_OF_PARTITION_8TOKENPARTITION = 3, //!< No additional details 8395 }; 8396 8397 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT0 8398 //! \details 8399 //! There are max 4 segments per frame, each segment can have its own 8400 //! deblocking filter level. When segmentation is disabled, only segment 0 8401 //! parameter is used for the entire frame. 8402 enum DBLKFILTERLEVEL_FOR_SEGMENT0 8403 { 8404 DBLKFILTERLEVEL_FOR_SEGMENT0_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8405 }; 8406 8407 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT1 8408 //! \details 8409 //! There are max 4 segments per frame, each segment can have its own 8410 //! deblocking filter level. When segmentation is disabled, only segment 0 8411 //! parameter is used for the entire frame. 8412 enum DBLKFILTERLEVEL_FOR_SEGMENT1 8413 { 8414 DBLKFILTERLEVEL_FOR_SEGMENT1_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8415 }; 8416 8417 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT2 8418 //! \details 8419 //! There are max 4 segments per frame, each segment can have its own 8420 //! deblocking filter level. When segmentation is disabled, only segment 0 8421 //! parameter is used for the entire frame. 8422 enum DBLKFILTERLEVEL_FOR_SEGMENT2 8423 { 8424 DBLKFILTERLEVEL_FOR_SEGMENT2_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8425 }; 8426 8427 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT3 8428 //! \details 8429 //! There are max 4 segments per frame, each segment can have its own 8430 //! deblocking filter level. When segmentation is disabled, only segment 0 8431 //! parameter is used for the entire frame. 8432 enum DBLKFILTERLEVEL_FOR_SEGMENT3 8433 { 8434 DBLKFILTERLEVEL_FOR_SEGMENT3_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8435 }; 8436 8437 //! \brief COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL 8438 //! \details 8439 //! This field controls the priority of arbitration used in the GAC/GAM 8440 //! pipeline for this surface. 8441 enum COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL 8442 { 8443 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8444 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8445 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8446 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8447 }; 8448 8449 //! \brief COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE 8450 //! \details 8451 //! Distinguishes Vertical from Horizontal compression. Please refer to 8452 //! vol1aMemory Data Formats chapter, Media Memory Compression 8453 //! section for more details. 8454 enum COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE 8455 { 8456 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 8457 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 8458 }; 8459 8460 //! \brief COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE 8461 //! \details 8462 //! For Media Surfaces:This field specifies the tiled resource mode. 8463 enum COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE 8464 { 8465 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 8466 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 8467 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 8468 }; 8469 8470 //! \brief SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL 8471 //! \details 8472 //! This field controls the priority of arbitration used in the GAC/GAM 8473 //! pipeline for this surface. 8474 enum SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL 8475 { 8476 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8477 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8478 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8479 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8480 }; 8481 8482 //! \brief SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE 8483 //! \details 8484 //! Distinguishes Vertical from Horizontal compression. Please refer to 8485 //! vol1aMemory Data Formats chapter, Media Memory Compression 8486 //! section for more details. 8487 enum SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE 8488 { 8489 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 8490 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 8491 }; 8492 8493 //! \brief SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE 8494 //! \details 8495 //! For Media Surfaces:This field specifies the tiled resource mode. 8496 enum SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE 8497 { 8498 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 8499 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 8500 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 8501 }; 8502 8503 //! \name Initializations 8504 8505 //! \brief Explicit member initialization function 8506 MFX_VP8_PIC_STATE_CMD(); 8507 8508 static const size_t dwSize = 38; 8509 static const size_t byteSize = 152; 8510 }; 8511 8512 //! 8513 //! \brief MFX_JPEG_HUFF_TABLE_STATE 8514 //! \details 8515 //! This Huffman table commands contains both DC and AC tables for either 8516 //! luma or chroma. Once a Huffman table has been defined for a particular 8517 //! destination, it replaces the previous tables stored in that destination 8518 //! and shall be used in the remaining Scans of the current image. A Huffman 8519 //! table will be sent to H/W only when it is loaded from bitstream. 8520 //! 8521 struct MFX_JPEG_HUFF_TABLE_STATE_CMD 8522 { 8523 union 8524 { 8525 struct 8526 { 8527 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 8528 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 8529 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 8530 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 8531 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 8532 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 8533 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 8534 }; 8535 uint32_t Value; 8536 } DW0; 8537 union 8538 { 8539 struct 8540 { 8541 uint32_t Hufftableid1Bit : __CODEGEN_BITFIELD(0, 0); //!< HUFFTABLEID_1_BIT 8542 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 8543 }; 8544 uint32_t Value; 8545 } DW1; 8546 uint32_t DcBits128BitArray[3]; //!< DC_BITS (12 8-bit array) 8547 uint32_t DcHuffval128BitArray[3]; //!< DC_HUFFVAL (12 8-bit array) 8548 uint32_t AcBits168BitArray[4]; //!< AC_BITS (16 8-bit array) 8549 uint32_t AcHuffval1608BitArray[40]; //!< AC_HUFFVAL (160 8-bit array) 8550 union 8551 { 8552 struct 8553 { 8554 uint32_t AcHuffval28BitArray : __CODEGEN_BITFIELD(0, 15); //!< AC_HUFFVAL(2-8 bit array) 8555 uint32_t Reserved1680 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8556 }; 8557 uint32_t Value; 8558 } DW52; 8559 8560 //! \name Local enumerations 8561 8562 enum SUBOPCODE_B 8563 { 8564 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 8565 }; 8566 8567 enum SUBOPCODE_A 8568 { 8569 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 8570 }; 8571 8572 enum MEDIA_COMMAND_OPCODE 8573 { 8574 MEDIA_COMMAND_OPCODE_JPEGCOMMON = 7, //!< No additional details 8575 }; 8576 8577 enum PIPELINE 8578 { 8579 PIPELINE_MFXMULTIDW = 2, //!< No additional details 8580 }; 8581 8582 enum COMMAND_TYPE 8583 { 8584 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8585 }; 8586 8587 //! \brief HUFFTABLEID_1_BIT 8588 //! \details 8589 //! Identifies the huffman table. 8590 enum HUFFTABLEID_1_BIT 8591 { 8592 HUFFTABLEID_1_BIT_Y = 0, //!< Huffman table for Y 8593 }; 8594 8595 //! \name Initializations 8596 8597 //! \brief Explicit member initialization function 8598 MFX_JPEG_HUFF_TABLE_STATE_CMD(); 8599 8600 static const size_t dwSize = 53; 8601 static const size_t byteSize = 212; 8602 }; 8603 8604 //! 8605 //! \brief MFX_PIPE_BUF_ADDR_STATE 8606 //! \details 8607 //! This state command provides the memory base addresses for all row 8608 //! stores, StreamOut buffer and reconstructed picture output buffers 8609 //! required by the MFD or MFC Engine (that are in addition to the row 8610 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 8611 //! reference picture buffers). This is a picture level state command and 8612 //! is common among all codec standards and for both encoder and decoder 8613 //! operating modes. However, some fields may only applicable to a specific 8614 //! codec standard. All Pixel Surfaces (original, reference frame and 8615 //! reconstructed frame) in the Encoder are programmed with the same surface 8616 //! state (NV12 and TileY format), except each has its own frame buffer base 8617 //! address. In the tile format, there is no need to provide buffer offset 8618 //! for each slice; since from each MB address, the hardware can calculated 8619 //! the corresponding memory location within the frame buffer directly. 8620 //! 8621 struct MFX_PIPE_BUF_ADDR_STATE_CMD 8622 { 8623 union 8624 { 8625 struct 8626 { 8627 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 8628 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 8629 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 8630 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 8631 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMON_OPCODE 8632 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 8633 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 8634 }; 8635 uint32_t Value; 8636 } DW0; 8637 union 8638 { 8639 struct 8640 { 8641 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8642 uint32_t PreDeblockingDestinationAddress : __CODEGEN_BITFIELD(6, 31); //!< Pre Deblocking Destination Address 8643 }; 8644 uint32_t Value; 8645 } DW1; 8646 union 8647 { 8648 struct 8649 { 8650 uint32_t PreDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Pre Deblocking Destination Address High 8651 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8652 }; 8653 uint32_t Value; 8654 } DW2; 8655 union 8656 { 8657 struct 8658 { 8659 uint32_t PreDeblockingMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Pre Deblocking - Memory Object Control State 8660 uint32_t PreDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 8661 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31); //!< Reserved 8662 }; 8663 uint32_t Value; 8664 } DW3; 8665 union 8666 { 8667 struct 8668 { 8669 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8670 uint32_t PostDeblockingDestinationAddress : __CODEGEN_BITFIELD(6, 31); //!< Post Deblocking Destination Address 8671 }; 8672 uint32_t Value; 8673 } DW4; 8674 union 8675 { 8676 struct 8677 { 8678 uint32_t PostDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Post Deblocking Destination Address High 8679 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8680 }; 8681 uint32_t Value; 8682 } DW5; 8683 union 8684 { 8685 struct 8686 { 8687 uint32_t PostDeblockingMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Post Deblocking - Memory Object Control State 8688 uint32_t PostDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 8689 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31); //!< Reserved 8690 }; 8691 uint32_t Value; 8692 } DW6; 8693 union 8694 { 8695 struct 8696 { 8697 uint32_t Reserved224 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8698 uint32_t OriginalUncompressedPictureSourceAddress : __CODEGEN_BITFIELD(6, 31); //!< Original Uncompressed Picture Source Address 8699 }; 8700 uint32_t Value; 8701 } DW7; 8702 union 8703 { 8704 struct 8705 { 8706 uint32_t OriginalUncompressedPictureSourceAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Original Uncompressed Picture Source Address High 8707 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8708 }; 8709 uint32_t Value; 8710 } DW8; 8711 union 8712 { 8713 struct 8714 { 8715 uint32_t OriginalUncompressedPictureSourceMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Original Uncompressed Picture Source - Memory Object Control State 8716 uint32_t OriginalUncompressedPictureSourceArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL 8717 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 31); //!< Reserved 8718 }; 8719 uint32_t Value; 8720 } DW9; 8721 union 8722 { 8723 struct 8724 { 8725 uint32_t Reserved320 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8726 uint32_t StreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< StreamOut Data Destination Base Address 8727 }; 8728 uint32_t Value; 8729 } DW10; 8730 union 8731 { 8732 struct 8733 { 8734 uint32_t StreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< StreamOut Data Destination Base Address High 8735 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8736 }; 8737 uint32_t Value; 8738 } DW11; 8739 union 8740 { 8741 struct 8742 { 8743 uint32_t StreamoutDataDestinationMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< StreamOut Data Destination - Memory Object Control State 8744 uint32_t StreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 8745 uint32_t Reserved393 : __CODEGEN_BITFIELD( 9, 31); //!< Reserved 8746 }; 8747 uint32_t Value; 8748 } DW12; 8749 union 8750 { 8751 struct 8752 { 8753 uint32_t Reserved416 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8754 uint32_t IntraRowStoreScratchBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Intra Row Store Scratch Buffer Base Address 8755 }; 8756 uint32_t Value; 8757 } DW13; 8758 union 8759 { 8760 struct 8761 { 8762 uint32_t IntraRowStoreScratchBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Intra Row Store Scratch Buffer Base Address High 8763 uint32_t Reserved464 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8764 }; 8765 uint32_t Value; 8766 } DW14; 8767 union 8768 { 8769 struct 8770 { 8771 uint32_t IntraRowStoreScratchBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Intra Row Store Scratch Buffer - Memory Object Control State 8772 uint32_t IntraRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 8773 uint32_t Reserved489 : __CODEGEN_BITFIELD( 9, 11); //!< Reserved 8774 uint32_t IntraRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 8775 uint32_t Reserved493 : __CODEGEN_BITFIELD(13, 31); //!< Reserved 8776 }; 8777 uint32_t Value; 8778 } DW15; 8779 union 8780 { 8781 struct 8782 { 8783 uint32_t Reserved512 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8784 uint32_t DeblockingFilterRowStoreScratchBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Deblocking Filter Row Store Scratch Base Address 8785 }; 8786 uint32_t Value; 8787 } DW16; 8788 union 8789 { 8790 struct 8791 { 8792 uint32_t DeblockingFilterRowStoreScratchBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Deblocking Filter Row Store Scratch Base Address High 8793 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8794 }; 8795 uint32_t Value; 8796 } DW17; 8797 union 8798 { 8799 struct 8800 { 8801 uint32_t DeblockingFilterRowStoreScratchMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Deblocking Filter Row Store Scratch - Memory Object Control State 8802 uint32_t DeblockingFilterRowStoreScratchArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL 8803 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 9); //!< Reserved 8804 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Deblocking Filter Row Store Scratch - Memory Compression Mode 8805 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 8806 uint32_t DeblockingFilterRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 8807 uint32_t Reserved589 : __CODEGEN_BITFIELD(13, 31); //!< Reserved 8808 }; 8809 uint32_t Value; 8810 } DW18; 8811 8812 SPLITBASEADDRESS64BYTEALIGNED_CMD Refpicbaseaddr[16]; //!< RefPicBaseAddr 8813 8814 union 8815 { 8816 struct 8817 { 8818 uint32_t ReferncePictureMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Refernce Picture - Memory Object Control State 8819 uint32_t ReferencePictureArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL 8820 uint32_t Reserved1641 : __CODEGEN_BITFIELD(9, 31); //!< Reserved 8821 }; 8822 uint32_t Value; 8823 } DW51; 8824 union 8825 { 8826 struct 8827 { 8828 uint32_t Reserved1664 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8829 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address 8830 }; 8831 uint32_t Value; 8832 } DW52; 8833 union 8834 { 8835 struct 8836 { 8837 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address High 8838 uint32_t Reserved1712 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8839 }; 8840 uint32_t Value; 8841 } DW53; 8842 union 8843 { 8844 struct 8845 { 8846 uint32_t MacroblockStatusBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Macroblock Status Buffer - Memory Object Control State 8847 uint32_t MacroblockStatusBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL 8848 uint32_t Reserved1737 : __CODEGEN_BITFIELD( 9, 9); //!< Reserved 8849 uint32_t MacroblockStatusBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Macroblock Status Buffer - Memory Compression Mode 8850 uint32_t Reserved1739 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8851 }; 8852 uint32_t Value; 8853 } DW54; 8854 union 8855 { 8856 struct 8857 { 8858 uint32_t Reserved1760 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8859 uint32_t MacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Macroblock ILDB StreamOut Buffer Base Address 8860 }; 8861 uint32_t Value; 8862 } DW55; 8863 union 8864 { 8865 struct 8866 { 8867 uint32_t MacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Macroblock ILDB StreamOut Buffer Base Address High 8868 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8869 }; 8870 uint32_t Value; 8871 } DW56; 8872 union 8873 { 8874 struct 8875 { 8876 uint32_t MacroblockIldbStreamoutBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Macroblock ILDB StreamOut Buffer - Memory Object Control State 8877 uint32_t MacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL 8878 uint32_t Reserved1833 : __CODEGEN_BITFIELD( 9, 9); //!< Reserved 8879 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Macroblock ILDB StreamOut Buffer - Memory Compression Mode 8880 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8881 }; 8882 uint32_t Value; 8883 } DW57; 8884 union 8885 { 8886 struct 8887 { 8888 uint32_t Reserved1856 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8889 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Second Macroblock ILDB StreamOut Buffer Base Address 8890 }; 8891 uint32_t Value; 8892 } DW58; 8893 union 8894 { 8895 struct 8896 { 8897 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Second Macroblock ILDB StreamOut Buffer Base Address High 8898 uint32_t Reserved1904 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8899 }; 8900 uint32_t Value; 8901 } DW59; 8902 union 8903 { 8904 struct 8905 { 8906 uint32_t SecondMacroblockIldbStreamoutBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Second Macroblock ILDB StreamOut Buffer - Memory Object Control State 8907 uint32_t SecondMacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Second Macroblock ILDB StreamOut Buffer - Arbitration Priority Control 8908 uint32_t Reserved1929 : __CODEGEN_BITFIELD( 9, 9); //!< Reserved 8909 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Second Macroblock ILDB StreamOut Buffer - Memory Compression Mode 8910 uint32_t Reserved1931 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8911 }; 8912 uint32_t Value; 8913 } DW60; 8914 union 8915 { 8916 struct 8917 { 8918 uint32_t Reserved1952; //!< Reserved 8919 }; 8920 uint32_t Value; 8921 } DW61; 8922 union 8923 { 8924 struct 8925 { 8926 uint32_t Reserved1984 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8927 uint32_t ScaledReferenceSurfaceBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Scaled Reference Surface Base Address 8928 }; 8929 uint32_t Value; 8930 } DW62; 8931 union 8932 { 8933 struct 8934 { 8935 uint32_t ScaledReferenceSurfaceBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Scaled Reference Surface Base Address High 8936 uint32_t Reserved2032 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8937 }; 8938 uint32_t Value; 8939 } DW63; 8940 union 8941 { 8942 struct 8943 { 8944 uint32_t ScaledReferenceSurfaceMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Scaled Reference Surface - Memory Object Control State 8945 uint32_t ScaleReferenceSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL 8946 uint32_t ScaledReferenceSurfaceMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Scaled Reference Surface - Memory Compression Enable 8947 uint32_t ScaledReferenceSurfaceRenderCompressionEnable : __CODEGEN_BITFIELD(10, 10); //!< SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE 8948 uint32_t Reserved2059 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8949 }; 8950 uint32_t Value; 8951 } DW64; 8952 union 8953 { 8954 struct 8955 { 8956 uint32_t Reserved2080 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8957 uint32_t SlicesizeStreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< SliceSize StreamOut Data Destination Base Address 8958 }; 8959 uint32_t Value; 8960 } DW65; 8961 union 8962 { 8963 struct 8964 { 8965 uint32_t SlicesizeStreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< SliceSize StreamOut Data Destination Base Address High 8966 uint32_t Reserved2128 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8967 }; 8968 uint32_t Value; 8969 } DW66; 8970 union 8971 { 8972 struct 8973 { 8974 uint32_t SlicesizeStreamoutDataDestinationMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< SliceSize StreamOut Data Destination - Memory Object Control State 8975 uint32_t SlicesizeStreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 8976 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< SliceSize StreamOut Data Destination - Memory Compression Enable 8977 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< SliceSize StreamOut Data Destination - Memory Compression Mode 8978 uint32_t Reserved2155 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8979 }; 8980 uint32_t Value; 8981 } DW67; 8982 8983 //! \name Local enumerations 8984 8985 enum SUBOPCODE_B 8986 { 8987 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 8988 }; 8989 8990 enum SUBOPCODE_A 8991 { 8992 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 8993 }; 8994 8995 enum COMMON_OPCODE 8996 { 8997 COMMON_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 8998 }; 8999 9000 enum PIPELINE 9001 { 9002 PIPELINE_MFXPIPEBUFADDRSTATE = 2, //!< No additional details 9003 }; 9004 9005 enum COMMAND_TYPE 9006 { 9007 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9008 }; 9009 9010 //! \brief PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9011 //! \details 9012 //! This field controls the priority of arbitration used in the GAC/GAM 9013 //! pipeline for this surface. 9014 enum PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9015 { 9016 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9017 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9018 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9019 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9020 }; 9021 9022 //! \brief POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9023 //! \details 9024 //! This field controls the priority of arbitration used in the GAC/GAM 9025 //! pipeline for this surface. 9026 enum POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9027 { 9028 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9029 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9030 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9031 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9032 }; 9033 9034 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL 9035 //! \details 9036 //! This field controls the priority of arbitration used in the GAC/GAM 9037 //! pipeline for this surface. 9038 enum ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL 9039 { 9040 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9041 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9042 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9043 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9044 }; 9045 9046 //! \brief STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9047 //! \details 9048 //! This field controls the priority of arbitration used in the GAC/GAM 9049 //! pipeline for this surface. 9050 enum STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9051 { 9052 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9053 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9054 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9055 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9056 }; 9057 9058 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 9059 //! \details 9060 //! This field controls the priority of arbitration used in the GAC/GAM 9061 //! pipeline for this surface. 9062 enum INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 9063 { 9064 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9065 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9066 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9067 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9068 }; 9069 9070 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9071 //! \details 9072 //! This field controls if Intra Row Store is going to store inside Media 9073 //! Cache or to LLC. 9074 enum INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9075 { 9076 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 9077 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 9078 }; 9079 9080 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL 9081 //! \details 9082 //! This field controls the priority of arbitration used in the GAC/GAM 9083 //! pipeline for this surface. 9084 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL 9085 { 9086 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9087 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9088 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9089 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9090 }; 9091 9092 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9093 //! \details 9094 //! This field controls if Intra Row Store is going to store inside Media 9095 //! Internal Storage or to LLC. 9096 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9097 { 9098 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 9099 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Media Internal Storage 9100 }; 9101 9102 //! \brief REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL 9103 //! \details 9104 //! This field controls the priority of arbitration used in the GAC/GAM 9105 //! pipeline for this surface. 9106 enum REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL 9107 { 9108 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9109 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9110 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9111 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9112 }; 9113 9114 //! \brief MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL 9115 //! \details 9116 //! This field controls the priority of arbitration used in the GAC/GAM 9117 //! pipeline for this surface. 9118 enum MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL 9119 { 9120 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9121 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9122 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9123 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9124 }; 9125 9126 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL 9127 //! \details 9128 //! This field controls the priority of arbitration used in the GAC/GAM 9129 //! pipeline for this surface. 9130 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL 9131 { 9132 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9133 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9134 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9135 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9136 }; 9137 9138 //! \brief SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL 9139 //! \details 9140 //! This field controls the priority of arbitration used in the GAC/GAM 9141 //! pipeline for this surface. 9142 enum SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL 9143 { 9144 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9145 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9146 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9147 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9148 }; 9149 9150 enum SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE 9151 { 9152 SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 9153 SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 9154 }; 9155 9156 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9157 //! \details 9158 //! This field controls the priority of arbitration used in the GAC/GAM 9159 //! pipeline for this surface. 9160 enum SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9161 { 9162 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9163 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9164 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9165 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9166 }; 9167 9168 //! \name Initializations 9169 9170 //! \brief Explicit member initialization function 9171 MFX_PIPE_BUF_ADDR_STATE_CMD(); 9172 9173 static const size_t dwSize = 68; 9174 static const size_t byteSize = 272; 9175 }; 9176 9177 //! 9178 //! \brief MFX_AVC_DIRECTMODE_STATE 9179 //! \details 9180 //! This is a picture level command and is issued once per picture. All DMV 9181 //! buffers are treated as standard media surfaces, in which the lower 6 9182 //! bits are used for conveying surface states.Current Pic POC number is 9183 //! assumed to be available in POCList[32 and 33] of the 9184 //! MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC 9185 //! decoding in VLD and IT modes, and AVC encoder mode. The same command 9186 //! supports both Long and Short AVC Interface. The DMV buffers are not 9187 //! required to be programmed for encoder mode. 9188 //! 9189 struct MFX_AVC_DIRECTMODE_STATE_CMD 9190 { 9191 union 9192 { 9193 struct 9194 { 9195 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 9196 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 9197 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 9198 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 9199 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 9200 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 9201 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 9202 }; 9203 uint32_t Value; 9204 } DW0; 9205 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvBufferBaseAddress[16]; //!< DW1..32, Direct MV Buffer for Reference Frame 0 to 15 - Base Address 9206 MEMORYADDRESSATTRIBUTES_CMD DirectMvBufferAttributes; //!< DW33, Direct MV Buffer for Reference Frame 0 to 15 - Attributes 9207 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvBufferForWriteBaseAddress; //!< DW34..35, Direct MV Buffer for Write - Base Address 9208 MEMORYADDRESSATTRIBUTES_CMD DirectMvBufferForWriteAttributes; //!< DW36, Direct MV Buffer for Write - Attributes 9209 uint32_t PocList[34]; //!< POCList[34][31:0] 9210 9211 //! \name Local enumerations 9212 9213 enum SUBOPCODEB 9214 { 9215 SUBOPCODEB_UNNAMED2 = 2, //!< No additional details 9216 }; 9217 9218 enum SUBOPCODEA 9219 { 9220 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 9221 }; 9222 9223 enum MEDIA_COMMAND_OPCODE 9224 { 9225 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 9226 }; 9227 9228 enum PIPELINE 9229 { 9230 PIPELINE_MFXSINGLEDW = 2, //!< No additional details 9231 }; 9232 9233 enum COMMAND_TYPE 9234 { 9235 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9236 }; 9237 9238 //! \name Initializations 9239 9240 //! \brief Explicit member initialization function 9241 MFX_AVC_DIRECTMODE_STATE_CMD(); 9242 9243 static const size_t dwSize = 71; 9244 static const size_t byteSize = 284; 9245 }; 9246 MEDIA_CLASS_DEFINE_END(mhw__vdbox__mfx__xe2_lpm_base__xe2_lpm__Cmd) 9247 }; 9248 } // namespace xe2_lpm 9249 } // namespace xe2_lpm_base 9250 } // namespace mfx 9251 } // namespace vdbox 9252 } // namespace mhw 9253 9254 #pragma pack() 9255 9256 #endif // __MHW_VDBOX_MFX_HWCMD_XE2_LPM_H__ 9257