1 /*
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15 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 */
22 //!
23 //! \file     mhw_vdbox_mfx_impl_xe2_lpm_base.h
24 //! \brief    MHW VDBOX MFX interface common base for all XE2_LPM platforms
25 //! \details
26 //!
27 
28 #ifndef __MHW_VDBOX_MFX_IMPL_XE2_LPM_BASE_H__
29 #define __MHW_VDBOX_MFX_IMPL_XE2_LPM_BASE_H__
30 
31 #include "mhw_vdbox_mfx_impl.h"
32 #include "mhw_mi_hwcmd_xe2_lpm_base_next.h"
33 
34 namespace mhw
35 {
36 namespace vdbox
37 {
38 namespace mfx
39 {
40 namespace xe2_lpm_base
41 {
42 #define mpeg2WeightScaleSize 16
43 
44 template <typename cmd_t>
45 class BaseImpl : public mfx::Impl<cmd_t>
46 {
47 public:
GetMfxStateCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool isShortFormat)48     MOS_STATUS GetMfxStateCommandsDataSize(
49         uint32_t  mode,
50         uint32_t *commandsSize,
51         uint32_t *patchListSize,
52         bool      isShortFormat)
53     {
54         MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
55 
56         MHW_FUNCTION_ENTER;
57 
58         MHW_MI_CHK_NULL(commandsSize);
59         MHW_MI_CHK_NULL(patchListSize);
60 
61         uint32_t maxSize =
62             mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize +
63             cmd_t::MFX_PIPE_MODE_SELECT_CMD::byteSize +
64             cmd_t::MFX_SURFACE_STATE_CMD::byteSize +
65             cmd_t::MFX_PIPE_BUF_ADDR_STATE_CMD::byteSize +
66             cmd_t::MFX_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize +
67             2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize +
68             2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_REGISTER_MEM_CMD::byteSize +
69             8 * mhw::mi::xe2_lpm_base_next::Cmd::MI_LOAD_REGISTER_REG_CMD::byteSize;
70 
71         uint32_t patchListMaxSize =
72             PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) +
73             PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_PIPE_MODE_SELECT_CMD) +
74             PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_SURFACE_STATE_CMD) +
75             PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_PIPE_BUF_ADDR_STATE_CMD) +
76             PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_IND_OBJ_BASE_ADDR_STATE_CMD) +
77             (2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD)) +
78             (2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_REGISTER_MEM_CMD));
79 
80         uint32_t standard = CodecHal_GetStandardFromMode(mode);
81         if (standard == CODECHAL_AVC)
82         {
83             maxSize +=
84                 cmd_t::MFX_BSP_BUF_BASE_ADDR_STATE_CMD::byteSize +
85                 cmd_t::MFD_AVC_PICID_STATE_CMD::byteSize +
86                 cmd_t::MFX_AVC_DIRECTMODE_STATE_CMD::byteSize +
87                 cmd_t::MFX_AVC_IMG_STATE_CMD::byteSize +
88                 cmd_t::MFX_QM_STATE_CMD::byteSize * 4;  // QM_State sent 4 times
89 
90             patchListMaxSize +=
91                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_BSP_BUF_BASE_ADDR_STATE_CMD) +
92                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_AVC_PICID_STATE_CMD) +
93                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_DIRECTMODE_STATE_CMD) +
94                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_IMG_STATE_CMD) +
95                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_QM_STATE_CMD) * 4;
96 
97             if (mode == CODECHAL_ENCODE_MODE_AVC)
98             {
99                 maxSize +=
100                     mhw::mi::xe2_lpm_base_next::Cmd::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize +
101                     mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize * 3 +            // 3 extra MI_FLUSH_DWs for encode
102                     cmd_t::MFX_FQM_STATE_CMD::byteSize * 4 +                                    // FQM_State sent 4 times
103                     mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_REGISTER_MEM_CMD::byteSize * 8 +  // 5 extra register queries for encode, 3 extra slice level commands for BrcPakStatistics
104                     mhw::mi::xe2_lpm_base_next::Cmd::MI_STORE_DATA_IMM_CMD::byteSize * 3 +      // slice level commands for StatusReport, BrcPakStatistics
105                     MHW_VDBOX_PAK_BITSTREAM_OVERFLOW_SIZE +                                     // accounting for the max DW payload for PAK_INSERT_OBJECT, for frame header payload
106                     cmd_t::MFX_PAK_INSERT_OBJECT_CMD::byteSize * 4;                             // for inserting AU, SPS, PSP, SEI headers before first slice header
107 
108                 patchListMaxSize +=
109                     PATCH_LIST_COMMAND(mhw::mi::Itf::MI_CONDITIONAL_BATCH_BUFFER_END_CMD) +
110                     PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) * 3 +  // 3 extra MI_FLUSH_DWs for encode
111                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_FQM_STATE_CMD) * 4 +  // FQM_State sent 4 times
112                     PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_REGISTER_MEM_CMD) * 8 +  // 5 extra register queries for encode, 3 extra slice level commands for BrcPakStatistics
113                     PATCH_LIST_COMMAND(mhw::mi::Itf::MI_STORE_DATA_IMM_CMD) * 3;       // slice level commands for StatusReport, BrcPakStatistics
114                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFC_AVC_PAK_INSERT_OBJECT_CMD) * 4;  // for inserting AU, SPS, PSP, SEI headers before first slice header
115             }
116         }
117         else if (standard == CODECHAL_MPEG2)
118         {
119             maxSize += cmd_t::MFX_MPEG2_PIC_STATE_CMD::byteSize;
120             patchListMaxSize += PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_MPEG2_PIC_STATE_CMD);
121 
122             if (mode == CODECHAL_DECODE_MODE_MPEG2VLD)
123             {
124                 maxSize +=
125                     cmd_t::MFX_BSP_BUF_BASE_ADDR_STATE_CMD::byteSize +
126                     ((cmd_t::MFX_QM_STATE_CMD::byteSize + (16 * sizeof(uint32_t))) * 2);
127 
128                 patchListMaxSize +=
129                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_BSP_BUF_BASE_ADDR_STATE_CMD) +
130                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_QM_STATE_CMD) * 2;
131             }
132             else if (mode == CODECHAL_DECODE_MODE_MPEG2IDCT)
133             {
134                 maxSize +=
135                     mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize * 2;
136 
137                 patchListMaxSize +=
138                     PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD) * 2;
139             }
140         }
141         else if (standard == CODECHAL_VP8)
142         {
143             maxSize +=
144                 cmd_t::MFX_BSP_BUF_BASE_ADDR_STATE_CMD::byteSize +
145                 cmd_t::MFX_VP8_PIC_STATE_CMD::byteSize;
146 
147             patchListMaxSize +=
148                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_BSP_BUF_BASE_ADDR_STATE_CMD) +
149                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_VP8_PIC_STATE_CMD);
150         }
151         else if (standard == CODECHAL_JPEG)
152         {
153             // Added to prevent error for JPEG
154         }
155         else
156         {
157             MHW_ASSERTMESSAGE("Unsupported decode mode.");
158             maxSize          = 0;
159             patchListMaxSize = 0;
160             eStatus          = MOS_STATUS_UNKNOWN;
161         }
162 
163         *commandsSize  = maxSize;
164         *patchListSize = patchListMaxSize;
165 
166         return eStatus;
167     }
168 
GetMfxPrimitiveCommandsDataSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool isModeSpecific)169     MOS_STATUS GetMfxPrimitiveCommandsDataSize(
170         uint32_t  mode,
171         uint32_t *commandsSize,
172         uint32_t *patchListSize,
173         bool      isModeSpecific)
174     {
175         MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
176 
177         MHW_FUNCTION_ENTER;
178 
179         MHW_MI_CHK_NULL(commandsSize);
180         MHW_MI_CHK_NULL(patchListSize);
181 
182         uint32_t maxSize = 0, patchListMaxSize = 0;
183         uint32_t standard = CodecHal_GetStandardFromMode(mode);
184 
185         if (standard == CODECHAL_AVC)
186         {
187             if (mode == CODECHAL_DECODE_MODE_AVCVLD)
188             {
189                 maxSize =
190                     cmd_t::MFX_AVC_SLICE_STATE_CMD::byteSize +
191                     cmd_t::MFD_AVC_BSD_OBJECT_CMD::byteSize +
192                     cmd_t::MFD_AVC_DPB_STATE_CMD::byteSize +
193                     mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize;
194 
195                 patchListMaxSize =
196                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_SLICE_STATE_CMD) +
197                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_AVC_BSD_OBJECT_CMD) +
198                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_AVC_DPB_STATE_CMD) +
199                     PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD);
200 
201                 if (isModeSpecific)
202                 {
203                     // isModeSpecific = bShortFormat for AVC decode
204                     maxSize +=
205                         cmd_t::MFD_AVC_DPB_STATE_CMD::byteSize +
206                         cmd_t::MFD_AVC_SLICEADDR_CMD::byteSize;
207 
208                     patchListMaxSize +=
209                         PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_AVC_DPB_STATE_CMD) +
210                         PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_AVC_SLICEADDR_CMD);
211                 }
212                 else
213                 {
214                     maxSize +=
215                         (2 * cmd_t::MFX_AVC_REF_IDX_STATE_CMD::byteSize) +
216                         (2 * cmd_t::MFX_AVC_WEIGHTOFFSET_STATE_CMD::byteSize);
217 
218                     patchListMaxSize +=
219                         (2 * PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_REF_IDX_STATE_CMD)) +
220                         (2 * PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_WEIGHTOFFSET_STATE_CMD));
221                 }
222             }
223             else  // CODECHAL_ENCODE_MODE_AVC
224             {
225                 // 1 PAK_INSERT_OBJECT inserted for every end of frame/stream with 1 DW payload
226                 maxSize          = cmd_t::MFX_PAK_INSERT_OBJECT_CMD::byteSize + sizeof(uint32_t);
227                 patchListMaxSize = PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFC_AVC_PAK_INSERT_OBJECT_CMD);
228 
229                 if (isModeSpecific)
230                 {
231                     // isModeSpecific = bSingleTaskPhaseSupported for AVC encode
232                     maxSize += (2 * mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_START_CMD::byteSize);
233                     patchListMaxSize += (2 * PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD));
234                 }
235                 else
236                 {
237                     maxSize +=
238                         (2 * cmd_t::MFX_AVC_REF_IDX_STATE_CMD::byteSize) +
239                         (2 * cmd_t::MFX_AVC_WEIGHTOFFSET_STATE_CMD::byteSize) +
240                         cmd_t::MFX_AVC_SLICE_STATE_CMD::byteSize +
241                         MHW_VDBOX_PAK_SLICE_HEADER_OVERFLOW_SIZE +  // slice header payload
242                         (2 * cmd_t::MFX_PAK_INSERT_OBJECT_CMD::byteSize) +
243                         mhw::mi::xe2_lpm_base_next::Cmd::MI_BATCH_BUFFER_START_CMD::byteSize +
244                         mhw::mi::xe2_lpm_base_next::Cmd::MI_FLUSH_DW_CMD::byteSize;
245 
246                     patchListMaxSize +=
247                         (2 * PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_REF_IDX_STATE_CMD)) +
248                         (2 * PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_WEIGHTOFFSET_STATE_CMD)) +
249                         PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFX_AVC_SLICE_STATE_CMD) +
250                         (2 * PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFC_AVC_PAK_INSERT_OBJECT_CMD)) +
251                         PATCH_LIST_COMMAND(mhw::mi::Itf::MI_BATCH_BUFFER_START_CMD) +
252                         PATCH_LIST_COMMAND(mhw::mi::Itf::MI_FLUSH_DW_CMD);
253                 }
254             }
255         }
256         else if (standard == CODECHAL_MPEG2)
257         {
258             if (mode == CODECHAL_DECODE_MODE_MPEG2VLD)
259             {
260                 maxSize =
261                     cmd_t::MFD_MPEG2_BSD_OBJECT_CMD::byteSize;
262 
263                 patchListMaxSize =
264                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_MPEG2_BSD_OBJECT_CMD);
265             }
266             else if (mode == CODECHAL_DECODE_MODE_MPEG2IDCT)
267             {
268                 maxSize =
269                     cmd_t::MFD_IT_OBJECT_CMD::byteSize +
270                     cmd_t::MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD::byteSize;
271 
272                 patchListMaxSize =
273                     PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_MPEG2_IT_OBJECT_CMD);
274             }
275         }
276         else if (standard == CODECHAL_VP8)
277         {
278             maxSize =
279                 cmd_t::MFD_VP8_BSD_OBJECT_CMD::byteSize;
280 
281             patchListMaxSize +=
282                 PATCH_LIST_COMMAND(mhw::vdbox::mfx::Itf::MFD_VP8_BSD_OBJECT_CMD);
283         }
284         else if (standard == CODECHAL_JPEG)
285         {
286             maxSize +=
287                 cmd_t::MFX_FQM_STATE_CMD::byteSize * 3 +
288                 cmd_t::MFC_JPEG_HUFF_TABLE_STATE_CMD::byteSize * 2 +
289                 cmd_t::MFC_JPEG_SCAN_OBJECT_CMD::byteSize +
290                 cmd_t::MFX_PAK_INSERT_OBJECT_CMD::byteSize * 10;
291         }
292         else
293         {
294             MHW_ASSERTMESSAGE("Unsupported decode mode.");
295             eStatus = MOS_STATUS_UNKNOWN;
296         }
297 
298         *commandsSize  = maxSize;
299         *patchListSize = patchListMaxSize;
300 
301         return eStatus;
302     }
303 
304 protected:
305     using base_t = mfx::Impl<cmd_t>;
306 
BaseImpl(PMOS_INTERFACE osItf,MhwCpInterface * cpItf)307     BaseImpl(PMOS_INTERFACE osItf, MhwCpInterface *cpItf) : base_t(osItf, cpItf){};
308 MEDIA_CLASS_DEFINE_END(mhw__vdbox__mfx__xe2_lpm_base__BaseImpl)
309 };
310 }  // namespace xe2_lpm_base
311 }  // namespace mfx
312 }  // namespace vdbox
313 }  // namespace mhw
314 
315 #endif  // __MHW_VDBOX_MFX_IMPL_XE2_LPM_BASE_H__
316