1 /* 2 * Copyright (c) 2021-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_itf.h 24 //! \brief MHW VDBOX MFX interface common base 25 //! \details 26 //! 27 #ifndef __MHW_VDBOX_MFX_ITF_H__ 28 #define __MHW_VDBOX_MFX_ITF_H__ 29 #include "mhw_itf.h" 30 #include "mhw_vdbox_mfx_cmdpar.h" 31 #include "mhw_vdbox.h" 32 33 #define AVC_MPR_ROWSTORE_BASEADDRESS 256 34 #define AVC_MPR_ROWSTORE_BASEADDRESS_MBAFF 512 35 #define AVC_IP_ROWSTORE_BASEADDRESS 512 36 #define AVC_IP_ROWSTORE_BASEADDRESS_MBAFF 1024 37 #define AVC_VLF_ROWSTORE_BASEADDRESS 768 38 #define VP8_IP_ROWSTORE_BASEADDRESS 256 39 #define VP8_VLF_ROWSTORE_BASEADDRESS 512 40 41 #define _MFX_CMD_DEF(DEF) \ 42 DEF(MFX_QM_STATE);\ 43 DEF(MFX_FQM_STATE);\ 44 DEF(MFX_PIPE_MODE_SELECT);\ 45 DEF(MFX_SURFACE_STATE);\ 46 DEF(MFX_PIPE_BUF_ADDR_STATE);\ 47 DEF(MFX_IND_OBJ_BASE_ADDR_STATE);\ 48 DEF(MFX_BSP_BUF_BASE_ADDR_STATE);\ 49 DEF(MFX_PAK_INSERT_OBJECT);\ 50 DEF(MFX_AVC_IMG_STATE);\ 51 DEF(MFX_AVC_REF_IDX_STATE);\ 52 DEF(MFX_AVC_WEIGHTOFFSET_STATE);\ 53 DEF(MFX_AVC_SLICE_STATE);\ 54 DEF(MFX_AVC_DIRECTMODE_STATE);\ 55 DEF(MFD_AVC_PICID_STATE);\ 56 DEF(MFD_AVC_DPB_STATE);\ 57 DEF(MFD_AVC_SLICEADDR);\ 58 DEF(MFD_AVC_BSD_OBJECT);\ 59 DEF(MFX_JPEG_PIC_STATE);\ 60 DEF(MFC_JPEG_HUFF_TABLE_STATE);\ 61 DEF(MFC_JPEG_SCAN_OBJECT);\ 62 DEF(MFD_JPEG_BSD_OBJECT);\ 63 DEF(MFX_JPEG_HUFF_TABLE_STATE);\ 64 DEF(MFX_MPEG2_PIC_STATE);\ 65 DEF(MFD_MPEG2_BSD_OBJECT);\ 66 DEF(MFX_VP8_PIC_STATE);\ 67 DEF(MFD_VP8_BSD_OBJECT);\ 68 DEF(MFD_IT_OBJECT);\ 69 DEF(MFD_IT_OBJECT_MPEG2_INLINE_DATA); 70 71 namespace mhw 72 { 73 namespace vdbox 74 { 75 namespace mfx 76 { 77 class Itf 78 { 79 public: 80 #define PATCH_LIST_COMMAND(x) (x##_NUMBER_OF_ADDRESSES) 81 //! 82 //! \enum CommandsNumberOfAddresses 83 //! \brief Commands number of addresses 84 //! 85 enum CommandsNumberOfAddresses 86 { 87 // MFX Engine Commands 88 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 89 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 90 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 91 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 92 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 93 MFX_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 94 MFX_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 95 MFX_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 27, // 50 DW for 25 address fields, added 2 for DownScaledReconPicAddr 96 MFX_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 5, // 10 DW for 5 address fields 97 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 98 MFX_BSP_BUF_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 3, // 2 DW for 3 address fields 99 MFD_AVC_PICID_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 100 MFX_AVC_DIRECTMODE_STATE_CMD_NUMBER_OF_ADDRESSES = 17, // 50 DW for 17 address fields 101 MFX_AVC_IMG_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 102 MFX_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 103 MFX_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 104 MFX_MPEG2_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 105 MFX_DBK_OBJECT_CMD_NUMBER_OF_ADDRESSES = 4, // 2 DW for 4 address fields 106 MFX_VP8_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 2 DW for 2 address fields 107 MFX_AVC_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 108 MFD_AVC_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 109 MFD_AVC_DPB_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 110 MFD_AVC_SLICEADDR_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 111 MFX_AVC_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 112 MFX_AVC_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 113 MFC_AVC_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 114 MFD_MPEG2_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 115 MFD_MPEG2_IT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 116 MFD_VP8_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 117 }; 118 MosGetHWTileType(MOS_TILE_TYPE tileType,MOS_TILE_MODE_GMM tileModeGMM,bool gmmTileEnabled)119 static __inline uint32_t MosGetHWTileType(MOS_TILE_TYPE tileType, MOS_TILE_MODE_GMM tileModeGMM, bool gmmTileEnabled) 120 { 121 uint32_t tileMode = 0; 122 123 if (gmmTileEnabled) 124 { 125 return tileModeGMM; 126 } 127 128 switch (tileType) 129 { 130 case MOS_TILE_LINEAR: 131 tileMode = 0; 132 break; 133 case MOS_TILE_YS: 134 tileMode = 1; 135 break; 136 case MOS_TILE_X: 137 tileMode = 2; 138 break; 139 default: 140 tileMode = 3; 141 break; 142 } 143 return tileMode; 144 } 145 146 class ParSetting 147 { 148 public: 149 virtual ~ParSetting() = default; 150 151 _MFX_CMD_DEF(_MHW_SETPAR_DEF); 152 }; 153 virtual ~Itf() = default; 154 155 virtual MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) = 0; 156 157 virtual MOS_STATUS GetRowstoreCachingAddrs(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams) = 0; 158 159 virtual bool IsRowStoreCachingSupported() = 0; 160 161 virtual bool IsDeblockingFilterRowstoreCacheEnabled() = 0; 162 163 virtual bool IsIntraRowstoreCacheEnabled() = 0; 164 165 virtual bool IsBsdMpcRowstoreCacheEnabled() = 0; 166 167 virtual bool IsMprRowstoreCacheEnabled() = 0; 168 169 virtual MHW_VDBOX_NODE_IND GetMaxVdboxIndex() = 0; 170 171 virtual uint8_t GetNumVdbox() = 0; 172 173 virtual MOS_STATUS FindGpuNodeToUse(PMHW_VDBOX_GPUNODE_LIMIT gpuNodeLimit) = 0; 174 175 virtual MOS_STATUS GetMfxStateCommandsDataSize( 176 uint32_t mode, 177 uint32_t *commandsSize, 178 uint32_t *patchListSize, 179 bool isShortFormat) = 0; 180 181 virtual MOS_STATUS GetMfxPrimitiveCommandsDataSize( 182 uint32_t mode, 183 uint32_t *commandsSize, 184 uint32_t *patchListSize, 185 bool isModeSpecific) = 0; 186 GetMfxErrorFlagsMask()187 inline uint32_t GetMfxErrorFlagsMask() { return m_mfxErrorFlagsMask; } 188 189 vdbox::RowStoreCache m_intraRowstoreCache = {}; //!< Intra rowstore cache 190 vdbox::RowStoreCache m_deblockingFilterRowstoreCache = {}; //!< Deblocking filter row store cache 191 vdbox::RowStoreCache m_bsdMpcRowstoreCache = {}; //!< BSD/MPC row store cache 192 vdbox::RowStoreCache m_mprRowstoreCache = {}; //!< MPR row store cache 193 bool m_rowstoreCachingSupported = false; 194 MHW_VDBOX_NODE_IND m_maxVdboxIndex = MHW_VDBOX_NODE_1; //!< max vdbox index 195 uint8_t m_numVdbox = 1; //!< vdbox num 196 bool m_scalabilitySupported = false; //!< Indicate if scalability supported 197 static const uint32_t m_mfxErrorFlagsMask = 0xFBFF; //!< Mfx error flags mask 198 static const uint32_t m_mpeg2WeightScaleSize = 16; //!< Size of MPEG2 weight scale 199 //!< Bit 10 of MFD_ERROR_STATUS register is set to a random value during RC6, so it is not used 200 _MFX_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 201 202 MEDIA_CLASS_DEFINE_END(mhw__vdbox__mfx__Itf) 203 }; 204 }//namespace mfx 205 }//namespace vdbox 206 }//namespace mhw 207 208 #endif //__MHW_VDBOX_MFX_ITF_H__ 209 210