1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2019-2022, Intel Corporation 4 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 25 26 //! 27 //! \file mhw_vdbox_vdenc_hwcmd_xe_hpm.h 28 //! \brief Auto-generated constructors for MHW and states. 29 //! \details This file may not be included outside of Xe_HPM as other components 30 //! should use MHW interface to interact with MHW commands and states. 31 //! 32 #ifndef __MHW_VDBOX_VDENC_HWCMD_XE_HPM_H__ 33 #define __MHW_VDBOX_VDENC_HWCMD_XE_HPM_H__ 34 35 #include "mhw_hwcmd.h" 36 #include "mos_utilities.h" 37 #pragma once 38 #pragma pack(1) 39 40 namespace mhw 41 { 42 namespace vdbox 43 { 44 namespace vdenc 45 { 46 namespace xe_hpm 47 { 48 49 struct _VDENC_CMD1_CMD 50 { 51 union 52 { 53 struct 54 { 55 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 56 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 57 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 58 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 59 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 60 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 61 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 62 }; 63 uint32_t Value; 64 } DW0; 65 union 66 { 67 //!< DWORD 1 68 struct 69 { 70 uint32_t VDENC_CMD1_DW1_BIT0 : __CODEGEN_BITFIELD(0, 7); 71 uint32_t VDENC_CMD1_DW1_BIT8 : __CODEGEN_BITFIELD(8, 15); 72 uint32_t VDENC_CMD1_DW1_BIT16 : __CODEGEN_BITFIELD(16, 23); 73 uint32_t VDENC_CMD1_DW1_BIT24 : __CODEGEN_BITFIELD(24, 31); 74 }; 75 uint32_t Value; 76 } DW1; 77 union 78 { 79 //!< DWORD 2 80 struct 81 { 82 uint32_t VDENC_CMD1_DW2_BIT0 : __CODEGEN_BITFIELD(0, 7); 83 uint32_t VDENC_CMD1_DW2_BIT8 : __CODEGEN_BITFIELD(8, 15); 84 uint32_t VDENC_CMD1_DW2_BIT16 : __CODEGEN_BITFIELD(16, 23); 85 uint32_t VDENC_CMD1_DW2_BIT24 : __CODEGEN_BITFIELD(24, 31); 86 }; 87 uint32_t Value; 88 } DW2; 89 union 90 { 91 //!< DWORD 3 92 struct 93 { 94 uint32_t VDENC_CMD1_DW3_BIT0 : __CODEGEN_BITFIELD(0, 7); 95 uint32_t VDENC_CMD1_DW3_BIT8 : __CODEGEN_BITFIELD(8, 15); 96 uint32_t VDENC_CMD1_DW3_BIT16 : __CODEGEN_BITFIELD(16, 23); 97 uint32_t VDENC_CMD1_DW3_BIT24 : __CODEGEN_BITFIELD(24, 31); 98 }; 99 uint32_t Value; 100 } DW3; 101 union 102 { 103 //!< DWORD 4 104 struct 105 { 106 uint32_t VDENC_CMD1_DW4_BIT0 : __CODEGEN_BITFIELD(0, 7); 107 uint32_t VDENC_CMD1_DW4_BIT8 : __CODEGEN_BITFIELD(8, 15); 108 uint32_t VDENC_CMD1_DW4_BIT16 : __CODEGEN_BITFIELD(16, 23); 109 uint32_t VDENC_CMD1_DW4_BIT24 : __CODEGEN_BITFIELD(24, 31); 110 }; 111 uint32_t Value; 112 } DW4; 113 union 114 { 115 //!< DWORD 5 116 struct 117 { 118 uint32_t VDENC_CMD1_DW5_BIT0 : __CODEGEN_BITFIELD(0, 7); 119 uint32_t VDENC_CMD1_DW5_BIT8 : __CODEGEN_BITFIELD(8, 15); 120 uint32_t VDENC_CMD1_DW5_BIT16 : __CODEGEN_BITFIELD(16, 23); 121 uint32_t VDENC_CMD1_DW5_BIT24 : __CODEGEN_BITFIELD(24, 31); 122 }; 123 uint32_t Value; 124 } DW5; 125 union 126 { 127 //!< DWORD 6 128 struct 129 { 130 uint32_t VDENC_CMD1_DW6_BIT0 : __CODEGEN_BITFIELD(0, 7); 131 uint32_t VDENC_CMD1_DW6_BIT8 : __CODEGEN_BITFIELD(8, 15); 132 uint32_t VDENC_CMD1_DW6_BIT16 : __CODEGEN_BITFIELD(16, 23); 133 uint32_t VDENC_CMD1_DW6_BIT24 : __CODEGEN_BITFIELD(24, 31); 134 }; 135 uint32_t Value; 136 } DW6; 137 union 138 { 139 //!< DWORD 7 140 struct 141 { 142 uint32_t VDENC_CMD1_DW7_BIT0 : __CODEGEN_BITFIELD(0, 7); 143 uint32_t VDENC_CMD1_DW7_BIT8 : __CODEGEN_BITFIELD(8, 15); 144 uint32_t VDENC_CMD1_DW7_BIT16 : __CODEGEN_BITFIELD(16, 23); 145 uint32_t VDENC_CMD1_DW7_BIT24 : __CODEGEN_BITFIELD(24, 31); 146 }; 147 uint32_t Value; 148 } DW7; 149 union 150 { 151 //!< DWORD 8 152 struct 153 { 154 uint32_t VDENC_CMD1_DW8_BIT0 : __CODEGEN_BITFIELD(0, 7); 155 uint32_t VDENC_CMD1_DW8_BIT8 : __CODEGEN_BITFIELD(8, 15); 156 uint32_t VDENC_CMD1_DW8_BIT16 : __CODEGEN_BITFIELD(16, 23); 157 uint32_t VDENC_CMD1_DW8_BIT24 : __CODEGEN_BITFIELD(24, 31); 158 }; 159 uint32_t Value; 160 } DW8; 161 union 162 { 163 //!< DWORD 9 164 struct 165 { 166 uint32_t VDENC_CMD1_DW9_BIT0 : __CODEGEN_BITFIELD(0, 7); 167 uint32_t VDENC_CMD1_DW9_BIT8 : __CODEGEN_BITFIELD(8, 15); 168 uint32_t VDENC_CMD1_DW9_BIT16 : __CODEGEN_BITFIELD(16, 23); 169 uint32_t VDENC_CMD1_DW9_BIT24 : __CODEGEN_BITFIELD(24, 31); 170 }; 171 uint32_t Value; 172 } DW9; 173 union 174 { 175 //!< DWORD 10 176 struct 177 { 178 uint32_t VDENC_CMD1_DW10_BIT0 : __CODEGEN_BITFIELD(0, 7); 179 uint32_t VDENC_CMD1_DW10_BIT8 : __CODEGEN_BITFIELD(8, 15); 180 uint32_t VDENC_CMD1_DW10_BIT16 : __CODEGEN_BITFIELD(16, 23); 181 uint32_t VDENC_CMD1_DW10_BIT24 : __CODEGEN_BITFIELD(24, 31); 182 }; 183 uint32_t Value; 184 } DW10; 185 union 186 { 187 //!< DWORD 11 188 struct 189 { 190 uint32_t VDENC_CMD1_DW11_BIT0 : __CODEGEN_BITFIELD(0, 7); 191 uint32_t VDENC_CMD1_DW11_BIT8 : __CODEGEN_BITFIELD(8, 15); 192 uint32_t VDENC_CMD1_DW11_BIT16 : __CODEGEN_BITFIELD(16, 23); 193 uint32_t VDENC_CMD1_DW11_BIT24 : __CODEGEN_BITFIELD(24, 31); 194 }; 195 uint32_t Value; 196 } DW11; 197 union 198 { 199 //!< DWORD 12 200 struct 201 { 202 uint32_t VDENC_CMD1_DW12_BIT0 : __CODEGEN_BITFIELD(0, 7); 203 uint32_t VDENC_CMD1_DW12_BIT8 : __CODEGEN_BITFIELD(8, 15); 204 uint32_t VDENC_CMD1_DW12_BIT16 : __CODEGEN_BITFIELD(16, 23); 205 uint32_t VDENC_CMD1_DW12_BIT24 : __CODEGEN_BITFIELD(24, 31); 206 }; 207 uint32_t Value; 208 } DW12; 209 union 210 { 211 //!< DWORD 13 212 struct 213 { 214 uint32_t VDENC_CMD1_DW13_BIT0 : __CODEGEN_BITFIELD(0, 7); 215 uint32_t VDENC_CMD1_DW13_BIT8 : __CODEGEN_BITFIELD(8, 15); 216 uint32_t VDENC_CMD1_DW13_BIT16 : __CODEGEN_BITFIELD(16, 23); 217 uint32_t VDENC_CMD1_DW13_BIT24 : __CODEGEN_BITFIELD(24, 31); 218 }; 219 uint32_t Value; 220 } DW13; 221 union 222 { 223 //!< DWORD 14 224 struct 225 { 226 uint32_t VDENC_CMD1_DW14_BIT0 : __CODEGEN_BITFIELD(0, 7); 227 uint32_t VDENC_CMD1_DW14_BIT8 : __CODEGEN_BITFIELD(8, 15); 228 uint32_t VDENC_CMD1_DW14_BIT16 : __CODEGEN_BITFIELD(16, 23); 229 uint32_t VDENC_CMD1_DW14_BIT24 : __CODEGEN_BITFIELD(24, 31); 230 }; 231 uint32_t Value; 232 } DW14; 233 union 234 { 235 //!< DWORD 15 236 struct 237 { 238 uint32_t VDENC_CMD1_DW15_BIT0 : __CODEGEN_BITFIELD(0, 7); 239 uint32_t VDENC_CMD1_DW15_BIT8 : __CODEGEN_BITFIELD(8, 15); 240 uint32_t VDENC_CMD1_DW15_BIT16 : __CODEGEN_BITFIELD(16, 23); 241 uint32_t VDENC_CMD1_DW15_BIT24 : __CODEGEN_BITFIELD(24, 31); 242 }; 243 uint32_t Value; 244 } DW15; 245 union 246 { 247 //!< DWORD 16 248 struct 249 { 250 uint32_t VDENC_CMD1_DW16_BIT0 : __CODEGEN_BITFIELD(0, 7); 251 uint32_t VDENC_CMD1_DW16_BIT8 : __CODEGEN_BITFIELD(8, 15); 252 uint32_t VDENC_CMD1_DW16_BIT16 : __CODEGEN_BITFIELD(16, 23); 253 uint32_t VDENC_CMD1_DW16_BIT24 : __CODEGEN_BITFIELD(24, 31); 254 }; 255 uint32_t Value; 256 } DW16; 257 union 258 { 259 //!< DWORD 17 260 struct 261 { 262 uint32_t VDENC_CMD1_DW17_BIT0 : __CODEGEN_BITFIELD(0, 7); 263 uint32_t VDENC_CMD1_DW17_BIT8 : __CODEGEN_BITFIELD(8, 15); 264 uint32_t VDENC_CMD1_DW17_BIT16 : __CODEGEN_BITFIELD(16, 23); 265 uint32_t VDENC_CMD1_DW17_BIT24 : __CODEGEN_BITFIELD(24, 31); 266 }; 267 uint32_t Value; 268 } DW17; 269 union 270 { 271 //!< DWORD 18 272 struct 273 { 274 uint32_t VDENC_CMD1_DW18_BIT0 : __CODEGEN_BITFIELD(0, 7); 275 uint32_t VDENC_CMD1_DW18_BIT8 : __CODEGEN_BITFIELD(8, 15); 276 uint32_t VDENC_CMD1_DW18_BIT16 : __CODEGEN_BITFIELD(16, 23); 277 uint32_t VDENC_CMD1_DW18_BIT24 : __CODEGEN_BITFIELD(24, 31); 278 }; 279 uint32_t Value; 280 } DW18; 281 union 282 { 283 //!< DWORD 19 284 struct 285 { 286 uint32_t VDENC_CMD1_DW19_BIT0 : __CODEGEN_BITFIELD(0, 7); 287 uint32_t VDENC_CMD1_DW19_BIT8 : __CODEGEN_BITFIELD(8, 15); 288 uint32_t VDENC_CMD1_DW19_BIT16 : __CODEGEN_BITFIELD(16, 23); 289 uint32_t VDENC_CMD1_DW19_BIT24 : __CODEGEN_BITFIELD(24, 31); 290 }; 291 uint32_t Value; 292 } DW19; 293 union 294 { 295 //!< DWORD 20 296 struct 297 { 298 uint32_t VDENC_CMD1_DW20_BIT0 : __CODEGEN_BITFIELD(0, 7); 299 uint32_t VDENC_CMD1_DW20_BIT8 : __CODEGEN_BITFIELD(8, 15); 300 uint32_t VDENC_CMD1_DW20_BIT16 : __CODEGEN_BITFIELD(16, 23); 301 uint32_t VDENC_CMD1_DW20_BIT24 : __CODEGEN_BITFIELD(24, 31); 302 }; 303 uint32_t Value; 304 } DW20; 305 union 306 { 307 //!< DWORD 21 308 struct 309 { 310 uint32_t VDENC_CMD1_DW21_BIT0 : __CODEGEN_BITFIELD(0, 7); 311 uint32_t VDENC_CMD1_DW21_BIT8 : __CODEGEN_BITFIELD(8, 15); 312 uint32_t VDENC_CMD1_DW21_BIT16 : __CODEGEN_BITFIELD(16, 23); 313 uint32_t VDENC_CMD1_DW21_BIT24 : __CODEGEN_BITFIELD(24, 31); 314 }; 315 uint32_t Value; 316 } DW21; 317 union 318 { 319 //!< DWORD 22 320 struct 321 { 322 uint32_t VDENC_CMD1_DW22_BIT0 : __CODEGEN_BITFIELD(0, 15); 323 uint32_t VDENC_CMD1_DW22_BIT16 : __CODEGEN_BITFIELD(16, 24); 324 uint32_t VDENC_CMD1_DW22_BIT25 : __CODEGEN_BITFIELD(25, 31); 325 }; 326 uint32_t Value; 327 } DW22; 328 union 329 { 330 //!< DWORD 23 331 struct 332 { 333 uint32_t VDENC_CMD1_DW23_BIT0 : __CODEGEN_BITFIELD(0, 7); 334 uint32_t VDENC_CMD1_DW23_BIT8 : __CODEGEN_BITFIELD(8, 15); 335 uint32_t VDENC_CMD1_DW23_BIT16 : __CODEGEN_BITFIELD(16, 23); 336 uint32_t VDENC_CMD1_DW23_BIT24 : __CODEGEN_BITFIELD(24, 31); 337 }; 338 uint32_t Value; 339 } DW23; 340 union 341 { 342 //!< DWORD 24 343 struct 344 { 345 uint32_t VDENC_CMD1_DW24_BIT0 : __CODEGEN_BITFIELD(0, 7); 346 uint32_t VDENC_CMD1_DW24_BIT8 : __CODEGEN_BITFIELD(8, 15); 347 uint32_t VDENC_CMD1_DW24_BIT16 : __CODEGEN_BITFIELD(16, 23); 348 uint32_t VDENC_CMD1_DW24_BIT24 : __CODEGEN_BITFIELD(24, 31); 349 }; 350 uint32_t Value; 351 } DW24; 352 union 353 { 354 //!< DWORD 25 355 struct 356 { 357 uint32_t VDENC_CMD1_DW25_BIT0 : __CODEGEN_BITFIELD(0, 7); 358 uint32_t VDENC_CMD1_DW25_BIT8 : __CODEGEN_BITFIELD(8, 15); 359 uint32_t VDENC_CMD1_DW25_BIT16 : __CODEGEN_BITFIELD(16, 23); 360 uint32_t VDENC_CMD1_DW25_BIT24 : __CODEGEN_BITFIELD(24, 31); 361 }; 362 uint32_t Value; 363 } DW25; 364 union 365 { 366 //!< DWORD 26 367 struct 368 { 369 uint32_t VDENC_CMD1_DW26_BIT0 : __CODEGEN_BITFIELD(0, 7); 370 uint32_t VDENC_CMD1_DW26_BIT8 : __CODEGEN_BITFIELD(8, 15); 371 uint32_t VDENC_CMD1_DW26_BIT16 : __CODEGEN_BITFIELD(16, 23); 372 uint32_t VDENC_CMD1_DW26_BIT24 : __CODEGEN_BITFIELD(24, 31); 373 }; 374 uint32_t Value; 375 } DW26; 376 union 377 { 378 //!< DWORD 27 379 struct 380 { 381 uint32_t VDENC_CMD1_DW27_BIT0 : __CODEGEN_BITFIELD(0, 7); 382 uint32_t VDENC_CMD1_DW27_BIT8 : __CODEGEN_BITFIELD(8, 15); 383 uint32_t VDENC_CMD1_DW27_BIT16 : __CODEGEN_BITFIELD(16, 23); 384 uint32_t VDENC_CMD1_DW27_BIT24 : __CODEGEN_BITFIELD(24, 31); 385 }; 386 uint32_t Value; 387 } DW27; 388 union 389 { 390 //!< DWORD 28 391 struct 392 { 393 uint32_t VDENC_CMD1_DW28_BIT0 : __CODEGEN_BITFIELD(0, 7); 394 uint32_t VDENC_CMD1_DW28_BIT8 : __CODEGEN_BITFIELD(8, 15); 395 uint32_t VDENC_CMD1_DW28_BIT16 : __CODEGEN_BITFIELD(16, 23); 396 uint32_t VDENC_CMD1_DW28_BIT24 : __CODEGEN_BITFIELD(24, 31); 397 }; 398 uint32_t Value; 399 } DW28; 400 union 401 { 402 //!< DWORD 29 403 struct 404 { 405 uint32_t VDENC_CMD1_DW29_BIT0 : __CODEGEN_BITFIELD(0, 7); 406 uint32_t VDENC_CMD1_DW29_BIT8 : __CODEGEN_BITFIELD(8, 15); 407 uint32_t VDENC_CMD1_DW29_BIT16 : __CODEGEN_BITFIELD(16, 23); 408 uint32_t VDENC_CMD1_DW29_BIT24 : __CODEGEN_BITFIELD(24, 31); 409 }; 410 uint32_t Value; 411 } DW29; 412 union 413 { 414 //!< DWORD 30 415 struct 416 { 417 uint32_t VDENC_CMD1_DW30_BIT0 : __CODEGEN_BITFIELD(0, 7); 418 uint32_t VDENC_CMD1_DW30_BIT8 : __CODEGEN_BITFIELD(8, 15); 419 uint32_t VDENC_CMD1_DW30_BIT16 : __CODEGEN_BITFIELD(16, 23); 420 uint32_t VDENC_CMD1_DW30_BIT24 : __CODEGEN_BITFIELD(24, 31); 421 }; 422 uint32_t Value; 423 } DW30; 424 union 425 { 426 struct 427 { 428 uint32_t VDENC_CMD1_DW31_BIT0 : __CODEGEN_BITFIELD(0, 7); 429 uint32_t VDENC_CMD1_DW31_BIT8 : __CODEGEN_BITFIELD(8, 15); 430 uint32_t VDENC_CMD1_DW31_BIT16 : __CODEGEN_BITFIELD(16, 23); 431 uint32_t VDENC_CMD1_DW31_BIT24 : __CODEGEN_BITFIELD(24, 31); 432 }; 433 uint32_t Value; 434 } DW31; 435 union 436 { 437 struct 438 { 439 uint32_t VDENC_CMD1_DW32_BIT0 : __CODEGEN_BITFIELD(0, 7); 440 uint32_t VDENC_CMD1_DW32_BIT8 : __CODEGEN_BITFIELD(8, 15); 441 uint32_t VDENC_CMD1_DW32_BIT16 : __CODEGEN_BITFIELD(16, 23); 442 uint32_t VDENC_CMD1_DW32_BIT24 : __CODEGEN_BITFIELD(24, 31); 443 }; 444 uint32_t Value; 445 } DW32; 446 447 //! \name Local enumerations 448 449 enum SUBOPB 450 { 451 SUBOPB_VDENCCMD1CMD = 10, //!< No additional details 452 }; 453 454 enum SUBOPA 455 { 456 SUBOPA_UNNAMED0 = 0, //!< No additional details 457 }; 458 459 enum OPCODE 460 { 461 OPCODE_VDENCPIPE = 1, //!< No additional details 462 }; 463 464 enum PIPELINE 465 { 466 PIPELINE_MFXCOMMON = 2, //!< No additional details 467 }; 468 469 enum COMMAND_TYPE 470 { 471 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 472 }; 473 474 //! \name Initializations 475 476 //! \brief Explicit member initialization function _VDENC_CMD1_CMD_VDENC_CMD1_CMD477 _VDENC_CMD1_CMD() 478 { 479 MOS_ZeroMemory(this, sizeof(*this)); 480 481 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 482 DW0.Subopb = SUBOPB_VDENCCMD1CMD; 483 DW0.Subopa = SUBOPA_UNNAMED0; 484 DW0.Opcode = OPCODE_VDENCPIPE; 485 DW0.Pipeline = PIPELINE_MFXCOMMON; 486 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 487 } 488 489 static const size_t dwSize = 33; 490 static const size_t byteSize = 132; 491 }; 492 493 #if IGFX_VDENC_INTERFACE_EXT_SUPPORT 494 #include "mhw_vdbox_vdenc_hwcmd_xe_hpm_ext.h" 495 #else 496 struct _VDENC_CMD2_CMD 497 { 498 union 499 { 500 //!< DWORD 0 501 struct 502 { 503 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWord Length 504 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 505 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 506 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 507 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 508 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 509 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 510 }; 511 uint32_t Value; 512 } DW0; 513 union 514 { 515 //!< DWORD 1 516 struct 517 { 518 uint32_t FrameWidthInPixelsMinusOne : __CODEGEN_BITFIELD(0, 15); //!< FrameWidthInPixelsMinusOne 519 uint32_t FrameHeightInPixelsMinusOne : __CODEGEN_BITFIELD(16, 31); //!< FrameHeightInPixelsMinusOne 520 }; 521 uint32_t Value; 522 } DW1; 523 union 524 { 525 //!< DWORD 2 526 struct 527 { 528 uint32_t : __CODEGEN_BITFIELD(0, 19); 529 uint32_t PictureType : __CODEGEN_BITFIELD(20, 21); //!< Picture Type 530 uint32_t TemporalMvpEnableFlag : __CODEGEN_BITFIELD(22, 22); //!< TemporalMvpEnableFlag 531 uint32_t Collocatedfroml0Flag : __CODEGEN_BITFIELD(23, 23); //!< CollocatedFromL0Flag 532 uint32_t LongTermReferenceFlagsL0 : __CODEGEN_BITFIELD(24, 26); //!< LongTermReferenceFlags_L0 533 uint32_t LongTermReferenceFlagsL1 : __CODEGEN_BITFIELD(27, 27); //!< LongTermReferenceFlags_L1 534 uint32_t : __CODEGEN_BITFIELD(28, 29); 535 uint32_t TransformSkip : __CODEGEN_BITFIELD(30, 30); //!< TransformSkip 536 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD(31, 31); //!< ConstrainedIntraPredFlag 537 }; 538 uint32_t Value; 539 } DW2; 540 union 541 { 542 //!< DWORD 3 543 struct 544 { 545 uint32_t FwdPocNumberForRefid0InL0 : __CODEGEN_BITFIELD(0, 7); //!< FWD_POC_NUMBER_FOR_REFID_0_IN_L0 546 uint32_t BwdPocNumberForRefid0InL1 : __CODEGEN_BITFIELD(8, 15); //!< BWD_POC_NUMBER_FOR_REFID_0_IN_L1 547 uint32_t PocNumberForRefid1InL0 : __CODEGEN_BITFIELD(16, 23); //!< POC_NUMBER_FOR_REFID_1_IN_L0 548 uint32_t PocNumberForRefid1InL1 : __CODEGEN_BITFIELD(24, 31); //!< POC_NUMBER_FOR_REFID_1_IN_L1 549 }; 550 uint32_t Value; 551 } DW3; 552 union 553 { 554 //!< DWORD 4 555 struct 556 { 557 uint32_t PocNumberForRefid2InL0 : __CODEGEN_BITFIELD(0, 7); //!< FWD_POC_NUMBER_FOR_REFID_2_IN_L0 558 uint32_t PocNumberForRefid2InL1 : __CODEGEN_BITFIELD(8, 15); //!< BWD_POC_NUMBER_FOR_REFID_2_IN_L1 559 uint32_t PocNumberForRefid3InL0 : __CODEGEN_BITFIELD(16, 23); //!< POC_NUMBER_FOR_REFID_3_IN_L0 560 uint32_t PocNumberForRefid3InL1 : __CODEGEN_BITFIELD(24, 31); //!< POC_NUMBER_FOR_REFID_3_IN_L1 561 }; 562 uint32_t Value; 563 } DW4; 564 union 565 { 566 //!< DWORD 5 567 struct 568 { 569 uint32_t : __CODEGEN_BITFIELD(0, 7); 570 uint32_t StreaminRoiEnable : __CODEGEN_BITFIELD(8, 8); //!< StreamIn ROI Enable 571 uint32_t : __CODEGEN_BITFIELD(9, 9); 572 uint32_t SubPelMode : __CODEGEN_BITFIELD(10, 11); //!< SubPelMode 573 uint32_t : __CODEGEN_BITFIELD(12, 23); 574 uint32_t NumRefIdxL0Minus1 : __CODEGEN_BITFIELD(24, 27); //!< NumRefIdxL0_minus1 575 uint32_t NumRefIdxL1Minus1 : __CODEGEN_BITFIELD(28, 31); //!< NumRefIdxL1_minus1 576 }; 577 uint32_t Value; 578 } DW5; 579 union 580 { 581 //!< DWORD 6 582 struct 583 { 584 uint32_t : __CODEGEN_BITFIELD(0, 31); 585 }; 586 uint32_t Value; 587 } DW6; 588 union 589 { 590 //!< DWORD 7 591 struct 592 { 593 uint32_t : __CODEGEN_BITFIELD(0, 3); 594 uint32_t SegmentationEnable : __CODEGEN_BITFIELD(4, 4); //!< Segmentation Enable 595 uint32_t SegmentationMapTemporalPredictionEnable : __CODEGEN_BITFIELD(5, 5); //!< Segmentation map temporal prediction enable 596 uint32_t : __CODEGEN_BITFIELD(6, 6); 597 uint32_t TilingEnable : __CODEGEN_BITFIELD(7, 7); //!< Tiling enable 598 uint32_t : __CODEGEN_BITFIELD(8, 8); 599 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD(9, 9); //!< VDENC Stream IN 600 uint32_t : __CODEGEN_BITFIELD(10, 15); 601 uint32_t PakOnlyMultiPassEnable : __CODEGEN_BITFIELD(16, 16); //!< PAK-Only Multi-Pass Enable 602 uint32_t : __CODEGEN_BITFIELD(17, 31); 603 }; 604 uint32_t Value; 605 } DW7; 606 union 607 { 608 //!< DWORD 8 609 struct 610 { 611 uint32_t : __CODEGEN_BITFIELD(0, 31); 612 }; 613 uint32_t Value; 614 } DW8; 615 union 616 { 617 //!< DWORD 9 618 struct 619 { 620 uint32_t : __CODEGEN_BITFIELD(0, 31); 621 }; 622 uint32_t Value; 623 } DW9; 624 union 625 { 626 //!< DWORD 10 627 struct 628 { 629 uint32_t : __CODEGEN_BITFIELD(0, 31); 630 }; 631 uint32_t Value; 632 } DW10; 633 union 634 { 635 //!< DWORD 11 636 struct 637 { 638 uint32_t FwdRef0RefPic : __CODEGEN_BITFIELD(0, 2); 639 uint32_t : __CODEGEN_BITFIELD(3, 7); 640 uint32_t FwdRef1RefPic : __CODEGEN_BITFIELD(8, 10); 641 uint32_t : __CODEGEN_BITFIELD(11, 15); 642 uint32_t FwdRef2RefPic : __CODEGEN_BITFIELD(16, 18); 643 uint32_t : __CODEGEN_BITFIELD(19, 23); 644 uint32_t BwdRef0RefPic : __CODEGEN_BITFIELD(24, 26); 645 uint32_t : __CODEGEN_BITFIELD(27, 31); 646 }; 647 uint32_t Value; 648 } DW11; 649 union 650 { 651 //!< DWORD 12 652 struct 653 { 654 uint32_t : __CODEGEN_BITFIELD(0, 31); 655 }; 656 uint32_t Value; 657 } DW12; 658 union 659 { 660 //!< DWORD 13 661 struct 662 { 663 uint32_t : __CODEGEN_BITFIELD(0, 31); 664 }; 665 uint32_t Value; 666 } DW13; 667 union 668 { 669 //!< DWORD 14 670 struct 671 { 672 uint32_t : __CODEGEN_BITFIELD(0, 31); 673 }; 674 uint32_t Value; 675 } DW14; 676 union 677 { 678 //!< DWORD 15 679 struct 680 { 681 uint32_t : __CODEGEN_BITFIELD(0, 31); 682 }; 683 uint32_t Value; 684 } DW15; 685 union 686 { 687 //!< DWORD 16 688 struct 689 { 690 uint32_t MinQp : __CODEGEN_BITFIELD(0, 7); //!< MINQP 691 uint32_t MaxQp : __CODEGEN_BITFIELD(8, 15); //!< MAXQP 692 uint32_t : __CODEGEN_BITFIELD(16, 31); 693 }; 694 uint32_t Value; 695 } DW16; 696 union 697 { 698 //!< DWORD 17 699 struct 700 { 701 uint32_t : __CODEGEN_BITFIELD(0, 19); 702 uint32_t TemporalMVEnableForIntegerSearch : __CODEGEN_BITFIELD(20, 20); //!< Setting this bit enables Temporal MV Enable for Integer search 703 uint32_t : __CODEGEN_BITFIELD(21, 31); 704 }; 705 uint32_t Value; 706 } DW17; 707 union 708 { 709 //!< DWORD 18 710 struct 711 { 712 uint32_t : __CODEGEN_BITFIELD(0, 31); 713 }; 714 uint32_t Value; 715 } DW18; 716 union 717 { 718 //!< DWORD 19 719 struct 720 { 721 uint32_t : __CODEGEN_BITFIELD(0, 31); 722 }; 723 uint32_t Value; 724 } DW19; 725 union 726 { 727 //!< DWORD 20 728 struct 729 { 730 uint32_t : __CODEGEN_BITFIELD(0, 31); 731 }; 732 uint32_t Value; 733 } DW20; 734 union 735 { 736 //!< DWORD 21 737 struct 738 { 739 uint32_t IntraRefreshPos : __CODEGEN_BITFIELD(0, 8); //!< IntraRefreshPos 740 uint32_t : __CODEGEN_BITFIELD(9, 15); 741 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD(16, 23); //!< IntraRefreshMBSizeMinusOne 742 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(24, 24); //!< IntraRefreshMode 743 uint32_t IntraRefreshEnable : __CODEGEN_BITFIELD(25, 25); //!< IntraRefreshEnable (Rolling I Enable) 744 uint32_t : __CODEGEN_BITFIELD(26, 27); 745 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(28, 31); //!< QP_ADJUSTMENT_FOR_ROLLING_I 746 }; 747 uint32_t Value; 748 } DW21; 749 union 750 { 751 //!< DWORD 22 752 struct 753 { 754 uint32_t : __CODEGEN_BITFIELD(0, 31); 755 }; 756 uint32_t Value; 757 } DW22; 758 union 759 { 760 //!< DWORD 23 761 struct 762 { 763 uint32_t : __CODEGEN_BITFIELD(0, 31); 764 }; 765 uint32_t Value; 766 } DW23; 767 union 768 { 769 //!< DWORD 24 770 struct 771 { 772 uint32_t QpForSeg0 : __CODEGEN_BITFIELD(0, 7); //!< QP for Seg0 773 uint32_t QpForSeg1 : __CODEGEN_BITFIELD(8, 15); //!< QP for Seg1 774 uint32_t QpForSeg2 : __CODEGEN_BITFIELD(16, 23); //!< QP for Seg2 775 uint32_t QpForSeg3 : __CODEGEN_BITFIELD(24, 31); //!< QP for Seg3 776 }; 777 uint32_t Value; 778 } DW24; 779 union 780 { 781 //!< DWORD 25 782 struct 783 { 784 uint32_t QpForSeg4 : __CODEGEN_BITFIELD(0, 7); //!< QP for Seg4 785 uint32_t QpForSeg5 : __CODEGEN_BITFIELD(8, 15); //!< QP for Seg5 786 uint32_t QpForSeg6 : __CODEGEN_BITFIELD(16, 23); //!< QP for Seg6 787 uint32_t QpForSeg7 : __CODEGEN_BITFIELD(24, 31); //!< QP for Seg7 788 }; 789 uint32_t Value; 790 } DW25; 791 union 792 { 793 //!< DWORD 26 794 struct 795 { 796 uint32_t : __CODEGEN_BITFIELD(0, 24); 797 uint32_t Vp9DynamicSliceEnable : __CODEGEN_BITFIELD(25, 25); //!< VP9 Dynamic slice enable 798 uint32_t : __CODEGEN_BITFIELD(26, 31); 799 }; 800 uint32_t Value; 801 } DW26; 802 union 803 { 804 //!< DWORD 27 805 struct 806 { 807 uint32_t QpPrimeYDc : __CODEGEN_BITFIELD(0, 7); //!< QPPRIMEY_DC 808 uint32_t QpPrimeYAc : __CODEGEN_BITFIELD(8, 15); //!< QPPRIMEY_AC 809 uint32_t : __CODEGEN_BITFIELD(16, 31); 810 }; 811 uint32_t Value; 812 } DW27; 813 union 814 { 815 //!< DWORD 28 816 struct 817 { 818 uint32_t : __CODEGEN_BITFIELD(0, 31); 819 }; 820 uint32_t Value; 821 } DW28; 822 union 823 { 824 //!< DWORD 29 825 struct 826 { 827 uint32_t : __CODEGEN_BITFIELD(0, 31); 828 }; 829 uint32_t Value; 830 } DW29; 831 union 832 { 833 //!< DWORD 30 834 struct 835 { 836 uint32_t : __CODEGEN_BITFIELD(0, 31); 837 }; 838 uint32_t Value; 839 } DW30; 840 union 841 { 842 //!< DWORD 31 843 struct 844 { 845 uint32_t : __CODEGEN_BITFIELD(0, 31); 846 }; 847 uint32_t Value; 848 } DW31; 849 union 850 { 851 //!< DWORD 32 852 struct 853 { 854 uint32_t : __CODEGEN_BITFIELD(0, 31); 855 }; 856 uint32_t Value; 857 } DW32; 858 union 859 { 860 //!< DWORD 33 861 struct 862 { 863 uint32_t : __CODEGEN_BITFIELD(0, 31); 864 }; 865 uint32_t Value; 866 } DW33; 867 union 868 { 869 //!< DWORD 34 870 struct 871 { 872 uint32_t : __CODEGEN_BITFIELD(0, 31); 873 }; 874 uint32_t Value; 875 } DW34; 876 union 877 { 878 //!< DWORD 35 879 struct 880 { 881 uint32_t : __CODEGEN_BITFIELD(0, 31); 882 }; 883 uint32_t Value; 884 } DW35; 885 union 886 { 887 //!< DWORD 36 888 struct 889 { 890 uint32_t IntraRefreshBoundaryRef0 : __CODEGEN_BITFIELD(0, 8); //!< IntraRefreshBoundary Ref0 891 uint32_t : __CODEGEN_BITFIELD(9, 9); 892 uint32_t IntraRefreshBoundaryRef1 : __CODEGEN_BITFIELD(10, 18); //!< IntraRefreshBoundary Ref1 893 uint32_t : __CODEGEN_BITFIELD(19, 19); 894 uint32_t IntraRefreshBoundaryRef2 : __CODEGEN_BITFIELD(20, 28); //!< IntraRefreshBoundary Ref2 895 uint32_t : __CODEGEN_BITFIELD(29, 31); 896 }; 897 uint32_t Value; 898 } DW36; 899 union 900 { 901 struct 902 { 903 uint32_t : __CODEGEN_BITFIELD(0, 31); 904 }; 905 uint32_t Value; 906 } DW37; 907 union 908 { 909 //!< DWORD 38 910 struct 911 { 912 uint32_t : __CODEGEN_BITFIELD(0, 31); 913 }; 914 uint32_t Value; 915 } DW38; 916 union 917 { 918 //!< DWORD 39 919 struct 920 { 921 uint32_t : __CODEGEN_BITFIELD(0, 31); 922 }; 923 uint32_t Value; 924 } DW39; 925 union 926 { 927 //!< DWORD 40 928 struct 929 { 930 uint32_t : __CODEGEN_BITFIELD(0, 31); 931 }; 932 uint32_t Value; 933 } DW40; 934 union 935 { 936 //!< DWORD 41 937 struct 938 { 939 uint32_t : __CODEGEN_BITFIELD(0, 31); 940 }; 941 uint32_t Value; 942 } DW41; 943 union 944 { 945 //!< DWORD 42 946 struct 947 { 948 uint32_t : __CODEGEN_BITFIELD(0, 31); 949 }; 950 uint32_t Value; 951 } DW42; 952 union 953 { 954 //!< DWORD 43 955 struct 956 { 957 uint32_t : __CODEGEN_BITFIELD(0, 31); 958 }; 959 uint32_t Value; 960 } DW43; 961 union 962 { 963 //!< DWORD 44 964 struct 965 { 966 uint32_t : __CODEGEN_BITFIELD(0, 31); 967 }; 968 uint32_t Value; 969 } DW44; 970 union 971 { 972 //!< DWORD 45 973 struct 974 { 975 uint32_t : __CODEGEN_BITFIELD(0, 31); 976 }; 977 uint32_t Value; 978 } DW45; 979 union 980 { 981 //!< DWORD 46 982 struct 983 { 984 uint32_t : __CODEGEN_BITFIELD(0, 31); 985 }; 986 uint32_t Value; 987 } DW46; 988 union 989 { 990 //!< DWORD 47 991 struct 992 { 993 uint32_t : __CODEGEN_BITFIELD(0, 31); 994 }; 995 uint32_t Value; 996 } DW47; 997 union 998 { 999 //!< DWORD 48 1000 struct 1001 { 1002 uint32_t : __CODEGEN_BITFIELD(0, 31); 1003 }; 1004 uint32_t Value; 1005 } DW48; 1006 union 1007 { 1008 //!< DWORD 49 1009 struct 1010 { 1011 uint32_t : __CODEGEN_BITFIELD(0, 31); 1012 }; 1013 uint32_t Value; 1014 } DW49; 1015 union 1016 { 1017 //!< DWORD 50 1018 struct 1019 { 1020 uint32_t : __CODEGEN_BITFIELD(0, 31); 1021 }; 1022 uint32_t Value; 1023 } DW50; 1024 union 1025 { 1026 //!< DWORD 51 1027 struct 1028 { 1029 uint32_t : __CODEGEN_BITFIELD(0, 31); 1030 }; 1031 uint32_t Value; 1032 } DW51; 1033 union 1034 { 1035 //!< DWORD 52 1036 struct 1037 { 1038 uint32_t : __CODEGEN_BITFIELD(0, 31); 1039 }; 1040 uint32_t Value; 1041 } DW52; 1042 union 1043 { 1044 //!< DWORD 53 1045 struct 1046 { 1047 uint32_t : __CODEGEN_BITFIELD(0, 31); 1048 }; 1049 uint32_t Value; 1050 } DW53; 1051 union 1052 { 1053 //!< DWORD 54 1054 struct 1055 { 1056 uint32_t : __CODEGEN_BITFIELD(0, 31); 1057 }; 1058 uint32_t Value; 1059 } DW54; 1060 union 1061 { 1062 //!< DWORD 55 1063 struct 1064 { 1065 uint32_t : __CODEGEN_BITFIELD(0, 31); 1066 }; 1067 uint32_t Value; 1068 } DW55; 1069 union 1070 { 1071 //!< DWORD 56 1072 struct 1073 { 1074 uint32_t : __CODEGEN_BITFIELD(0, 31); 1075 }; 1076 uint32_t Value; 1077 } DW56; 1078 union 1079 { 1080 //!< DWORD 57 1081 struct 1082 { 1083 uint32_t : __CODEGEN_BITFIELD(0, 31); 1084 }; 1085 uint32_t Value; 1086 } DW57; 1087 union 1088 { 1089 //!< DWORD 58 1090 struct 1091 { 1092 uint32_t : __CODEGEN_BITFIELD(0, 31); 1093 }; 1094 uint32_t Value; 1095 } DW58; 1096 union 1097 { 1098 //!< DWORD 59 1099 struct 1100 { 1101 uint32_t : __CODEGEN_BITFIELD(0, 31); 1102 }; 1103 uint32_t Value; 1104 } DW59; 1105 union 1106 { 1107 //!< DWORD 60 1108 struct 1109 { 1110 uint32_t : __CODEGEN_BITFIELD(0, 31); 1111 }; 1112 uint32_t Value; 1113 } DW60; 1114 union 1115 { 1116 //!< DWORD 61 1117 struct 1118 { 1119 uint32_t Av1L0RefID0 : __CODEGEN_BITFIELD(0, 3); 1120 uint32_t Av1L1RefID0 : __CODEGEN_BITFIELD(4, 7); 1121 uint32_t Av1L0RefID1 : __CODEGEN_BITFIELD(8, 11); 1122 uint32_t Av1L1RefID1 : __CODEGEN_BITFIELD(12, 15); 1123 uint32_t Av1L0RefID2 : __CODEGEN_BITFIELD(16, 19); 1124 uint32_t Av1L1RefID2 : __CODEGEN_BITFIELD(20, 23); 1125 uint32_t Av1L0RefID3 : __CODEGEN_BITFIELD(24, 27); 1126 uint32_t Av1L1RefID3 : __CODEGEN_BITFIELD(28, 31); 1127 }; 1128 uint32_t Value; 1129 } DW61; 1130 //! \name Local enumerations 1131 1132 enum SUBOPB 1133 { 1134 SUBOPB_VDENCCMD2CMD = 9, //!< No additional details 1135 }; 1136 1137 enum SUBOPA 1138 { 1139 SUBOPA_UNNAMED0 = 0, //!< No additional details 1140 }; 1141 1142 enum OPCODE 1143 { 1144 OPCODE_VDENCPIPE = 1, //!< No additional details 1145 }; 1146 1147 enum PIPELINE 1148 { 1149 PIPELINE_MFXCOMMON = 2, //!< No additional details 1150 }; 1151 1152 enum COMMAND_TYPE 1153 { 1154 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1155 }; 1156 1157 //! \name Initializations 1158 1159 //! \brief Explicit member initialization function _VDENC_CMD2_CMD_VDENC_CMD2_CMD1160 _VDENC_CMD2_CMD() 1161 { 1162 MOS_ZeroMemory(this, sizeof(*this)); 1163 1164 DW0.Value = 0; 1165 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 1166 DW0.Subopb = SUBOPB_VDENCCMD2CMD; 1167 DW0.Subopa = SUBOPA_UNNAMED0; 1168 DW0.Opcode = OPCODE_VDENCPIPE; 1169 DW0.Pipeline = PIPELINE_MFXCOMMON; 1170 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1171 } 1172 1173 static const size_t dwSize = 62; 1174 static const size_t byteSize = 248; 1175 }; 1176 1177 struct _VDENC_CMD3_CMD 1178 { 1179 union 1180 { 1181 struct 1182 { 1183 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1184 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1185 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 1186 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 1187 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 1188 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1189 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1190 }; 1191 uint32_t Value; 1192 } DW0; 1193 union 1194 { 1195 struct 1196 { 1197 uint32_t VDENC_CMD3_DW1_BIT0 : __CODEGEN_BITFIELD(0, 7); 1198 uint32_t VDENC_CMD3_DW1_BIT8 : __CODEGEN_BITFIELD(8, 15); 1199 uint32_t VDENC_CMD3_DW1_BIT16 : __CODEGEN_BITFIELD(16, 23); 1200 uint32_t VDENC_CMD3_DW1_BIT24 : __CODEGEN_BITFIELD(24, 31); 1201 1202 uint32_t VDENC_CMD3_DW2_BIT0 : __CODEGEN_BITFIELD(0, 7); 1203 uint32_t VDENC_CMD3_DW2_BIT8 : __CODEGEN_BITFIELD(8, 15); 1204 uint32_t VDENC_CMD3_DW2_BIT16 : __CODEGEN_BITFIELD(16, 23); 1205 uint32_t VDENC_CMD3_DW2_BIT24 : __CODEGEN_BITFIELD(24, 31); 1206 }; 1207 uint32_t Value[2]; 1208 } DW1_2; 1209 uint8_t VDENC_CMD3_DW3_5[12]; 1210 uint8_t VDENC_CMD3_DW6_8[12]; 1211 union 1212 { 1213 struct 1214 { 1215 uint32_t VDENC_CMD3_DW9; 1216 }; 1217 uint32_t Value; 1218 } DW9; 1219 union 1220 { 1221 struct 1222 { 1223 uint32_t VDENC_CMD3_DW10_BIT0 : __CODEGEN_BITFIELD(0, 15); 1224 uint32_t VDENC_CMD3_DW10_BIT16 : __CODEGEN_BITFIELD(16, 23); 1225 uint32_t VDENC_CMD3_DW10_BIT24 : __CODEGEN_BITFIELD(24, 31); 1226 }; 1227 uint32_t Value; 1228 } DW10; 1229 union 1230 { 1231 struct 1232 { 1233 uint32_t VDENC_CMD3_DW11; 1234 }; 1235 uint32_t Value; 1236 } DW11; 1237 union 1238 { 1239 struct 1240 { 1241 uint32_t VDENC_CMD3_DW12_BIT0 : __CODEGEN_BITFIELD(0, 7); 1242 uint32_t VDENC_CMD3_DW12_BIT8 : __CODEGEN_BITFIELD(8, 15); 1243 uint32_t VDENC_CMD3_DW12_BIT16 : __CODEGEN_BITFIELD(16, 23); 1244 uint32_t VDENC_CMD3_DW12_BIT24 : __CODEGEN_BITFIELD(24, 31); 1245 }; 1246 uint32_t Value; 1247 } DW12; 1248 union 1249 { 1250 struct 1251 { 1252 uint32_t VDENC_CMD3_DW13_BIT0 : __CODEGEN_BITFIELD(0, 7); 1253 uint32_t VDENC_CMD3_DW13_BIT8 : __CODEGEN_BITFIELD(8, 15); 1254 uint32_t VDENC_CMD3_DW13_BIT16 : __CODEGEN_BITFIELD(16, 23); 1255 uint32_t VDENC_CMD3_DW13_BIT24 : __CODEGEN_BITFIELD(24, 31); 1256 }; 1257 uint32_t Value; 1258 } DW13; 1259 union 1260 { 1261 struct 1262 { 1263 uint32_t VDENC_CMD3_DW14_BIT0 : __CODEGEN_BITFIELD(0, 7); 1264 uint32_t VDENC_CMD3_DW14_BIT8 : __CODEGEN_BITFIELD(8, 15); 1265 uint32_t VDENC_CMD3_DW14_BIT16 : __CODEGEN_BITFIELD(16, 23); 1266 uint32_t VDENC_CMD3_DW14_BIT24 : __CODEGEN_BITFIELD(24, 31); 1267 }; 1268 uint32_t Value; 1269 } DW14; 1270 union 1271 { 1272 struct 1273 { 1274 uint32_t VDENC_CMD3_DW15_BIT0 : __CODEGEN_BITFIELD(0, 7); 1275 uint32_t VDENC_CMD3_DW15_BIT8 : __CODEGEN_BITFIELD(8, 15); 1276 uint32_t VDENC_CMD3_DW15_BIT16 : __CODEGEN_BITFIELD(16, 23); 1277 uint32_t VDENC_CMD3_DW15_BIT24 : __CODEGEN_BITFIELD(24, 31); 1278 }; 1279 uint32_t Value; 1280 } DW15; 1281 union 1282 { 1283 struct 1284 { 1285 uint32_t VDENC_CMD3_DW16_BIT0 : __CODEGEN_BITFIELD(0, 15); 1286 uint32_t VDENC_CMD3_DW16_BIT16 : __CODEGEN_BITFIELD(16, 23); 1287 uint32_t VDENC_CMD3_DW16_BIT24 : __CODEGEN_BITFIELD(24, 31); 1288 }; 1289 uint32_t Value; 1290 } DW16; 1291 union 1292 { 1293 struct 1294 { 1295 uint32_t VDENC_CMD3_DW17_BIT0 : __CODEGEN_BITFIELD(0, 7); 1296 uint32_t VDENC_CMD3_DW17_BIT8 : __CODEGEN_BITFIELD(8, 15); 1297 uint32_t VDENC_CMD3_DW17_BIT16 : __CODEGEN_BITFIELD(16, 23); 1298 uint32_t VDENC_CMD3_DW17_BIT24 : __CODEGEN_BITFIELD(24, 31); 1299 }; 1300 uint32_t Value; 1301 } DW17; 1302 union 1303 { 1304 struct 1305 { 1306 uint32_t VDENC_CMD3_DW18; 1307 }; 1308 uint32_t Value; 1309 } DW18; 1310 union 1311 { 1312 struct 1313 { 1314 uint32_t VDENC_CMD3_DW19_BIT0 : __CODEGEN_BITFIELD(0, 7); 1315 uint32_t VDENC_CMD3_DW19_BIT8 : __CODEGEN_BITFIELD(8, 15); 1316 uint32_t VDENC_CMD3_DW19_BIT16 : __CODEGEN_BITFIELD(16, 23); 1317 uint32_t VDENC_CMD3_DW19_BIT24 : __CODEGEN_BITFIELD(24, 31); 1318 }; 1319 uint32_t Value; 1320 } DW19; 1321 union 1322 { 1323 struct 1324 { 1325 uint32_t VDENC_CMD3_DW20_BIT0 : __CODEGEN_BITFIELD(0, 7); 1326 uint32_t VDENC_CMD3_DW20_BIT8 : __CODEGEN_BITFIELD(8, 15); 1327 uint32_t VDENC_CMD3_DW20_BIT16 : __CODEGEN_BITFIELD(16, 31); 1328 }; 1329 uint32_t Value; 1330 } DW20; 1331 union 1332 { 1333 struct 1334 { 1335 uint32_t VDENC_CMD3_DW21_BIT0 : __CODEGEN_BITFIELD(0, 7); 1336 uint32_t VDENC_CMD3_DW21_BIT8 : __CODEGEN_BITFIELD(8, 15); 1337 uint32_t VDENC_CMD3_DW21_BIT16 : __CODEGEN_BITFIELD(16, 31); 1338 }; 1339 uint32_t Value; 1340 } DW21; 1341 union 1342 { 1343 struct 1344 { 1345 uint32_t VDENC_CMD3_DW22_BIT0 : __CODEGEN_BITFIELD(0, 15); 1346 uint32_t VDENC_CMD3_DW22_BIT16 : __CODEGEN_BITFIELD(16, 24); 1347 uint32_t VDENC_CMD3_DW22_BIT25 : __CODEGEN_BITFIELD(25, 31); 1348 }; 1349 uint32_t Value; 1350 } DW22; 1351 1352 //! \name Local enumerations 1353 1354 enum SUBOPB 1355 { 1356 SUBOPB_VDENCAVCCOSTSSTATE = 10, 1357 }; 1358 1359 enum SUBOPA 1360 { 1361 SUBOPA_UNNAMED0 = 0, 1362 }; 1363 1364 enum OPCODE 1365 { 1366 OPCODE_VDENCPIPE = 1, 1367 }; 1368 1369 enum PIPELINE 1370 { 1371 PIPELINE_MFXCOMMON = 2, 1372 }; 1373 1374 enum COMMAND_TYPE 1375 { 1376 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, 1377 }; 1378 1379 //! \name Initializations 1380 1381 //! \brief Explicit member initialization function _VDENC_CMD3_CMD_VDENC_CMD3_CMD1382 _VDENC_CMD3_CMD() 1383 { 1384 MOS_ZeroMemory(this, sizeof(*this)); 1385 1386 DW0.Value = 0x708a0015; 1387 } 1388 1389 static const size_t dwSize = 23; 1390 static const size_t byteSize = 92; 1391 }; 1392 1393 #define VDENC_AVC_IMG_STATE_CMD_DW1 \ 1394 union \ 1395 { \ 1396 struct \ 1397 { \ 1398 uint32_t Reserved871 : __CODEGEN_BITFIELD(0, 1); \ 1399 uint32_t PictureType : __CODEGEN_BITFIELD(2, 3); \ 1400 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD(4, 4); \ 1401 uint32_t colloc_mv_wr_en : __CODEGEN_BITFIELD(5, 5); \ 1402 uint32_t SubpelMode : __CODEGEN_BITFIELD(6, 7); \ 1403 uint32_t Reserved872 : __CODEGEN_BITFIELD(8, 31); \ 1404 }; \ 1405 uint32_t Value; \ 1406 } 1407 1408 #define VDENC_AVC_IMG_STATE_CMD_DW2 \ 1409 union \ 1410 { \ 1411 struct \ 1412 { \ 1413 uint32_t Reserved873 : __CODEGEN_BITFIELD(0, 12); \ 1414 uint32_t colloc_mv_rd_en : __CODEGEN_BITFIELD(13, 13); \ 1415 uint32_t Reserved874 : __CODEGEN_BITFIELD(14, 17); \ 1416 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(18, 23); \ 1417 uint32_t Reserved875 : __CODEGEN_BITFIELD(24, 31); \ 1418 }; \ 1419 uint32_t Value; \ 1420 } 1421 1422 #define VDENC_AVC_IMG_STATE_CMD_DW4 \ 1423 union \ 1424 { \ 1425 struct \ 1426 { \ 1427 uint32_t Reserved877; \ 1428 }; \ 1429 uint32_t Value; \ 1430 } 1431 1432 #define VDENC_AVC_IMG_STATE_CMD_DW5 \ 1433 union \ 1434 { \ 1435 struct \ 1436 { \ 1437 uint32_t FwdRefIdx0ReferencePicture : __CODEGEN_BITFIELD(0, 3); \ 1438 uint32_t BwdRefIdx0ReferencePicture : __CODEGEN_BITFIELD(4, 7); \ 1439 uint32_t FwdRefIdx1ReferencePicture : __CODEGEN_BITFIELD(8, 11); \ 1440 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15); \ 1441 uint32_t FwdRefIdx2ReferencePicture : __CODEGEN_BITFIELD(16, 19); \ 1442 uint32_t NumberOfL0ReferencesMinusOne : __CODEGEN_BITFIELD(20, 23); \ 1443 uint32_t NumberOfL1ReferencesMinusOne : __CODEGEN_BITFIELD(24, 27); \ 1444 uint32_t Reserved188 : __CODEGEN_BITFIELD(28, 31); \ 1445 }; \ 1446 uint32_t Value; \ 1447 } 1448 1449 #define VDENC_AVC_IMG_STATE_CMD_DW7 \ 1450 union \ 1451 { \ 1452 struct \ 1453 { \ 1454 uint32_t Reserved189; \ 1455 }; \ 1456 uint32_t Value; \ 1457 } 1458 1459 #define VDENC_AVC_IMG_STATE_CMD_DW8 \ 1460 union \ 1461 { \ 1462 struct \ 1463 { \ 1464 uint32_t Reserved190; \ 1465 }; \ 1466 uint32_t Value; \ 1467 } 1468 1469 #define VDENC_AVC_IMG_STATE_CMD_DW9 \ 1470 union \ 1471 { \ 1472 struct \ 1473 { \ 1474 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD(0, 3); \ 1475 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD(4, 7); \ 1476 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD(8, 11); \ 1477 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15); \ 1478 uint32_t Reserved316 : __CODEGEN_BITFIELD(16, 31); \ 1479 }; \ 1480 uint32_t Value; \ 1481 } 1482 1483 #define VDENC_AVC_IMG_STATE_CMD_DW10 \ 1484 union \ 1485 { \ 1486 struct \ 1487 { \ 1488 uint32_t Reserved192; \ 1489 }; \ 1490 uint32_t Value; \ 1491 } 1492 1493 #define VDENC_AVC_IMG_STATE_CMD_DW11 \ 1494 union \ 1495 { \ 1496 struct \ 1497 { \ 1498 uint32_t Reserved193; \ 1499 }; \ 1500 uint32_t Value; \ 1501 } 1502 1503 #define VDENC_AVC_IMG_STATE_CMD_DW12 \ 1504 union \ 1505 { \ 1506 struct \ 1507 { \ 1508 uint32_t MinQp : __CODEGEN_BITFIELD(0, 7); \ 1509 uint32_t MaxQp : __CODEGEN_BITFIELD(8, 15); \ 1510 uint32_t Reserved412 : __CODEGEN_BITFIELD(16, 31); \ 1511 }; \ 1512 uint32_t Value; \ 1513 } 1514 1515 #define VDENC_AVC_IMG_STATE_CMD_DW13 \ 1516 union \ 1517 { \ 1518 struct \ 1519 { \ 1520 uint32_t RoiEnable : __CODEGEN_BITFIELD(0, 0); \ 1521 uint32_t Reserved421 : __CODEGEN_BITFIELD(1, 2); \ 1522 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD(3, 3); \ 1523 uint32_t Reserved422 : __CODEGEN_BITFIELD(4, 4); \ 1524 uint32_t MbLevelDeltaQpEnable : __CODEGEN_BITFIELD(5, 5); \ 1525 uint32_t Reserved424 : __CODEGEN_BITFIELD(6, 9); \ 1526 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10); \ 1527 uint32_t Reserved427 : __CODEGEN_BITFIELD(11, 31); \ 1528 }; \ 1529 uint32_t Value; \ 1530 } 1531 1532 #define VDENC_AVC_IMG_STATE_CMD_DW14 \ 1533 union \ 1534 { \ 1535 struct \ 1536 { \ 1537 uint32_t QpPrimeY : __CODEGEN_BITFIELD(0, 7); \ 1538 uint32_t Reserved467 : __CODEGEN_BITFIELD(8, 18); \ 1539 uint32_t TrellisQuantEn : __CODEGEN_BITFIELD(19, 19); \ 1540 uint32_t Reserved468 : __CODEGEN_BITFIELD(20, 31); \ 1541 }; \ 1542 uint32_t Value; \ 1543 } 1544 1545 #define VDENC_AVC_IMG_STATE_CMD_DW15 \ 1546 union \ 1547 { \ 1548 struct \ 1549 { \ 1550 uint32_t Reserved873 : __CODEGEN_BITFIELD(0, 7); \ 1551 uint32_t PocNumberForCurrentPicture : __CODEGEN_BITFIELD(8, 15); \ 1552 uint32_t Reserved874 : __CODEGEN_BITFIELD(16, 31); \ 1553 }; \ 1554 uint32_t Value; \ 1555 } 1556 1557 #define VDENC_AVC_IMG_STATE_CMD_DW16 \ 1558 union \ 1559 { \ 1560 struct \ 1561 { \ 1562 uint32_t Reserved875 : __CODEGEN_BITFIELD(0, 7); \ 1563 uint32_t PocNumberForFwdRef0 : __CODEGEN_BITFIELD(8, 15); \ 1564 uint32_t Reserved876 : __CODEGEN_BITFIELD(16, 31); \ 1565 }; \ 1566 uint32_t Value; \ 1567 } 1568 1569 #define VDENC_AVC_IMG_STATE_CMD_DW17 \ 1570 union \ 1571 { \ 1572 struct \ 1573 { \ 1574 uint32_t Reserved877 : __CODEGEN_BITFIELD(0, 7); \ 1575 uint32_t PocNumberForFwdRef1 : __CODEGEN_BITFIELD(8, 15); \ 1576 uint32_t Reserved878 : __CODEGEN_BITFIELD(16, 31); \ 1577 }; \ 1578 uint32_t Value; \ 1579 } 1580 1581 #define VDENC_AVC_IMG_STATE_CMD_DW18 \ 1582 union \ 1583 { \ 1584 struct \ 1585 { \ 1586 uint32_t Reserved879 : __CODEGEN_BITFIELD(0, 7); \ 1587 uint32_t PocNumberForFwdRef2 : __CODEGEN_BITFIELD(8, 15); \ 1588 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31); \ 1589 }; \ 1590 uint32_t Value; \ 1591 } 1592 1593 #define VDENC_AVC_IMG_STATE_CMD_DW19 \ 1594 union \ 1595 { \ 1596 struct \ 1597 { \ 1598 uint32_t Reserved881 : __CODEGEN_BITFIELD(0, 7); \ 1599 uint32_t PocNumberForBwdRef0 : __CODEGEN_BITFIELD(8, 15); \ 1600 uint32_t Reserved882 : __CODEGEN_BITFIELD(16, 31); \ 1601 }; \ 1602 uint32_t Value; \ 1603 } 1604 1605 #endif 1606 1607 struct Cmd 1608 { 1609 public: 1610 //! \brief VDENC_64B_Aligned_Lower_Address 1611 //! \details 1612 //! 1613 //! 1614 struct VDENC_64B_Aligned_Lower_Address_CMD 1615 { 1616 union 1617 { 1618 //!< DWORD 0 1619 struct 1620 { 1621 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1622 uint32_t Address : __CODEGEN_BITFIELD(6, 31); //!< Address 1623 }; 1624 uint32_t Value; 1625 } DW0; 1626 1627 //! \name Local enumerations 1628 1629 //! \name Initializations 1630 1631 //! \brief Explicit member initialization function VDENC_64B_Aligned_Lower_Address_CMDCmd::VDENC_64B_Aligned_Lower_Address_CMD1632 VDENC_64B_Aligned_Lower_Address_CMD() 1633 { 1634 DW0.Value = 0; 1635 } 1636 1637 static const size_t dwSize = 1; 1638 static const size_t byteSize = 4; 1639 }; 1640 1641 //! 1642 //! \brief VDENC_64B_Aligned_Upper_Address 1643 //! \details 1644 //! 1645 //! 1646 struct VDENC_64B_Aligned_Upper_Address_CMD 1647 { 1648 union 1649 { 1650 //!< DWORD 0 1651 struct 1652 { 1653 uint32_t AddressUpperDword : __CODEGEN_BITFIELD(0, 15); //!< Address Upper DWord 1654 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1655 }; 1656 uint32_t Value; 1657 } DW0; 1658 1659 //! \name Local enumerations 1660 1661 //! \name Initializations 1662 1663 //! \brief Explicit member initialization function VDENC_64B_Aligned_Upper_Address_CMDCmd::VDENC_64B_Aligned_Upper_Address_CMD1664 VDENC_64B_Aligned_Upper_Address_CMD() 1665 { 1666 DW0.Value = 0; 1667 } 1668 1669 static const size_t dwSize = 1; 1670 static const size_t byteSize = 4; 1671 }; 1672 1673 //! 1674 //! \brief VDENC_Surface_Control_Bits 1675 //! \details 1676 //! 1677 //! 1678 struct VDENC_Surface_Control_Bits_CMD 1679 { 1680 union 1681 { 1682 //!< DWORD 0 1683 struct 1684 { 1685 uint32_t VDENC_Surface_Control_Bits_DW0_BIT0 : __CODEGEN_BITFIELD(0, 0); //!< 1686 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(1, 6); //!< Index to Memory Object Control State (MOCS) Tables: 1687 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< ARBITRATION_PRIORITY_CONTROL 1688 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< MEMORY_COMPRESSION_ENABLE 1689 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10); //!< Compression Type 1690 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 1691 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12); //!< CACHE_SELECT 1692 uint32_t Reserved13 : __CODEGEN_BITFIELD(13, 14); //!< Reserved 1693 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1694 uint32_t CompressionFormat : __CODEGEN_BITFIELD(16, 20); //!< Compression Format 1695 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 1696 }; 1697 uint32_t Value; 1698 } DW0; 1699 1700 //! \name Local enumerations 1701 1702 //! \brief ARBITRATION_PRIORITY_CONTROL 1703 //! \details 1704 //! This field controls the priority of arbitration used in the GAC/GAM 1705 //! pipeline for this surface. 1706 enum ARBITRATION_PRIORITY_CONTROL 1707 { 1708 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1709 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1710 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1711 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1712 }; 1713 1714 //! \brief MEMORY_COMPRESSION_ENABLE 1715 //! \details 1716 //! Memory compression will be attempted for this surface. 1717 enum MEMORY_COMPRESSION_ENABLE 1718 { 1719 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 1720 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 1721 }; 1722 1723 //! \brief MEMORY_COMPRESSION_MODE 1724 //! \details 1725 //! Distinguishes Vertical from Horizontal compression. Please refer to 1726 //! vol1a <b>Memory Data</b>. 1727 enum MEMORY_COMPRESSION_MODE 1728 { 1729 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 1730 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 1731 }; 1732 1733 //! \brief CACHE_SELECT 1734 //! \details 1735 //! This field controls if the Row Store is going to store inside Media 1736 //! Cache (rowstore cache) or to LLC. 1737 enum CACHE_SELECT 1738 { 1739 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 1740 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 1741 }; 1742 1743 //! \brief TILED_RESOURCE_MODE 1744 //! \details 1745 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 1746 enum TILED_RESOURCE_MODE 1747 { 1748 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 1749 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1750 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1751 }; 1752 1753 //! \name Initializations 1754 1755 //! \brief Explicit member initialization function VDENC_Surface_Control_Bits_CMDCmd::VDENC_Surface_Control_Bits_CMD1756 VDENC_Surface_Control_Bits_CMD() 1757 { 1758 DW0.Value = 0; 1759 DW0.ArbitrationPriorityControl = ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY; 1760 DW0.MemoryCompressionEnable = MEMORY_COMPRESSION_ENABLE_DISABLE; 1761 DW0.CacheSelect = CACHE_SELECT_UNNAMED0; 1762 } 1763 1764 static const size_t dwSize = 1; 1765 static const size_t byteSize = 4; 1766 }; 1767 1768 //! 1769 //! \brief VDENC_Sub_Mb_Pred_Mode 1770 //! \details 1771 //! 1772 //! 1773 struct VDENC_Sub_Mb_Pred_Mode_CMD 1774 { 1775 union 1776 { 1777 //!< WORD 0 1778 struct 1779 { 1780 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD(0, 1); //!< SubMbPredMode[0] 1781 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD(2, 3); //!< SubMbPredMode[1] 1782 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD(4, 5); //!< SubMbPredMode[2] 1783 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD(6, 7); //!< SubMbPredMode[3] 1784 }; 1785 uint8_t Value; 1786 } DW0; 1787 1788 //! \name Local enumerations 1789 1790 //! \name Initializations 1791 1792 //! \brief Explicit member initialization function VDENC_Sub_Mb_Pred_Mode_CMDCmd::VDENC_Sub_Mb_Pred_Mode_CMD1793 VDENC_Sub_Mb_Pred_Mode_CMD() 1794 { 1795 DW0.Value = 0; 1796 } 1797 1798 static const size_t dwSize = 0; 1799 static const size_t byteSize = 1; 1800 }; 1801 1802 //! 1803 //! \brief VDENC_Block_8x8_4 1804 //! \details 1805 //! 1806 //! 1807 struct VDENC_Block_8x8_4_CMD 1808 { 1809 union 1810 { 1811 //!< WORD 0 1812 struct 1813 { 1814 uint16_t Block8X80 : __CODEGEN_BITFIELD(0, 3); //!< Block8x8[0] 1815 uint16_t Block8X81 : __CODEGEN_BITFIELD(4, 7); //!< Block8x8[1] 1816 uint16_t Block8X82 : __CODEGEN_BITFIELD(8, 11); //!< Block8x8[2] 1817 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15); //!< Block8x8[3] 1818 }; 1819 uint16_t Value; 1820 } DW0; 1821 1822 //! \name Local enumerations 1823 1824 //! \name Initializations 1825 1826 //! \brief Explicit member initialization function VDENC_Block_8x8_4_CMDCmd::VDENC_Block_8x8_4_CMD1827 VDENC_Block_8x8_4_CMD() 1828 { 1829 DW0.Value = 0; 1830 } 1831 1832 static const size_t dwSize = 0; 1833 static const size_t byteSize = 2; 1834 }; 1835 1836 //! 1837 //! \brief VDENC_Delta_MV_XY 1838 //! \details 1839 //! 1840 //! 1841 //! Calculates the difference between the actual MV for the Sub Macroblock 1842 //! and the predicted MV based on the availability of the neighbors. 1843 //! 1844 //! This is calculated and populated for Inter frames only. In case of an 1845 //! Intra MB in Inter frames, this value should be 0. 1846 //! 1847 struct VDENC_Delta_MV_XY_CMD 1848 { 1849 union 1850 { 1851 //!< DWORD 0 1852 struct 1853 { 1854 uint32_t X0 : __CODEGEN_BITFIELD(0, 15); //!< X0 1855 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31); //!< Y0 1856 }; 1857 uint32_t Value; 1858 } DW0; 1859 union 1860 { 1861 //!< DWORD 1 1862 struct 1863 { 1864 uint32_t X1 : __CODEGEN_BITFIELD(0, 15); //!< X1 1865 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31); //!< Y1 1866 }; 1867 uint32_t Value; 1868 } DW1; 1869 union 1870 { 1871 //!< DWORD 2 1872 struct 1873 { 1874 uint32_t X2 : __CODEGEN_BITFIELD(0, 15); //!< X2 1875 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31); //!< Y2 1876 }; 1877 uint32_t Value; 1878 } DW2; 1879 union 1880 { 1881 //!< DWORD 3 1882 struct 1883 { 1884 uint32_t X3 : __CODEGEN_BITFIELD(0, 15); //!< X3 1885 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31); //!< Y3 1886 }; 1887 uint32_t Value; 1888 } DW3; 1889 1890 //! \name Local enumerations 1891 1892 //! \brief X0 1893 //! \details 1894 enum X0 1895 { 1896 X0_UNNAMED0 = 0, //!< No additional details 1897 }; 1898 1899 //! \brief Y0 1900 //! \details 1901 enum Y0 1902 { 1903 Y0_UNNAMED0 = 0, //!< No additional details 1904 }; 1905 1906 //! \brief X1 1907 //! \details 1908 enum X1 1909 { 1910 X1_UNNAMED0 = 0, //!< No additional details 1911 }; 1912 1913 //! \brief Y1 1914 //! \details 1915 enum Y1 1916 { 1917 Y1_UNNAMED0 = 0, //!< No additional details 1918 }; 1919 1920 //! \brief X2 1921 //! \details 1922 enum X2 1923 { 1924 X2_UNNAMED0 = 0, //!< No additional details 1925 }; 1926 1927 //! \brief Y2 1928 //! \details 1929 enum Y2 1930 { 1931 Y2_UNNAMED0 = 0, //!< No additional details 1932 }; 1933 1934 //! \brief X3 1935 //! \details 1936 enum X3 1937 { 1938 X3_UNNAMED0 = 0, //!< No additional details 1939 }; 1940 1941 //! \brief Y3 1942 //! \details 1943 enum Y3 1944 { 1945 Y3_UNNAMED0 = 0, //!< No additional details 1946 }; 1947 1948 //! \name Initializations 1949 1950 //! \brief Explicit member initialization function VDENC_Delta_MV_XY_CMDCmd::VDENC_Delta_MV_XY_CMD1951 VDENC_Delta_MV_XY_CMD() 1952 { 1953 MOS_ZeroMemory(this, sizeof(*this)); 1954 1955 DW0.X0 = X0_UNNAMED0; 1956 DW0.Y0 = Y0_UNNAMED0; 1957 1958 DW1.X1 = X1_UNNAMED0; 1959 DW1.Y1 = Y1_UNNAMED0; 1960 1961 DW2.X2 = X2_UNNAMED0; 1962 DW2.Y2 = Y2_UNNAMED0; 1963 1964 DW3.X3 = X3_UNNAMED0; 1965 DW3.Y3 = Y3_UNNAMED0; 1966 } 1967 1968 static const size_t dwSize = 4; 1969 static const size_t byteSize = 16; 1970 }; 1971 1972 //! 1973 //! \brief VDENC_Colocated_MV_Picture 1974 //! \details 1975 //! 1976 //! 1977 struct VDENC_Colocated_MV_Picture_CMD 1978 { 1979 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 1980 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 1981 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 1982 1983 //! \name Local enumerations 1984 1985 //! \name Initializations 1986 1987 //! \brief Explicit member initialization function VDENC_Colocated_MV_Picture_CMDCmd::VDENC_Colocated_MV_Picture_CMD1988 VDENC_Colocated_MV_Picture_CMD() 1989 { 1990 } 1991 1992 static const size_t dwSize = 3; 1993 static const size_t byteSize = 12; 1994 }; 1995 1996 //! 1997 //! \brief VDENC_Down_Scaled_Reference_Picture 1998 //! \details 1999 //! 2000 //! 2001 struct VDENC_Down_Scaled_Reference_Picture_CMD 2002 { 2003 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2004 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2005 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2006 2007 //! \name Local enumerations 2008 2009 //! \name Initializations 2010 2011 //! \brief Explicit member initialization function VDENC_Down_Scaled_Reference_Picture_CMDCmd::VDENC_Down_Scaled_Reference_Picture_CMD2012 VDENC_Down_Scaled_Reference_Picture_CMD() 2013 { 2014 } 2015 2016 static const size_t dwSize = 3; 2017 static const size_t byteSize = 12; 2018 }; 2019 2020 //! 2021 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 2022 //! \details 2023 //! 2024 //! 2025 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 2026 { 2027 union 2028 { 2029 //!< DWORD 0 2030 struct 2031 { 2032 uint32_t SumSadHaarForBestMbChoice; //!< Sum sad\haar for best MB choice 2033 }; 2034 uint32_t Value; 2035 } DW0; 2036 union 2037 { 2038 //!< DWORD 1 2039 struct 2040 { 2041 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD(0, 15); //!< Intra iso 16x16 MB count 2042 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31); //!< Intra MB count 2043 }; 2044 uint32_t Value; 2045 } DW1; 2046 union 2047 { 2048 //!< DWORD 2 2049 struct 2050 { 2051 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD(0, 15); //!< Intra iso 4x4 MB count 2052 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31); //!< Intra iso 8x8 MB count 2053 }; 2054 uint32_t Value; 2055 } DW2; 2056 union 2057 { 2058 //!< DWORD 3 2059 struct 2060 { 2061 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD(0, 15); //!< segment map count 0 2062 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31); //!< segment map count 1 2063 }; 2064 uint32_t Value; 2065 } DW3; 2066 union 2067 { 2068 //!< DWORD 4 2069 struct 2070 { 2071 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD(0, 15); //!< segment map count 2 2072 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31); //!< segment map count 3 2073 }; 2074 uint32_t Value; 2075 } DW4; 2076 2077 uint32_t Reserved160[12]; //!< Reserved 2078 2079 union 2080 { 2081 //!< DWORD 17 2082 struct 2083 { 2084 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation; //!< Sum sad\haar for best MB choice bottom half population 2085 }; 2086 uint32_t Value; 2087 } DW17; 2088 union 2089 { 2090 //!< DWORD 18 2091 struct 2092 { 2093 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation; //!< Sum sad\haar for best MB choice top half population 2094 }; 2095 uint32_t Value; 2096 } DW18; 2097 union 2098 { 2099 //!< DWORD 19 2100 struct 2101 { 2102 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD(0, 15); //!< Sum top half population occurrences 2103 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31); //!< Sum bottom half population occurrences 2104 }; 2105 uint32_t Value; 2106 } DW19; 2107 2108 //! \name Local enumerations 2109 2110 //! \name Initializations 2111 2112 //! \brief Explicit member initialization function VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMDCmd::VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD2113 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD() 2114 { 2115 MOS_ZeroMemory(this, sizeof(*this)); 2116 } 2117 2118 static const size_t dwSize = 20; 2119 static const size_t byteSize = 80; 2120 }; 2121 2122 //! 2123 //! \brief VDENC_Mode_StreamOut_Data 2124 //! \details 2125 //! 2126 //! 2127 struct VDENC_Mode_StreamOut_Data_CMD 2128 { 2129 union 2130 { 2131 //!< DWORD 0 2132 struct 2133 { 2134 uint32_t MbX : __CODEGEN_BITFIELD(0, 7); //!< MB.X 2135 uint32_t MbY : __CODEGEN_BITFIELD(8, 15); //!< MB.Y 2136 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31); //!< Minimal Distortion 2137 }; 2138 uint32_t Value; 2139 } DW0; 2140 union 2141 { 2142 //!< DWORD 1 2143 struct 2144 { 2145 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD(0, 15); //!< SkipRawDistortion 2146 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31); //!< InterRawDistortion 2147 }; 2148 uint32_t Value; 2149 } DW1; 2150 union 2151 { 2152 //!< DWORD 2 2153 struct 2154 { 2155 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD(0, 15); //!< BestIntraRawDistortion 2156 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17); //!< INTERMBMODECHROMA_PREDICTION_MODE 2157 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19); //!< INTRAMBMODE 2158 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20); //!< INTRAMBFLAG 2159 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21); //!< LASTMBFLAG 2160 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22); //!< Coefficient Clamp Occurred 2161 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23); //!< Conformance Violation 2162 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31); //!< SubMbPredMode 2163 }; 2164 uint32_t Value; 2165 } DW2; 2166 union 2167 { 2168 //!< DWORD 3 2169 struct 2170 { 2171 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD(0, 15); //!< LumaIntraMode[0] 2172 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31); //!< LumaIntraMode[1] 2173 }; 2174 uint32_t Value; 2175 } DW3; 2176 union 2177 { 2178 //!< DWORD 4 2179 struct 2180 { 2181 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD(0, 15); //!< LumaIntraMode[2] 2182 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31); //!< LumaIntraMode[3] 2183 }; 2184 uint32_t Value; 2185 } DW4; 2186 VDENC_Delta_MV_XY_CMD DeltaMv0; //!< Delta MV0 2187 VDENC_Delta_MV_XY_CMD DeltaMv1; //!< Delta MV1 2188 union 2189 { 2190 //!< DWORD 13 2191 struct 2192 { 2193 uint32_t FwdRefids : __CODEGEN_BITFIELD(0, 15); //!< FWD REFIDs 2194 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31); //!< BWD REFIDs 2195 }; 2196 uint32_t Value; 2197 } DW13; 2198 union 2199 { 2200 //!< DWORD 14 2201 struct 2202 { 2203 uint32_t QpY : __CODEGEN_BITFIELD(0, 5); //!< QP_y 2204 uint32_t MbBitCount : __CODEGEN_BITFIELD(6, 18); //!< MB_Bit_Count 2205 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31); //!< MB_Header_Count 2206 }; 2207 uint32_t Value; 2208 } DW14; 2209 union 2210 { 2211 //!< DWORD 15 2212 struct 2213 { 2214 uint32_t MbType : __CODEGEN_BITFIELD(0, 4); //!< MB Type 2215 uint32_t BlockCbp : __CODEGEN_BITFIELD(5, 30); //!< Block CBP 2216 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31); //!< SkipMbFlag 2217 }; 2218 uint32_t Value; 2219 } DW15; 2220 2221 //! \name Local enumerations 2222 2223 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 2224 //! \details 2225 //! This field indicates the InterMB Parition type for Inter MB. 2226 //! <br>OR</br> 2227 //! This field indicates Chroma Prediction Mode for Intra MB. 2228 enum INTERMBMODECHROMA_PREDICTION_MODE 2229 { 2230 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 2231 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 2232 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 2233 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 2234 }; 2235 2236 //! \brief INTRAMBMODE 2237 //! \details 2238 //! This field indicates the Best Intra Partition. 2239 enum INTRAMBMODE 2240 { 2241 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 2242 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 2243 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 2244 }; 2245 2246 //! \brief INTRAMBFLAG 2247 //! \details 2248 //! This field specifies whether the current macroblock is an Intra (I) 2249 //! macroblock. 2250 enum INTRAMBFLAG 2251 { 2252 INTRAMBFLAG_INTER = 0, //!< inter macroblock 2253 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 2254 }; 2255 2256 enum LASTMBFLAG 2257 { 2258 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 2259 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 2260 }; 2261 2262 //! \name Initializations 2263 2264 //! \brief Explicit member initialization function VDENC_Mode_StreamOut_Data_CMDCmd::VDENC_Mode_StreamOut_Data_CMD2265 VDENC_Mode_StreamOut_Data_CMD() 2266 { 2267 MOS_ZeroMemory(this, sizeof(*this)); 2268 2269 DW2.IntermbmodeChromaPredictionMode = INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0; 2270 DW2.Intrambmode = INTRAMBMODE_UNNAMED0; 2271 DW2.Intrambflag = INTRAMBFLAG_INTER; 2272 DW2.Lastmbflag = LASTMBFLAG_NOTLAST; 2273 } 2274 2275 static const size_t dwSize = 16; 2276 static const size_t byteSize = 64; 2277 }; 2278 2279 //! 2280 //! \brief VDENC_Original_Uncompressed_Picture 2281 //! \details 2282 //! 2283 //! 2284 struct VDENC_Original_Uncompressed_Picture_CMD 2285 { 2286 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2287 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2288 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2289 2290 //! \name Local enumerations 2291 2292 //! \name Initializations 2293 2294 //! \brief Explicit member initialization function VDENC_Original_Uncompressed_Picture_CMDCmd::VDENC_Original_Uncompressed_Picture_CMD2295 VDENC_Original_Uncompressed_Picture_CMD() 2296 { 2297 } 2298 2299 static const size_t dwSize = 3; 2300 static const size_t byteSize = 12; 2301 }; 2302 2303 //! 2304 //! \brief VDENC_Reference_Picture 2305 //! \details 2306 //! 2307 //! 2308 struct VDENC_Reference_Picture_CMD 2309 { 2310 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2311 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2312 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2313 2314 //! \name Local enumerations 2315 2316 //! \name Initializations 2317 2318 //! \brief Explicit member initialization function VDENC_Reference_Picture_CMDCmd::VDENC_Reference_Picture_CMD2319 VDENC_Reference_Picture_CMD() 2320 { 2321 } 2322 2323 static const size_t dwSize = 3; 2324 static const size_t byteSize = 12; 2325 }; 2326 2327 //! 2328 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 2329 //! \details 2330 //! 2331 //! 2332 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 2333 { 2334 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2335 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2336 VDENC_Surface_Control_Bits_CMD BufferPictureFields; //!< Buffer Picture Fields 2337 2338 //! \name Local enumerations 2339 2340 //! \name Initializations 2341 2342 //! \brief Explicit member initialization function VDENC_Row_Store_Scratch_Buffer_Picture_CMDCmd::VDENC_Row_Store_Scratch_Buffer_Picture_CMD2343 VDENC_Row_Store_Scratch_Buffer_Picture_CMD() 2344 { 2345 } 2346 2347 static const size_t dwSize = 3; 2348 static const size_t byteSize = 12; 2349 }; 2350 2351 //! 2352 //! \brief VDENC_Statistics_Streamout 2353 //! \details 2354 //! 2355 //! 2356 struct VDENC_Statistics_Streamout_CMD 2357 { 2358 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2359 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2360 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2361 2362 //! \name Local enumerations 2363 2364 //! \name Initializations 2365 2366 //! \brief Explicit member initialization function VDENC_Statistics_Streamout_CMDCmd::VDENC_Statistics_Streamout_CMD2367 VDENC_Statistics_Streamout_CMD() 2368 { 2369 } 2370 2371 static const size_t dwSize = 3; 2372 static const size_t byteSize = 12; 2373 }; 2374 2375 //! 2376 //! \brief VDENC_Streamin_Data_Picture 2377 //! \details 2378 //! 2379 //! 2380 struct VDENC_Streamin_Data_Picture_CMD 2381 { 2382 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress; //!< Lower Address 2383 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress; //!< Upper Address 2384 VDENC_Surface_Control_Bits_CMD PictureFields; //!< Picture Fields 2385 2386 //! \name Local enumerations 2387 2388 //! \name Initializations 2389 2390 //! \brief Explicit member initialization function VDENC_Streamin_Data_Picture_CMDCmd::VDENC_Streamin_Data_Picture_CMD2391 VDENC_Streamin_Data_Picture_CMD() 2392 { 2393 } 2394 2395 static const size_t dwSize = 3; 2396 static const size_t byteSize = 12; 2397 }; 2398 2399 //! 2400 //! \brief VDENC_STREAMIN_STATE 2401 //! \details 2402 //! 2403 //! 2404 struct VDENC_STREAMIN_STATE_CMD 2405 { 2406 union 2407 { 2408 //!< DWORD 0 2409 struct 2410 { 2411 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD(0, 7); //!< Region of Interest (ROI) Selection 2412 uint32_t Forceintra : __CODEGEN_BITFIELD(8, 8); //!< FORCEINTRA 2413 uint32_t Forceskip : __CODEGEN_BITFIELD(9, 9); //!< FORCESKIP 2414 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 2415 }; 2416 uint32_t Value; 2417 } DW0; 2418 union 2419 { 2420 //!< DWORD 1 2421 struct 2422 { 2423 uint32_t Qpprimey : __CODEGEN_BITFIELD(0, 7); //!< QPPRIMEY 2424 uint32_t Targetsizeinword : __CODEGEN_BITFIELD(8, 15); //!< TargetSizeInWord 2425 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23); //!< MaxSizeInWord 2426 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 2427 }; 2428 uint32_t Value; 2429 } DW1; 2430 union 2431 { 2432 //!< DWORD 2 2433 struct 2434 { 2435 uint32_t FwdPredictorX : __CODEGEN_BITFIELD(0, 15); //!< Fwd Predictor.X 2436 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31); //!< Fwd Predictor.Y 2437 }; 2438 uint32_t Value; 2439 } DW2; 2440 union 2441 { 2442 //!< DWORD 3 2443 struct 2444 { 2445 uint32_t BwdPredictorX : __CODEGEN_BITFIELD(0, 15); //!< Bwd Predictor.X 2446 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31); //!< Bwd Predictor.Y 2447 }; 2448 uint32_t Value; 2449 } DW3; 2450 union 2451 { 2452 //!< DWORD 4 2453 struct 2454 { 2455 uint32_t FwdRefid0 : __CODEGEN_BITFIELD(0, 3); //!< Fwd RefID0 2456 uint32_t BwdRefid0 : __CODEGEN_BITFIELD(4, 7); //!< Bwd RefID0 2457 uint32_t Reserved136 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 2458 }; 2459 uint32_t Value; 2460 } DW4; 2461 2462 uint32_t Reserved160[11]; //!< Reserved 2463 2464 //! \name Local enumerations 2465 2466 //! \brief FORCEINTRA 2467 //! \details 2468 //! This field specifies whether current macroblock should be coded as an 2469 //! intra macroblock. 2470 //! It is illegal to enable both ForceSkip and ForceIntra for 2471 //! the same macroblock. 2472 //! This should be disabled if Rolling-I is enabled in the 2473 //! VDEnc Image State. 2474 enum FORCEINTRA 2475 { 2476 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 2477 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 2478 }; 2479 2480 //! \brief FORCESKIP 2481 //! \details 2482 //! This field specifies whether current macroblock should be coded as a 2483 //! skipped macroblock. 2484 //! It is illegal to enable both ForceSkip and ForceIntra for 2485 //! the same macroblock. 2486 //! This should be disabled if Rolling-I is enabled in the 2487 //! VDEnc Image State. 2488 //! It is illegal to enable ForceSkip for I-Frames. 2489 enum FORCESKIP 2490 { 2491 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 2492 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 2493 }; 2494 2495 //! \brief QPPRIMEY 2496 //! \details 2497 //! Quantization parameter for Y. 2498 enum QPPRIMEY 2499 { 2500 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 2501 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 2502 }; 2503 2504 //! \name Initializations 2505 2506 //! \brief Explicit member initialization function VDENC_STREAMIN_STATE_CMDCmd::VDENC_STREAMIN_STATE_CMD2507 VDENC_STREAMIN_STATE_CMD() 2508 { 2509 MOS_ZeroMemory(this, sizeof(*this)); 2510 2511 DW0.Forceintra = FORCEINTRA_DISABLE; 2512 DW0.Forceskip = FORCESKIP_DISABLE; 2513 2514 DW1.Qpprimey = QPPRIMEY_UNNAMED0; 2515 } 2516 2517 static const size_t dwSize = 16; 2518 static const size_t byteSize = 64; 2519 }; 2520 2521 //! 2522 //! \brief VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT 2523 //! \details 2524 //! 2525 //! 2526 struct VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD 2527 { 2528 union 2529 { 2530 //!< DWORD 0 2531 struct 2532 { 2533 uint32_t SumSadHaarForBestModeDecision; //!< Sum sad\haar for best mode decision 2534 }; 2535 uint32_t Value; 2536 } DW0; 2537 union 2538 { 2539 //!< DWORD 1 2540 struct 2541 { 2542 uint32_t IntraCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< Intra CU count normalized 2543 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2544 }; 2545 uint32_t Value; 2546 } DW1; 2547 union 2548 { 2549 //!< DWORD 2 2550 struct 2551 { 2552 uint32_t NonSkipInterCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< Non-skip Inter CU count normalized 2553 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2554 }; 2555 uint32_t Value; 2556 } DW2; 2557 union 2558 { 2559 //!< DWORD 3 2560 struct 2561 { 2562 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 0 2563 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2564 }; 2565 uint32_t Value; 2566 } DW3; 2567 union 2568 { 2569 //!< DWORD 4 2570 struct 2571 { 2572 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 1 2573 uint32_t Reserved148 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2574 }; 2575 uint32_t Value; 2576 } DW4; 2577 union 2578 { 2579 //!< DWORD 5 2580 struct 2581 { 2582 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 2 2583 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2584 }; 2585 uint32_t Value; 2586 } DW5; 2587 union 2588 { 2589 //!< DWORD 6 2590 struct 2591 { 2592 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(0, 19); //!< segment map count 3 2593 uint32_t Reserved212 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2594 }; 2595 uint32_t Value; 2596 } DW6; 2597 union 2598 { 2599 //!< DWORD 7 2600 struct 2601 { 2602 uint32_t MvXGlobalMeSample025X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 0 (.25x,.25x) 2603 uint32_t MvYGlobalMeSample025X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 0 (.25x,.25x) 2604 }; 2605 uint32_t Value; 2606 } DW7; 2607 union 2608 { 2609 //!< DWORD 8 2610 struct 2611 { 2612 uint32_t MvXGlobalMeSample125X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 1 (.25x,.25x) 2613 uint32_t MvYGlobalMeSample125X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 1 (.25x,.25x) 2614 }; 2615 uint32_t Value; 2616 } DW8; 2617 union 2618 { 2619 //!< DWORD 9 2620 struct 2621 { 2622 uint32_t MvXGlobalMeSample225X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 2 (.25x,.25x) 2623 uint32_t MvYGlobalMeSample225X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 2 (.25x,.25x) 2624 }; 2625 uint32_t Value; 2626 } DW9; 2627 union 2628 { 2629 //!< DWORD 10 2630 struct 2631 { 2632 uint32_t MvXGlobalMeSample325X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 3 (.25x,.25x) 2633 uint32_t MvYGlobalMeSample325X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 3 (.25x,.25x) 2634 }; 2635 uint32_t Value; 2636 } DW10; 2637 union 2638 { 2639 //!< DWORD 11 2640 struct 2641 { 2642 uint32_t MvXGlobalMeSample425X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 4 (.25x,.25x) 2643 uint32_t MvYGlobalMeSample425X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 4 (.25x,.25x) 2644 }; 2645 uint32_t Value; 2646 } DW11; 2647 union 2648 { 2649 //!< DWORD 12 2650 struct 2651 { 2652 uint32_t MvXGlobalMeSample525X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 5 (.25x,.25x) 2653 uint32_t MvYGlobalMeSample525X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 5 (.25x,.25x) 2654 }; 2655 uint32_t Value; 2656 } DW12; 2657 union 2658 { 2659 //!< DWORD 13 2660 struct 2661 { 2662 uint32_t MvXGlobalMeSample625X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 6 (.25x,.25x) 2663 uint32_t MvYGlobalMeSample625X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 6 (.25x,.25x) 2664 }; 2665 uint32_t Value; 2666 } DW13; 2667 union 2668 { 2669 //!< DWORD 14 2670 struct 2671 { 2672 uint32_t MvXGlobalMeSample725X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 7 (.25x,.25x) 2673 uint32_t MvYGlobalMeSample725X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 7 (.25x,.25x) 2674 }; 2675 uint32_t Value; 2676 } DW14; 2677 union 2678 { 2679 //!< DWORD 15 2680 struct 2681 { 2682 uint32_t MvXGlobalMeSample825X25X : __CODEGEN_BITFIELD(0, 15); //!< MV.x Global ME sample 8 (.25x,.25x) 2683 uint32_t MvYGlobalMeSample825X25X : __CODEGEN_BITFIELD(16, 31); //!< MV.y Global ME sample 8 (.25x,.25x) 2684 }; 2685 uint32_t Value; 2686 } DW15; 2687 union 2688 { 2689 //!< DWORD 16 2690 struct 2691 { 2692 uint32_t RefidForGlobalmeSample0 : __CODEGEN_BITFIELD(0, 1); //!< RefID for GlobalME sample 0 2693 uint32_t RefidForGlobalmeSample18 : __CODEGEN_BITFIELD(2, 17); //!< RefID for GlobalME sample 1-8 2694 uint32_t Reserved530 : __CODEGEN_BITFIELD(18, 31); //!< Reserved 2695 }; 2696 uint32_t Value; 2697 } DW16; 2698 union 2699 { 2700 //!< DWORD 17 2701 struct 2702 { 2703 uint32_t PaletteCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< Palette CU Count Normalized 2704 uint32_t Reserved564 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2705 }; 2706 uint32_t Value; 2707 } DW17; 2708 union 2709 { 2710 //!< DWORD 18 2711 struct 2712 { 2713 uint32_t IbcCuCountNormalized : __CODEGEN_BITFIELD(0, 19); //!< IBC CU Count Normalized 2714 uint32_t Reserved596 : __CODEGEN_BITFIELD(20, 31); //!< Reserved 2715 }; 2716 uint32_t Value; 2717 } DW18; 2718 union 2719 { 2720 //!< DWORD 19 2721 struct 2722 { 2723 uint32_t Reserved; 2724 }; 2725 uint32_t Value; 2726 } DW19; 2727 union 2728 { 2729 //!< DWORD 20 2730 struct 2731 { 2732 uint32_t Reserved656; //!< Reserved 2733 }; 2734 uint32_t Value; 2735 } DW20; 2736 union 2737 { 2738 //!< DWORD 21 2739 struct 2740 { 2741 uint32_t Reserved672; //!< Reserved 2742 }; 2743 uint32_t Value; 2744 } DW21; 2745 union 2746 { 2747 //!< DWORD 22 2748 struct 2749 { 2750 uint32_t PositionOfTimerExpiration : __CODEGEN_BITFIELD(0, 15); //!< Position of Timer expiration 2751 uint32_t TimerExpireStatus : __CODEGEN_BITFIELD(16, 16); //!< Timer Expire status 2752 uint32_t Reserved721 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 2753 }; 2754 uint32_t Value; 2755 } DW22; 2756 union 2757 { 2758 //!< DWORD 23 2759 struct 2760 { 2761 uint32_t LocationOfPanic : __CODEGEN_BITFIELD(0, 15); //!< Location of panic 2762 uint32_t PanicDetected : __CODEGEN_BITFIELD(16, 16); //!< Panic detected 2763 uint32_t Reserved753 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 2764 }; 2765 uint32_t Value; 2766 } DW23; 2767 2768 uint32_t Reserved768[5]; //!< Reserved 2769 2770 union 2771 { 2772 //!< DWORD 29 2773 struct 2774 { 2775 uint32_t SumSadHaarForBestModeDecisionBottomHalfPopulation; //!< Sum sad\haar for best mode decision bottom half population 2776 }; 2777 uint32_t Value; 2778 } DW29; 2779 union 2780 { 2781 //!< DWORD 30 2782 struct 2783 { 2784 uint32_t SumSadHaarForBestModeDecisionTopHalfPopulation; //!< Sum sad\haar for best mode decision top half population 2785 }; 2786 uint32_t Value; 2787 } DW30; 2788 union 2789 { 2790 //!< DWORD 31 2791 struct 2792 { 2793 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD(0, 15); //!< Sum top half population occurrences 2794 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31); //!< Sum bottom half population occurrences 2795 }; 2796 uint32_t Value; 2797 } DW31; 2798 2799 //! \name Local enumerations 2800 2801 //! \name Initializations 2802 2803 //! \brief Explicit member initialization function VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMDCmd::VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD2804 VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD() 2805 { 2806 MOS_ZeroMemory(this, sizeof(*this)); 2807 } 2808 2809 static const size_t dwSize = 32; 2810 static const size_t byteSize = 128; 2811 }; 2812 2813 //! 2814 //! \brief VDENC_HEVC_VP9_STREAMIN_STATE 2815 //! \details 2816 //! For the NumMergeCandidate paramaters [64x64/32x32/16x16/8x8], only the 2817 //! following configurations are valid. 2818 //! Normal Mode without force mv or force intra: 4321 [64x64 --> 16x16]. 2819 //! Speed Mode without force mv or force intra: 2220, 2110, 1210, 2200, 1110 2820 //! [64x64 --> 16x16]. 2821 //! 2822 struct VDENC_HEVC_VP9_STREAMIN_STATE_CMD 2823 { 2824 union 2825 { 2826 //!< DWORD 0 2827 struct 2828 { 2829 uint32_t Roi32X32016X1603 : __CODEGEN_BITFIELD(0, 7); //!< ROI 32x32_0 16x16_03 2830 uint32_t Maxtusize : __CODEGEN_BITFIELD(8, 9); //!< MaxTUSize 2831 uint32_t Maxcusize : __CODEGEN_BITFIELD(10, 11); //!< MaxCUSize 2832 uint32_t Numimepredictors : __CODEGEN_BITFIELD(12, 15); //!< NUMIMEPREDICTORS 2833 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 20); 2834 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 21); 2835 uint32_t PaletteDisable : __CODEGEN_BITFIELD(22, 22); 2836 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23); 2837 uint32_t PuType32X32016X1603 : __CODEGEN_BITFIELD(24, 31); //!< PU Type 32x32_0 16x16_03 2838 }; 2839 uint32_t Value; 2840 } DW0; 2841 union 2842 { 2843 //!< DWORD 1 2844 struct 2845 { 2846 uint32_t ForceMvX32X32016X160 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_0 2847 uint32_t ForceMvY32X32016X160 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_0 2848 }; 2849 uint32_t Value; 2850 } DW1; 2851 union 2852 { 2853 //!< DWORD 2 2854 struct 2855 { 2856 uint32_t ForceMvX32X32016X161 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_1 2857 uint32_t ForceMvY32X32016X161 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_1 2858 }; 2859 uint32_t Value; 2860 } DW2; 2861 union 2862 { 2863 //!< DWORD 3 2864 struct 2865 { 2866 uint32_t ForceMvX32X32016X162 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_2 2867 uint32_t ForceMvY32X32016X162 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_2 2868 }; 2869 uint32_t Value; 2870 } DW3; 2871 union 2872 { 2873 //!< DWORD 4 2874 struct 2875 { 2876 uint32_t ForceMvX32X32016X163 : __CODEGEN_BITFIELD(0, 15); //!< force_mv.x 32x32_0 16x16_3 2877 uint32_t ForceMvY32X32016X163 : __CODEGEN_BITFIELD(16, 31); //!< force_mv.y 32x32_0 16x16_3 2878 }; 2879 uint32_t Value; 2880 } DW4; 2881 union 2882 { 2883 //!< DWORD 5 2884 struct 2885 { 2886 uint32_t Reserved160; //!< Reserved 2887 }; 2888 uint32_t Value; 2889 } DW5; 2890 union 2891 { 2892 //!< DWORD 6 2893 struct 2894 { 2895 uint32_t ForceMvRefidx32X32016X160 : __CODEGEN_BITFIELD(0, 3); //!< force_mv refidx 32x32_0 16x16_0 2896 uint32_t ForceMvRefidx32X32016X1613 : __CODEGEN_BITFIELD(4, 15); //!< force_mv refidx 32x32_0 16x16_1-3 2897 uint32_t Nummergecandidatecu8X8 : __CODEGEN_BITFIELD(16, 19); //!< NumMergeCandidateCU8x8 2898 uint32_t Nummergecandidatecu16X16 : __CODEGEN_BITFIELD(20, 23); //!< NumMergeCandidateCU16x16 2899 uint32_t Nummergecandidatecu32X32 : __CODEGEN_BITFIELD(24, 27); //!< NumMergeCandidateCU32x32 2900 uint32_t Nummergecandidatecu64X64 : __CODEGEN_BITFIELD(28, 31); //!< NumMergeCandidateCU64x64 2901 }; 2902 uint32_t Value; 2903 } DW6; 2904 union 2905 { 2906 //!< DWORD 7 2907 struct 2908 { 2909 uint32_t Segid32X32016X1603Vp9Only : __CODEGEN_BITFIELD(0, 15); //!< SegID 32x32_0 16x16_03 (VP9 only) 2910 uint32_t QpEn32X32016X1603 : __CODEGEN_BITFIELD(16, 19); //!< QP_En 32x32_0 16x16_03 2911 uint32_t SegidEnable : __CODEGEN_BITFIELD(20, 20); //!< SegID Enable 2912 uint32_t Reserved245 : __CODEGEN_BITFIELD(21, 22); //!< Reserved 2913 uint32_t ForceRefidEnable32X320 : __CODEGEN_BITFIELD(23, 23); //!< Force Refid Enable (32x32_0) 2914 uint32_t ImePredictorRefidSelect0332X320 : __CODEGEN_BITFIELD(24, 31); //!< IME predictor/refid Select0-3 32x32_0 2915 }; 2916 uint32_t Value; 2917 } DW7; 2918 union 2919 { 2920 //!< DWORD 8 2921 struct 2922 { 2923 uint32_t ImePredictor0X32X320 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_0 2924 uint32_t ImePredictor0Y32X320 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_0 2925 }; 2926 uint32_t Value; 2927 } DW8; 2928 union 2929 { 2930 //!< DWORD 9 2931 struct 2932 { 2933 uint32_t ImePredictor0X32X321 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_1 2934 uint32_t ImePredictor0Y32X321 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_1 2935 }; 2936 uint32_t Value; 2937 } DW9; 2938 union 2939 { 2940 //!< DWORD 10 2941 struct 2942 { 2943 uint32_t ImePredictor0X32X322 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_2 2944 uint32_t ImePredictor0Y32X322 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_2 2945 }; 2946 uint32_t Value; 2947 } DW10; 2948 union 2949 { 2950 //!< DWORD 11 2951 struct 2952 { 2953 uint32_t ImePredictor0X32X323 : __CODEGEN_BITFIELD(0, 15); //!< ime_predictor0.x 32x32_3 2954 uint32_t ImePredictor0Y32X323 : __CODEGEN_BITFIELD(16, 31); //!< ime_predictor0.y 32x32_3 2955 }; 2956 uint32_t Value; 2957 } DW11; 2958 union 2959 { 2960 //!< DWORD 12 2961 struct 2962 { 2963 uint32_t ImePredictor0Refidx32X320 : __CODEGEN_BITFIELD(0, 3); //!< ime_predictor0 refidx 32x32_0 2964 uint32_t ImePredictor13Refidx32X3213 : __CODEGEN_BITFIELD(4, 15); //!< ime_predictor1-3 refidx 32x32_1-3 2965 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 2966 }; 2967 uint32_t Value; 2968 } DW12; 2969 union 2970 { 2971 //!< DWORD 13 2972 struct 2973 { 2974 uint32_t Panicmodelcuthreshold : __CODEGEN_BITFIELD(0, 15); //!< PanicModeLCUThreshold 2975 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 2976 }; 2977 uint32_t Value; 2978 } DW13; 2979 union 2980 { 2981 //!< DWORD 14 2982 struct 2983 { 2984 uint32_t ForceQpValue16X160 : __CODEGEN_BITFIELD(0, 7); //!< Force QP Value 16x16_0 2985 uint32_t ForceQpValue16X161 : __CODEGEN_BITFIELD(8, 15); //!< Force QP Value 16x16_1 2986 uint32_t ForceQpValue16X162 : __CODEGEN_BITFIELD(16, 23); //!< Force QP Value 16x16_2 2987 uint32_t ForceQpValue16X163 : __CODEGEN_BITFIELD(24, 31); //!< Force QP Value 16x16_3 2988 }; 2989 uint32_t Value; 2990 } DW14; 2991 union 2992 { 2993 //!< DWORD 15 2994 struct 2995 { 2996 uint32_t Reserved480; //!< Reserved 2997 }; 2998 uint32_t Value; 2999 } DW15; 3000 3001 //! \name Local enumerations 3002 3003 //! \brief NUMIMEPREDICTORS 3004 //! \details 3005 //! <p>This parameter specifes the number of IME predictors to be processed 3006 //! in stage3 IME.</p> 3007 //! <p></p> 3008 enum NUMIMEPREDICTORS 3009 { 3010 NUMIMEPREDICTORS_UNNAMED0 = 0, //!< No additional details 3011 NUMIMEPREDICTORS_UNNAMED4 = 4, //!< No additional details 3012 NUMIMEPREDICTORS_UNNAMED8 = 8, //!< No additional details 3013 NUMIMEPREDICTORS_UNNAMED12 = 12, //!< No additional details 3014 }; 3015 3016 //! \name Initializations 3017 3018 //! \brief Explicit member initialization function VDENC_HEVC_VP9_STREAMIN_STATE_CMDCmd::VDENC_HEVC_VP9_STREAMIN_STATE_CMD3019 VDENC_HEVC_VP9_STREAMIN_STATE_CMD() 3020 { 3021 MOS_ZeroMemory(this, sizeof(*this)); 3022 3023 DW0.Numimepredictors = NUMIMEPREDICTORS_UNNAMED0; 3024 } 3025 3026 static const size_t dwSize = 16; 3027 static const size_t byteSize = 64; 3028 }; 3029 3030 //! 3031 //! \brief VDENC_Surface_State_Fields 3032 //! \details 3033 //! 3034 //! 3035 struct VDENC_Surface_State_Fields_CMD 3036 { 3037 union 3038 { 3039 //!< DWORD 0 3040 struct 3041 { 3042 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD(0, 1); //!< Cr(V)/Cb(U) Pixel Offset V Direction 3043 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD(2, 2); //!< Surface Format Byte Swizzle 3044 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD(3, 3); //!< Color space selection 3045 uint32_t Width : __CODEGEN_BITFIELD(4, 17); //!< Width 3046 uint32_t Height : __CODEGEN_BITFIELD(18, 31); //!< Height 3047 }; 3048 uint32_t Value; 3049 } DW0; 3050 union 3051 { 3052 //!< DWORD 1 3053 struct 3054 { 3055 uint32_t TileMode : __CODEGEN_BITFIELD(0, 1); //!< TILE_MODE 3056 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(2, 2); //!< HALF_PITCH_FOR_CHROMA 3057 uint32_t SurfacePitch : __CODEGEN_BITFIELD(3, 19); //!< Surface Pitch 3058 uint32_t ChromaDownsampleFilterControl : __CODEGEN_BITFIELD(20, 22); //!< Chroma Downsample Filter Control 3059 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 26); //!< Reserved 3060 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31); //!< SURFACE_FORMAT 3061 }; 3062 uint32_t Value; 3063 } DW1; 3064 union 3065 { 3066 //!< DWORD 2 3067 struct 3068 { 3069 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD(0, 14); //!< Y Offset for U(Cb) 3070 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 3071 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30); //!< X Offset for U(Cb) 3072 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 3073 }; 3074 uint32_t Value; 3075 } DW2; 3076 union 3077 { 3078 //!< DWORD 3 3079 struct 3080 { 3081 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(0, 15); //!< Y Offset for V(Cr) 3082 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28); //!< X Offset for V(Cr) 3083 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 3084 }; 3085 uint32_t Value; 3086 } DW3; 3087 3088 //! \name Local enumerations 3089 3090 //! \brief TILE_MODE 3091 enum TILE_MODE 3092 { 3093 TILE_LINEAR = 0, //!< Linear 3094 TILE_S = 1, //!< TileS(64K) 3095 TILE_X = 2, //!< Tile X 3096 TILE_F = 3, //!< Tile F 3097 }; 3098 3099 //! \brief HALF_PITCH_FOR_CHROMA 3100 //! \details 3101 //! (This field must be set to Disable.) This field indicates that the 3102 //! chroma plane(s) will use a pitch equal 3103 //! to half the value specified in the Surface Pitch field. This field 3104 //! is only used for PLANAR surface formats. 3105 //! This field is igored by VDEnc (unless we support YV12). 3106 enum HALF_PITCH_FOR_CHROMA 3107 { 3108 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 3109 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 3110 }; 3111 3112 //! \brief SURFACE_FORMAT 3113 //! \details 3114 //! Specifies the format of the surface. 3115 enum SURFACE_FORMAT 3116 { 3117 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 3118 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 3119 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 3120 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 3121 SURFACE_FORMAT_PLANAR_420_8 = 4, //!< (NV12, IMC1,2,3,4, YV12) 3122 SURFACE_FORMAT_YCRCB_SWAPY_422 = 5, //!< UYVY (8:8:8:8 MSB Y1 V0 Y0 U0) 3123 SURFACE_FORMAT_YCRCB_SWAPUV_422 = 6, //!< YVYU (8:8:8:8 MSB U0 Y1 V0 Y0) 3124 SURFACE_FORMAT_YCRCB_SWAPUVY_422 = 7, //!< VYUY (8:8:8:8 MSB Y1 U0 Y0 V0) 3125 SURFACE_FORMAT_P010 = 8, //!< 10 - bit planar 420 (Tile - Y / Linear / Tile - X) 3126 SURFACE_FORMAT_RGBA_10_10_10_2 = 9, //!< Need to convert to YUV. 2 bits Alpha, 10 bits R 10 bits G 10 bits B 3127 SURFACE_FORMAT_Y410 = 10, //!< 10 bit 4:4:4 packed 3128 SURFACE_FORMAT_NV21 = 11, //!< 8-bit, same as NV12 but UV interleave is reversed 3129 SURFACE_FORMAT_P010_VARIANT = 12, //!< >8 bit planar 420 with MSB together and LSB at an offset in x direction 3130 }; 3131 3132 //! \name Initializations 3133 3134 //! \brief Explicit member initialization function VDENC_Surface_State_Fields_CMDCmd::VDENC_Surface_State_Fields_CMD3135 VDENC_Surface_State_Fields_CMD() 3136 { 3137 MOS_ZeroMemory(this, sizeof(*this)); 3138 3139 DW1.TileMode = TILE_F; 3140 DW1.HalfPitchForChroma = HALF_PITCH_FOR_CHROMA_DISABLE; 3141 } 3142 3143 static const size_t dwSize = 4; 3144 static const size_t byteSize = 16; 3145 }; 3146 3147 //! 3148 //! \brief VD_PIPELINE_FLUSH 3149 //! \details 3150 //! 3151 //! 3152 struct VD_PIPELINE_FLUSH_CMD 3153 { 3154 union 3155 { 3156 //!< DWORD 0 3157 struct 3158 { 3159 uint32_t DwordCountN : __CODEGEN_BITFIELD(0, 11); //!< DWORD_COUNT_N 3160 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3161 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 3162 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22); //!< SUBOPCODEA 3163 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_COMMAND_OPCODE 3164 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3165 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3166 }; 3167 uint32_t Value; 3168 } DW0; 3169 union 3170 { 3171 //!< DWORD 1 3172 struct 3173 { 3174 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD(0, 0); //!< HEVC pipeline Done 3175 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD(1, 1); //!< VD-ENC pipeline Done 3176 uint32_t MflPipelineDone : __CODEGEN_BITFIELD(2, 2); //!< MFL pipeline Done 3177 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD(3, 3); //!< MFX pipeline Done 3178 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD(4, 4); //!< VD command/message parser Done 3179 uint32_t HucPipelineDone : __CODEGEN_BITFIELD(5, 5); //!< HUC Pipeline Done 3180 uint32_t AvpPipelineDone : __CODEGEN_BITFIELD(6, 6); //!< AVP Pipeline Done 3181 uint32_t Reserved37 : __CODEGEN_BITFIELD(7, 15); //!< Reserved 3182 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16); //!< HEVC pipeline command flush 3183 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17); //!< VD-ENC pipeline command flush 3184 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18); //!< MFL pipeline command flush 3185 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19); //!< MFX pipeline command flush 3186 uint32_t HucPipelineCommandFlush : __CODEGEN_BITFIELD(20, 20); //!< HUC pipeline command flush 3187 uint32_t AvpPipelineCommandFlush : __CODEGEN_BITFIELD(21, 21); //!< AVP Pipeline Command Flush 3188 uint32_t Reserved52 : __CODEGEN_BITFIELD(22, 31); //!< Reserved 3189 }; 3190 uint32_t Value; 3191 } DW1; 3192 3193 //! \name Local enumerations 3194 3195 //! \brief DWORD_COUNT_N 3196 //! \details 3197 //! Total Length - 2 3198 enum DWORD_COUNT_N 3199 { 3200 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 3201 }; 3202 3203 enum SUBOPCODEB 3204 { 3205 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 3206 }; 3207 3208 enum SUBOPCODEA 3209 { 3210 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 3211 }; 3212 3213 enum MEDIA_COMMAND_OPCODE 3214 { 3215 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 3216 }; 3217 3218 enum PIPELINE 3219 { 3220 PIPELINE_MEDIA = 2, //!< No additional details 3221 }; 3222 3223 enum COMMAND_TYPE 3224 { 3225 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3226 }; 3227 3228 //! \name Initializations 3229 3230 //! \brief Explicit member initialization function VD_PIPELINE_FLUSH_CMDCmd::VD_PIPELINE_FLUSH_CMD3231 VD_PIPELINE_FLUSH_CMD() 3232 { 3233 MOS_ZeroMemory(this, sizeof(*this)); 3234 3235 DW0.DwordCountN = __CODEGEN_OP_LENGTH(dwSize); 3236 DW0.Subopcodeb = SUBOPCODEB_UNNAMED0; 3237 DW0.Subopcodea = SUBOPCODEA_UNNAMED0; 3238 DW0.MediaCommandOpcode = MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND; 3239 DW0.Pipeline = PIPELINE_MEDIA; 3240 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3241 } 3242 3243 static const size_t dwSize = 2; 3244 static const size_t byteSize = 8; 3245 }; 3246 3247 //! 3248 //! \brief VDENC_WEIGHTSOFFSETS_STATE 3249 //! \details 3250 //! 3251 //! 3252 struct VDENC_WEIGHTSOFFSETS_STATE_CMD 3253 { 3254 union 3255 { 3256 //!< DWORD 0 3257 struct 3258 { 3259 uint32_t DwLength : __CODEGEN_BITFIELD(0, 11); //!< DW_LENGTH 3260 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3261 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3262 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3263 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3264 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3265 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3266 }; 3267 uint32_t Value; 3268 } DW0; 3269 union 3270 { 3271 //!< DWORD 1 3272 struct 3273 { 3274 uint32_t WeightsForwardReference0 : __CODEGEN_BITFIELD(0, 7); //!< Weights Forward Reference0 3275 uint32_t OffsetForwardReference0 : __CODEGEN_BITFIELD(8, 15); //!< Offset Forward Reference0 3276 uint32_t WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23); //!< Weights Forward Reference1 3277 uint32_t OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31); //!< Offset Forward Reference1 3278 }; 3279 uint32_t Value; 3280 } DW1; 3281 union 3282 { 3283 //!< DWORD 2 3284 struct 3285 { 3286 uint32_t WeightsForwardReference2 : __CODEGEN_BITFIELD(0, 7); //!< Weights Forward Reference2 3287 uint32_t OffsetForwardReference2 : __CODEGEN_BITFIELD(8, 15); //!< Offset Forward Reference2 3288 uint32_t WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23); //!< Weights Backward Reference0 3289 uint32_t OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31); //!< Offset Backward Reference0 3290 }; 3291 uint32_t Value; 3292 } DW2; 3293 union 3294 { 3295 //!< DWORD 3 3296 struct 3297 { 3298 uint32_t CbWeightsForwardReference0 : __CODEGEN_BITFIELD(0, 7); //!< Cb Weights Forward Reference0 3299 uint32_t CbOffsetForwardReference0 : __CODEGEN_BITFIELD(8, 15); //!< Cb Offset Forward Reference0 3300 uint32_t CbWeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23); //!< Cb Weights Forward Reference1 3301 uint32_t CbOffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31); //!< Cb Offset Forward Reference1 3302 }; 3303 uint32_t Value; 3304 } DW3; 3305 union 3306 { 3307 //!< DWORD 4 3308 struct 3309 { 3310 uint32_t CbWeightsForwardReference2 : __CODEGEN_BITFIELD(0, 7); //!< Cb Weights Forward Reference2 3311 uint32_t CbOffsetForwardReference2 : __CODEGEN_BITFIELD(8, 15); //!< Cb Offset Forward Reference2 3312 uint32_t CbWeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23); //!< Cb Weights Backward Reference0 3313 uint32_t CbOffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31); //!< Cb Offset Backward Reference0 3314 }; 3315 uint32_t Value; 3316 } DW4; 3317 union 3318 { 3319 //!< DWORD 5 3320 struct 3321 { 3322 uint32_t CrWeightsForwardReference0 : __CODEGEN_BITFIELD(0, 7); //!< Cr Weights Forward Reference0 3323 uint32_t CrOffsetForwardReference0 : __CODEGEN_BITFIELD(8, 15); //!< Cr Offset Forward Reference0 3324 uint32_t CrWeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23); //!< Cr Weights Forward Reference1 3325 uint32_t CrOffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31); //!< Cr Offset Forward Reference1 3326 }; 3327 uint32_t Value; 3328 } DW5; 3329 union 3330 { 3331 //!< DWORD 6 3332 struct 3333 { 3334 uint32_t CrWeightsForwardReference2 : __CODEGEN_BITFIELD(0, 7); //!< Cr Weights Forward Reference2 3335 uint32_t CrOffsetForwardReference2 : __CODEGEN_BITFIELD(8, 15); //!< Cr Offset Forward Reference2 3336 uint32_t CrWeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23); //!< Cr Weights Backward Reference0 3337 uint32_t CrOffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31); //!< Cr Offset Backward Reference0 3338 }; 3339 uint32_t Value; 3340 } DW6; 3341 3342 //! \name Local enumerations 3343 3344 //! \brief DW_LENGTH 3345 //! \details 3346 //! Total Length - 2 3347 enum DW_LENGTH 3348 { 3349 DW_LENGTH_DWORDCOUNTN = 5, //!< Excludes DWord (0,1) 3350 }; 3351 3352 enum SUBOPB 3353 { 3354 SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE = 8, //!< No additional details 3355 }; 3356 3357 enum SUBOPA 3358 { 3359 SUBOPA_UNNAMED0 = 0, //!< No additional details 3360 }; 3361 3362 enum OPCODE 3363 { 3364 OPCODE_VDENCPIPE = 1, //!< No additional details 3365 }; 3366 3367 enum PIPELINE 3368 { 3369 PIPELINE_MFXCOMMON = 2, //!< No additional details 3370 }; 3371 3372 enum COMMAND_TYPE 3373 { 3374 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3375 }; 3376 3377 //! \name Initializations 3378 3379 //! \brief Explicit member initialization function VDENC_WEIGHTSOFFSETS_STATE_CMDCmd::VDENC_WEIGHTSOFFSETS_STATE_CMD3380 VDENC_WEIGHTSOFFSETS_STATE_CMD() 3381 { 3382 MOS_ZeroMemory(this, sizeof(*this)); 3383 3384 DW0.DwLength = __CODEGEN_OP_LENGTH(dwSize); 3385 DW0.Subopb = SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE; 3386 DW0.Subopa = SUBOPA_UNNAMED0; 3387 DW0.Opcode = OPCODE_VDENCPIPE; 3388 DW0.Pipeline = PIPELINE_MFXCOMMON; 3389 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3390 3391 DW1.WeightsForwardReference0 = 1; 3392 DW1.OffsetForwardReference0 = 0; 3393 DW1.WeightsForwardReference1 = 1; 3394 DW1.OffsetForwardReference1 = 0; 3395 3396 DW2.WeightsForwardReference2 = 1; 3397 DW2.OffsetForwardReference2 = 0; 3398 DW2.WeightsBackwardReference0 = 1; 3399 DW2.OffsetBackwardReference0 = 0; 3400 } 3401 3402 static const size_t dwSize = 7; 3403 static const size_t byteSize = 28; 3404 }; 3405 3406 //! 3407 //! \brief VDENC_DS_REF_SURFACE_STATE 3408 //! \details 3409 //! This command specifies the surface state parameters for the downscaled 3410 //! reference surfaces. 3411 //! 3412 struct VDENC_DS_REF_SURFACE_STATE_CMD 3413 { 3414 union 3415 { 3416 //!< DWORD 0 3417 struct 3418 { 3419 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3420 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3421 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3422 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3423 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3424 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3425 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3426 }; 3427 uint32_t Value; 3428 } DW0; 3429 union 3430 { 3431 //!< DWORD 1 3432 struct 3433 { 3434 uint32_t Reserved32; //!< Reserved 3435 }; 3436 uint32_t Value; 3437 } DW1; 3438 VDENC_Surface_State_Fields_CMD Dwords25; //!< Dwords 2..5 3439 VDENC_Surface_State_Fields_CMD Dwords69; //!< Dwords 6..9 3440 3441 //! \name Local enumerations 3442 3443 enum SUBOPB 3444 { 3445 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 3446 }; 3447 3448 enum SUBOPA 3449 { 3450 SUBOPA_UNNAMED0 = 0, //!< No additional details 3451 }; 3452 3453 enum OPCODE 3454 { 3455 OPCODE_VDENCPIPE = 1, //!< No additional details 3456 }; 3457 3458 enum PIPELINE 3459 { 3460 PIPELINE_MFXCOMMON = 2, //!< No additional details 3461 }; 3462 3463 enum COMMAND_TYPE 3464 { 3465 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3466 }; 3467 3468 //! \name Initializations 3469 3470 //! \brief Explicit member initialization function VDENC_DS_REF_SURFACE_STATE_CMDCmd::VDENC_DS_REF_SURFACE_STATE_CMD3471 VDENC_DS_REF_SURFACE_STATE_CMD() 3472 { 3473 MOS_ZeroMemory(this, sizeof(*this)); 3474 3475 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 3476 DW0.Subopb = SUBOPB_VDENCDSREFSURFACESTATE; 3477 DW0.Subopa = SUBOPA_UNNAMED0; 3478 DW0.Opcode = OPCODE_VDENCPIPE; 3479 DW0.Pipeline = PIPELINE_MFXCOMMON; 3480 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3481 } 3482 3483 static const size_t dwSize = 10; 3484 static const size_t byteSize = 40; 3485 }; 3486 3487 //! 3488 //! \brief VDENC_AVC_IMG_STATE 3489 //! \details 3490 //! This command programs the frame level parameters required by the VDEnc 3491 //! pipeline. 3492 //! 3493 struct VDENC_AVC_IMG_STATE_CMD 3494 { 3495 union 3496 { 3497 struct 3498 { 3499 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3500 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3501 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3502 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3503 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3504 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3505 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3506 }; 3507 uint32_t Value; 3508 } DW0; 3509 VDENC_AVC_IMG_STATE_CMD_DW1 DW1; 3510 VDENC_AVC_IMG_STATE_CMD_DW2 DW2; 3511 union 3512 { 3513 struct 3514 { 3515 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD(0, 15); //!< Picture Height Minus One 3516 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 31); //!< Picture Width 3517 }; 3518 uint32_t Value; 3519 } DW3; 3520 VDENC_AVC_IMG_STATE_CMD_DW4 DW4; 3521 VDENC_AVC_IMG_STATE_CMD_DW5 DW5; 3522 union 3523 { 3524 struct 3525 { 3526 uint32_t IntraRefreshMbPos : __CODEGEN_BITFIELD(0, 7); //!< IntraRefreshMBPos 3527 uint32_t IntraRefreshMbSizeMinusOne : __CODEGEN_BITFIELD(8, 15); //!< IntraRefreshMBSizeMinusOne 3528 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16); //!< INTRAREFRESHENABLE_ROLLING_I_ENABLE 3529 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17); //!< INTRAREFRESHMODE 3530 uint32_t Reserved210 : __CODEGEN_BITFIELD(18, 23); //!< Reserved 3531 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31); //!< QP adjustment for Rolling-I 3532 }; 3533 uint32_t Value; 3534 } DW6; 3535 VDENC_AVC_IMG_STATE_CMD_DW7 DW7; 3536 VDENC_AVC_IMG_STATE_CMD_DW8 DW8; 3537 VDENC_AVC_IMG_STATE_CMD_DW9 DW9; 3538 VDENC_AVC_IMG_STATE_CMD_DW10 DW10; 3539 VDENC_AVC_IMG_STATE_CMD_DW11 DW11; 3540 VDENC_AVC_IMG_STATE_CMD_DW12 DW12; 3541 VDENC_AVC_IMG_STATE_CMD_DW13 DW13; 3542 VDENC_AVC_IMG_STATE_CMD_DW14 DW14; 3543 VDENC_AVC_IMG_STATE_CMD_DW15 DW15; 3544 VDENC_AVC_IMG_STATE_CMD_DW16 DW16; 3545 VDENC_AVC_IMG_STATE_CMD_DW17 DW17; 3546 VDENC_AVC_IMG_STATE_CMD_DW18 DW18; 3547 VDENC_AVC_IMG_STATE_CMD_DW19 DW19; 3548 3549 //! \name Local enumerations 3550 3551 enum SUBOPB 3552 { 3553 SUBOPB_VDENCAVCIMGSTATE = 5, //!< No additional details 3554 }; 3555 3556 enum SUBOPA 3557 { 3558 SUBOPA_UNNAMED0 = 0, //!< No additional details 3559 }; 3560 3561 enum OPCODE 3562 { 3563 OPCODE_VDENCPIPE = 1, //!< No additional details 3564 }; 3565 3566 enum PIPELINE 3567 { 3568 PIPELINE_MFXCOMMON = 2, //!< No additional details 3569 }; 3570 3571 enum COMMAND_TYPE 3572 { 3573 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3574 }; 3575 3576 //! \brief PICTURE_TYPE 3577 //! \details 3578 //! This parameter indicates the picture type of the current frame. The 3579 //! supported frame types for AVC are I, P and B. 3580 enum PICTURE_TYPE 3581 { 3582 PICTURE_TYPE_I_FRAME = 0, //!< No additional details 3583 PICTURE_TYPE_P_FRAME = 1, //!< No additional details 3584 PICTURE_TYPE_B_FRAME = 2, //!< No additional details 3585 }; 3586 3587 //! \brief BIDIRECTIONAL_WEIGHT 3588 //! \details 3589 //! The programmingof the Bidirectional Weight depends on the distance 3590 //! between the B and reference pictures. 3591 //! Here the notation is for bidirectional prediction with 3592 //! display picture order, whereas Rf stands for forward reference, Rb for 3593 //! backward reference, B for the current bidirectional predicted picture 3594 //! and X is another picture in the sequence. 3595 //! 16 (quarter distance like Rf B X X Rb), 3596 //! 21 (one third distance like Rf B X Rb), 3597 //! 32 (half distance like Rf B Rb), 3598 //! 43 (two third distance like Rf X B Rb), 3599 //! 48 (three quarter distance like RXXBR). 3600 enum BIDIRECTIONAL_WEIGHT 3601 { 3602 BIDIRECTIONAL_WEIGHT_QUARTERDISTANCE = 16, //!< No additional details 3603 BIDIRECTIONAL_WEIGHT_ONETHIRDDISTANCE = 21, //!< No additional details 3604 BIDIRECTIONAL_WEIGHT_HALFDISTANCE = 32, //!< No additional details 3605 BIDIRECTIONAL_WEIGHT_TWOTHIRDDISTANCE = 43, //!< No additional details 3606 BIDIRECTIONAL_WEIGHT_THREEQUARTERDISTANCE = 48, //!< No additional details 3607 }; 3608 3609 //! \brief BWD_REFIDX0_REFERENCE_PICTURE 3610 //! \details 3611 //! Reference Picture corresponding to BWD Reference Index 0. This value 3612 //! should be consistent with MFX_REF_IDX state 3613 enum BWD_REFIDX0_REFERENCE_PICTURE 3614 { 3615 BWD_REFIDX0_REFERENCE_PICTURE_BWDREFIDX = 0, //!< No additional details 3616 }; 3617 3618 //! \brief INTRAREFRESHENABLE_ROLLING_I_ENABLE 3619 //! \details 3620 //! This parameter indicates if the IntraRefresh is enabled or 3621 //! disabled. 3622 //! This must be disabled on I-Frames. 3623 enum INTRAREFRESHENABLE_ROLLING_I_ENABLE 3624 { 3625 INTRAREFRESHENABLE_ROLLING_I_ENABLE_DISABLE = 0, //!< No additional details 3626 INTRAREFRESHENABLE_ROLLING_I_ENABLE_ENABLE = 1, //!< No additional details 3627 }; 3628 3629 //! \brief INTRAREFRESHMODE 3630 //! \details 3631 //! This parameter indicates if the IntraRefresh is row based or column 3632 //! based. 3633 enum INTRAREFRESHMODE 3634 { 3635 INTRAREFRESHMODE_ROWBASED = 0, //!< No additional details 3636 INTRAREFRESHMODE_COLUMNBASED = 1, //!< No additional details 3637 }; 3638 3639 //! \brief LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 3640 //! \details 3641 //! Indicates whether the reference frame is a long or short term reference. 3642 enum LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 3643 { 3644 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 3645 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 3646 }; 3647 3648 //! \name Initializations 3649 3650 //! \brief Explicit member initialization function VDENC_AVC_IMG_STATE_CMDCmd::VDENC_AVC_IMG_STATE_CMD3651 VDENC_AVC_IMG_STATE_CMD() 3652 { 3653 MOS_ZeroMemory(this, sizeof(*this)); 3654 3655 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 3656 DW0.Subopb = SUBOPB_VDENCAVCIMGSTATE; 3657 DW0.Subopa = SUBOPA_UNNAMED0; 3658 DW0.Opcode = OPCODE_VDENCPIPE; 3659 DW0.Pipeline = PIPELINE_MFXCOMMON; 3660 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3661 } 3662 3663 static const size_t dwSize = 20; 3664 static const size_t byteSize = 80; 3665 }; 3666 3667 //! 3668 //! \brief VDENC_PIPE_BUF_ADDR_STATE 3669 //! \details 3670 //! This state command provides the memory base addresses for all row 3671 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 3672 //! source, reference pictures and downscaled reference pictures required by 3673 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 3674 //! programmed with the same surface state (NV12 and TileY format), except 3675 //! each has its own frame buffer base address. Same holds true for the 3676 //! down-scaled reference pictures too. In the tile format, there is no need 3677 //! to provide buffer offset for each slice; since from each MB address, the 3678 //! hardware can calculated the corresponding memory location within the 3679 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 3680 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 3681 //! will sort out the base address from the DPB table and populate the base 3682 //! addresses that map to the corresponding reference index for both DS 3683 //! references and normal reference frames. Each of the individual DS ref/ 3684 //! Normal ref frames have their own MOCS DW that corresponds to the 3685 //! respective base address. The only thing that is different in the MOCS DW 3686 //! amongst the DS reference frames is the MMCD controls (specified in bits 3687 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 3688 //! to be the same across the different DS ref frames. The same is 3689 //! applicable for the normal reference frames. 3690 //! 3691 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 3692 { 3693 union 3694 { 3695 //!< DWORD 0 3696 struct 3697 { 3698 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3699 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3700 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3701 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3702 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3703 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3704 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3705 }; 3706 uint32_t Value; 3707 } DW0; 3708 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0; //!< DS FWD REF0 3709 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1; //!< DS FWD REF1 3710 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0; //!< DS BWD REF0 3711 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture; //!< Original Uncompressed Picture 3712 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture; //!< Streamin Data Picture 3713 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer; //!< Row Store Scratch Buffer 3714 VDENC_Colocated_MV_Picture_CMD ColocatedMv; //!< Colocated MV 3715 VDENC_Reference_Picture_CMD FwdRef0; //!< FWD REF0 3716 VDENC_Reference_Picture_CMD FwdRef1; //!< FWD REF1 3717 VDENC_Reference_Picture_CMD FwdRef2; //!< FWD REF2 3718 VDENC_Reference_Picture_CMD BwdRef0; //!< BWD REF0 3719 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout; //!< VDEnc Statistics Streamout 3720 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef04X; //!< DS FWD REF0 4X 3721 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef14X; //!< DS FWD REF1 4X 3722 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef04X; //!< DS BWD REF1 4X 3723 VDENC_Statistics_Streamout_CMD VdencLcuPakObjCmdBuffer; //!< VDEnc LCU PAK OBJ CMD Buffer 3724 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurfaceStage1; //!< Scaled Reference Surface (8X for HEVC/VP9, 4X for AVC) 3725 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurfaceStage2; //!< Scaled Reference Surface (8X for HEVC/VP9, not used for AVC) 3726 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreaminBuffer; //!< VP9 Segmentation Map Streamin Buffer 3727 VDENC_Statistics_Streamout_CMD Vp9SegmentationMapStreamoutBuffer; //!< VP9 Segmentation Map Streamout Buffer 3728 union 3729 { 3730 //!< DWORD 61 3731 struct 3732 { 3733 uint32_t WeightsHistogramStreamoutOffset; //!< Weights Histogram Streamout offset 3734 }; 3735 uint32_t Value; 3736 } DW61; 3737 VDENC_Row_Store_Scratch_Buffer_Picture_CMD VdencTileRowStoreBuffer; //!< VDENC Tile Row store Buffer 3738 VDENC_Statistics_Streamout_CMD VdencCumulativeCuCountStreamoutSurface; //!< VDENC Cumulative CU count streamout surface 3739 VDENC_Statistics_Streamout_CMD VdencPaletteModeStreamoutSurface; //!< VDENC Palette Mode streamout surface 3740 uint32_t VDENC_PIPE_BUF_ADDR_STATE_DW71_73[3]; 3741 uint32_t VDENC_PIPE_BUF_ADDR_STATE_DW74_76[3]; 3742 VDENC_Row_Store_Scratch_Buffer_Picture_CMD IntraPredictionRowstoreBaseAddress; //!< Intra Prediction RowStore Base Address 3743 VDENC_Statistics_Streamout_CMD VDENC_PIPE_BUF_ADDR_STATE_DW80_82; 3744 VDENC_Colocated_MV_Picture_CMD ColocatedMvAvcWriteBuffer; //!< DW83..85, Colocated MV AVC Write Buffer 3745 VDENC_Down_Scaled_Reference_Picture_CMD Additional4xDsFwdRef; //!< DW86..88, Additional x4 DS FWD REF 3746 3747 //! \name Local enumerations 3748 3749 enum SUBOPB 3750 { 3751 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 3752 }; 3753 3754 enum SUBOPA 3755 { 3756 SUBOPA_UNNAMED0 = 0, //!< No additional details 3757 }; 3758 3759 enum OPCODE 3760 { 3761 OPCODE_VDENCPIPE = 1, //!< No additional details 3762 }; 3763 3764 enum PIPELINE 3765 { 3766 PIPELINE_MFXCOMMON = 2, //!< No additional details 3767 }; 3768 3769 enum COMMAND_TYPE 3770 { 3771 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3772 }; 3773 3774 //! \name Initializations 3775 3776 //! \brief Explicit member initialization function VDENC_PIPE_BUF_ADDR_STATE_CMDCmd::VDENC_PIPE_BUF_ADDR_STATE_CMD3777 VDENC_PIPE_BUF_ADDR_STATE_CMD() 3778 { 3779 MOS_ZeroMemory(this, sizeof(*this)); 3780 3781 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 3782 DW0.Subopb = SUBOPB_VDENCPIPEBUFADDRSTATE; 3783 DW0.Subopa = SUBOPA_UNNAMED0; 3784 DW0.Opcode = OPCODE_VDENCPIPE; 3785 DW0.Pipeline = PIPELINE_MFXCOMMON; 3786 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3787 } 3788 3789 static const size_t dwSize = 89; 3790 static const size_t byteSize = 356; 3791 }; 3792 3793 //! 3794 //! \brief VDENC_PIPE_MODE_SELECT 3795 //! \details 3796 //! Specifies which codec and hardware module is being used to encode/decode 3797 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 3798 //! specifies which codec and hardware module is being used to encode/decode 3799 //! the video data, on a per-frame basis. It also configures the hardware 3800 //! pipeline according to the active encoder/decoder operating mode for 3801 //! encoding/decoding the current picture. 3802 //! 3803 struct VDENC_PIPE_MODE_SELECT_CMD 3804 { 3805 union 3806 { 3807 //!< DWORD 0 3808 struct 3809 { 3810 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3811 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3812 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 3813 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 3814 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 3815 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3816 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3817 }; 3818 uint32_t Value; 3819 } DW0; 3820 union 3821 { 3822 //!< DWORD 1 3823 struct 3824 { 3825 uint32_t StandardSelect : __CODEGEN_BITFIELD(0, 3); //!< STANDARD_SELECT 3826 uint32_t ScalabilityMode : __CODEGEN_BITFIELD(4, 4); //!< Scalability Mode 3827 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD(5, 5); //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 3828 uint32_t VdencPakObjCmdStreamOutEnable : __CODEGEN_BITFIELD(6, 6); //!< VDEnc PAK_OBJ_CMD Stream-Out Enable 3829 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD(7, 7); //!< TLB_PREFETCH_ENABLE 3830 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD(8, 8); //!< PAK_THRESHOLD_CHECK_ENABLE 3831 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD(9, 9); //!< VDENC_STREAM_IN_ENABLE 3832 uint32_t Downscaled8XWriteDisable : __CODEGEN_BITFIELD(10, 10); //!< DownScaled 8x write Disable 3833 uint32_t Downscaled4XWriteDisable : __CODEGEN_BITFIELD(11, 11); //!< DownScaled 4x write Disable 3834 uint32_t BitDepth : __CODEGEN_BITFIELD(12, 14); //!< BIT_DEPTH 3835 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16); //!< PAK_CHROMA_SUB_SAMPLING_TYPE 3836 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17); //!< output range control after color space conversion 3837 uint32_t IsRandomAccess : __CODEGEN_BITFIELD(18, 18); //!< Is random access B frame or not 3838 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 3839 uint32_t RgbEncodingEnable : __CODEGEN_BITFIELD(20, 20); //!< RGB encoding enable 3840 uint32_t PrimaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(21, 22); //!< PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3841 uint32_t FirstSecondaryChannelSelectionForRgbEncoding : __CODEGEN_BITFIELD(23, 24); //!< FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 3842 uint32_t TileReplayEnable : __CODEGEN_BITFIELD(25, 25); //!< Tile replay enable 3843 uint32_t StreamingBufferConfig : __CODEGEN_BITFIELD(26, 27); //!< Streaming buffer config 3844 uint32_t Reserved58 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 3845 }; 3846 uint32_t Value; 3847 } DW1; 3848 union 3849 { 3850 //!< DWORD 2 3851 struct 3852 { 3853 uint32_t HmeRegionPreFetchenable : __CODEGEN_BITFIELD(0, 0); //!< HME_REGION_PRE_FETCHENABLE 3854 uint32_t Topprefetchenablemode : __CODEGEN_BITFIELD(1, 2); //!< TOPPREFETCHENABLEMODE 3855 uint32_t LeftpreFetchatwraparound : __CODEGEN_BITFIELD(3, 3); //!< LEFTPRE_FETCHATWRAPAROUND 3856 uint32_t Verticalshift32Minus1 : __CODEGEN_BITFIELD(4, 7); //!< VERTICALSHIFT32MINUS1 3857 uint32_t Hzshift32Minus1 : __CODEGEN_BITFIELD(8, 11); //!< HZSHIFT32MINUS1 3858 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3859 uint32_t NumVerticalReqMinus1 : __CODEGEN_BITFIELD(16, 19); //!< NUMVERTICALREQMINUS1 3860 uint32_t Numhzreqminus1 : __CODEGEN_BITFIELD(20, 23); //!< NUMHZREQMINUS1 3861 uint32_t PreFetchOffsetForReferenceIn16PixelIncrement : __CODEGEN_BITFIELD(24, 27); //!< PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 3862 uint32_t Reserved92 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 3863 }; 3864 uint32_t Value; 3865 } DW2; 3866 union 3867 { 3868 /* DWORD 3 */ 3869 struct 3870 { 3871 uint32_t SourceLumaPackedDataTlbPreFetchenable : __CODEGEN_BITFIELD(0, 0); /* SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE */ 3872 uint32_t SourceChromaTlbPreFetchenable : __CODEGEN_BITFIELD(1, 1); /* SOURCE_CHROMA_TLB_PRE_FETCHENABLE */ 3873 uint32_t Reserved98 : __CODEGEN_BITFIELD(2, 3); /* Reserved */ 3874 uint32_t Verticalshift32Minus1Src : __CODEGEN_BITFIELD(4, 7); /* VERTICALSHIFT32MINUS1SRC */ 3875 uint32_t Hzshift32Minus1Src : __CODEGEN_BITFIELD(8, 11); /* HZSHIFT32MINUS1SRC */ 3876 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15); /* Reserved */ 3877 uint32_t Numverticalreqminus1Src : __CODEGEN_BITFIELD(16, 19); /* NUMVERTICALREQMINUS1SRC */ 3878 uint32_t Numhzreqminus1Src : __CODEGEN_BITFIELD(20, 23); /* NUMHZREQMINUS1SRC */ 3879 uint32_t PreFetchoffsetforsource : __CODEGEN_BITFIELD(24, 27); /* PRE_FETCHOFFSETFORSOURCE */ 3880 uint32_t VDENC_PIPE_MODE_SELECT_DW3_BIT28 : __CODEGEN_BITFIELD(28, 31); 3881 }; 3882 uint32_t Value; 3883 } DW3; 3884 union 3885 { 3886 /* DWORD 4 */ 3887 struct 3888 { 3889 uint32_t Debugtilepassnum : __CODEGEN_BITFIELD(0, 3); /* DebugTilePassNum */ 3890 uint32_t Debugtilenum : __CODEGEN_BITFIELD(4, 11); /* DebugTileNum */ 3891 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT12 : __CODEGEN_BITFIELD(12, 14); 3892 uint32_t Reserved_143 : __CODEGEN_BITFIELD(15, 15); 3893 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT16 : __CODEGEN_BITFIELD(16, 17); 3894 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT18 : __CODEGEN_BITFIELD(18, 19); 3895 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT20 : __CODEGEN_BITFIELD(20, 20); 3896 uint32_t VDENC_PIPE_MODE_SELECT_DW4_BIT21 : __CODEGEN_BITFIELD(21, 21); 3897 uint32_t Reserved_150 : __CODEGEN_BITFIELD(22, 31); 3898 }; 3899 uint32_t Value; 3900 } DW4; 3901 union 3902 { 3903 struct 3904 { 3905 uint32_t FrameNumber : __CODEGEN_BITFIELD(0, 3); /* Frame Number */ 3906 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT4 : __CODEGEN_BITFIELD(4, 5); 3907 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT6 : __CODEGEN_BITFIELD(6, 7); 3908 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT8 : __CODEGEN_BITFIELD(8, 8); 3909 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT9 : __CODEGEN_BITFIELD(9, 9); 3910 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT10 : __CODEGEN_BITFIELD(10, 10); 3911 uint32_t CaptureMode : __CODEGEN_BITFIELD(11, 12); /* CAPTURE_MODE */ 3912 uint32_t ParallelCaptureAndEncodeSessionId : __CODEGEN_BITFIELD(13, 15); /* PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID */ 3913 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT16 : __CODEGEN_BITFIELD(16, 16); 3914 uint32_t VDENC_PIPE_MODE_SELECT_DW5_BIT17 : __CODEGEN_BITFIELD(17, 17); 3915 uint32_t Reserved185 : __CODEGEN_BITFIELD(18, 23); /* Reserved */ 3916 uint32_t TailPointerReadFrequency : __CODEGEN_BITFIELD(24, 31); /* Tail pointer read frequency */ 3917 }; 3918 uint32_t Value; 3919 } DW5; 3920 3921 //! \name Local enumerations 3922 3923 enum SUBOPB 3924 { 3925 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 3926 }; 3927 3928 enum SUBOPA 3929 { 3930 SUBOPA_UNNAMED0 = 0, //!< No additional details 3931 }; 3932 3933 enum OPCODE 3934 { 3935 OPCODE_VDENCPIPE = 1, //!< No additional details 3936 }; 3937 3938 enum PIPELINE 3939 { 3940 PIPELINE_MFXCOMMON = 2, //!< No additional details 3941 }; 3942 3943 enum COMMAND_TYPE 3944 { 3945 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3946 }; 3947 3948 enum STANDARD_SELECT 3949 { 3950 STANDARD_SELECT_AVC = 2, //!< No additional details 3951 }; 3952 3953 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 3954 //! \details 3955 //! This field controls whether the frame statistics stream-out is enabled. 3956 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 3957 { 3958 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 3959 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 3960 }; 3961 3962 //! \brief TLB_PREFETCH_ENABLE 3963 //! \details 3964 //! This field controls whether TLB prefetching is enabled. 3965 enum TLB_PREFETCH_ENABLE 3966 { 3967 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 3968 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 3969 }; 3970 3971 //! \brief PAK_THRESHOLD_CHECK_ENABLE 3972 //! \details 3973 //! For AVC standard: This field controls whether VDEnc will check the 3974 //! PAK indicator for bits overflow and terminates the slice. This mode is 3975 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 3976 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 3977 //! Minus One to terminate the slice. This feature is also referred to as 3978 //! slice size conformance. 3979 //! For HEVC standard: This bit is used to enable dynamic slice size 3980 //! control. 3981 enum PAK_THRESHOLD_CHECK_ENABLE 3982 { 3983 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 3984 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 3985 }; 3986 3987 //! \brief VDENC_STREAM_IN_ENABLE 3988 //! \details 3989 //! This field controls whether VDEnc will read the stream-in surface 3990 //! that is programmed. Currently the stream-in surface has MB level QP, 3991 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 3992 //! individual enables for each of the fields is programmed in the 3993 //! VDENC_IMG_STATE. 3994 //! (ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 3995 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable). 3996 //! This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 3997 //! reserved and should be set to zero. 3998 enum VDENC_STREAM_IN_ENABLE 3999 { 4000 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 4001 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 4002 }; 4003 4004 //! \brief BIT_DEPTH 4005 //! \details 4006 //! This parameter indicates the PAK bit depth. The valid values for this 4007 //! are 0 / 2 in HEVC / VP9 standard. In AVC standard this field should be 4008 //! set to 0. 4009 enum BIT_DEPTH 4010 { 4011 BIT_DEPTH_8BIT = 0, //!< No additional details 4012 BIT_DEPTH_10BIT = 2, //!< No additional details 4013 BIT_DEPTH_12BIT = 3, //!< No additional details 4014 }; 4015 4016 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 4017 //! \details 4018 //! This field is applicable only in HEVC and VP9. In AVC, this field is ignored. 4019 enum PAK_CHROMA_SUB_SAMPLING_TYPE 4020 { 4021 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 4022 PAK_CHROMA_SUB_SAMPLING_TYPE_4_4_4 = 3, //!< HEVC RExt 444, VP9 444 profiles. 4023 }; 4024 4025 //! \brief PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4026 //! \details 4027 //! In RGB encoding, any one of the channel could be primary. This field is 4028 //! used for selcting primary channel 4029 enum PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4030 { 4031 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is primary channel 4032 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is primary channel. 4033 PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is primary channel 4034 }; 4035 4036 //! \brief FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4037 //! \details 4038 //! In RGB encoding, any one of the channel could be primary. This field is 4039 //! used for selcting primary channel 4040 enum FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING 4041 { 4042 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED0 = 0, //!< Channel R is first secondary channel 4043 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1 = 1, //!< Channel G is first secondary channel 4044 FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2 = 2, //!< Channel B is first secondary channel. 4045 }; 4046 4047 //! \brief HME_REGION_PRE_FETCHENABLE 4048 //! \details 4049 //! When this bit is set, for all reference frames HME region pages are pre-fetched. 4050 enum HME_REGION_PRE_FETCHENABLE 4051 { 4052 HME_REGION_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 4053 HME_REGION_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 4054 }; 4055 4056 //! \brief TOPPREFETCHENABLEMODE 4057 //! \details 4058 //! Top Pre-fetch enable Mode 4059 enum TOPPREFETCHENABLEMODE 4060 { 4061 TOPPREFETCHENABLEMODE_UNNAMED0 = 0, //!< No additional details 4062 TOPPREFETCHENABLEMODE_UNNAMED1 = 1, //!< No additional details 4063 }; 4064 4065 //! \brief LEFTPRE_FETCHATWRAPAROUND 4066 //! \details 4067 //! Left pre-fetch enabled on wraparound 4068 enum LEFTPRE_FETCHATWRAPAROUND 4069 { 4070 LEFTPRE_FETCHATWRAPAROUND_UNNAMED1 = 1, //!< No additional details 4071 }; 4072 4073 enum VERTICALSHIFT32MINUS1 4074 { 4075 VERTICALSHIFT32MINUS1_UNNAMED0 = 0, //!< No additional details 4076 }; 4077 4078 //! \brief HZSHIFT32MINUS1 4079 //! \details 4080 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 4081 enum HZSHIFT32MINUS1 4082 { 4083 HZSHIFT32MINUS1_UNNAMED3 = 3, //!< No additional details 4084 }; 4085 4086 //! \brief NUMHZREQMINUS1 4087 //! \details 4088 //! Number of Vertical requests in each region for a constant horizontal position. 4089 enum NUMVERTICALREQMINUS1 4090 { 4091 NUMVERTICALREQMINUS1_UNNAMED11 = 11, //!< No additional details 4092 }; 4093 4094 //! \brief NUMHZREQMINUS1 4095 //! \details 4096 //! Number of Horizontal Requests minus 1 at row begining. 4097 enum NUMHZREQMINUS1 4098 { 4099 NUMHZREQMINUS1_UNNAMED2 = 2, //!< No additional details 4100 }; 4101 4102 enum PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT 4103 { 4104 PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT_UNNAMED0 = 0, //!< No additional details 4105 }; 4106 4107 //! \brief SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 4108 //! \details 4109 //! When this bit is set, Source Luma / Packed data TLB pre-fetches are 4110 //! performed. 4111 enum SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE 4112 { 4113 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 4114 SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 4115 }; 4116 4117 //! \brief SOURCE_CHROMA_TLB_PRE_FETCHENABLE 4118 //! \details 4119 //! When this bit is set, Source Chroma TLB pre-fetches are performed. 4120 enum SOURCE_CHROMA_TLB_PRE_FETCHENABLE 4121 { 4122 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED0 = 0, //!< No additional details 4123 SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED1 = 1, //!< No additional details 4124 }; 4125 4126 enum VERTICALSHIFT32MINUS1SRC 4127 { 4128 VERTICALSHIFT32MINUS1SRC_UNNAMED0 = 0, //!< No additional details 4129 }; 4130 4131 //! \brief HZSHIFT32MINUS1SRC 4132 //! \details 4133 //! Horizontal_shift >= LCU_size and Horizontal_shift prefetch_offset 4134 enum HZSHIFT32MINUS1SRC 4135 { 4136 HZSHIFT32MINUS1SRC_UNNAMED0 = 0, //!< No additional details 4137 HZSHIFT32MINUS1SRC_UNNAMED3 = 3, //!< No additional details 4138 }; 4139 4140 //! \brief NUMVERTICALREQMINUS1SRC 4141 //! \details 4142 //! Number of Horizontal requests Minus 1 for source 4143 enum NUMVERTICALREQMINUS1SRC 4144 { 4145 NUMVERTICALREQMINUS1SRC_UNNAMED0 = 0, //!< This is the valid for AVC 4146 NUMVERTICALREQMINUS1SRC_UNNAMED1 = 1, //!< This is the valid value for HEVC 4147 }; 4148 4149 //! \brief NUMHZREQMINUS1SRC 4150 //! \details 4151 //! Number of Horizontal requests Minus 1 for source 4152 enum NUMHZREQMINUS1SRC 4153 { 4154 NUMHZREQMINUS1SRC_UNNAMED0 = 0, //!< No additional details 4155 }; 4156 4157 //! \brief PRE_FETCHOFFSETFORSOURCE 4158 //! \details 4159 //! Pre-fetch offset for Reference in 16 pixel increment. 4160 enum PRE_FETCHOFFSETFORSOURCE 4161 { 4162 PRE_FETCHOFFSETFORSOURCE_UNNAMED0 = 0, //!< No additional details 4163 PRE_FETCHOFFSETFORSOURCE_UNNAMED_4 = 4, //!< This value is applicable in HEVC mode 4164 PRE_FETCHOFFSETFORSOURCE_UNNAMED7 = 7, //!< This Value is applicable in AVC mode 4165 }; 4166 4167 enum CAPTURE_MODE 4168 { 4169 CAPTURE_MODE_UNNAMED0 = 0, //!< No Parallel capture 4170 CAPTURE_MODE_UNNAMED1 = 1, //!< Parallel encode from Display overlay 4171 CAPTURE_MODE_CAMERA = 2, //!< Parallel encode from Camera Pipe 4172 CAPTURE_MODE_UNNAMED3 = 3, //!< Reserved 4173 }; 4174 4175 enum STREAMING_BUFFER_CONFIG 4176 { 4177 STREAMING_BUFFER_UNSUPPORTED = 0, 4178 STREAMING_BUFFER_64 = 1, 4179 STREAMING_BUFFER_128 = 2, 4180 STREAMING_BUFFER_256 = 3, 4181 }; 4182 4183 enum PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID 4184 { 4185 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED0 = 0, //!< Display tailpointer address location 00ED0h-00ED3h 4186 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED1 = 1, //!< Display tailpointer address location 00ED4h-00ED7h 4187 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED2 = 2, //!< Display tailpointer address location 00ED8h-00EDBh 4188 PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED3 = 3, //!< Display tailpointer address location 00EDCh-00EDFh 4189 }; 4190 4191 //! \name Initializations 4192 4193 //! \brief Explicit member initialization function VDENC_PIPE_MODE_SELECT_CMDCmd::VDENC_PIPE_MODE_SELECT_CMD4194 VDENC_PIPE_MODE_SELECT_CMD() 4195 { 4196 MOS_ZeroMemory(this, sizeof(*this)); 4197 4198 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4199 DW0.Subopb = SUBOPB_VDENCPIPEMODESELECT; 4200 DW0.Subopa = SUBOPA_UNNAMED0; 4201 DW0.Opcode = OPCODE_VDENCPIPE; 4202 DW0.Pipeline = PIPELINE_MFXCOMMON; 4203 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4204 4205 DW1.FrameStatisticsStreamOutEnable = FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE; 4206 DW1.TlbPrefetchEnable = TLB_PREFETCH_ENABLE_DISABLE; 4207 DW1.PakThresholdCheckEnable = PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE; 4208 DW1.VdencStreamInEnable = VDENC_STREAM_IN_ENABLE_DISABLE; 4209 DW1.BitDepth = BIT_DEPTH_8BIT; 4210 DW1.PrimaryChannelSelectionForRgbEncoding = PRIMARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED1; 4211 DW1.FirstSecondaryChannelSelectionForRgbEncoding = FIRST_SECONDARY_CHANNEL_SELECTION_FOR_RGB_ENCODING_UNNAMED2; 4212 DW1.StreamingBufferConfig = STREAMING_BUFFER_UNSUPPORTED; 4213 4214 DW2.HmeRegionPreFetchenable = HME_REGION_PRE_FETCHENABLE_UNNAMED1; 4215 DW2.Topprefetchenablemode = TOPPREFETCHENABLEMODE_UNNAMED0; 4216 DW2.LeftpreFetchatwraparound = LEFTPRE_FETCHATWRAPAROUND_UNNAMED1; 4217 DW2.Verticalshift32Minus1 = VERTICALSHIFT32MINUS1_UNNAMED0; 4218 DW2.Hzshift32Minus1 = HZSHIFT32MINUS1_UNNAMED3; 4219 DW2.NumVerticalReqMinus1 = NUMVERTICALREQMINUS1_UNNAMED11; 4220 DW2.Numhzreqminus1 = NUMHZREQMINUS1_UNNAMED2; 4221 DW2.PreFetchOffsetForReferenceIn16PixelIncrement = PRE_FETCH_OFFSET_FOR_REFERENCE_IN_16_PIXEL_INCREMENT_UNNAMED0; 4222 4223 DW3.SourceLumaPackedDataTlbPreFetchenable = SOURCE_LUMAPACKED_DATA_TLB_PRE_FETCHENABLE_UNNAMED0; 4224 DW3.SourceChromaTlbPreFetchenable = SOURCE_CHROMA_TLB_PRE_FETCHENABLE_UNNAMED0; 4225 DW3.Verticalshift32Minus1Src = VERTICALSHIFT32MINUS1SRC_UNNAMED0; 4226 DW3.Hzshift32Minus1Src = HZSHIFT32MINUS1SRC_UNNAMED0; 4227 DW3.Numverticalreqminus1Src = NUMVERTICALREQMINUS1SRC_UNNAMED0; 4228 DW3.Numhzreqminus1Src = NUMHZREQMINUS1SRC_UNNAMED0; 4229 DW3.PreFetchoffsetforsource = PRE_FETCHOFFSETFORSOURCE_UNNAMED0; 4230 4231 DW5.CaptureMode = CAPTURE_MODE_UNNAMED0; 4232 DW5.ParallelCaptureAndEncodeSessionId = PARALLEL_CAPTURE_AND_ENCODE_SESSION_ID_UNNAMED0; 4233 } 4234 4235 static const size_t dwSize = 6; 4236 static const size_t byteSize = 24; 4237 }; 4238 4239 //! 4240 //! \brief VDENC_REF_SURFACE_STATE 4241 //! \details 4242 //! This command specifies the surface state parameters for the normal 4243 //! reference surfaces. 4244 //! 4245 struct VDENC_REF_SURFACE_STATE_CMD 4246 { 4247 union 4248 { 4249 //!< DWORD 0 4250 struct 4251 { 4252 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4253 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4254 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4255 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4256 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4257 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4258 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4259 }; 4260 uint32_t Value; 4261 } DW0; 4262 union 4263 { 4264 //!< DWORD 1 4265 struct 4266 { 4267 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 2); //!< Surface ID 4268 uint32_t Reserved : __CODEGEN_BITFIELD(3, 31); //!< Reserved 4269 }; 4270 uint32_t Value; 4271 } DW1; 4272 VDENC_Surface_State_Fields_CMD Dwords25; //!< Dwords 2..5 4273 4274 //! \name Local enumerations 4275 4276 enum SUBOPB 4277 { 4278 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 4279 }; 4280 4281 enum SUBOPA 4282 { 4283 SUBOPA_UNNAMED0 = 0, //!< No additional details 4284 }; 4285 4286 enum OPCODE 4287 { 4288 OPCODE_VDENCPIPE = 1, //!< No additional details 4289 }; 4290 4291 enum PIPELINE 4292 { 4293 PIPELINE_MFXCOMMON = 2, //!< No additional details 4294 }; 4295 4296 enum COMMAND_TYPE 4297 { 4298 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4299 }; 4300 4301 //! \name Initializations 4302 4303 //! \brief Explicit member initialization function VDENC_REF_SURFACE_STATE_CMDCmd::VDENC_REF_SURFACE_STATE_CMD4304 VDENC_REF_SURFACE_STATE_CMD() 4305 { 4306 MOS_ZeroMemory(this, sizeof(*this)); 4307 4308 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4309 DW0.Subopb = SUBOPB_VDENCREFSURFACESTATE; 4310 DW0.Subopa = SUBOPA_UNNAMED0; 4311 DW0.Opcode = OPCODE_VDENCPIPE; 4312 DW0.Pipeline = PIPELINE_MFXCOMMON; 4313 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4314 } 4315 4316 static const size_t dwSize = 6; 4317 static const size_t byteSize = 24; 4318 }; 4319 4320 //! 4321 //! \brief VDENC_SRC_SURFACE_STATE 4322 //! \details 4323 //! This command specifies the uncompressed original input picture to be 4324 //! encoded. The actual base address is defined in the 4325 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 4326 //! pixels and garbage will be there at the end of each line. The following 4327 //! describes all the different formats that are supported in WLV+ VDEnc: 4328 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 4329 //! 0 (the only format supported for video codec); vertical UV offset is MB 4330 //! aligned; UV xoffsets = 0. 4331 //! This surface state here is identical to the Surface State for 4332 //! deinterlace and sample_8x8 messages described in the Shared Function 4333 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 4334 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 4335 //! is designed to guarantee legal memory accesses (read and write). For the 4336 //! remaining cases, indirect object base address, indirect object address 4337 //! upper bound, object data start address (offset) and object data length 4338 //! are used to fully specified their corresponding buffer. This mechanism 4339 //! is chosen over the pixel surface type because of their variable record 4340 //! sizes. All row store surfaces are linear surface. Their addresses are 4341 //! programmed in VDEnc_Pipe_Buf_Base_State. 4342 //! 4343 struct VDENC_SRC_SURFACE_STATE_CMD 4344 { 4345 union 4346 { 4347 //!< DWORD 0 4348 struct 4349 { 4350 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4351 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4352 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4353 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4354 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4355 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4356 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4357 }; 4358 uint32_t Value; 4359 } DW0; 4360 union 4361 { 4362 //!< DWORD 1 4363 struct 4364 { 4365 uint32_t Reserved32; //!< Reserved 4366 }; 4367 uint32_t Value; 4368 } DW1; 4369 VDENC_Surface_State_Fields_CMD Dwords25; //!< Dwords 2..5 4370 4371 //! \name Local enumerations 4372 4373 enum SUBOPB 4374 { 4375 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 4376 }; 4377 4378 enum SUBOPA 4379 { 4380 SUBOPA_UNNAMED0 = 0, //!< No additional details 4381 }; 4382 4383 enum OPCODE 4384 { 4385 OPCODE_VDENCPIPE = 1, //!< No additional details 4386 }; 4387 4388 enum PIPELINE 4389 { 4390 PIPELINE_MFXCOMMON = 2, //!< No additional details 4391 }; 4392 4393 enum COMMAND_TYPE 4394 { 4395 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4396 }; 4397 4398 //! \name Initializations 4399 4400 //! \brief Explicit member initialization function VDENC_SRC_SURFACE_STATE_CMDCmd::VDENC_SRC_SURFACE_STATE_CMD4401 VDENC_SRC_SURFACE_STATE_CMD() 4402 { 4403 MOS_ZeroMemory(this, sizeof(*this)); 4404 4405 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4406 DW0.Subopb = SUBOPB_VDENCSRCSURFACESTATE; 4407 DW0.Subopa = SUBOPA_UNNAMED0; 4408 DW0.Opcode = OPCODE_VDENCPIPE; 4409 DW0.Pipeline = PIPELINE_MFXCOMMON; 4410 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4411 } 4412 4413 static const size_t dwSize = 6; 4414 static const size_t byteSize = 24; 4415 }; 4416 4417 //! 4418 //! \brief VDENC_WALKER_STATE 4419 //! \details 4420 //! 4421 //! 4422 struct VDENC_WALKER_STATE_CMD 4423 { 4424 union 4425 { 4426 struct 4427 { 4428 uint32_t Length : __CODEGEN_BITFIELD(0, 11); //!< LENGTH 4429 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4430 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4431 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4432 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4433 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4434 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4435 }; 4436 uint32_t Value; 4437 } DW0; 4438 union 4439 { 4440 struct 4441 { 4442 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD(0, 8); //!< MB/LCU Start Y Position 4443 uint32_t Reserved41 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 4444 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24); //!< MB/LCU Start X Position 4445 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27); //!< Reserved 4446 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28); //!< First Super Slice 4447 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4448 }; 4449 uint32_t Value; 4450 } DW1; 4451 union 4452 { 4453 struct 4454 { 4455 uint32_t NextsliceMbStartYPosition : __CODEGEN_BITFIELD(0, 9); //!< NextSlice MB Start Y Position 4456 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15); //!< Reserved 4457 uint32_t NextsliceMbLcuStartXPosition : __CODEGEN_BITFIELD(16, 25); //!< NextSlice MB/LCU Start X Position 4458 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 4459 }; 4460 uint32_t Value; 4461 } DW2; 4462 4463 //! \name Local enumerations 4464 4465 enum LENGTH 4466 { 4467 LENGTH_UNNAMED1 = 1, //!< No additional details 4468 }; 4469 4470 enum SUBOPB 4471 { 4472 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 4473 }; 4474 4475 enum SUBOPA 4476 { 4477 SUBOPA_UNNAMED0 = 0, //!< No additional details 4478 }; 4479 4480 enum OPCODE 4481 { 4482 OPCODE_VDENCPIPE = 1, //!< No additional details 4483 }; 4484 4485 enum PIPELINE 4486 { 4487 PIPELINE_MFXCOMMON = 2, //!< No additional details 4488 }; 4489 4490 enum COMMAND_TYPE 4491 { 4492 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4493 }; 4494 4495 //! \name Initializations 4496 4497 //! \brief Explicit member initialization function VDENC_WALKER_STATE_CMDCmd::VDENC_WALKER_STATE_CMD4498 VDENC_WALKER_STATE_CMD() 4499 { 4500 MOS_ZeroMemory(this, sizeof(*this)); 4501 4502 DW0.Length = LENGTH_UNNAMED1; 4503 DW0.Subopb = SUBOPB_VDENCWALKERSTATE; 4504 DW0.Subopa = SUBOPA_UNNAMED0; 4505 DW0.Opcode = OPCODE_VDENCPIPE; 4506 DW0.Pipeline = PIPELINE_MFXCOMMON; 4507 DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4508 } 4509 4510 static const size_t dwSize = 3; 4511 static const size_t byteSize = 12; 4512 }; 4513 4514 //! 4515 //! \brief VDENC_CONTROL_STATE 4516 //! \details 4517 //! 4518 //! 4519 struct VDENC_CONTROL_STATE_CMD 4520 { 4521 union 4522 { 4523 //!< DWORD 0 4524 struct 4525 { 4526 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< Dword Length 4527 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4528 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< Media Instruction Command 4529 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< Media Instruction Opcode 4530 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< Pipeline Type 4531 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< Command Type 4532 }; 4533 uint32_t Value; 4534 } DW0; 4535 union 4536 { 4537 //!< DWORD 1 4538 struct 4539 { 4540 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 4541 uint32_t VdencInitialization : __CODEGEN_BITFIELD(1, 1); //!< VDenc Initialization 4542 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved 4543 }; 4544 uint32_t Value; 4545 } DW1; 4546 4547 //! \name Local enumerations 4548 4549 //! \name Initializations 4550 4551 //! \brief Explicit member initialization function VDENC_CONTROL_STATE_CMDCmd::VDENC_CONTROL_STATE_CMD4552 VDENC_CONTROL_STATE_CMD() 4553 { 4554 MOS_ZeroMemory(this, sizeof(*this)); 4555 4556 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 4557 DW0.MediaInstructionCommand = 0xB; 4558 DW0.MediaInstructionOpcode = 0x1; 4559 DW0.PipelineType = 0x2; 4560 DW0.CommandType = 0x3; 4561 } 4562 4563 static const size_t dwSize = 2; 4564 static const size_t byteSize = 8; 4565 }; 4566 4567 //! 4568 //! \brief VDENC_AVC_SLICE_STATE 4569 //! \details 4570 //! 4571 //! 4572 struct VDENC_AVC_SLICE_STATE_CMD 4573 { 4574 union 4575 { 4576 struct 4577 { 4578 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4579 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4580 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4581 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4582 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4583 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4584 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4585 }; 4586 uint32_t Value; 4587 } DW0; 4588 union 4589 { 4590 struct 4591 { 4592 uint32_t RoundIntra : __CODEGEN_BITFIELD(0, 2); //!< RoundIntra 4593 uint32_t RoundIntraEnable : __CODEGEN_BITFIELD(3, 3); //!< RoundIntraEnable 4594 uint32_t RoundInter : __CODEGEN_BITFIELD(4, 6); //!< RoundInter 4595 uint32_t RoundInterEnable : __CODEGEN_BITFIELD(7, 7); //!< RoundInterEnable 4596 uint32_t Reserved32 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 4597 }; 4598 uint32_t Value; 4599 } DW1; 4600 union 4601 { 4602 struct 4603 { 4604 uint32_t Reserved64; //!< Reserved 4605 }; 4606 uint32_t Value; 4607 } DW2; 4608 union 4609 { 4610 struct 4611 { 4612 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD(0, 2); //!< Log 2 Weight Denom Luma 4613 uint32_t Reserved99 : __CODEGEN_BITFIELD(3, 31); //!< Reserved 4614 }; 4615 uint32_t Value; 4616 } DW3; 4617 4618 //! \name Local enumerations 4619 4620 enum SUBOPB 4621 { 4622 SUBOPB_VDENCAVCSLICESTATE = 12, //!< No additional details 4623 }; 4624 4625 enum SUBOPA 4626 { 4627 SUBOPA_UNNAMED0 = 0, //!< No additional details 4628 }; 4629 4630 enum OPCODE 4631 { 4632 OPCODE_VDENCPIPE = 1, //!< No additional details 4633 }; 4634 4635 enum PIPELINE 4636 { 4637 PIPELINE_MFXCOMMON = 2, //!< No additional details 4638 }; 4639 4640 enum COMMAND_TYPE 4641 { 4642 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4643 }; 4644 4645 //! \name Initializations 4646 4647 //! \brief Explicit member initialization function VDENC_AVC_SLICE_STATE_CMDCmd::VDENC_AVC_SLICE_STATE_CMD4648 VDENC_AVC_SLICE_STATE_CMD() 4649 { 4650 MOS_ZeroMemory(this, sizeof(*this)); 4651 4652 DW0.Value = 0x708c0002; 4653 } 4654 4655 static const size_t dwSize = 4; 4656 static const size_t byteSize = 16; 4657 }; 4658 4659 struct VDENC_HEVC_VP9_TILE_SLICE_STATE_CMD 4660 { 4661 union 4662 { 4663 struct 4664 { 4665 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4666 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4667 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 4668 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22); //!< SUBOPA 4669 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26); //!< OPCODE 4670 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4671 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4672 }; 4673 uint32_t Value; 4674 } DW0; 4675 union 4676 { 4677 struct 4678 { 4679 uint32_t Reserved32; //!< Reserved 4680 }; 4681 uint32_t Value; 4682 } DW1; 4683 union 4684 { 4685 struct 4686 { 4687 uint32_t Reserved64; //!< Reserved 4688 }; 4689 uint32_t Value; 4690 } DW2; 4691 union 4692 { 4693 struct 4694 { 4695 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD(0, 2); //!< Log 2 Weight Denom Luma 4696 uint32_t Reserved99 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 4697 uint32_t HevcVp9Log2WeightDenomLuma : __CODEGEN_BITFIELD(4, 6); //!< HEVC/VP9 Log 2 Weight Denom Luma 4698 uint32_t Reserved103 : __CODEGEN_BITFIELD(7, 8); //!< Reserved 4699 uint32_t NumParEngine : __CODEGEN_BITFIELD(9, 10); //!< NUM_PAR_ENGINE 4700 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15); //!< Reserved 4701 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD(16, 16); //!< Tile Row store Select 4702 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD(17, 19); //!< Log 2 Weight Denom Chroma 4703 uint32_t Reserved113 : __CODEGEN_BITFIELD(20, 23); //!< Reserved 4704 uint32_t TileNumber : __CODEGEN_BITFIELD(24, 31); //!< Tile number 4705 }; 4706 uint32_t Value; 4707 } DW3; 4708 union 4709 { 4710 struct 4711 { 4712 uint32_t TileStartCtbY : __CODEGEN_BITFIELD(0, 15); //!< Tile Start CTB-Y 4713 uint32_t TileStartCtbX : __CODEGEN_BITFIELD(16, 31); //!< Tile Start CTB-X 4714 }; 4715 uint32_t Value; 4716 } DW4; 4717 union 4718 { 4719 struct 4720 { 4721 uint32_t TileWidth : __CODEGEN_BITFIELD(0, 15); //!< Tile Width 4722 uint32_t TileHeight : __CODEGEN_BITFIELD(16, 31); //!< Tile Height 4723 }; 4724 uint32_t Value; 4725 } DW5; 4726 union 4727 { 4728 struct 4729 { 4730 uint32_t StreaminOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< Streamin Offset enable 4731 uint32_t Reserved193 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4732 uint32_t TileStreaminOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile Streamin Offset 4733 }; 4734 uint32_t Value; 4735 } DW6; 4736 union 4737 { 4738 struct 4739 { 4740 uint32_t RowStoreOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< Row store Offset enable 4741 uint32_t Reserved225 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4742 uint32_t TileRowstoreOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile Rowstore Offset 4743 }; 4744 uint32_t Value; 4745 } DW7; 4746 union 4747 { 4748 struct 4749 { 4750 uint32_t TileStreamoutOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< Tile streamout offset enable 4751 uint32_t Reserved257 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4752 uint32_t TileStreamoutOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile streamout offset 4753 }; 4754 uint32_t Value; 4755 } DW8; 4756 union 4757 { 4758 struct 4759 { 4760 uint32_t LcuStreamOutOffsetEnable : __CODEGEN_BITFIELD(0, 0); //!< LCU stream out offset enable 4761 uint32_t Reserved289 : __CODEGEN_BITFIELD(1, 5); //!< Reserved 4762 uint32_t TileLcuStreamOutOffset : __CODEGEN_BITFIELD(6, 31); //!< Tile LCU stream out offset 4763 }; 4764 uint32_t Value; 4765 } DW9; 4766 union 4767 { 4768 struct 4769 { 4770 uint32_t Reserved320; //!< Reserved 4771 }; 4772 uint32_t Value; 4773 } DW10; 4774 union 4775 { 4776 struct 4777 { 4778 uint32_t DeltaQp : __CODEGEN_BITFIELD(0, 7); /* DELTA_QP*/ 4779 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW11_BIT8 : __CODEGEN_BITFIELD(8, 17); 4780 uint32_t Reserved370 : __CODEGEN_BITFIELD(18, 31); /* Reserved*/ 4781 }; 4782 uint32_t Value; 4783 } DW11; 4784 union 4785 { 4786 struct 4787 { 4788 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT0 : __CODEGEN_BITFIELD(0, 2); 4789 uint32_t Reserved387 : __CODEGEN_BITFIELD(3, 7); 4790 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT8 : __CODEGEN_BITFIELD(8, 15); 4791 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT16 : __CODEGEN_BITFIELD(16, 17); 4792 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT18 : __CODEGEN_BITFIELD(18, 22); 4793 uint32_t Reserved407 : __CODEGEN_BITFIELD(23, 23); 4794 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW12_BIT24 : __CODEGEN_BITFIELD(24, 25); 4795 uint32_t PaletteModeEnable : __CODEGEN_BITFIELD(26, 26); /* Palette Mode Enable*/ 4796 uint32_t IbcControl : __CODEGEN_BITFIELD(27, 28); /* IBC_CONTROL*/ 4797 uint32_t Reserved413 : __CODEGEN_BITFIELD(29, 31); /* Reserved*/ 4798 }; 4799 uint32_t Value; 4800 } DW12; 4801 union 4802 { 4803 struct 4804 { 4805 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW13_BIT0 : __CODEGEN_BITFIELD(0, 9); 4806 uint32_t Reserved426 : __CODEGEN_BITFIELD(10, 15); 4807 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW13_BIT16 : __CODEGEN_BITFIELD(16, 25); 4808 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 31); 4809 }; 4810 uint32_t Value; 4811 } DW13; 4812 union 4813 { 4814 struct 4815 { 4816 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT0 : __CODEGEN_BITFIELD(0, 5); 4817 uint32_t Reserved454 : __CODEGEN_BITFIELD(6, 7); 4818 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT8 : __CODEGEN_BITFIELD(8, 13); 4819 uint32_t Reserved462 : __CODEGEN_BITFIELD(14, 15); 4820 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT16 : __CODEGEN_BITFIELD(16, 20); 4821 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT21 : __CODEGEN_BITFIELD(21, 22); 4822 uint32_t Reserved471 : __CODEGEN_BITFIELD(23, 23); 4823 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT24 : __CODEGEN_BITFIELD(24, 30); 4824 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW14_BIT31 : __CODEGEN_BITFIELD(31, 31); 4825 }; 4826 uint32_t Value; 4827 } DW14; 4828 union 4829 { 4830 struct 4831 { 4832 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW15_BIT0 : __CODEGEN_BITFIELD(0, 9); 4833 uint32_t Reserved490 : __CODEGEN_BITFIELD(10, 15); 4834 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW15_BIT16 : __CODEGEN_BITFIELD(16, 25); 4835 uint32_t Reserved506 : __CODEGEN_BITFIELD(26, 31); 4836 }; 4837 uint32_t Value; 4838 } DW15; 4839 union 4840 { 4841 struct 4842 { 4843 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT0 : __CODEGEN_BITFIELD(0, 5); 4844 uint32_t Reserved518 : __CODEGEN_BITFIELD(6, 7); 4845 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT8 : __CODEGEN_BITFIELD(8, 13); 4846 uint32_t Reserved526 : __CODEGEN_BITFIELD(14, 15); 4847 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT16 : __CODEGEN_BITFIELD(16, 21); 4848 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 23); 4849 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT24 : __CODEGEN_BITFIELD(24, 28); 4850 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT29 : __CODEGEN_BITFIELD(29, 29); 4851 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT30 : __CODEGEN_BITFIELD(30, 30); 4852 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW16_BIT31 : __CODEGEN_BITFIELD(31, 31); 4853 }; 4854 uint32_t Value; 4855 } DW16; 4856 union 4857 { 4858 struct 4859 { 4860 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW17_BIT0 : __CODEGEN_BITFIELD(0, 0); 4861 uint32_t Reserved545 : __CODEGEN_BITFIELD(1, 5); 4862 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW17_BIT6 : __CODEGEN_BITFIELD(6, 31); 4863 }; 4864 uint32_t Value; 4865 } DW17; 4866 union 4867 { 4868 struct 4869 { 4870 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW18_BIT0 : __CODEGEN_BITFIELD(0, 0); 4871 uint32_t Reserved577 : __CODEGEN_BITFIELD(1, 5); 4872 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW18_BIT6 : __CODEGEN_BITFIELD(6, 31); 4873 }; 4874 uint32_t Value; 4875 } DW18; 4876 union 4877 { 4878 struct 4879 { 4880 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW19_BIT0; 4881 }; 4882 uint32_t Value; 4883 } DW19; 4884 union 4885 { 4886 struct 4887 { 4888 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW20_BIT0; 4889 }; 4890 uint32_t Value; 4891 } DW20; 4892 union 4893 { 4894 struct 4895 { 4896 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW21_BIT0; 4897 }; 4898 uint32_t Value; 4899 } DW21; 4900 union 4901 { 4902 struct 4903 { 4904 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW22_BIT0; 4905 }; 4906 uint32_t Value; 4907 } DW22; 4908 union 4909 { 4910 struct 4911 { 4912 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW23_BIT0; 4913 }; 4914 uint32_t Value; 4915 } DW23; 4916 union 4917 { 4918 struct 4919 { 4920 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW24_BIT0; 4921 }; 4922 uint32_t Value; 4923 } DW24; 4924 union 4925 { 4926 struct 4927 { 4928 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW25_BIT0; 4929 }; 4930 uint32_t Value; 4931 } DW25; 4932 union 4933 { 4934 struct 4935 { 4936 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW26_BIT0; 4937 }; 4938 uint32_t Value; 4939 } DW26; 4940 union 4941 { 4942 struct 4943 { 4944 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW27_BIT0 : __CODEGEN_BITFIELD(0, 0); 4945 uint32_t Reserved15 : __CODEGEN_BITFIELD(1, 5); 4946 uint32_t VDENC_HEVC_VP9_TILE_SLICE_STATE_DW27_BIT6 : __CODEGEN_BITFIELD(6, 31); 4947 }; 4948 uint32_t Value; 4949 } DW27; 4950 4951 //! \brief Explicit member initialization function VDENC_HEVC_VP9_TILE_SLICE_STATE_CMDCmd::VDENC_HEVC_VP9_TILE_SLICE_STATE_CMD4952 VDENC_HEVC_VP9_TILE_SLICE_STATE_CMD() 4953 { 4954 MOS_ZeroMemory(this, sizeof(*this)); 4955 4956 DW0.Value = 0x708d001a; 4957 4958 DW14.Value = 0x3f400000; 4959 4960 DW16.Value = 0x003f3f3f; 4961 } 4962 4963 static const size_t dwSize = 28; 4964 static const size_t byteSize = 112; 4965 }; 4966 using VDENC_CMD1_CMD = _VDENC_CMD1_CMD; 4967 using VDENC_CMD2_CMD = _VDENC_CMD2_CMD; 4968 using VDENC_CMD3_CMD = _VDENC_CMD3_CMD; 4969 }; 4970 4971 } // namespace xe_hpm 4972 } // namespace vdenc 4973 } // namespace vdbox 4974 } // namespace mhw 4975 class mhw_vdbox_vdenc_xe_hpm 4976 { 4977 }; 4978 #pragma pack() 4979 4980 #endif // __MHW_VDBOX_VDENC_HWCMD_XE_HPM_H__ 4981