1 /* 2 * Copyright (c) 2021-2023, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_vdenc_impl_xe2_lpm.h 24 //! \brief MHW VDBOX VDENC interface common base for Xe2_LPM 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_VDENC_IMPL_XE2_LPM_H__ 29 #define __MHW_VDBOX_VDENC_IMPL_XE2_LPM_H__ 30 31 #include "mhw_vdbox_vdenc_hwcmd_xe2_lpm.h" 32 #include "mhw_vdbox_vdenc_impl_xe2_lpm_base.h" 33 34 namespace mhw 35 { 36 namespace vdbox 37 { 38 namespace vdenc 39 { 40 namespace xe2_lpm_base 41 { 42 namespace xe2_lpm 43 { 44 class Impl : public BaseImpl<Cmd> 45 { 46 protected: 47 using cmd_t = Cmd; 48 using base_t = BaseImpl<cmd_t>; 49 50 public: Impl(PMOS_INTERFACE osItf)51 Impl(PMOS_INTERFACE osItf) : base_t(osItf){}; 52 53 protected: _MHW_SETCMD_OVERRIDE_DECL(VDENC_CMD1)54 _MHW_SETCMD_OVERRIDE_DECL(VDENC_CMD1) 55 { 56 _MHW_SETCMD_CALLBASE(VDENC_CMD1); 57 58 #define DO_FIELDS() \ 59 DO_FIELD(DW9, VDENC_CMD1_DW9_BIT24, params.vdencCmd1Par95); \ 60 DO_FIELD(DW32, VDENC_CMD1_DW32_BIT24, params.vdencCmd1Par93); \ 61 DO_FIELD(DW31, VDENC_CMD1_DW31_BIT24, params.vdencCmd1Par94); \ 62 DO_FIELD(DW33, VDENC_CMD1_DW33_BIT0, params.vdencCmd1Par11[1]); \ 63 DO_FIELD(DW33, VDENC_CMD1_DW33_BIT8, params.vdencCmd1Par15[3]); \ 64 DO_FIELD(DW33, VDENC_CMD1_DW33_BIT16, params.vdencCmd1Par15[2]); \ 65 DO_FIELD(DW33, VDENC_CMD1_DW33_BIT24, params.vdencCmd1Par15[1]); \ 66 DO_FIELD(DW34, VDENC_CMD1_DW34_BIT0, params.vdencCmd1Par14[2]); \ 67 DO_FIELD(DW34, VDENC_CMD1_DW34_BIT8, params.vdencCmd1Par14[1]); \ 68 DO_FIELD(DW34, VDENC_CMD1_DW34_BIT16, params.vdencCmd1Par11[3]); \ 69 DO_FIELD(DW34, VDENC_CMD1_DW34_BIT24, params.vdencCmd1Par11[2]); \ 70 DO_FIELD(DW35, VDENC_CMD1_DW35_BIT0, params.vdencCmd1Par10[3]); \ 71 DO_FIELD(DW35, VDENC_CMD1_DW35_BIT8, params.vdencCmd1Par10[2]); \ 72 DO_FIELD(DW35, VDENC_CMD1_DW35_BIT16, params.vdencCmd1Par10[1]); \ 73 DO_FIELD(DW35, VDENC_CMD1_DW35_BIT24, params.vdencCmd1Par14[3]); \ 74 DO_FIELD(DW36, VDENC_CMD1_DW36_BIT0, params.vdencCmd1Par9[1]); \ 75 DO_FIELD(DW36, VDENC_CMD1_DW36_BIT8, params.vdencCmd1Par13[3]); \ 76 DO_FIELD(DW36, VDENC_CMD1_DW36_BIT16, params.vdencCmd1Par13[2]); \ 77 DO_FIELD(DW36, VDENC_CMD1_DW36_BIT24, params.vdencCmd1Par13[1]); \ 78 DO_FIELD(DW37, VDENC_CMD1_DW37_BIT0, params.vdencCmd1Par12[2]); \ 79 DO_FIELD(DW37, VDENC_CMD1_DW37_BIT8, params.vdencCmd1Par12[1]); \ 80 DO_FIELD(DW37, VDENC_CMD1_DW37_BIT16, params.vdencCmd1Par9[3]); \ 81 DO_FIELD(DW37, VDENC_CMD1_DW37_BIT24, params.vdencCmd1Par9[2]); \ 82 DO_FIELD(DW38, VDENC_CMD1_DW38_BIT0, params.vdencCmd1Par8[3]); \ 83 DO_FIELD(DW38, VDENC_CMD1_DW38_BIT8, params.vdencCmd1Par8[2]); \ 84 DO_FIELD(DW38, VDENC_CMD1_DW38_BIT16, params.vdencCmd1Par8[1]); \ 85 DO_FIELD(DW38, VDENC_CMD1_DW38_BIT24, params.vdencCmd1Par12[3]) 86 87 #include "mhw_hwcmd_process_cmdfields.h" 88 89 return MOS_STATUS_SUCCESS; 90 } 91 _MHW_SETCMD_OVERRIDE_DECL(VDENC_CMD2)92 _MHW_SETCMD_OVERRIDE_DECL(VDENC_CMD2) 93 { 94 _MHW_SETCMD_CALLBASE(VDENC_CMD2); 95 96 #define DO_FIELDS_EXT() \ 97 __MHW_VDBOX_VDENC_WRAPPER_EXT(VDENC_CMD2_IMPL_XE2_EXT) 98 99 #include "mhw_hwcmd_process_cmdfields.h" 100 } 101 _MHW_SETCMD_OVERRIDE_DECL(VDENC_HEVC_VP9_TILE_SLICE_STATE)102 _MHW_SETCMD_OVERRIDE_DECL(VDENC_HEVC_VP9_TILE_SLICE_STATE) 103 { 104 _MHW_SETCMD_CALLBASE(VDENC_HEVC_VP9_TILE_SLICE_STATE); 105 106 #define DO_FIELDS() \ 107 DO_FIELD(DW11, VDENC_HEVC_VP9_TILE_SLICE_STATE_DW11_BIT24, params.VdencHEVCVP9TileSlicePar22); 108 109 #include "mhw_hwcmd_process_cmdfields.h" 110 } 111 _MHW_SETCMD_OVERRIDE_DECL(VDENC_AVC_IMG_STATE)112 _MHW_SETCMD_OVERRIDE_DECL(VDENC_AVC_IMG_STATE) 113 { 114 _MHW_SETCMD_CALLBASE(VDENC_AVC_IMG_STATE); 115 116 #define DO_FIELDS_EXT() \ 117 __MHW_VDBOX_VDENC_WRAPPER_EXT(VDENC_AVC_IMG_STATE_IMPL_XE2_LPM_EXT) 118 119 #include "mhw_hwcmd_process_cmdfields.h" 120 } 121 _MHW_SETCMD_OVERRIDE_DECL(VD_PIPELINE_FLUSH)122 _MHW_SETCMD_OVERRIDE_DECL(VD_PIPELINE_FLUSH) 123 { 124 _MHW_SETCMD_CALLBASE(VD_PIPELINE_FLUSH); 125 126 #define DO_FIELDS() \ 127 DO_FIELD(DW1, VdaqmPipelineDone, params.waitDoneVDAQM); \ 128 DO_FIELD(DW1, VdaqmPipelineCommandFlush, params.flushVDAQM); \ 129 DO_FIELD(DW1, VdCommandMessageParserDone, params.waitDoneVDCmdMsgParser); \ 130 DO_FIELD(DW1, VvcpPipelineDone, params.vvcpPipelineDone); \ 131 DO_FIELD(DW1, VvcpPipelineCommandFlush, params.vvcpPipelineCommandFlush); 132 133 #include "mhw_hwcmd_process_cmdfields.h" 134 } 135 MEDIA_CLASS_DEFINE_END(mhw__vdbox__vdenc__xe2_lpm_base__xe2_lpm__Impl) 136 }; 137 } // namespace xe2_lpm 138 } // namespace xe2_lpm_base 139 } // namespace vdenc 140 } // namespace vdbox 141 } // namespace mhw 142 143 #endif // __MHW_VDBOX_VDENC_IMPL_XE2_LPM_H__ 144