1# Microcode updates 2 3When booting a modern x86 platform, one task of the firmware is to update 4[microcode] to correct hardware bugs and mitigate security issues found 5after silicon has been shipped. The [Pentium FDIV bug] could have been 6fixed with a microcode update, had the Pentium used updateable microcode. 7Starting with the Pentium Pro, CPU microcode can be updated by software. 8 9As per BIOS Writer's Guides, Intel defines a processor as the silicon and 10the accompanying microcode update, and considers any processor that does 11not have its microcode updated to be running out of specification. This 12suggests that microcode is a crucial ingredient for correct operation. 13 14On multi-processor or Hyper-Threading-enabled systems, each thread has 15its own microcode. Therefore, microcode must be updated on every thread. 16 17## When to update microcode 18 19When a CPU core comes out of reset, it uses microcode from an internal 20ROM. This “default” microcode often contains bugs, so it needs to be 21updated as soon as possible. For example, Core 2 CPUs can boot without 22microcode updates, but have stability problems. On newer platforms, 23it is nearly impossible to boot without having updated the microcode. 24On some platforms, an updated microcode is required in order to enable 25Cache-As-RAM or to be able to successfully initialize the DRAM. 26 27Plus, microcode needs to be loaded multiple times. Intel Document 504790 28explains that this is because of so-called *enhanced microcode updates*, 29which are large updates with errata workarounds for both core and uncore. 30In order to correctly apply enhanced microcode updates, the [MP-Init] 31algorithm must be decomposed into multiple initialization phases. 32 33### Firmware Interface Table 34 35Beginning with 4th generation Intel Core processors, it is possible for 36microcode to be updated before the CPU is taken out of reset. This is 37accomplished by means of [FIT], a data structure which contains pointers 38to various firmware ingredients in the BIOS flash. 39 40In rare cases, FIT microcode updates may not be successful. Therefore, 41it is important to check that the microcode is up-to-date and, if not, 42update it. This needs to be done as early as possible, like on older 43processor generations without FIT support. 44 45Whether all threads on a processor get their microcode updated through 46FIT is not clear. According to Intel Documents 493770 and 535094, FIT 47microcode updates are applied to all cores within the package. However, 48Intel Document 550049 states that FIT microcode updates are applied to 49all threads within the package. 50 51## SMM bring-up 52 53Prior to SMM relocation, microcode must have been updated at least once. 54 55## Multi-Processor bring-up 56 57The BWG briefly describes microcode updates as part of the *MP-Init*. 58 59### MP-Init 60 61As part of the [MP-Init] sequence, two microcode updates are required. 62 63* The first update must happen as soon as one AP comes out of reset. 64* The second update must happen after the MP-Init sequence has written MTRRs, 65 PRMRR, DCU mode and prefetcher configuration, SMM has been relocated, but 66 before clearing the MCE banks. 67 68## Recommendations 69 70The Linux kernel developer's recommendations are: 71* Serialize microcode updates if possible. 72* Idle as many APs as possible while updating. 73* Idle the sibling thread on a Hyper-Threading enabled CPU while updating. 74 75## Platform BWGs 76 77The requirements specified in BWGs differ between platforms: 78 79### Sandy Bridge 80 81* Before setting up Cache-As-RAM, load microcode update into the SBSP. 82* Losing (non-SBSP) NBSPs must load their microcode update before being placed 83 back in the wait-for-SIPI state. 84* Sibling threads on HT must use a semaphore. 85* Microcode update loading has been done prior to SMM relocation. 86* In MP-Init the microcode update on an AP must be done before initializing the 87 cache, MTRRs, SMRRs and PRMRRs. 88* In MP-Init a second update must happen on all threads after initializing the 89 cache, MTRRs, SMRRs and PRMRRs. 90 91Refer to Intel Document 504790 for details. 92 93### Haswell/Broadwell Client 94 95* A microcode update must exist in FIT. 96* During the race to the BSP semaphore, each NBSP must load its microcode update. 97* All HT enabled threads can load microcode in parallel. However, the 98 IA32_BIOS_UPDT_TRIG MSR is core-scoped, just like on other platforms. 99* Microcode update loading has been done prior to SMM relocation. 100* In MP-Init the microcode update on an AP must be done before initializing the 101 cache, MTRRs, SMRRs and EMRR. 102* In MP-Init a second update must happen on all threads after initializing the 103 cache, MTRRs, SMRRs and EMRR and after SMM initialization. 104 105Refer to Intel Document 493770 and 535094 for details. 106 107### Broadwell Server 108 109* A microcode update must exist in FIT. 110* Before setting up Cache-As-RAM, load microcode update into each BSP. 111* In MP-Init the microcode update on an AP must be done before initializing the 112 cache, MTRRs, SMRRs and EMRR. 113* In MP-Init a second update must happen on all threads after initializing the 114 cache, MTRRs, SMRRs and EMRR and after SMM initialization. 115 116Refer to Intel Document 546625 for details. 117 118### Skylake/Kaby Lake/Coffee Lake/Whiskey Lake/Comet Lake 119 120* A microcode update must exist in FIT. 121* Before setting up Cache-As-RAM, load microcode update into the BSP. 122* Microcode update loading has been done prior to SMM relocation. 123* In MP-Init the first update must happen as soon as one AP comes out of reset. 124* In MP-Init the second update must happen after the MP-Init sequence has 125 written MTRRs, PRMRR, DCU mode and prefetcher configuration, but before 126 clearing the MCE banks. 127* Microcode updates must happen on all threads. 128* Sibling threads on HT should use a semaphore. 129 130Refer to Intel Document 550049 for details. 131 132[microcode]: https://en.wikipedia.org/wiki/Microcode 133[Pentium FDIV bug]: https://en.wikipedia.org/wiki/Pentium_FDIV_bug 134[FIT]: fit.md 135[SDM]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf 136[MP-Init]: mp_init/mp_init.md 137