1# mrc.bin 2 3All Haswell boards supported by coreboot currently require a proprietary 4blob in order to initialise the DRAM and a few other components. The 5blob, named `mrc.bin`, largely consists of Intel's memory reference code 6(MRC), but it has been tailored specifically for ChromeOS. It is just 7under 200 KiB in size. Another name for `mrc.bin` is the system agent 8binary. 9 10Having a replacement for `mrc.bin` using native coreboot code is very 11much desired, but it is not an easy task. 12 13## Obtaining mrc.bin 14 15Unfortunately, it is not currently possible to distribute `mrc.bin` as 16part of coreboot. Though, it can be obtained from a Haswell Chromebook 17firmware image like so, starting in the root of the coreboot directory: 18 19```bash 20make -C util/cbfstool 21cd util/chromeos 22./crosfirmware.sh peppy 23../cbfstool/cbfstool coreboot-*.bin extract -f mrc.bin -n mrc.bin -r RO_SECTION 24``` 25 26Now, place `mrc.bin` in the root of the coreboot directory. 27Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to 28its location when building coreboot. 29 30## SPD Addresses 31 32When porting a board from vendor firmware, the SPD addresses can be obtained 33through `i2c-tools`, which can be found in many GNU/Linux distributions. A more 34[detailed description](https://hannuhartikainen.fi/blog/hacking-ddr3-spd/) of 35the procedure and beyond can be found in 36[Hannu Hartikainen's blog](https://hannuhartikainen.fi). 37 38First load the kernel modules: 39 40```bash 41modprobe i2c-dev 42modprobe eeprom 43``` 44 45Find the SMBus and the addresses of the DIMM's EEPROMs (example output): 46```bash 47$ decode-dimms | grep Decoding 48Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050 49Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052 50``` 51 52Alternatively, look at the sys filesystem: 53```bash 54$ ls -l /sys/bus/i2c/drivers/eeprom/ 55total 0 56lrwxrwxrwx 1 root root 0 Apr 4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/ 57lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/ 58lrwxrwxrwx 1 root root 0 Apr 4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/ 59--w------- 1 root root 4096 Apr 4 01:47 bind 60lrwxrwxrwx 1 root root 0 Apr 4 01:47 module -> ../../../../module/eeprom/ 61--w------- 1 root root 4096 Apr 4 01:46 uevent 62--w------- 1 root root 4096 Apr 4 01:47 unbind 63``` 64 65The correct I2C bus is 7 in this case, and the EEPROMs are at `0x50` and `0x52`. 66Note that the above values are actually hex values. 67 68You can check the correctness of the SMBus and the addresses of the EEPROMs via 69`i2cdetect`: 70 71```bash 72$ i2cdetect -l 73i2c-3 unknown i915 gmbus dpc N/A 74i2c-1 unknown i915 gmbus vga N/A 75i2c-6 unknown DPDDC-A N/A 76i2c-4 unknown i915 gmbus dpb N/A 77i2c-2 unknown i915 gmbus panel N/A 78i2c-0 unknown i915 gmbus ssc N/A 79i2c-7 unknown SMBus I801 adapter at f040 N/A 80i2c-5 unknown i915 gmbus dpd N/A 81``` 82 83Probing the SMBus: 84 85```bash 86$ i2cdetect -r 7 87WARNING! This program can confuse your I2C bus, cause data loss and worse! 88I will probe file /dev/i2c-7 using receive byte commands. 89I will probe address range 0x03-0x77. 90Continue? [Y/n] 91 0 1 2 3 4 5 6 7 8 9 a b c d e f 9200: -- -- -- -- -- -- -- -- -- -- -- -- -- 9310: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9420: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9530: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9640: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 9750: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- -- 9860: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9970: -- -- -- -- -- -- -- -- 100``` 101 102The SPD addresses need to be left-shifted by 1 for `mrc.bin`, i.e., multiplied 103by 2. For example, if the addresses read through `i2c-tools` when booted from 104vendor firmware are `0x50` and `0x52`, the correct values would be `0xa0` and 105`0xa4`. This is because the I2C addresses are 7 bits long. 106 107## ECC DRAM 108 109When `mrc.bin` has finished executing, ECC is active on the channels 110populated with ECC DIMMs. However, `mrc.bin` was tailored specifically 111for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM. 112While ECC likely functions correctly, it is advised to further validate 113the correct operation of ECC if data integrity is absolutely critical. 114