1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IOMMU_PRIV_H 8 #define IOMMU_PRIV_H 9 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 #include <mtk_iommu_plat.h> 13 #include <mtk_sip_svc.h> 14 15 #define LARB_CFG_ENTRY(bs, p_nr, dom) \ 16 { .base = (bs), .port_nr = (p_nr), \ 17 .dom_id = (dom), .to_sram = 0, } 18 19 #define LARB_CFG_ENTRY_WITH_PATH(bs, p_nr, dom, sram) \ 20 { .base = (bs), .port_nr = (p_nr), \ 21 .dom_id = (dom), .to_sram = (sram), } 22 23 #define IFR_MST_CFG_ENTRY(idx, bit) \ 24 { .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), } 25 26 #define SEC_IOMMU_CFG_ENTRY(s_bs) \ 27 { .base = (s_bs), } 28 29 enum IOMMU_ATF_CMD { 30 IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to enable iommu */ 31 IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ 32 IOMMU_ATF_CMD_GET_SECURE_IOMMU_STATUS, /* For secure iommu translation fault report */ 33 IOMMU_ATF_CMD_COUNT, 34 }; 35 36 struct mtk_smi_larb_config { 37 uint32_t base; 38 uint32_t port_nr; 39 uint32_t dom_id; 40 uint32_t to_sram; 41 uint32_t sec_en_msk; 42 }; 43 44 struct mtk_ifr_mst_config { 45 uint8_t cfg_addr_idx; 46 uint8_t r_mmu_en_bit; 47 }; 48 49 struct mtk_secure_iommu_config { 50 uint32_t base; 51 }; 52 53 54 #ifdef ATF_MTK_SMI_LARB_CFG_SUPPORT 55 /* mm smi larb security feature is used */ 56 extern struct mtk_smi_larb_config *g_larb_cfg; 57 extern const unsigned int g_larb_num; 58 #endif 59 60 #ifdef ATF_MTK_INFRA_MASTER_CFG_SUPPORT 61 /* infra iommu is used */ 62 extern struct mtk_ifr_mst_config *g_ifr_mst_cfg; 63 extern const unsigned int g_ifr_mst_num; 64 extern uint32_t *g_ifr_mst_cfg_base; 65 extern uint32_t *g_ifr_mst_cfg_offs; 66 extern void mtk_infra_iommu_enable_protect(void); 67 #endif 68 69 #ifdef ATF_MTK_IOMMU_CFG_SUPPORT 70 /* secure iommu is used */ 71 extern struct mtk_secure_iommu_config *g_sec_iommu_cfg; 72 extern const unsigned int g_sec_iommu_num; 73 #endif 74 75 #endif /* IOMMU_PRIV_H */ 76