1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H
4 #define NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H
5
6 #include <device/mmio.h>
7 #include <stdint.h>
8
9 _Static_assert(CONFIG_FIXED_MCHBAR_MMIO_BASE != 0, "MCHBAR base address is zero");
10
mchbar_read8(const uintptr_t offset)11 static __always_inline uint8_t mchbar_read8(const uintptr_t offset)
12 {
13 return read8p(CONFIG_FIXED_MCHBAR_MMIO_BASE + offset);
14 }
15
mchbar_read16(const uintptr_t offset)16 static __always_inline uint16_t mchbar_read16(const uintptr_t offset)
17 {
18 return read16p(CONFIG_FIXED_MCHBAR_MMIO_BASE + offset);
19 }
20
mchbar_read32(const uintptr_t offset)21 static __always_inline uint32_t mchbar_read32(const uintptr_t offset)
22 {
23 return read32p(CONFIG_FIXED_MCHBAR_MMIO_BASE + offset);
24 }
25
mchbar_write8(const uintptr_t offset,const uint8_t value)26 static __always_inline void mchbar_write8(const uintptr_t offset, const uint8_t value)
27 {
28 write8p(CONFIG_FIXED_MCHBAR_MMIO_BASE + offset, value);
29 }
30
mchbar_write16(const uintptr_t offset,const uint16_t value)31 static __always_inline void mchbar_write16(const uintptr_t offset, const uint16_t value)
32 {
33 write16p(CONFIG_FIXED_MCHBAR_MMIO_BASE + offset, value);
34 }
35
mchbar_write32(const uintptr_t offset,const uint32_t value)36 static __always_inline void mchbar_write32(const uintptr_t offset, const uint32_t value)
37 {
38 write32p(CONFIG_FIXED_MCHBAR_MMIO_BASE + offset, value);
39 }
40
mchbar_clrsetbits8(uintptr_t offset,uint8_t clear,uint8_t set)41 static __always_inline void mchbar_clrsetbits8(uintptr_t offset, uint8_t clear, uint8_t set)
42 {
43 clrsetbits8((void *)((uintptr_t)CONFIG_FIXED_MCHBAR_MMIO_BASE + offset), clear, set);
44 }
45
mchbar_clrsetbits16(uintptr_t offset,uint16_t clear,uint16_t set)46 static __always_inline void mchbar_clrsetbits16(uintptr_t offset, uint16_t clear, uint16_t set)
47 {
48 clrsetbits16((void *)((uintptr_t)CONFIG_FIXED_MCHBAR_MMIO_BASE + offset), clear, set);
49 }
50
mchbar_clrsetbits32(uintptr_t offset,uint32_t clear,uint32_t set)51 static __always_inline void mchbar_clrsetbits32(uintptr_t offset, uint32_t clear, uint32_t set)
52 {
53 clrsetbits32((void *)((uintptr_t)CONFIG_FIXED_MCHBAR_MMIO_BASE + offset), clear, set);
54 }
55
56 #define mchbar_setbits8(addr, set) mchbar_clrsetbits8(addr, 0, set)
57 #define mchbar_setbits16(addr, set) mchbar_clrsetbits16(addr, 0, set)
58 #define mchbar_setbits32(addr, set) mchbar_clrsetbits32(addr, 0, set)
59
60 #define mchbar_clrbits8(addr, clear) mchbar_clrsetbits8(addr, clear, 0)
61 #define mchbar_clrbits16(addr, clear) mchbar_clrsetbits16(addr, clear, 0)
62 #define mchbar_clrbits32(addr, clear) mchbar_clrsetbits32(addr, clear, 0)
63
64 _Static_assert(CONFIG_FIXED_DMIBAR_MMIO_BASE != 0, "DMIBAR base address is zero");
65
dmibar_read8(const uintptr_t offset)66 static __always_inline uint8_t dmibar_read8(const uintptr_t offset)
67 {
68 return read8p(CONFIG_FIXED_DMIBAR_MMIO_BASE + offset);
69 }
70
dmibar_read16(const uintptr_t offset)71 static __always_inline uint16_t dmibar_read16(const uintptr_t offset)
72 {
73 return read16p(CONFIG_FIXED_DMIBAR_MMIO_BASE + offset);
74 }
75
dmibar_read32(const uintptr_t offset)76 static __always_inline uint32_t dmibar_read32(const uintptr_t offset)
77 {
78 return read32p(CONFIG_FIXED_DMIBAR_MMIO_BASE + offset);
79 }
80
dmibar_write8(const uintptr_t offset,const uint8_t value)81 static __always_inline void dmibar_write8(const uintptr_t offset, const uint8_t value)
82 {
83 write8p(CONFIG_FIXED_DMIBAR_MMIO_BASE + offset, value);
84 }
85
dmibar_write16(const uintptr_t offset,const uint16_t value)86 static __always_inline void dmibar_write16(const uintptr_t offset, const uint16_t value)
87 {
88 write16p(CONFIG_FIXED_DMIBAR_MMIO_BASE + offset, value);
89 }
90
dmibar_write32(const uintptr_t offset,const uint32_t value)91 static __always_inline void dmibar_write32(const uintptr_t offset, const uint32_t value)
92 {
93 write32p(CONFIG_FIXED_DMIBAR_MMIO_BASE + offset, value);
94 }
95
dmibar_clrsetbits8(uintptr_t offset,uint8_t clear,uint8_t set)96 static __always_inline void dmibar_clrsetbits8(uintptr_t offset, uint8_t clear, uint8_t set)
97 {
98 clrsetbits8((void *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + offset), clear, set);
99 }
100
dmibar_clrsetbits16(uintptr_t offset,uint16_t clear,uint16_t set)101 static __always_inline void dmibar_clrsetbits16(uintptr_t offset, uint16_t clear, uint16_t set)
102 {
103 clrsetbits16((void *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + offset), clear, set);
104 }
105
dmibar_clrsetbits32(uintptr_t offset,uint32_t clear,uint32_t set)106 static __always_inline void dmibar_clrsetbits32(uintptr_t offset, uint32_t clear, uint32_t set)
107 {
108 clrsetbits32((void *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + offset), clear, set);
109 }
110
111 #define dmibar_setbits8(addr, set) dmibar_clrsetbits8(addr, 0, set)
112 #define dmibar_setbits16(addr, set) dmibar_clrsetbits16(addr, 0, set)
113 #define dmibar_setbits32(addr, set) dmibar_clrsetbits32(addr, 0, set)
114
115 #define dmibar_clrbits8(addr, clear) dmibar_clrsetbits8(addr, clear, 0)
116 #define dmibar_clrbits16(addr, clear) dmibar_clrsetbits16(addr, clear, 0)
117 #define dmibar_clrbits32(addr, clear) dmibar_clrsetbits32(addr, clear, 0)
118
119 _Static_assert(CONFIG_FIXED_EPBAR_MMIO_BASE != 0, "EPBAR base address is zero");
120
epbar_read8(const uintptr_t offset)121 static __always_inline uint8_t epbar_read8(const uintptr_t offset)
122 {
123 return read8p(CONFIG_FIXED_EPBAR_MMIO_BASE + offset);
124 }
125
epbar_read16(const uintptr_t offset)126 static __always_inline uint16_t epbar_read16(const uintptr_t offset)
127 {
128 return read16p(CONFIG_FIXED_EPBAR_MMIO_BASE + offset);
129 }
130
epbar_read32(const uintptr_t offset)131 static __always_inline uint32_t epbar_read32(const uintptr_t offset)
132 {
133 return read32p(CONFIG_FIXED_EPBAR_MMIO_BASE + offset);
134 }
135
epbar_write8(const uintptr_t offset,const uint8_t value)136 static __always_inline void epbar_write8(const uintptr_t offset, const uint8_t value)
137 {
138 write8p(CONFIG_FIXED_EPBAR_MMIO_BASE + offset, value);
139 }
140
epbar_write16(const uintptr_t offset,const uint16_t value)141 static __always_inline void epbar_write16(const uintptr_t offset, const uint16_t value)
142 {
143 write16p(CONFIG_FIXED_EPBAR_MMIO_BASE + offset, value);
144 }
145
epbar_write32(const uintptr_t offset,const uint32_t value)146 static __always_inline void epbar_write32(const uintptr_t offset, const uint32_t value)
147 {
148 write32p(CONFIG_FIXED_EPBAR_MMIO_BASE + offset, value);
149 }
150
epbar_clrsetbits8(uintptr_t offset,uint8_t clear,uint8_t set)151 static __always_inline void epbar_clrsetbits8(uintptr_t offset, uint8_t clear, uint8_t set)
152 {
153 clrsetbits8((void *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + offset), clear, set);
154 }
155
epbar_clrsetbits16(uintptr_t offset,uint16_t clear,uint16_t set)156 static __always_inline void epbar_clrsetbits16(uintptr_t offset, uint16_t clear, uint16_t set)
157 {
158 clrsetbits16((void *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + offset), clear, set);
159 }
160
epbar_clrsetbits32(uintptr_t offset,uint32_t clear,uint32_t set)161 static __always_inline void epbar_clrsetbits32(uintptr_t offset, uint32_t clear, uint32_t set)
162 {
163 clrsetbits32((void *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + offset), clear, set);
164 }
165
166 #define epbar_setbits8(addr, set) epbar_clrsetbits8(addr, 0, set)
167 #define epbar_setbits16(addr, set) epbar_clrsetbits16(addr, 0, set)
168 #define epbar_setbits32(addr, set) epbar_clrsetbits32(addr, 0, set)
169
170 #define epbar_clrbits8(addr, clear) epbar_clrsetbits8(addr, clear, 0)
171 #define epbar_clrbits16(addr, clear) epbar_clrsetbits16(addr, clear, 0)
172 #define epbar_clrbits32(addr, clear) epbar_clrsetbits32(addr, clear, 0)
173
174 #endif /* ! NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H */
175