1 /* 2 * Copyright 2011 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __NV50_IR_DRIVER_H__ 24 #define __NV50_IR_DRIVER_H__ 25 26 #include "compiler/shader_enums.h" 27 #include "util/macros.h" 28 #include "util/blob.h" 29 30 #define NV50_CODEGEN_MAX_VARYINGS 80 31 struct nir_shader; 32 struct nir_shader_compiler_options; 33 34 /* 35 * This struct constitutes linkage information in TGSI terminology. 36 * 37 * It is created by the code generator and handed to the pipe driver 38 * for input/output slot assignment. 39 */ 40 struct nv50_ir_varying 41 { 42 uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */ 43 44 unsigned mask : 4; /* vec4 mask */ 45 unsigned linear : 1; /* linearly interpolated if true (and not flat) */ 46 unsigned flat : 1; 47 unsigned sc : 1; /* special colour interpolation mode (SHADE_MODEL) */ 48 unsigned centroid : 1; 49 unsigned patch : 1; /* patch constant value */ 50 unsigned regular : 1; /* driver-specific meaning (e.g. input in sreg) */ 51 unsigned input : 1; /* indicates direction of system values */ 52 unsigned oread : 1; /* true if output is read from parallel TCP */ 53 54 uint8_t id; /* TGSI register index */ 55 uint8_t sn; /* TGSI semantic name */ 56 uint8_t si; /* TGSI semantic index */ 57 }; 58 59 struct nv50_ir_sysval 60 { 61 gl_system_value sn; 62 uint8_t slot[4]; /* for nv50: native slots for xyzw (addresses in 32-bit words) */ 63 }; 64 65 #ifndef NDEBUG 66 # define NV50_IR_DEBUG_BASIC (1 << 0) 67 # define NV50_IR_DEBUG_VERBOSE (2 << 0) 68 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2) 69 #else 70 # define NV50_IR_DEBUG_BASIC 0 71 # define NV50_IR_DEBUG_VERBOSE 0 72 # define NV50_IR_DEBUG_REG_ALLOC 0 73 #endif 74 75 struct nv50_ir_prog_symbol 76 { 77 uint32_t label; 78 uint32_t offset; 79 }; 80 81 #define NVISA_G80_CHIPSET 0x50 82 #define NVISA_GF100_CHIPSET 0xc0 83 #define NVISA_GK104_CHIPSET 0xe0 84 #define NVISA_GK20A_CHIPSET 0xea 85 #define NVISA_GM107_CHIPSET 0x110 86 #define NVISA_GM200_CHIPSET 0x120 87 #define NVISA_GV100_CHIPSET 0x140 88 89 struct nv50_ir_prog_info_out; 90 91 /* used for the input data and assignSlot interface */ 92 struct nv50_ir_prog_info 93 { 94 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 95 96 uint8_t type; /* PIPE_SHADER */ 97 98 uint8_t optLevel; /* optimization level (0 to 4). Level 4 enables MemoryOpt 99 * which does not work well with NVK */ 100 uint8_t dbgFlags; 101 bool omitLineNum; /* only used for printing the prog when dbgFlags is set */ 102 103 struct { 104 uint32_t smemSize; /* required shared memory per block */ 105 struct nir_shader *nir; 106 } bin; 107 108 union { 109 struct { 110 uint32_t inputOffset; /* base address for user args */ 111 uint32_t gridInfoBase; /* base address for NTID,NCTAID */ 112 uint16_t numThreads[3]; /* max number of threads */ 113 } cp; 114 } prop; 115 116 struct { 117 int8_t genUserClip; /* request user clip planes for ClipVertex */ 118 uint8_t auxCBSlot; /* driver constant buffer slot */ 119 uint16_t ucpBase; /* base address for UCPs */ 120 uint16_t drawInfoBase; /* base address for draw parameters */ 121 uint16_t alphaRefBase; /* base address for alpha test values */ 122 int8_t viewportId; /* output index of ViewportIndex */ 123 bool mul_zero_wins; /* program wants for x*0 = 0 */ 124 bool nv50styleSurfaces; /* generate gX[] access for raw buffers */ 125 uint16_t texBindBase; /* base address for tex handles (nve4) */ 126 uint16_t fbtexBindBase; /* base address for fbtex handle (nve4) */ 127 uint16_t suInfoBase; /* base address for surface info (nve4) */ 128 uint16_t bindlessBase; /* base address for bindless image info (nve4) */ 129 uint16_t bufInfoBase; /* base address for buffer info */ 130 uint16_t sampleInfoBase; /* base address for sample positions */ 131 uint8_t msInfoCBSlot; /* cX[] used for multisample info */ 132 uint16_t msInfoBase; /* base address for multisample info */ 133 uint16_t uboInfoBase; /* base address for compute UBOs (gk104+) */ 134 135 uint16_t membarOffset; /* base address for membar reads (nv50) */ 136 uint8_t gmemMembar; /* gX[] on which to perform membar reads (nv50) */ 137 } io; 138 139 /* driver callback to assign input/output locations */ 140 int (*assignSlots)(struct nv50_ir_prog_info_out *); 141 }; 142 143 /* the produced binary with metadata */ 144 struct nv50_ir_prog_info_out 145 { 146 uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */ 147 148 uint8_t type; /* PIPE_SHADER */ 149 150 struct { 151 int16_t maxGPR; /* may be -1 if none used */ 152 uint32_t tlsSpace; /* required local memory per thread */ 153 uint32_t smemSize; /* required shared memory per block */ 154 uint32_t *code; 155 uint32_t codeSize; 156 uint32_t instructions; 157 void *relocData; 158 void *fixupData; 159 } bin; 160 161 struct nv50_ir_sysval sv[NV50_CODEGEN_MAX_VARYINGS]; 162 struct nv50_ir_varying in[NV50_CODEGEN_MAX_VARYINGS]; 163 struct nv50_ir_varying out[NV50_CODEGEN_MAX_VARYINGS]; 164 uint8_t numInputs; 165 uint8_t numOutputs; 166 uint8_t numPatchConstants; /* also included in numInputs/numOutputs */ 167 uint8_t numSysVals; 168 uint32_t loops; 169 170 union { 171 struct { 172 bool usesDrawParameters; 173 } vp; 174 struct { 175 uint8_t outputPatchSize; 176 uint8_t partitioning; /* PIPE_TESS_PART */ 177 int8_t winding; /* +1 (clockwise) / -1 (counter-clockwise) */ 178 uint8_t domain; /* MESA_PRIM_{QUADS,TRIANGLES,LINES} */ 179 uint8_t outputPrim; /* MESA_PRIM_{TRIANGLES,LINES,POINTS} */ 180 } tp; 181 struct { 182 uint8_t outputPrim; 183 unsigned instanceCount; 184 unsigned maxVertices; 185 } gp; 186 struct { 187 unsigned numColourResults; 188 bool writesDepth : 1; 189 bool earlyFragTests : 1; 190 bool postDepthCoverage : 1; 191 bool usesDiscard : 1; 192 bool usesSampleMaskIn : 1; 193 bool readsFramebuffer : 1; 194 bool readsSampleLocations : 1; 195 bool separateFragData : 1; 196 } fp; 197 struct { 198 struct { 199 unsigned valid : 1; 200 unsigned image : 1; 201 unsigned slot : 6; 202 } gmem[16]; /* nv50 only */ 203 } cp; 204 } prop; 205 206 struct { 207 uint8_t clipDistances; /* number of clip distance outputs */ 208 uint8_t cullDistances; /* number of cull distance outputs */ 209 int8_t genUserClip; /* request user clip planes for ClipVertex */ 210 uint8_t instanceId; /* system value index of InstanceID */ 211 uint8_t vertexId; /* system value index of VertexID */ 212 uint8_t edgeFlagIn; 213 uint8_t edgeFlagOut; 214 uint8_t fragDepth; /* output index of FragDepth */ 215 uint8_t sampleMask; /* output index of SampleMask */ 216 uint8_t globalAccess; /* 1 for read, 2 for wr, 3 for rw */ 217 bool fp64; /* program uses fp64 math */ 218 bool layer_viewport_relative; 219 } io; 220 221 uint8_t numBarriers; 222 223 void *driverPriv; 224 }; 225 226 #ifdef __cplusplus 227 extern "C" { 228 #endif 229 230 const struct nir_shader_compiler_options * 231 nv50_ir_nir_shader_compiler_options(int chipset, uint8_t shader_type); 232 233 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *, 234 struct nv50_ir_prog_info_out *); 235 236 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code, 237 uint32_t codePos, 238 uint32_t libPos, 239 uint32_t dataPos); 240 241 extern void 242 nv50_ir_apply_fixups(void *fixupData, uint32_t *code, 243 bool force_per_sample, bool flatshade, 244 uint8_t alphatest, bool msaa); 245 246 /* obtain code that will be shared among programs */ 247 extern void nv50_ir_get_target_library(uint32_t chipset, 248 const uint32_t **code, uint32_t *size); 249 250 251 #ifdef __cplusplus 252 namespace nv50_ir 253 { 254 struct FixupEntry; 255 struct FixupData; 256 257 void 258 gk110_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 259 const nv50_ir::FixupData& data); 260 void 261 gm107_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 262 const nv50_ir::FixupData& data); 263 void 264 nv50_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 265 const nv50_ir::FixupData& data); 266 void 267 nvc0_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 268 const nv50_ir::FixupData& data); 269 void 270 gv100_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code, 271 const nv50_ir::FixupData& data); 272 void 273 gk110_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 274 const nv50_ir::FixupData& data); 275 void 276 gm107_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 277 const nv50_ir::FixupData& data); 278 void 279 nvc0_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 280 const nv50_ir::FixupData& data); 281 void 282 gv100_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code, 283 const nv50_ir::FixupData& data); 284 } 285 #endif 286 287 extern void 288 nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *); 289 290 /* Serialize a nv50_ir_prog_info structure and save it into blob */ 291 extern bool 292 nv50_ir_prog_info_serialize(struct blob *, struct nv50_ir_prog_info *); 293 294 /* Serialize a nv50_ir_prog_info_out structure and save it into blob */ 295 extern bool MUST_CHECK 296 nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *); 297 298 /* Deserialize from data and save into a nv50_ir_prog_info_out structure 299 * using a pointer. Size is a total size of the serialized data. 300 * Offset points to where info_out in data is located. */ 301 extern bool MUST_CHECK 302 nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset, 303 struct nv50_ir_prog_info_out *); 304 305 #ifdef __cplusplus 306 } 307 #endif 308 309 #endif // __NV50_IR_DRIVER_H__ 310