1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "compiler/nir/nir.h"
26 #include "compiler/nir/nir_builder.h"
27
28 #include "nir/pipe_nir.h"
29 #include "pipe/p_defines.h"
30
31 #include "util/u_inlines.h"
32 #include "util/u_pack_color.h"
33 #include "util/format/u_format.h"
34 #include "util/u_math.h"
35 #include "util/u_surface.h"
36 #include "util/u_thread.h"
37
38 #include "nv50_ir_driver.h"
39
40 #include "nv50/nv50_context.h"
41 #include "nv50/nv50_resource.h"
42
43 #include "nv50/g80_defs.xml.h"
44 #include "nv50/g80_texture.xml.h"
45
46 /* these are used in nv50_blit.h */
47 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
48 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
49 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
50 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
51 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
52
53 #define NOUVEAU_DRIVER 0x50
54 #include "nv50/nv50_blit.h"
55
56 static inline uint8_t
nv50_2d_format(enum pipe_format format,bool dst,bool dst_src_equal)57 nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
58 {
59 uint8_t id = nv50_format_table[format].rt;
60
61 /* Hardware values for color formats range from 0xc0 to 0xff,
62 * but the 2D engine doesn't support all of them.
63 */
64 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
65 return id;
66 assert(dst_src_equal);
67
68 switch (util_format_get_blocksize(format)) {
69 case 1:
70 return G80_SURFACE_FORMAT_R8_UNORM;
71 case 2:
72 return G80_SURFACE_FORMAT_R16_UNORM;
73 case 4:
74 return G80_SURFACE_FORMAT_BGRA8_UNORM;
75 case 8:
76 return G80_SURFACE_FORMAT_RGBA16_FLOAT;
77 case 16:
78 return G80_SURFACE_FORMAT_RGBA32_FLOAT;
79 default:
80 return 0;
81 }
82 }
83
84 static int
nv50_2d_texture_set(struct nouveau_pushbuf * push,int dst,struct nv50_miptree * mt,unsigned level,unsigned layer,enum pipe_format pformat,bool dst_src_pformat_equal)85 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
86 struct nv50_miptree *mt, unsigned level, unsigned layer,
87 enum pipe_format pformat, bool dst_src_pformat_equal)
88 {
89 struct nouveau_bo *bo = mt->base.bo;
90 uint32_t width, height, depth;
91 uint32_t format;
92 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
93 uint32_t offset = mt->level[level].offset;
94
95 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
96 if (!format) {
97 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
98 util_format_name(pformat));
99 return 1;
100 }
101
102 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
103 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
104 depth = u_minify(mt->base.base.depth0, level);
105
106 offset = mt->level[level].offset;
107 if (!mt->layout_3d) {
108 offset += mt->layer_stride * layer;
109 depth = 1;
110 layer = 0;
111 } else
112 if (!dst) {
113 offset += nv50_mt_zslice_offset(mt, level, layer);
114 layer = 0;
115 }
116
117 if (!nouveau_bo_memtype(bo)) {
118 BEGIN_NV04(push, SUBC_2D(mthd), 2);
119 PUSH_DATA (push, format);
120 PUSH_DATA (push, 1);
121 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
122 PUSH_DATA (push, mt->level[level].pitch);
123 PUSH_DATA (push, width);
124 PUSH_DATA (push, height);
125 PUSH_DATAh(push, mt->base.address + offset);
126 PUSH_DATA (push, mt->base.address + offset);
127 } else {
128 BEGIN_NV04(push, SUBC_2D(mthd), 5);
129 PUSH_DATA (push, format);
130 PUSH_DATA (push, 0);
131 PUSH_DATA (push, mt->level[level].tile_mode);
132 PUSH_DATA (push, depth);
133 PUSH_DATA (push, layer);
134 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
135 PUSH_DATA (push, width);
136 PUSH_DATA (push, height);
137 PUSH_DATAh(push, mt->base.address + offset);
138 PUSH_DATA (push, mt->base.address + offset);
139 }
140
141 #if 0
142 if (dst) {
143 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
144 PUSH_DATA (push, 0);
145 PUSH_DATA (push, 0);
146 PUSH_DATA (push, width);
147 PUSH_DATA (push, height);
148 }
149 #endif
150 return 0;
151 }
152
153 static int
nv50_2d_texture_do_copy(struct nouveau_pushbuf * push,struct nv50_miptree * dst,unsigned dst_level,unsigned dx,unsigned dy,unsigned dz,struct nv50_miptree * src,unsigned src_level,unsigned sx,unsigned sy,unsigned sz,unsigned w,unsigned h)154 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
155 struct nv50_miptree *dst, unsigned dst_level,
156 unsigned dx, unsigned dy, unsigned dz,
157 struct nv50_miptree *src, unsigned src_level,
158 unsigned sx, unsigned sy, unsigned sz,
159 unsigned w, unsigned h)
160 {
161 const enum pipe_format dfmt = dst->base.base.format;
162 const enum pipe_format sfmt = src->base.base.format;
163 int ret;
164 bool eqfmt = dfmt == sfmt;
165
166 if (!PUSH_SPACE(push, 2 * 16 + 32))
167 return PIPE_ERROR;
168
169 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
174 if (ret)
175 return ret;
176
177 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
178 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
179 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
180 PUSH_DATA (push, dx << dst->ms_x);
181 PUSH_DATA (push, dy << dst->ms_y);
182 PUSH_DATA (push, w << dst->ms_x);
183 PUSH_DATA (push, h << dst->ms_y);
184 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
185 PUSH_DATA (push, 0);
186 PUSH_DATA (push, 1);
187 PUSH_DATA (push, 0);
188 PUSH_DATA (push, 1);
189 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
190 PUSH_DATA (push, 0);
191 PUSH_DATA (push, sx << src->ms_x);
192 PUSH_DATA (push, 0);
193 PUSH_DATA (push, sy << src->ms_y);
194
195 return 0;
196 }
197
198 static void
nv50_resource_copy_region(struct pipe_context * pipe,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)199 nv50_resource_copy_region(struct pipe_context *pipe,
200 struct pipe_resource *dst, unsigned dst_level,
201 unsigned dstx, unsigned dsty, unsigned dstz,
202 struct pipe_resource *src, unsigned src_level,
203 const struct pipe_box *src_box)
204 {
205 struct nv50_context *nv50 = nv50_context(pipe);
206 int ret;
207 bool m2mf;
208 unsigned dst_layer = dstz, src_layer = src_box->z;
209
210 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
211 nouveau_copy_buffer(&nv50->base,
212 nv04_resource(dst), dstx,
213 nv04_resource(src), src_box->x, src_box->width);
214 return;
215 }
216
217 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
218 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
219
220 m2mf = (src->format == dst->format) ||
221 (util_format_get_blocksizebits(src->format) ==
222 util_format_get_blocksizebits(dst->format));
223
224 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
225
226 if (m2mf) {
227 struct nv50_miptree *src_mt = nv50_miptree(src);
228 struct nv50_miptree *dst_mt = nv50_miptree(dst);
229 struct nv50_m2mf_rect drect, srect;
230 unsigned i;
231 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
232 << src_mt->ms_x;
233 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
234 << src_mt->ms_y;
235
236 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
237 nv50_m2mf_rect_setup(&srect, src, src_level,
238 src_box->x, src_box->y, src_box->z);
239
240 for (i = 0; i < src_box->depth; ++i) {
241 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
242
243 if (dst_mt->layout_3d)
244 drect.z++;
245 else
246 drect.base += dst_mt->layer_stride;
247
248 if (src_mt->layout_3d)
249 srect.z++;
250 else
251 srect.base += src_mt->layer_stride;
252 }
253 return;
254 }
255
256 assert((src->format == dst->format) ||
257 (nv50_2d_src_format_faithful(src->format) &&
258 nv50_2d_dst_format_faithful(dst->format)));
259
260 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
261 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
262 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
263 PUSH_VAL(nv50->base.pushbuf);
264
265 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
266 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
267 nv50_miptree(dst), dst_level,
268 dstx, dsty, dst_layer,
269 nv50_miptree(src), src_level,
270 src_box->x, src_box->y, src_layer,
271 src_box->width, src_box->height);
272 if (ret)
273 break;
274 }
275 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
276 }
277
278 static void
nv50_clear_render_target(struct pipe_context * pipe,struct pipe_surface * dst,const union pipe_color_union * color,unsigned dstx,unsigned dsty,unsigned width,unsigned height,bool render_condition_enabled)279 nv50_clear_render_target(struct pipe_context *pipe,
280 struct pipe_surface *dst,
281 const union pipe_color_union *color,
282 unsigned dstx, unsigned dsty,
283 unsigned width, unsigned height,
284 bool render_condition_enabled)
285 {
286 struct nv50_context *nv50 = nv50_context(pipe);
287 struct nouveau_pushbuf *push = nv50->base.pushbuf;
288 struct nv50_miptree *mt = nv50_miptree(dst->texture);
289 struct nv50_surface *sf = nv50_surface(dst);
290 struct nouveau_bo *bo = mt->base.bo;
291 unsigned z;
292
293 assert(dst->texture->target != PIPE_BUFFER);
294
295 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
296 PUSH_DATAf(push, color->f[0]);
297 PUSH_DATAf(push, color->f[1]);
298 PUSH_DATAf(push, color->f[2]);
299 PUSH_DATAf(push, color->f[3]);
300
301 if (!PUSH_SPACE_EX(push, 64 + sf->depth, 1, 0))
302 return;
303
304 PUSH_REF1(push, bo, mt->base.domain | NOUVEAU_BO_WR);
305
306 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
307 PUSH_DATA (push, ( width << 16) | dstx);
308 PUSH_DATA (push, (height << 16) | dsty);
309 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
310 PUSH_DATA (push, 8192 << 16);
311 PUSH_DATA (push, 8192 << 16);
312 nv50->scissors_dirty |= 1;
313
314 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
315 PUSH_DATA (push, 1);
316 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
317 PUSH_DATAh(push, mt->base.address + sf->offset);
318 PUSH_DATA (push, mt->base.address + sf->offset);
319 PUSH_DATA (push, nv50_format_table[dst->format].rt);
320 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
321 PUSH_DATA (push, mt->layer_stride >> 2);
322 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
323 if (nouveau_bo_memtype(bo))
324 PUSH_DATA(push, sf->width);
325 else
326 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
327 PUSH_DATA (push, sf->height);
328 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
329 if (mt->layout_3d)
330 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
331 else
332 PUSH_DATA(push, 512);
333
334 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
335 PUSH_DATA (push, mt->ms_mode);
336
337 if (!nouveau_bo_memtype(bo)) {
338 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
339 PUSH_DATA (push, 0);
340 }
341
342 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
343
344 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
345 PUSH_DATA (push, (width << 16) | dstx);
346 PUSH_DATA (push, (height << 16) | dsty);
347
348 if (!render_condition_enabled) {
349 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
350 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
351 }
352
353 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
354 for (z = 0; z < sf->depth; ++z) {
355 PUSH_DATA (push, 0x3c |
356 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
357 }
358
359 if (!render_condition_enabled) {
360 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
361 PUSH_DATA (push, nv50->cond_condmode);
362 }
363
364 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
365 }
366
367 static void
nv50_clear_depth_stencil(struct pipe_context * pipe,struct pipe_surface * dst,unsigned clear_flags,double depth,unsigned stencil,unsigned dstx,unsigned dsty,unsigned width,unsigned height,bool render_condition_enabled)368 nv50_clear_depth_stencil(struct pipe_context *pipe,
369 struct pipe_surface *dst,
370 unsigned clear_flags,
371 double depth,
372 unsigned stencil,
373 unsigned dstx, unsigned dsty,
374 unsigned width, unsigned height,
375 bool render_condition_enabled)
376 {
377 struct nv50_context *nv50 = nv50_context(pipe);
378 struct nouveau_pushbuf *push = nv50->base.pushbuf;
379 struct nv50_miptree *mt = nv50_miptree(dst->texture);
380 struct nv50_surface *sf = nv50_surface(dst);
381 struct nouveau_bo *bo = mt->base.bo;
382 uint32_t mode = 0;
383 unsigned z;
384
385 assert(dst->texture->target != PIPE_BUFFER);
386 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
387
388 if (clear_flags & PIPE_CLEAR_DEPTH) {
389 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
390 PUSH_DATAf(push, depth);
391 mode |= NV50_3D_CLEAR_BUFFERS_Z;
392 }
393
394 if (clear_flags & PIPE_CLEAR_STENCIL) {
395 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
396 PUSH_DATA (push, stencil & 0xff);
397 mode |= NV50_3D_CLEAR_BUFFERS_S;
398 }
399
400 if (!PUSH_SPACE_EX(push, 64 + sf->depth, 1, 0))
401 return;
402
403 PUSH_REF1(push, bo, mt->base.domain | NOUVEAU_BO_WR);
404
405 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
406 PUSH_DATA (push, ( width << 16) | dstx);
407 PUSH_DATA (push, (height << 16) | dsty);
408 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
409 PUSH_DATA (push, 8192 << 16);
410 PUSH_DATA (push, 8192 << 16);
411 nv50->scissors_dirty |= 1;
412
413 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
414 PUSH_DATAh(push, mt->base.address + sf->offset);
415 PUSH_DATA (push, mt->base.address + sf->offset);
416 PUSH_DATA (push, nv50_format_table[dst->format].rt);
417 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
418 PUSH_DATA (push, mt->layer_stride >> 2);
419 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
420 PUSH_DATA (push, 1);
421 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
422 PUSH_DATA (push, sf->width);
423 PUSH_DATA (push, sf->height);
424 PUSH_DATA (push, (1 << 16) | 1);
425
426 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
427 PUSH_DATA (push, 512);
428
429 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
430 PUSH_DATA (push, mt->ms_mode);
431
432 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
433 PUSH_DATA (push, (width << 16) | dstx);
434 PUSH_DATA (push, (height << 16) | dsty);
435
436 if (!render_condition_enabled) {
437 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
438 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
439 }
440
441 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
442 for (z = 0; z < sf->depth; ++z) {
443 PUSH_DATA (push, mode |
444 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
445 }
446
447 if (!render_condition_enabled) {
448 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
449 PUSH_DATA (push, nv50->cond_condmode);
450 }
451
452 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
453 }
454
455 void
nv50_clear(struct pipe_context * pipe,unsigned buffers,const struct pipe_scissor_state * scissor_state,const union pipe_color_union * color,double depth,unsigned stencil)456 nv50_clear(struct pipe_context *pipe, unsigned buffers, const struct pipe_scissor_state *scissor_state,
457 const union pipe_color_union *color,
458 double depth, unsigned stencil)
459 {
460 struct nv50_context *nv50 = nv50_context(pipe);
461 struct nouveau_pushbuf *push = nv50->base.pushbuf;
462 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
463 unsigned i, j, k;
464 uint32_t mode = 0;
465
466 simple_mtx_lock(&nv50->screen->state_lock);
467
468 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
469 if (!nv50_state_validate_3d(nv50, NV50_NEW_3D_FRAMEBUFFER))
470 goto out;
471
472 if (scissor_state) {
473 uint32_t minx = scissor_state->minx;
474 uint32_t maxx = MIN2(fb->width, scissor_state->maxx);
475 uint32_t miny = scissor_state->miny;
476 uint32_t maxy = MIN2(fb->height, scissor_state->maxy);
477 if (maxx <= minx || maxy <= miny)
478 goto out;
479
480 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
481 PUSH_DATA (push, minx | (maxx - minx) << 16);
482 PUSH_DATA (push, miny | (maxy - miny) << 16);
483 }
484
485 /* We have to clear ALL of the layers, not up to the min number of layers
486 * of any attachment. */
487 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
488 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
489
490 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
491 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
492 PUSH_DATAf(push, color->f[0]);
493 PUSH_DATAf(push, color->f[1]);
494 PUSH_DATAf(push, color->f[2]);
495 PUSH_DATAf(push, color->f[3]);
496 if (buffers & PIPE_CLEAR_COLOR0)
497 mode =
498 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
499 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
500 }
501
502 if (buffers & PIPE_CLEAR_DEPTH) {
503 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
504 PUSH_DATA (push, fui(depth));
505 mode |= NV50_3D_CLEAR_BUFFERS_Z;
506 }
507
508 if (buffers & PIPE_CLEAR_STENCIL) {
509 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
510 PUSH_DATA (push, stencil & 0xff);
511 mode |= NV50_3D_CLEAR_BUFFERS_S;
512 }
513
514 if (mode) {
515 int zs_layers = 0, color0_layers = 0;
516 if (fb->cbufs[0] && (mode & 0x3c))
517 color0_layers = nv50_surface(fb->cbufs[0])->depth;
518 if (fb->zsbuf && (mode & ~0x3c))
519 zs_layers = nv50_surface(fb->zsbuf)->depth;
520
521 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
522 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
523 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
524 }
525 for (k = j; k < zs_layers; k++) {
526 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
527 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
528 }
529 for (k = j; k < color0_layers; k++) {
530 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
531 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
532 }
533 }
534
535 for (i = 1; i < fb->nr_cbufs; i++) {
536 struct pipe_surface *sf = fb->cbufs[i];
537 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
538 continue;
539 for (j = 0; j < nv50_surface(sf)->depth; j++) {
540 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
541 PUSH_DATA (push, (i << 6) | 0x3c |
542 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
543 }
544 }
545
546 /* restore the array mode */
547 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
548 PUSH_DATA (push, nv50->rt_array_mode);
549
550 /* restore screen scissor */
551 if (scissor_state) {
552 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
553 PUSH_DATA (push, fb->width << 16);
554 PUSH_DATA (push, fb->height << 16);
555 }
556
557 out:
558 PUSH_KICK(push);
559 simple_mtx_unlock(&nv50->screen->state_lock);
560 }
561
562 static void
nv50_clear_buffer_push(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size,const void * data,int data_size)563 nv50_clear_buffer_push(struct pipe_context *pipe,
564 struct pipe_resource *res,
565 unsigned offset, unsigned size,
566 const void *data, int data_size)
567 {
568 struct nv50_context *nv50 = nv50_context(pipe);
569 struct nouveau_pushbuf *push = nv50->base.pushbuf;
570 struct nv04_resource *buf = nv04_resource(res);
571 unsigned count = (size + 3) / 4;
572 unsigned xcoord = offset & 0xff;
573 unsigned tmp, i;
574
575 if (data_size == 1) {
576 tmp = *(unsigned char *)data;
577 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
578 data = &tmp;
579 data_size = 4;
580 } else if (data_size == 2) {
581 tmp = *(unsigned short *)data;
582 tmp = (tmp << 16) | tmp;
583 data = &tmp;
584 data_size = 4;
585 }
586
587 unsigned data_words = data_size / 4;
588
589 nouveau_bufctx_refn(nv50->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
590 nouveau_pushbuf_bufctx(push, nv50->bufctx);
591 PUSH_VAL(push);
592
593 offset &= ~0xff;
594
595 BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
596 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
597 PUSH_DATA (push, 1);
598 BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
599 PUSH_DATA (push, 262144);
600 PUSH_DATA (push, 65536);
601 PUSH_DATA (push, 1);
602 PUSH_DATAh(push, buf->address + offset);
603 PUSH_DATA (push, buf->address + offset);
604 BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
605 PUSH_DATA (push, 0);
606 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
607 BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
608 PUSH_DATA (push, size);
609 PUSH_DATA (push, 1);
610 PUSH_DATA (push, 0);
611 PUSH_DATA (push, 1);
612 PUSH_DATA (push, 0);
613 PUSH_DATA (push, 1);
614 PUSH_DATA (push, 0);
615 PUSH_DATA (push, xcoord);
616 PUSH_DATA (push, 0);
617 PUSH_DATA (push, 0);
618
619 while (count) {
620 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
621 unsigned nr = nr_data * data_words;
622
623 BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);
624 for (i = 0; i < nr_data; i++)
625 PUSH_DATAp(push, data, data_words);
626
627 count -= nr;
628 }
629
630 nv50_resource_validate(nv50, buf, NOUVEAU_BO_WR);
631
632 nouveau_bufctx_reset(nv50->bufctx, 0);
633 }
634
635 static void
nv50_clear_buffer(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size,const void * data,int data_size)636 nv50_clear_buffer(struct pipe_context *pipe,
637 struct pipe_resource *res,
638 unsigned offset, unsigned size,
639 const void *data, int data_size)
640 {
641 struct nv50_context *nv50 = nv50_context(pipe);
642 struct nouveau_pushbuf *push = nv50->base.pushbuf;
643 struct nv04_resource *buf = (struct nv04_resource *)res;
644 union pipe_color_union color;
645 enum pipe_format dst_fmt;
646 unsigned width, height, elements;
647
648 assert(res->target == PIPE_BUFFER);
649 assert(nouveau_bo_memtype(buf->bo) == 0);
650
651 switch (data_size) {
652 case 16:
653 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
654 memcpy(&color.ui, data, 16);
655 break;
656 case 8:
657 dst_fmt = PIPE_FORMAT_R32G32_UINT;
658 memcpy(&color.ui, data, 8);
659 memset(&color.ui[2], 0, 8);
660 break;
661 case 4:
662 dst_fmt = PIPE_FORMAT_R32_UINT;
663 memcpy(&color.ui, data, 4);
664 memset(&color.ui[1], 0, 12);
665 break;
666 case 2:
667 dst_fmt = PIPE_FORMAT_R16_UINT;
668 color.ui[0] = util_cpu_to_le32(
669 util_le16_to_cpu(*(unsigned short *)data));
670 memset(&color.ui[1], 0, 12);
671 break;
672 case 1:
673 dst_fmt = PIPE_FORMAT_R8_UINT;
674 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
675 memset(&color.ui[1], 0, 12);
676 break;
677 default:
678 assert(!"Unsupported element size");
679 return;
680 }
681
682 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
683
684 assert(size % data_size == 0);
685
686 if (offset & 0xff) {
687 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
688 assert(fixup_size % data_size == 0);
689 nv50_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
690 offset += fixup_size;
691 size -= fixup_size;
692 if (!size)
693 return;
694 }
695
696 elements = size / data_size;
697 height = (elements + 8191) / 8192;
698 width = elements / height;
699 if (height > 1)
700 width &= ~0xff;
701 assert(width > 0);
702
703 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
704 PUSH_DATA (push, color.ui[0]);
705 PUSH_DATA (push, color.ui[1]);
706 PUSH_DATA (push, color.ui[2]);
707 PUSH_DATA (push, color.ui[3]);
708
709 if (!PUSH_SPACE_EX(push, 64, 1, 0))
710 return;
711
712 PUSH_REF1(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
713
714 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
715 PUSH_DATA (push, width << 16);
716 PUSH_DATA (push, height << 16);
717 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
718 PUSH_DATA (push, 8192 << 16);
719 PUSH_DATA (push, 8192 << 16);
720 nv50->scissors_dirty |= 1;
721
722 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
723 PUSH_DATA (push, 1);
724 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
725 PUSH_DATAh(push, buf->address + offset);
726 PUSH_DATA (push, buf->address + offset);
727 PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
728 PUSH_DATA (push, 0);
729 PUSH_DATA (push, 0);
730 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
731 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | align(width * data_size, 0x100));
732 PUSH_DATA (push, height);
733 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
734 PUSH_DATA (push, 0);
735 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
736 PUSH_DATA (push, 0);
737
738 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
739
740 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
741 PUSH_DATA (push, (width << 16));
742 PUSH_DATA (push, (height << 16));
743
744 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
745 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
746
747 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
748 PUSH_DATA (push, 0x3c);
749
750 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
751 PUSH_DATA (push, nv50->cond_condmode);
752
753 nv50_resource_validate(nv50, buf, NOUVEAU_BO_WR);
754
755 if (width * height != elements) {
756 offset += width * height * data_size;
757 width = elements - width * height;
758 nv50_clear_buffer_push(pipe, res, offset, width * data_size,
759 data, data_size);
760 }
761
762 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
763 }
764
765 /* =============================== BLIT CODE ===================================
766 */
767
768 struct nv50_blitter
769 {
770 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
771 struct nv50_program vp;
772
773 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
774
775 mtx_t mutex;
776 };
777
778 struct nv50_blitctx
779 {
780 struct nv50_context *nv50;
781 struct nv50_program *fp;
782 uint8_t mode;
783 uint16_t color_mask;
784 uint8_t filter;
785 uint8_t render_condition_enable;
786 enum pipe_texture_target target;
787 struct {
788 struct pipe_framebuffer_state fb;
789 struct nv50_window_rect_stateobj window_rect;
790 struct nv50_rasterizer_stateobj *rast;
791 struct nv50_program *vp;
792 struct nv50_program *gp;
793 struct nv50_program *fp;
794 unsigned num_textures[NV50_MAX_3D_SHADER_STAGES];
795 unsigned num_samplers[NV50_MAX_3D_SHADER_STAGES];
796 struct pipe_sampler_view *texture[2];
797 struct nv50_tsc_entry *sampler[2];
798 unsigned min_samples;
799 uint32_t dirty_3d;
800 } saved;
801 struct nv50_rasterizer_stateobj rast;
802 };
803
804 static void
nv50_blitter_make_vp(struct nv50_blitter * blit)805 nv50_blitter_make_vp(struct nv50_blitter *blit)
806 {
807 static const uint32_t code[] =
808 {
809 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
810 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
811 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
812 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
813 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
814 };
815
816 blit->vp.type = PIPE_SHADER_VERTEX;
817 blit->vp.translated = true;
818 blit->vp.code = (uint32_t *)code; /* const_cast */
819 blit->vp.code_size = sizeof(code);
820 blit->vp.max_gpr = 4;
821 blit->vp.max_out = 5;
822 blit->vp.out_nr = 2;
823 blit->vp.out[0].mask = 0x3;
824 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
825 blit->vp.out[1].hw = 2;
826 blit->vp.out[1].mask = 0x7;
827 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
828 blit->vp.out[1].si = 0;
829 blit->vp.vp.attrs[0] = 0x73;
830 blit->vp.vp.psiz = 0x40;
831 blit->vp.vp.edgeflag = 0x40;
832 }
833
834 void *
nv50_blitter_make_fp(struct pipe_context * pipe,unsigned mode,enum pipe_texture_target ptarg)835 nv50_blitter_make_fp(struct pipe_context *pipe,
836 unsigned mode,
837 enum pipe_texture_target ptarg)
838 {
839 enum glsl_sampler_dim sampler_dim
840 = nv50_blit_get_glsl_sampler_dim(ptarg);
841 bool is_array = nv50_blit_is_array(ptarg);
842
843 bool tex_rgbaz = false;
844 bool tex_s = false;
845 bool cvt_un8 = false;
846
847 bool int_clamp = mode == NV50_BLIT_MODE_INT_CLAMP;
848 if (int_clamp)
849 mode = NV50_BLIT_MODE_PASS;
850
851 if (mode != NV50_BLIT_MODE_PASS &&
852 mode != NV50_BLIT_MODE_Z24X8 &&
853 mode != NV50_BLIT_MODE_X8Z24)
854 tex_s = true;
855
856 if (mode != NV50_BLIT_MODE_X24S8 &&
857 mode != NV50_BLIT_MODE_S8X24 &&
858 mode != NV50_BLIT_MODE_XS)
859 tex_rgbaz = true;
860
861 if (mode != NV50_BLIT_MODE_PASS &&
862 mode != NV50_BLIT_MODE_ZS &&
863 mode != NV50_BLIT_MODE_XS)
864 cvt_un8 = true;
865
866 const int chipset = nouveau_screen(pipe->screen)->device->chipset;
867 const nir_shader_compiler_options *options =
868 nv50_ir_nir_shader_compiler_options(chipset, PIPE_SHADER_FRAGMENT);
869
870 struct nir_builder b =
871 nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, options,
872 "blitter_fp");
873
874 /* load coordinates */
875 const struct glsl_type* float3 = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
876 nir_variable *coord_var =
877 nir_variable_create(b.shader, nir_var_shader_in, float3, "coord");
878 coord_var->data.location = VARYING_SLOT_VAR0;
879 coord_var->data.interpolation = INTERP_MODE_NOPERSPECTIVE;
880
881 nir_def *coord = nir_load_var(&b, coord_var);
882 if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
883 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
884 coord = nir_channels(&b, coord, TGSI_WRITEMASK_XZ);
885 } else {
886 int size = glsl_get_sampler_dim_coordinate_components(sampler_dim);
887 if (is_array) size += 1;
888 coord = nir_trim_vector(&b, coord, size);
889 }
890
891 /* sample textures */
892 const struct glsl_type *sampler_type =
893 glsl_sampler_type(sampler_dim, false, is_array, GLSL_TYPE_FLOAT);
894
895 nir_def *s = NULL;
896 if (tex_s) {
897 nir_variable *sampler =
898 nir_variable_create(b.shader, nir_var_uniform,
899 sampler_type, "sampler_s");
900 sampler->data.binding = 1;
901
902 nir_deref_instr *tex_deref = nir_build_deref_var(&b, sampler);
903
904 s = nir_tex_deref(&b, tex_deref, tex_deref, coord);
905 s = nir_channel(&b, s, 0);
906 }
907
908 nir_def *rgba = NULL, *z = NULL;
909 if (tex_rgbaz) {
910 nir_variable *sampler =
911 nir_variable_create(b.shader, nir_var_uniform,
912 sampler_type, "sampler_rgbaz");
913 sampler->data.binding = 0;
914
915 nir_deref_instr *tex_deref = nir_build_deref_var(&b, sampler);
916
917 rgba = nir_tex_deref(&b, tex_deref, tex_deref, coord);
918 z = nir_channel(&b, rgba, 0);
919 }
920
921 /* handle signed to unsigned integer conversions */
922 if (int_clamp) {
923 rgba = nir_umin(&b, rgba, nir_imm_int(&b, 0x7fffffff));
924 }
925
926 /* handle conversions */
927 nir_def *out_ssa;
928 nir_component_mask_t out_mask = 0;
929 if (cvt_un8) {
930 if (tex_s) {
931 s = nir_i2f32(&b, s);
932 s = nir_fmul_imm(&b, s, 1.0f / 0xff);
933 } else {
934 s = nir_undef(&b, 1, 32);
935 }
936
937 if (tex_rgbaz) {
938 z = nir_fmul_imm(&b, z, (1 << 24) - 1);
939 z = nir_f2i32(&b, z);
940 z = nir_iand(&b, z, nir_imm_ivec3(&b, 0x0000ff,
941 0x00ff00,
942 0xff0000));
943 z = nir_i2f32(&b, z);
944 z = nir_fmul(&b, z, nir_imm_vec3(&b, 1.0f / 0x0000ff,
945 1.0f / 0x00ff00,
946 1.0f / 0xff0000));
947 } else {
948 z = nir_undef(&b, 3, 32);
949 }
950
951 if (mode == NV50_BLIT_MODE_Z24S8 ||
952 mode == NV50_BLIT_MODE_X24S8 ||
953 mode == NV50_BLIT_MODE_Z24X8) {
954 out_ssa = nir_vec4(&b,
955 nir_channel(&b, z, 0),
956 nir_channel(&b, z, 1),
957 nir_channel(&b, z, 2),
958 s);
959
960 if (tex_rgbaz) out_mask |= TGSI_WRITEMASK_XYZ;
961 if (tex_s) out_mask |= TGSI_WRITEMASK_W;
962 } else {
963 out_ssa = nir_vec4(&b,
964 s,
965 nir_channel(&b, z, 0),
966 nir_channel(&b, z, 1),
967 nir_channel(&b, z, 2));
968
969 if (tex_rgbaz) out_mask |= TGSI_WRITEMASK_YZW;
970 if (tex_s) out_mask |= TGSI_WRITEMASK_X;
971 }
972 } else {
973 if (mode == NV50_BLIT_MODE_PASS) {
974 out_ssa = rgba;
975 out_mask |= TGSI_WRITEMASK_XYZW;
976 } else {
977 out_ssa = nir_vec2(&b, z ? z : nir_undef(&b, 1, 32),
978 s ? s : nir_undef(&b, 1, 32));
979 if (tex_rgbaz) out_mask |= TGSI_WRITEMASK_X;
980 if (tex_s) out_mask |= TGSI_WRITEMASK_Y;
981 }
982 }
983
984 /* write output */
985 const struct glsl_type* out_type =
986 glsl_vector_type(GLSL_TYPE_FLOAT, out_ssa->num_components);
987 nir_variable *out_var =
988 nir_variable_create(b.shader, nir_var_shader_out, out_type, "out");
989 out_var->data.location = FRAG_RESULT_DATA0;
990
991 nir_store_var(&b, out_var, out_ssa, out_mask);
992
993 /* return shader */
994 NIR_PASS_V(b.shader, nir_lower_samplers);
995
996 return pipe_shader_from_nir(pipe, b.shader);
997 }
998
999 static void
nv50_blitter_make_sampler(struct nv50_blitter * blit)1000 nv50_blitter_make_sampler(struct nv50_blitter *blit)
1001 {
1002 /* clamp to edge, min/max lod = 0, nearest filtering */
1003
1004 blit->sampler[0].id = -1;
1005
1006 blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
1007 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
1008 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
1009 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
1010 blit->sampler[0].tsc[1] =
1011 G80_TSC_1_MAG_FILTER_NEAREST |
1012 G80_TSC_1_MIN_FILTER_NEAREST |
1013 G80_TSC_1_MIP_FILTER_NONE;
1014
1015 /* clamp to edge, min/max lod = 0, bilinear filtering */
1016
1017 blit->sampler[1].id = -1;
1018
1019 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
1020 blit->sampler[1].tsc[1] =
1021 G80_TSC_1_MAG_FILTER_LINEAR |
1022 G80_TSC_1_MIN_FILTER_LINEAR |
1023 G80_TSC_1_MIP_FILTER_NONE;
1024 }
1025
1026 unsigned
nv50_blit_select_mode(const struct pipe_blit_info * info)1027 nv50_blit_select_mode(const struct pipe_blit_info *info)
1028 {
1029 const unsigned mask = info->mask;
1030
1031 switch (info->dst.resource->format) {
1032 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1033 case PIPE_FORMAT_Z24X8_UNORM:
1034 case PIPE_FORMAT_X24S8_UINT:
1035 switch (mask & PIPE_MASK_ZS) {
1036 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
1037 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
1038 default:
1039 return NV50_BLIT_MODE_X24S8;
1040 }
1041 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1042 case PIPE_FORMAT_X8Z24_UNORM:
1043 case PIPE_FORMAT_S8X24_UINT:
1044 switch (mask & PIPE_MASK_ZS) {
1045 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
1046 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
1047 default:
1048 return NV50_BLIT_MODE_S8X24;
1049 }
1050 case PIPE_FORMAT_Z32_FLOAT:
1051 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1052 case PIPE_FORMAT_X32_S8X24_UINT:
1053 switch (mask & PIPE_MASK_ZS) {
1054 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
1055 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
1056 default:
1057 return NV50_BLIT_MODE_XS;
1058 }
1059 default:
1060 if (util_format_is_pure_uint(info->src.format) &&
1061 util_format_is_pure_sint(info->dst.format))
1062 return NV50_BLIT_MODE_INT_CLAMP;
1063 return NV50_BLIT_MODE_PASS;
1064 }
1065 }
1066
1067 static void
nv50_blit_select_fp(struct nv50_blitctx * ctx,const struct pipe_blit_info * info)1068 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
1069 {
1070 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
1071
1072 const enum pipe_texture_target ptarg =
1073 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
1074
1075 const unsigned targ = nv50_blit_texture_type(ptarg);
1076 const unsigned mode = ctx->mode;
1077
1078 if (!blitter->fp[targ][mode]) {
1079 mtx_lock(&blitter->mutex);
1080 if (!blitter->fp[targ][mode])
1081 blitter->fp[targ][mode] =
1082 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
1083 mtx_unlock(&blitter->mutex);
1084 }
1085 ctx->fp = blitter->fp[targ][mode];
1086 }
1087
1088 static void
nv50_blit_set_dst(struct nv50_blitctx * ctx,struct pipe_resource * res,unsigned level,unsigned layer,enum pipe_format format)1089 nv50_blit_set_dst(struct nv50_blitctx *ctx,
1090 struct pipe_resource *res, unsigned level, unsigned layer,
1091 enum pipe_format format)
1092 {
1093 struct nv50_context *nv50 = ctx->nv50;
1094 struct pipe_context *pipe = &nv50->base.pipe;
1095 struct pipe_surface templ;
1096
1097 if (util_format_is_depth_or_stencil(format))
1098 templ.format = nv50_blit_zeta_to_colour_format(format);
1099 else
1100 templ.format = format;
1101
1102 templ.u.tex.level = level;
1103 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1104
1105 if (layer == -1) {
1106 templ.u.tex.first_layer = 0;
1107 templ.u.tex.last_layer =
1108 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1109 }
1110
1111 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
1112 nv50->framebuffer.nr_cbufs = 1;
1113 nv50->framebuffer.zsbuf = NULL;
1114 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
1115 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
1116 }
1117
1118 static void
nv50_blit_set_src(struct nv50_blitctx * blit,struct pipe_resource * res,unsigned level,unsigned layer,enum pipe_format format,const uint8_t filter)1119 nv50_blit_set_src(struct nv50_blitctx *blit,
1120 struct pipe_resource *res, unsigned level, unsigned layer,
1121 enum pipe_format format, const uint8_t filter)
1122 {
1123 struct nv50_context *nv50 = blit->nv50;
1124 struct pipe_context *pipe = &nv50->base.pipe;
1125 struct pipe_sampler_view templ = {0};
1126 uint32_t flags;
1127 enum pipe_texture_target target;
1128
1129 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
1130
1131 templ.target = target;
1132 templ.format = format;
1133 templ.u.tex.first_level = templ.u.tex.last_level = level;
1134 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1135 templ.swizzle_r = PIPE_SWIZZLE_X;
1136 templ.swizzle_g = PIPE_SWIZZLE_Y;
1137 templ.swizzle_b = PIPE_SWIZZLE_Z;
1138 templ.swizzle_a = PIPE_SWIZZLE_W;
1139
1140 if (layer == -1) {
1141 templ.u.tex.first_layer = 0;
1142 templ.u.tex.last_layer =
1143 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1144 }
1145
1146 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
1147 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
1148 if (filter && res->nr_samples == 8)
1149 flags |= NV50_TEXVIEW_FILTER_MSAA8;
1150
1151 nv50->textures[NV50_SHADER_STAGE_FRAGMENT][0] = nv50_create_texture_view(
1152 pipe, res, &templ, flags);
1153 nv50->textures[NV50_SHADER_STAGE_FRAGMENT][1] = NULL;
1154
1155 nv50->num_textures[NV50_SHADER_STAGE_VERTEX] = 0;
1156 nv50->num_textures[NV50_SHADER_STAGE_GEOMETRY] = 0;
1157 nv50->num_textures[NV50_SHADER_STAGE_FRAGMENT] = 1;
1158
1159 templ.format = nv50_zs_to_s_format(format);
1160 if (templ.format != res->format) {
1161 nv50->textures[NV50_SHADER_STAGE_FRAGMENT][1] = nv50_create_texture_view(
1162 pipe, res, &templ, flags);
1163 nv50->num_textures[NV50_SHADER_STAGE_FRAGMENT] = 2;
1164 }
1165 }
1166
1167 static void
nv50_blitctx_prepare_state(struct nv50_blitctx * blit)1168 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
1169 {
1170 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
1171
1172 if (blit->nv50->cond_query && !blit->render_condition_enable) {
1173 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
1174 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
1175 }
1176
1177 /* blend state */
1178 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
1179 PUSH_DATA (push, blit->color_mask);
1180 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
1181 PUSH_DATA (push, 0);
1182 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
1183 PUSH_DATA (push, 0);
1184
1185 /* rasterizer state */
1186 #ifndef NV50_SCISSORS_CLIPPING
1187 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
1188 PUSH_DATA (push, 1);
1189 #endif
1190 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
1191 PUSH_DATA (push, 0);
1192 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
1193 PUSH_DATA (push, 0);
1194 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
1195 PUSH_DATA (push, 0);
1196 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
1197 PUSH_DATA (push, 0xffff);
1198 PUSH_DATA (push, 0xffff);
1199 PUSH_DATA (push, 0xffff);
1200 PUSH_DATA (push, 0xffff);
1201 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
1202 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
1203 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
1204 PUSH_DATA (push, 0);
1205 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
1206 PUSH_DATA (push, 0);
1207 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
1208 PUSH_DATA (push, 0);
1209 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
1210 PUSH_DATA (push, 0);
1211
1212 /* zsa state */
1213 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
1214 PUSH_DATA (push, 0);
1215 BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
1216 PUSH_DATA (push, 0);
1217 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
1218 PUSH_DATA (push, 0);
1219 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
1220 PUSH_DATA (push, 0);
1221 }
1222
1223 static void
nv50_blitctx_pre_blit(struct nv50_blitctx * ctx,const struct pipe_blit_info * info)1224 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx,
1225 const struct pipe_blit_info *info)
1226 {
1227 struct nv50_context *nv50 = ctx->nv50;
1228 struct nv50_blitter *blitter = nv50->screen->blitter;
1229 int s;
1230
1231 ctx->saved.fb.width = nv50->framebuffer.width;
1232 ctx->saved.fb.height = nv50->framebuffer.height;
1233 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
1234 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
1235 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
1236
1237 ctx->saved.rast = nv50->rast;
1238
1239 ctx->saved.vp = nv50->vertprog;
1240 ctx->saved.gp = nv50->gmtyprog;
1241 ctx->saved.fp = nv50->fragprog;
1242
1243 ctx->saved.min_samples = nv50->min_samples;
1244 ctx->saved.window_rect = nv50->window_rect;
1245
1246 nv50->rast = &ctx->rast;
1247
1248 nv50->vertprog = &blitter->vp;
1249 nv50->gmtyprog = NULL;
1250 nv50->fragprog = ctx->fp;
1251
1252 nv50->window_rect.rects =
1253 MIN2(info->num_window_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1254 nv50->window_rect.inclusive = info->window_rectangle_include;
1255 if (nv50->window_rect.rects)
1256 memcpy(nv50->window_rect.rect, info->window_rectangles,
1257 sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1258
1259 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES; ++s) {
1260 ctx->saved.num_textures[s] = nv50->num_textures[s];
1261 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1262 }
1263 ctx->saved.texture[0] = nv50->textures[NV50_SHADER_STAGE_FRAGMENT][0];
1264 ctx->saved.texture[1] = nv50->textures[NV50_SHADER_STAGE_FRAGMENT][1];
1265 ctx->saved.sampler[0] = nv50->samplers[NV50_SHADER_STAGE_FRAGMENT][0];
1266 ctx->saved.sampler[1] = nv50->samplers[NV50_SHADER_STAGE_FRAGMENT][1];
1267
1268 nv50->samplers[NV50_SHADER_STAGE_FRAGMENT][0] = &blitter->sampler[ctx->filter];
1269 nv50->samplers[NV50_SHADER_STAGE_FRAGMENT][1] = &blitter->sampler[ctx->filter];
1270
1271 nv50->num_samplers[NV50_SHADER_STAGE_VERTEX] = 0;
1272 nv50->num_samplers[NV50_SHADER_STAGE_GEOMETRY] = 0;
1273 nv50->num_samplers[NV50_SHADER_STAGE_FRAGMENT] = 2;
1274
1275 nv50->min_samples = 1;
1276
1277 ctx->saved.dirty_3d = nv50->dirty_3d;
1278
1279 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1280 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
1281
1282 nv50->dirty_3d =
1283 NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_MIN_SAMPLES |
1284 NV50_NEW_3D_VERTPROG | NV50_NEW_3D_FRAGPROG | NV50_NEW_3D_GMTYPROG |
1285 NV50_NEW_3D_TEXTURES | NV50_NEW_3D_SAMPLERS | NV50_NEW_3D_WINDOW_RECTS;
1286 }
1287
1288 static void
nv50_blitctx_post_blit(struct nv50_blitctx * blit)1289 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1290 {
1291 struct nv50_context *nv50 = blit->nv50;
1292 int s;
1293
1294 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1295
1296 nv50->framebuffer.width = blit->saved.fb.width;
1297 nv50->framebuffer.height = blit->saved.fb.height;
1298 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1299 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1300 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1301
1302 nv50->rast = blit->saved.rast;
1303
1304 nv50->vertprog = blit->saved.vp;
1305 nv50->gmtyprog = blit->saved.gp;
1306 nv50->fragprog = blit->saved.fp;
1307
1308 nv50->min_samples = blit->saved.min_samples;
1309 nv50->window_rect = blit->saved.window_rect;
1310
1311 pipe_sampler_view_reference(&nv50->textures[NV50_SHADER_STAGE_FRAGMENT][0], NULL);
1312 pipe_sampler_view_reference(&nv50->textures[NV50_SHADER_STAGE_FRAGMENT][1], NULL);
1313
1314 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES; ++s) {
1315 nv50->num_textures[s] = blit->saved.num_textures[s];
1316 nv50->num_samplers[s] = blit->saved.num_samplers[s];
1317 }
1318 nv50->textures[NV50_SHADER_STAGE_FRAGMENT][0] = blit->saved.texture[0];
1319 nv50->textures[NV50_SHADER_STAGE_FRAGMENT][1] = blit->saved.texture[1];
1320 nv50->samplers[NV50_SHADER_STAGE_FRAGMENT][0] = blit->saved.sampler[0];
1321 nv50->samplers[NV50_SHADER_STAGE_FRAGMENT][1] = blit->saved.sampler[1];
1322
1323 if (nv50->cond_query && !blit->render_condition_enable)
1324 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1325 nv50->cond_cond, nv50->cond_mode);
1326
1327 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1328 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
1329
1330 nv50->dirty_3d = blit->saved.dirty_3d |
1331 (NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR | NV50_NEW_3D_SAMPLE_MASK |
1332 NV50_NEW_3D_RASTERIZER | NV50_NEW_3D_ZSA | NV50_NEW_3D_BLEND |
1333 NV50_NEW_3D_TEXTURES | NV50_NEW_3D_SAMPLERS | NV50_NEW_3D_WINDOW_RECTS |
1334 NV50_NEW_3D_VERTPROG | NV50_NEW_3D_GMTYPROG | NV50_NEW_3D_FRAGPROG);
1335 nv50->scissors_dirty |= 1;
1336
1337 nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1338 }
1339
1340
1341 static void
nv50_blit_3d(struct nv50_context * nv50,const struct pipe_blit_info * info)1342 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1343 {
1344 struct nv50_blitctx *blit = nv50->blit;
1345 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1346 struct pipe_resource *src = info->src.resource;
1347 struct pipe_resource *dst = info->dst.resource;
1348 int32_t minx, maxx, miny, maxy;
1349 int32_t i;
1350 float x0, x1, y0, y1, z;
1351 float dz;
1352 float x_range, y_range;
1353
1354 blit->mode = nv50_blit_select_mode(info);
1355 blit->color_mask = nv50_blit_derive_color_mask(info);
1356 blit->filter = nv50_blit_get_filter(info);
1357 blit->render_condition_enable = info->render_condition_enable;
1358
1359 nv50_blit_select_fp(blit, info);
1360 nv50_blitctx_pre_blit(blit, info);
1361
1362 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1363 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1364 blit->filter);
1365
1366 nv50_blitctx_prepare_state(blit);
1367
1368 nv50_state_validate_3d(nv50, ~0);
1369
1370 /* When flipping a surface from zeta <-> color "mode", we have to wait for
1371 * the GPU to flush its current draws.
1372 */
1373 struct nv50_miptree *mt = nv50_miptree(dst);
1374 bool serialize = util_format_is_depth_or_stencil(info->dst.format);
1375 if (serialize && mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
1376 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
1377 PUSH_DATA (push, 0);
1378 }
1379
1380 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1381 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1382
1383 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1384 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1385
1386 x1 = x0 + 16384.0f * x_range;
1387 y1 = y0 + 16384.0f * y_range;
1388
1389 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1390 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1391 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1392 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1393
1394 /* XXX: multiply by 6 for cube arrays ? */
1395 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1396 z = (float)info->src.box.z;
1397 if (nv50_miptree(src)->layout_3d)
1398 z += 0.5f * dz;
1399
1400 if (src->last_level > 0) {
1401 /* If there are mip maps, GPU always assumes normalized coordinates. */
1402 const unsigned l = info->src.level;
1403 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1404 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1405 x0 /= fh;
1406 x1 /= fh;
1407 y0 /= fv;
1408 y1 /= fv;
1409 if (nv50_miptree(src)->layout_3d) {
1410 z /= u_minify(src->depth0, l);
1411 dz /= u_minify(src->depth0, l);
1412 }
1413 }
1414
1415 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1416 PUSH_DATA (push, 0);
1417 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1418 PUSH_DATA (push, 0x1);
1419
1420 /* Draw a large triangle in screen coordinates covering the whole
1421 * render target, with scissors defining the destination region.
1422 * The vertex is supplied with non-normalized texture coordinates
1423 * arranged in a way to yield the desired offset and scale.
1424 */
1425
1426 minx = info->dst.box.x;
1427 maxx = info->dst.box.x + info->dst.box.width;
1428 miny = info->dst.box.y;
1429 maxy = info->dst.box.y + info->dst.box.height;
1430 if (info->scissor_enable) {
1431 minx = MAX2(minx, info->scissor.minx);
1432 maxx = MIN2(maxx, info->scissor.maxx);
1433 miny = MAX2(miny, info->scissor.miny);
1434 maxy = MIN2(maxy, info->scissor.maxy);
1435 }
1436 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1437 PUSH_DATA (push, (maxx << 16) | minx);
1438 PUSH_DATA (push, (maxy << 16) | miny);
1439
1440 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1441 if (info->dst.box.z + i) {
1442 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1443 PUSH_DATA (push, info->dst.box.z + i);
1444 }
1445 PUSH_SPACE(push, 32);
1446 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1447 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1448 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1449 PUSH_DATAf(push, x0);
1450 PUSH_DATAf(push, y0);
1451 PUSH_DATAf(push, z);
1452 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1453 PUSH_DATAf(push, 0.0f);
1454 PUSH_DATAf(push, 0.0f);
1455 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1456 PUSH_DATAf(push, x1);
1457 PUSH_DATAf(push, y0);
1458 PUSH_DATAf(push, z);
1459 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1460 PUSH_DATAf(push, 16384.0f);
1461 PUSH_DATAf(push, 0.0f);
1462 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1463 PUSH_DATAf(push, x0);
1464 PUSH_DATAf(push, y1);
1465 PUSH_DATAf(push, z);
1466 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1467 PUSH_DATAf(push, 0.0f);
1468 PUSH_DATAf(push, 16384.0f);
1469 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1470 PUSH_DATA (push, 0);
1471 }
1472 if (info->dst.box.z + info->dst.box.depth - 1) {
1473 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1474 PUSH_DATA (push, 0);
1475 }
1476
1477 /* re-enable normally constant state */
1478
1479 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1480 PUSH_DATA (push, 1);
1481
1482 /* mark the surface as reading, which will force a serialize next time it's
1483 * used for writing.
1484 */
1485 if (serialize)
1486 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
1487
1488 nv50_blitctx_post_blit(blit);
1489 }
1490
1491 static void
nv50_blit_eng2d(struct nv50_context * nv50,const struct pipe_blit_info * info)1492 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1493 {
1494 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1495 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1496 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1497 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1498 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1499 const int32_t dz = info->dst.box.z;
1500 const int32_t sz = info->src.box.z;
1501 uint32_t dstw, dsth;
1502 int32_t dstx, dsty;
1503 int64_t srcx, srcy;
1504 int64_t du_dx, dv_dy;
1505 int i;
1506 uint32_t mode;
1507 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1508 bool b;
1509
1510 mode = nv50_blit_get_filter(info) ?
1511 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1512 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1513 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1514 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1515
1516 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1517 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1518
1519 b = info->dst.format == info->src.format;
1520 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1521 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1522
1523 if (info->scissor_enable) {
1524 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1525 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1526 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1527 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1528 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1529 PUSH_DATA (push, 1); /* enable */
1530 }
1531
1532 if (nv50->cond_query && info->render_condition_enable) {
1533 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1534 PUSH_DATA (push, nv50->cond_condmode);
1535 }
1536
1537 if (mask != 0xffffffff) {
1538 BEGIN_NV04(push, NV50_2D(ROP), 1);
1539 PUSH_DATA (push, 0xca); /* DPSDxax */
1540 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1541 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1542 BEGIN_NV04(push, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1543 PUSH_DATA (push, 0x00000000);
1544 PUSH_DATA (push, mask);
1545 PUSH_DATA (push, 0xffffffff);
1546 PUSH_DATA (push, 0xffffffff);
1547 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1548 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1549 } else
1550 if (info->src.format != info->dst.format) {
1551 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1552 info->src.format == PIPE_FORMAT_R16_UNORM ||
1553 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1554 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1555 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1556 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1557 PUSH_DATA (push, mask);
1558 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1559 }
1560 }
1561
1562 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1563 /* ms_x is always >= ms_y */
1564 du_dx <<= src->ms_x - dst->ms_x;
1565 dv_dy <<= src->ms_y - dst->ms_y;
1566 } else {
1567 du_dx >>= dst->ms_x - src->ms_x;
1568 dv_dy >>= dst->ms_y - src->ms_y;
1569 }
1570
1571 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1572 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1573
1574 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1575 /* center src coorinates for proper MS resolve filtering */
1576 srcx += (int64_t)1 << (src->ms_x + 31);
1577 srcy += (int64_t)1 << (src->ms_y + 31);
1578 }
1579
1580 dstx = info->dst.box.x << dst->ms_x;
1581 dsty = info->dst.box.y << dst->ms_y;
1582
1583 dstw = info->dst.box.width << dst->ms_x;
1584 dsth = info->dst.box.height << dst->ms_y;
1585
1586 if (dstx < 0) {
1587 dstw += dstx;
1588 srcx -= du_dx * dstx;
1589 dstx = 0;
1590 }
1591 if (dsty < 0) {
1592 dsth += dsty;
1593 srcy -= dv_dy * dsty;
1594 dsty = 0;
1595 }
1596
1597 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1598 PUSH_DATA (push, mode);
1599 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1600 PUSH_DATA (push, dstx);
1601 PUSH_DATA (push, dsty);
1602 PUSH_DATA (push, dstw);
1603 PUSH_DATA (push, dsth);
1604 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1605 PUSH_DATA (push, du_dx);
1606 PUSH_DATA (push, du_dx >> 32);
1607 PUSH_DATA (push, dv_dy);
1608 PUSH_DATA (push, dv_dy >> 32);
1609
1610 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1611 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1612 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1613 if (PUSH_VAL(nv50->base.pushbuf))
1614 return;
1615
1616 for (i = 0; i < info->dst.box.depth; ++i) {
1617 if (i > 0) {
1618 /* no scaling in z-direction possible for eng2d blits */
1619 if (dst->layout_3d) {
1620 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1621 PUSH_DATA (push, info->dst.box.z + i);
1622 } else {
1623 const unsigned z = info->dst.box.z + i;
1624 const uint64_t address = dst->base.address +
1625 dst->level[info->dst.level].offset +
1626 z * dst->layer_stride;
1627 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1628 PUSH_DATAh(push, address);
1629 PUSH_DATA (push, address);
1630 }
1631 if (src->layout_3d) {
1632 /* not possible because of depth tiling */
1633 assert(0);
1634 } else {
1635 const unsigned z = info->src.box.z + i;
1636 const uint64_t address = src->base.address +
1637 src->level[info->src.level].offset +
1638 z * src->layer_stride;
1639 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1640 PUSH_DATAh(push, address);
1641 PUSH_DATA (push, address);
1642 }
1643 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1644 PUSH_DATA (push, srcy >> 32);
1645 } else {
1646 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1647 PUSH_DATA (push, srcx);
1648 PUSH_DATA (push, srcx >> 32);
1649 PUSH_DATA (push, srcy);
1650 PUSH_DATA (push, srcy >> 32);
1651 }
1652 }
1653 nv50_bufctx_fence(nv50, nv50->bufctx, false);
1654
1655 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1656
1657 if (info->scissor_enable) {
1658 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1659 PUSH_DATA (push, 0);
1660 }
1661 if (mask != 0xffffffff) {
1662 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1663 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1664 }
1665 if (nv50->cond_query && info->render_condition_enable) {
1666 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1667 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1668 }
1669 }
1670
1671 static void
nv50_blit(struct pipe_context * pipe,const struct pipe_blit_info * info)1672 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1673 {
1674 struct nv50_context *nv50 = nv50_context(pipe);
1675 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1676 bool eng3d = false;
1677
1678 if (info->src.box.width == 0 || info->src.box.height == 0 ||
1679 info->dst.box.width == 0 || info->dst.box.height == 0) {
1680 util_debug_message(&nv50->base.debug, ERROR,
1681 "Blit with zero-size src or dst box");
1682 return;
1683 }
1684
1685 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1686 if (!(info->mask & PIPE_MASK_ZS))
1687 return;
1688 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1689 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1690 eng3d = true;
1691 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1692 eng3d = true;
1693 } else {
1694 if (!(info->mask & PIPE_MASK_RGBA))
1695 return;
1696 if (info->mask != PIPE_MASK_RGBA)
1697 eng3d = true;
1698 }
1699
1700 if (nv50_miptree(info->src.resource)->layout_3d) {
1701 eng3d = true;
1702 } else
1703 if (info->src.box.depth != info->dst.box.depth) {
1704 eng3d = true;
1705 debug_printf("blit: cannot filter array or cube textures in z direction");
1706 }
1707
1708 if (!eng3d && info->dst.format != info->src.format) {
1709 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1710 !nv50_2d_src_format_faithful(info->src.format)) {
1711 eng3d = true;
1712 } else
1713 if (!nv50_2d_src_format_faithful(info->src.format)) {
1714 if (!util_format_is_luminance(info->src.format)) {
1715 if (util_format_is_intensity(info->src.format))
1716 eng3d = true;
1717 else
1718 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1719 eng3d = true;
1720 else
1721 eng3d = !nv50_2d_format_supported(info->src.format);
1722 }
1723 } else
1724 if (util_format_is_luminance_alpha(info->src.format))
1725 eng3d = true;
1726 }
1727
1728 if (info->src.resource->nr_samples == 8 &&
1729 info->dst.resource->nr_samples <= 1)
1730 eng3d = true;
1731
1732 if (info->num_window_rectangles > 0 || info->window_rectangle_include)
1733 eng3d = true;
1734
1735 /* FIXME: can't make this work with eng2d anymore */
1736 if ((info->src.resource->nr_samples | 1) !=
1737 (info->dst.resource->nr_samples | 1))
1738 eng3d = true;
1739
1740 /* FIXME: find correct src coordinate adjustments */
1741 if ((info->src.box.width != info->dst.box.width &&
1742 info->src.box.width != -info->dst.box.width) ||
1743 (info->src.box.height != info->dst.box.height &&
1744 info->src.box.height != -info->dst.box.height))
1745 eng3d = true;
1746
1747 simple_mtx_lock(&nv50->screen->state_lock);
1748 if (nv50->screen->num_occlusion_queries_active) {
1749 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1750 PUSH_DATA (push, 0);
1751 }
1752
1753 if (!eng3d)
1754 nv50_blit_eng2d(nv50, info);
1755 else
1756 nv50_blit_3d(nv50, info);
1757
1758 if (nv50->screen->num_occlusion_queries_active) {
1759 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1760 PUSH_DATA (push, 1);
1761 }
1762 PUSH_KICK(push);
1763 simple_mtx_unlock(&nv50->screen->state_lock);
1764 }
1765
1766 static void
nv50_flush_resource(struct pipe_context * ctx,struct pipe_resource * resource)1767 nv50_flush_resource(struct pipe_context *ctx,
1768 struct pipe_resource *resource)
1769 {
1770 }
1771
1772 bool
nv50_blitter_create(struct nv50_screen * screen)1773 nv50_blitter_create(struct nv50_screen *screen)
1774 {
1775 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1776 if (!screen->blitter) {
1777 NOUVEAU_ERR("failed to allocate blitter struct\n");
1778 return false;
1779 }
1780
1781 (void) mtx_init(&screen->blitter->mutex, mtx_plain);
1782
1783 nv50_blitter_make_vp(screen->blitter);
1784 nv50_blitter_make_sampler(screen->blitter);
1785
1786 return true;
1787 }
1788
1789 void
nv50_blitter_destroy(struct nv50_screen * screen)1790 nv50_blitter_destroy(struct nv50_screen *screen)
1791 {
1792 struct nv50_blitter *blitter = screen->blitter;
1793 unsigned i, m;
1794
1795 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1796 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1797 struct nv50_program *prog = blitter->fp[i][m];
1798 if (prog) {
1799 nv50_program_destroy(NULL, prog);
1800 ralloc_free((void *)prog->nir);
1801 FREE(prog);
1802 }
1803 }
1804 }
1805
1806 mtx_destroy(&blitter->mutex);
1807 FREE(blitter);
1808 }
1809
1810 bool
nv50_blitctx_create(struct nv50_context * nv50)1811 nv50_blitctx_create(struct nv50_context *nv50)
1812 {
1813 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1814 if (!nv50->blit) {
1815 NOUVEAU_ERR("failed to allocate blit context\n");
1816 return false;
1817 }
1818
1819 nv50->blit->nv50 = nv50;
1820
1821 nv50->blit->rast.pipe.half_pixel_center = 1;
1822
1823 return true;
1824 }
1825
1826 void
nv50_init_surface_functions(struct nv50_context * nv50)1827 nv50_init_surface_functions(struct nv50_context *nv50)
1828 {
1829 struct pipe_context *pipe = &nv50->base.pipe;
1830
1831 pipe->resource_copy_region = nv50_resource_copy_region;
1832 pipe->blit = nv50_blit;
1833 pipe->flush_resource = nv50_flush_resource;
1834 pipe->clear_texture = u_default_clear_texture;
1835 pipe->clear_render_target = nv50_clear_render_target;
1836 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1837 pipe->clear_buffer = nv50_clear_buffer;
1838 }
1839