xref: /aosp_15_r20/external/coreboot/Documentation/mainboard/ocp/deltalake.md (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1# OCP Delta Lake
2
3This page describes coreboot support status for the [OCP] (Open Compute Project)
4Delta Lake server platform.
5
6## Introduction
7
8OCP Delta Lake server platform is a component of multi-host server system
9Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design
10spec] were [OCP] accepted.
11
12On the other hand, Wiwynn's Yosemite-V3 system and Delta Lake server product
13along with its OSF implementation, which is based on FSP/coreboot/LinuxBoot
14stack, was [OCP] accepted; For details, check:
15- [The OCP blog]
16- [The Wiwynn Press Release]
17- [The Wiwynn's Yosemite-V3 product in OCP market place]
18Wiwynn and 9Elements formed a partnership to offer the Wiwynn's Yosemite-V3
19product and OSF for it.
20
21Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
22Intel Cooper Lake Scalable Processor was launched in Q2 2020.
23
24Yosemite-V3 has multiple configurations. Depending on configurations, it may
25host up to 4 Delta Lake servers (blades) in one sled.
26
27The Yosemite-V3 system is in mass production. Meta, Intel and partners
28jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
29solution. The OSF solution reached production quality for some use cases
30in July, 2021.
31
32## How to build
33
34OSF code base is publicly available at
35https://github.com/opencomputeproject/OpenSystemFirmware
36
37Run following commands to build Delta Lake OSF image from scratch:
38    git clone https://github.com/opencomputeproject/OpenSystemFirmware.git
39    cd OpenSystemFirmware/Wiwynn/deltalake && ./download_and_build.sh
40
41The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
42Linux kernel and u-root code from their upstream repo, and sync down needed
43binary blobs. [osf-builder] also provides the top level build system.
44
45Besides coreboot, the Delta Lake OSF solution includes following components:
46- FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
47  is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
48- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
49- ME ignition binary: downloaded from
50	https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
51- ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
52- Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
53  U-root as initramfs, is used in the joint development. It is built
54  following [All about u-root].
55
56The Delta Lake OSF solution is updated periodically to newer versions of
57upstream coreboot code base and other components.
58
59## How to verify Delta Lake OSF image
60
61To do in-band FW image update, use [flashrom]:
62    flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
63			-i bios --noverify-all -w <path to coreboot image>
64
65From OpenBMC, to update FW image:
66    fw-util slotx --update bios <path to coreboot image>
67
68To power off/on the host:
69    power-util slotx off
70    power-util slotx on
71
72To connect to console through SOL (Serial Over Lan):
73    sol-util slotx
74
75## How to work on coreboot for Delta Lake
76After the OSF image for Delta Lake is built and verified, under
77OpenSystemFirmware/Wiwynn/deltalake directory:
78    cd src/osf-builder/projects/craterlake/coreboot
79
80Run "git remote -v" to confirm the origin is from coreboot upstream repo.
81
82Run "git branch -v" to know the confirmed working coreboot commit ID for the
83Delta Lake OSF solution.
84
85Fetch down the tip of coreboot upstream repo, run "make" to build a new OSF
86image for Delta Lake, verify that it works.
87
88Now you are in a familiar coreboot environment, happy coding!
89
90## Firmware configurations
91[ChromeOS VPD] is used to store most of the firmware configurations.
92RO_VPD region holds default values, while RW_VPD region holds customized
93values.
94
95VPD variables supported are:
96- firmware_version: This variable holds overall firmware version. coreboot
97  uses that value to populate smbios type 1 version field.
98- bmc_bootorder_override: When it's set to 1 IPMI OEM command can override boot
99  order. The boot order override is done in the u-root LinuxBoot payload.
100- systemboot_log_level: u-root package systemboot log levels, would be mapped to
101  quiet/verbose in systemboot as that is all we have for now. 5 to 8 would be
102  mapped to verbose, 0 to 4 and 9 would be mapped to quiet.
103- VPDs affecting coreboot are listed/documented in [src/mainboard/ocp/deltalake/vpd.h].
104
105## Features
106The solution is developed using LinuxBoot payload with Linux kernel 5.2.9,
107and [u-root] as initramfs.
108- SMBIOS:
109    - Type 0 -- BIOS Information
110    - Type 1 -- System Information
111    - Type 2 -- Baseboard Information
112    - Type 3 -- System Enclosure or Chassis
113    - Type 4 -- Processor Information
114    - Type 7 -- Cache Information
115    - Type 8 -- Port Connector Information
116    - Type 9 -- PCI Slot Information
117    - Type 11 -- OEM String
118    - Type 16 -- Physical Memory Array
119    - Type 17 -- Memory Device
120    - Type 19 -- Memory Array Mapped Address
121    - Type 32 -- System Boot Information
122    - Type 38 -- IPMI Device Information
123    - Type 41 -- Onboard Devices Extended Information
124    - Type 127 -- End-of-Table
125- BMC integration:
126    - BMC readiness check
127    - IPMI commands
128    - watchdog timer
129    - POST complete pin acknowledgement
130    - Check BMC version: ipmidump -device
131- SEL record generation
132- Converged Bootguard and TXT (CBnT)
133    - TPM
134    - Bootguard profile 0T
135    - TXT
136    - SRTM
137    - DRTM (verified through tboot)
138		- unsigned KM/BPM generation
139		- KM/BPM signing
140		- memory secret clearance upon ungraceful shutdown
141- Early serial output
142- port 80h direct to GPIO
143- ACPI tables: APIC/DMAR/DSDT/EINJ/FACP/FACS/HEST/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
144- Skipping memory training upon subsequent reboots by using MRC cache
145- BMC crash dump
146- Error injection through ITP
147- Versions
148    - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION
149    - Check Microcode version: cat /proc/cpuinfo | grep microcode
150- Devices:
151    - Boot drive
152    - All 5 data drives
153    - NIC card
154- Power button
155- localboot
156- netboot from IPv6
157- RAS (SMI handlers not upstreamed)
158    - EINJ/HEST
159    - error injection through ITP
160    - memory error handling
161    - PCIe error handling
162    - PCIe live error recovery (LER)
163
164## Stress/performance tests passed
165- OS warm reboot (1000 cycles)
166- DC reboot (1000 cycles)
167- AC reboot (1000 cycle)
168- Mprime test (6 hours)
169- StressAppTest (6 hours)
170- Ptugen (6 hours)
171
172## Performance on par with traditional firmware
173- coremark
174- FIO
175- Iperf(IPv6)
176- Linpack
177- Intel MLC (memory latency and bandwidth)
178- SpecCPU
179- stream
180
181## Other tests passed
182- Power
183- Thermal
184- coreboot address sanitizer (both romstage and ramstage)
185- Intel selftest tool (all errors analyzed; applicable errors clean)
186
187## Known issues
188- HECI access at OS run time:
189    - spsInfoLinux64 command fail to return ME version
190    - ptugen command fail to get memory power
191- CLTT (Closed Loop Thermal Throttling, eg. thermal protection for DIMMs)
192- ProcHot (thermal protection for processors)
193
194## Feature gaps
195- flashrom command not able to update ME region
196- ACPI BERT table
197- PCIe hotplug through VPP (Virtual Pin Ports)
198- RO_VPD region as well as other RO regions are not write protected
199- Not able to selectively enable/disable core
200
201## Technology
202
203```{eval-rst}
204+------------------------+---------------------------------------------+
205| Processor (1 socket)   | Intel Cooper Lake Scalable Processor        |
206+------------------------+---------------------------------------------+
207| BMC                    | Aspeed AST 2500                             |
208+------------------------+---------------------------------------------+
209| PCH                    | Intel Lewisburg C620 Series                 |
210+------------------------+---------------------------------------------+
211```
212
213[OCP]: https://www.opencompute.org
214[Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specification-1v05-pdf
215[Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf
216[The OCP blog]: https://www.opencompute.org/blog/open-system-firmware-for-ocp-server-deltalake-is-published
217[The Wiwynn Press Release]: https://www.prnewswire.com/news-releases/wiwynn-successfully-implemented-open-system-firmware-on-its-ocp-yosemite-v3-server-301417374.html?tc=eml_cleartime
218[The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server
219[osf-builder]: https://github.com/facebookincubator/osf-builder
220[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
221[flashrom]: https://flashrom.org/Flashrom
222[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
223[u-root]: https://u-root.org/
224[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
225[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD/src/mainboard/ocp/deltalake/vpd.h
226