1 /*
2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/cadence/cdns_sdmmc.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <drivers/synopsys/dw_mmc.h>
17 #include <drivers/ti/uart/uart_16550.h>
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20
21 #include "agilex5_clock_manager.h"
22 #include "agilex5_memory_controller.h"
23 #include "agilex5_mmc.h"
24 #include "agilex5_pinmux.h"
25 #include "agilex5_system_manager.h"
26 #include "ccu/ncore_ccu.h"
27 #include "combophy/combophy.h"
28 #include "nand/nand.h"
29 #include "qspi/cadence_qspi.h"
30 #include "sdmmc/sdmmc.h"
31 #include "socfpga_emac.h"
32 #include "socfpga_f2sdram_manager.h"
33 #include "socfpga_handoff.h"
34 #include "socfpga_mailbox.h"
35 #include "socfpga_private.h"
36 #include "socfpga_reset_manager.h"
37 #include "socfpga_ros.h"
38 #include "wdt/watchdog.h"
39
40
41 /* Declare mmc_info */
42 static struct mmc_device_info mmc_info;
43
44 /* Declare cadence idmac descriptor */
45 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32);
46
47 const mmap_region_t agilex_plat_mmap[] = {
48 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
49 MT_MEMORY | MT_RW | MT_NS),
50 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE,
51 MT_DEVICE | MT_RW | MT_NS),
52 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE,
53 MT_DEVICE | MT_RW | MT_SECURE),
54 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
55 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
56 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE,
57 MT_DEVICE | MT_RW | MT_SECURE),
58 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
59 MT_DEVICE | MT_RW | MT_NS),
60 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE,
61 MT_DEVICE | MT_RW | MT_SECURE),
62 {0},
63 };
64
65 boot_source_type boot_source = BOOT_SOURCE;
66
bl2_el3_early_platform_setup(u_register_t x0,u_register_t x1,u_register_t x2,u_register_t x4)67 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
68 u_register_t x2, u_register_t x4)
69 {
70 static console_t console;
71
72 handoff reverse_handoff_ptr = { 0 };
73
74 generic_delay_timer_init();
75 config_clkmgr_handoff(&reverse_handoff_ptr);
76 mailbox_init();
77 enable_nonsecure_access();
78
79 deassert_peripheral_reset();
80 if (combo_phy_init(&reverse_handoff_ptr) != 0) {
81 ERROR("Combo Phy initialization failed\n");
82 }
83
84 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
85 PLAT_BAUDRATE, &console);
86
87 /* Store magic number */
88 // TODO: Temp workaround to ungate testing
89 // mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ);
90
91 if (!intel_mailbox_is_fpga_not_ready()) {
92 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK |
93 FPGA2SOC_MASK | F2SDRAM0_MASK);
94 }
95 }
96
bl2_el3_plat_arch_setup(void)97 void bl2_el3_plat_arch_setup(void)
98 {
99 handoff reverse_handoff_ptr;
100 unsigned long offset = 0;
101
102 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk());
103
104 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE;
105 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
106
107 /* Request ownership and direct access to QSPI */
108 mailbox_hps_qspi_enable();
109
110 switch (boot_source) {
111 case BOOT_SOURCE_SDMMC:
112 NOTICE("SDMMC boot\n");
113 sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info);
114 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
115 break;
116
117 case BOOT_SOURCE_QSPI:
118 NOTICE("QSPI boot\n");
119 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
120 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
121 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
122 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) {
123 offset = PLAT_QSPI_DATA_BASE;
124 }
125 socfpga_io_setup(boot_source, offset);
126 break;
127
128 case BOOT_SOURCE_NAND:
129 NOTICE("NAND boot\n");
130 nand_init(&reverse_handoff_ptr);
131 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE);
132 break;
133
134 default:
135 ERROR("Unsupported boot source\n");
136 panic();
137 break;
138 }
139 }
140
get_spsr_for_bl33_entry(void)141 uint32_t get_spsr_for_bl33_entry(void)
142 {
143 unsigned long el_status;
144 unsigned int mode;
145 uint32_t spsr;
146
147 /* Figure out what mode we enter the non-secure world in */
148 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
149 el_status &= ID_AA64PFR0_ELX_MASK;
150
151 mode = (el_status) ? MODE_EL2 : MODE_EL1;
152
153 /*
154 * TODO: Consider the possibility of specifying the SPSR in
155 * the FIP ToC and allowing the platform to have a say as
156 * well.
157 */
158 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
159 return spsr;
160 }
161
bl2_plat_handle_post_image_load(unsigned int image_id)162 int bl2_plat_handle_post_image_load(unsigned int image_id)
163 {
164 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
165
166 assert(bl_mem_params);
167
168 switch (image_id) {
169 case BL33_IMAGE_ID:
170 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
171 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
172 break;
173 default:
174 break;
175 }
176
177 return 0;
178 }
179
180 /*******************************************************************************
181 * Perform any BL3-1 platform setup code
182 ******************************************************************************/
bl2_platform_setup(void)183 void bl2_platform_setup(void)
184 {
185 }
186