1 /* 2 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <common/debug.h> 10 #include <drivers/delay_timer.h> 11 #include <lib/mmio.h> 12 13 #include "agilex5_power_manager.h" 14 #include "socfpga_reset_manager.h" 15 wait_verify_fsm(uint16_t timeout,uint32_t peripheral_handoff)16int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff) 17 { 18 uint32_t data = 0; 19 uint32_t count = 0; 20 uint32_t pgstat = 0; 21 22 /* Wait FSM ready */ 23 do { 24 data = mmio_read_32(AGX5_PWRMGR(PSS_PGSTAT)); 25 count++; 26 if (count >= 1000) { 27 return -ETIMEDOUT; 28 } 29 30 } while (AGX5_PWRMGR_PSS_STAT_BUSY(data) == AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY); 31 32 /* Verify PSS SRAM power gated */ 33 pgstat = mmio_read_32(AGX5_PWRMGR(PSS_PGSTAT)); 34 if (pgstat != (AGX5_PWRMGR_PSS_PGEN_OUT(peripheral_handoff))) { 35 return AGX5_PWRMGR_HANDOFF_PERIPHERAL; 36 } 37 38 return 0; 39 } 40 pss_sram_power_off(handoff * hoff_ptr)41int pss_sram_power_off(handoff *hoff_ptr) 42 { 43 int ret = 0; 44 uint32_t peripheral_handoff = 0; 45 46 /* Get PSS SRAM handoff data */ 47 peripheral_handoff = hoff_ptr->peripheral_pwr_gate_array; 48 49 /* Enable firewall for PSS SRAM */ 50 mmio_write_32(AGX5_PWRMGR(PSS_FWENCTL), 51 AGX5_PWRMGR_PSS_FWEN(peripheral_handoff)); 52 53 /* Wait */ 54 udelay(1); 55 56 /* Power gating PSS SRAM */ 57 mmio_write_32(AGX5_PWRMGR(PSS_PGENCTL), 58 AGX5_PWRMGR_PSS_PGEN(peripheral_handoff)); 59 60 ret = wait_verify_fsm(1000, peripheral_handoff); 61 62 return ret; 63 } 64 config_pwrmgr_handoff(handoff * hoff_ptr)65void config_pwrmgr_handoff(handoff *hoff_ptr) 66 { 67 int ret = 0; 68 69 switch (hoff_ptr->header_magic) { 70 case HANDOFF_MAGIC_PERIPHERAL: 71 ret = pss_sram_power_off(hoff_ptr); 72 break; 73 default: 74 break; 75 } 76 77 if (ret != 0) { 78 ERROR("Config PwrMgr handoff failed. error %d\n", ret); 79 assert(false); 80 } 81 } 82