1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef INTEL_COMMON_PMUTIL_H 4 #define INTEL_COMMON_PMUTIL_H 5 6 #include <cpu/x86/smm.h> 7 8 #define GPE0_HAS_64_EVENTS \ 9 (!(CONFIG(SOUTHBRIDGE_INTEL_I82801DX) || CONFIG(SOUTHBRIDGE_INTEL_I82801GX))) 10 11 #define D31F0_PMBASE 0x40 12 #define D31F0_GEN_PMCON_1 0xa0 13 #define SMI_LOCK (1 << 4) 14 #define D31F0_GEN_PMCON_2 0xa2 15 #define D31F0_GEN_PMCON_3 0xa4 16 #define RTC_BATTERY_DEAD (1 << 2) 17 #define RTC_POWER_FAILED (1 << 1) 18 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 19 #define D31F0_GEN_PMCON_LOCK 0xa6 20 #define ACPI_BASE_LOCK (1 << 1) 21 #define SLP_STR_POL_LOCK (1 << 2) 22 #define D31F0_ETR3 0xac 23 #define ETR3_CWORWRE (1 << 18) 24 #define ETR3_CF9GR (1 << 20) 25 #define ETR3_CF9LOCK (1 << 31) 26 #define D31F0_GPIO_ROUT 0xb8 27 #define GPI_DISABLE 0x00 28 #define GPI_IS_SMI 0x01 29 #define GPI_IS_SCI 0x02 30 #define GPI_IS_NMI 0x03 31 32 #define MAINBOARD_POWER_OFF 0 33 #define MAINBOARD_POWER_ON 1 34 #define MAINBOARD_POWER_KEEP 2 35 36 #define PM1_STS 0x00 37 #define WAK_STS (1 << 15) 38 #define PCIEXPWAK_STS (1 << 14) 39 #define PRBTNOR_STS (1 << 11) 40 #define RTC_STS (1 << 10) 41 #define PWRBTN_STS (1 << 8) 42 #define GBL_STS (1 << 5) 43 #define BM_STS (1 << 4) 44 #define TMROF_STS (1 << 0) 45 #define PM1_EN 0x02 46 #define PCIEXPWAK_DIS (1 << 14) 47 #define RTC_EN (1 << 10) 48 #define PWRBTN_EN (1 << 8) 49 #define GBL_EN (1 << 5) 50 #define TMROF_EN (1 << 0) 51 #define PM1_CNT 0x04 52 #define GBL_RLS (1 << 2) 53 #define BM_RLD (1 << 1) 54 #define SCI_EN (1 << 0) 55 #define PM1_TMR 0x08 56 #define PROC_CNT 0x10 57 #define LV2 0x14 58 #define LV3 0x15 59 #define LV4 0x16 60 61 #if GPE0_HAS_64_EVENTS 62 #define GPE0_STS 0x20 63 #define GPE0_EN 0x28 // GPE0_STS + 8 64 #define PM2_CNT 0x50 // mobile only 65 #else 66 #define PM2_CNT 0x20 // mobile only 67 #define GPE0_STS 0x28 68 #define GPE0_EN 0x2c // GPE0_STS + 4 69 #endif 70 71 /* def GPE0_STS */ 72 #define USB4_STS (1 << 14) /* i82801gx only */ 73 #define PME_B0_STS (1 << 13) 74 #define PME_STS (1 << 11) 75 #define BATLOW_STS (1 << 10) 76 #define PCI_EXP_STS (1 << 9) 77 #define RI_STS (1 << 8) 78 #define SMB_WAK_STS (1 << 7) 79 #define TCOSCI_STS (1 << 6) 80 #define SWGPE_STS (1 << 2) 81 #define HOT_PLUG_STS (1 << 1) 82 83 /* def GPE0_EN */ 84 #define PME_B0_EN (1 << 13) 85 #define PME_EN (1 << 11) 86 #define TCOSCI_EN (1 << 6) 87 #define SMI_EN 0x30 88 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic 89 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic 90 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS 91 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) 92 #define MCSMI_EN (1 << 11) // Trap microcontroller range access 93 #define BIOS_RLS (1 << 7) // asserts SCI on bit set 94 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set 95 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# 96 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# 97 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic 98 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit 99 #define EOS (1 << 1) // End of SMI (deassert SMI#) 100 #define GBL_SMI_EN (1 << 0) // SMI# generation at all? 101 #define SMI_STS 0x34 102 #define ALT_GP_SMI_EN 0x38 103 #define ALT_GP_SMI_STS 0x3a 104 #define GPE_CNTL 0x42 105 #define DEVACT_STS 0x44 106 107 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) 108 #define TCO1_STS 0x64 109 #define DMISCI_STS (1 << 9) 110 #define BOOT_STS (1 << 18) 111 #define TCO2_STS 0x66 112 #define TCO1_CNT 0x68 113 #define TCO_LOCK (1 << 12) 114 #define TCO2_CNT 0x6a 115 #endif 116 117 u16 get_pmbase(void); 118 119 u16 reset_pm1_status(void); 120 void dump_pm1_status(u16 pm1_sts); 121 void dump_tco_status(u32 tco_sts); 122 u32 reset_tco_status(void); 123 void dump_gpe0_status(u64 gpe0_sts); 124 u64 reset_gpe0_status(void); 125 void dump_smi_status(u32 smi_sts); 126 u32 reset_smi_status(void); 127 void gpe0_mask(u32 clr, u32 set); 128 void alt_gpi_mask(u16 clr, u16 set); 129 void dump_alt_gp_smi_status(u16 alt_gp_smi_sts); 130 u16 reset_alt_gp_smi_status(void); 131 void dump_all_status(void); 132 133 void southbridge_smm_xhci_sleep(u8 slp_type); 134 void gpi_route_interrupt(u8 gpi, u8 mode); 135 void southbridge_gate_memory_reset(void); 136 void southbridge_finalize_all(void); 137 void southbridge_smi_monitor(void); 138 void pch_log_state(void); 139 140 #endif /*INTEL_COMMON_PMUTIL_H */ 141