1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <console/console.h> 4 #include <device/mmio.h> 5 #include <device/pci_ops.h> 6 #include <security/intel/txt/txt_register.h> 7 #include <soc/pci_devs.h> 8 #include <stdint.h> 9 10 #include "ptt.h" 11 12 #define PCI_ME_HFSTS4 0x64 13 #define PTT_ENABLE (1 << 19) 14 15 /* Dump Intel ME register */ read_register(int reg_addr)16static uint32_t read_register(int reg_addr) 17 { 18 if (!PCH_DEV_CSE) 19 return 0xFFFFFFFF; 20 21 return pci_read_config32(PCH_DEV_CSE, reg_addr); 22 } 23 24 /* 25 * ptt_active() 26 * 27 * Check if PTT Flag is set - so that PTT is active. 28 * 29 * Return true if active, false otherwise. 30 */ ptt_active(void)31bool ptt_active(void) 32 { 33 uint32_t sts_ftif; 34 uint32_t fwsts4 = read_register(PCI_ME_HFSTS4); 35 36 if (fwsts4 == 0xFFFFFFFF) 37 return false; 38 39 if ((fwsts4 & PTT_ENABLE) == 0) { 40 printk(BIOS_DEBUG, "Intel ME Establishment bit not valid.\n"); 41 sts_ftif = read32p(TXT_STS_FTIF); 42 43 if (sts_ftif != 0 && sts_ftif != UINT32_MAX) { 44 if ((sts_ftif & TXT_PTT_PRESENT) == TXT_PTT_PRESENT) { 45 printk(BIOS_DEBUG, "TXT_STS_FTIF: PTT present and active\n"); 46 return true; 47 } 48 } 49 return false; 50 } 51 52 return true; 53 } 54