1 /*
2 * Copyright 2010 Jerome Glisse <[email protected]>
3 * Authors:
4 * Jerome Glisse
5 * SPDX-License-Identifier: MIT
6 */
7
8 #ifndef R600_PIPE_H
9 #define R600_PIPE_H
10
11 #include "r600_pipe_common.h"
12 #include "r600_cs.h"
13 #include "r600_public.h"
14 #include "pipe/p_defines.h"
15
16 #include "util/u_suballoc.h"
17 #include "util/list.h"
18 #include "util/u_transfer.h"
19 #include "util/u_memory.h"
20
21 #include "tgsi/tgsi_scan.h"
22
23 #define R600_NUM_ATOMS 56
24
25 #define R600_MAX_IMAGES 8
26 /*
27 * ranges reserved for images on evergreen
28 * first set for the immediate buffers,
29 * second for the actual resources for RESQ.
30 */
31 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
32 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
33
34 /* read caches */
35 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
36 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
37 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
38 /* read-write caches */
39 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
40 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
41 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
42 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
43 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
44 /* engine synchronization */
45 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
46 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
47 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
48 #define R600_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
49
50 /* the number of CS dwords for flushing and drawing */
51 #define R600_MAX_FLUSH_CS_DWORDS 18
52 #define R600_MAX_DRAW_CS_DWORDS 58
53 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
54
55 #define EG_MAX_ATOMIC_BUFFERS 8
56
57 #define R600_MAX_USER_CONST_BUFFERS 15
58 #define R600_MAX_DRIVER_CONST_BUFFERS 3
59 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
60
61 /* start driver buffers after user buffers */
62 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
63 #define R600_UCP_SIZE (4*4*8)
64 #define R600_CS_BLOCK_GRID_SIZE (8 * 4)
65 #define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4)
66 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
67
68 /*
69 * We only access this buffer through vtx clauses hence it's fine to exist
70 * at index beyond 15.
71 */
72 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
73 /*
74 * Note GS doesn't use a constant buffer binding, just a resource index,
75 * so it's fine to have it exist at index beyond 15. I.e. it's not actually
76 * a const buffer, just a buffer resource.
77 */
78 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
79 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
80 * of 16 const buffers.
81 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
82 *
83 * In order to support d3d 11 mandated minimum of 15 user const buffers
84 * we'd have to squash all use cases into one driver buffer.
85 */
86 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
87
88 /* HW stages */
89 #define R600_HW_STAGE_PS 0
90 #define R600_HW_STAGE_VS 1
91 #define R600_HW_STAGE_GS 2
92 #define R600_HW_STAGE_ES 3
93 #define EG_HW_STAGE_LS 4
94 #define EG_HW_STAGE_HS 5
95
96 #define R600_NUM_HW_STAGES 4
97 #define EG_NUM_HW_STAGES 6
98
99 struct r600_context;
100 struct r600_bytecode;
101 union r600_shader_key;
102
103 /* This is an atom containing GPU commands that never change.
104 * This is supposed to be copied directly into the CS. */
105 struct r600_command_buffer {
106 uint32_t *buf;
107 unsigned num_dw;
108 unsigned max_num_dw;
109 unsigned pkt_flags;
110 };
111
112 struct r600_db_state {
113 struct r600_atom atom;
114 struct r600_surface *rsurf;
115 };
116
117 struct r600_db_misc_state {
118 struct r600_atom atom;
119 bool occlusion_queries_disabled;
120 bool flush_depthstencil_through_cb;
121 bool flush_depth_inplace;
122 bool flush_stencil_inplace;
123 bool copy_depth, copy_stencil;
124 unsigned copy_sample;
125 unsigned log_samples;
126 unsigned db_shader_control;
127 bool htile_clear;
128 uint8_t ps_conservative_z;
129 };
130
131 struct r600_cb_misc_state {
132 struct r600_atom atom;
133 unsigned cb_color_control; /* this comes from blend state */
134 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
135 unsigned nr_cbufs;
136 unsigned bound_cbufs_target_mask;
137 unsigned nr_ps_color_outputs;
138 unsigned ps_color_export_mask;
139 unsigned image_rat_enabled_mask;
140 unsigned buffer_rat_enabled_mask;
141 bool multiwrite;
142 bool dual_src_blend;
143 };
144
145 struct r600_clip_misc_state {
146 struct r600_atom atom;
147 unsigned pa_cl_clip_cntl; /* from rasterizer */
148 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
149 unsigned clip_plane_enable; /* from rasterizer */
150 unsigned cc_dist_mask; /* from vertex shader */
151 unsigned clip_dist_write; /* from vertex shader */
152 unsigned cull_dist_write; /* from vertex shader */
153 bool clip_disable; /* from vertex shader */
154 bool vs_out_viewport; /* from vertex shader */
155 };
156
157 struct r600_alphatest_state {
158 struct r600_atom atom;
159 unsigned sx_alpha_test_control; /* this comes from dsa state */
160 unsigned sx_alpha_ref; /* this comes from dsa state */
161 bool bypass;
162 bool cb0_export_16bpc; /* from set_framebuffer_state */
163 };
164
165 struct r600_vgt_state {
166 struct r600_atom atom;
167 uint32_t vgt_multi_prim_ib_reset_en;
168 uint32_t vgt_multi_prim_ib_reset_indx;
169 uint32_t vgt_indx_offset;
170 bool last_draw_was_indirect;
171 };
172
173 struct r600_blend_color {
174 struct r600_atom atom;
175 struct pipe_blend_color state;
176 };
177
178 struct r600_clip_state {
179 struct r600_atom atom;
180 struct pipe_clip_state state;
181 };
182
183 struct r600_cs_shader_state {
184 struct r600_atom atom;
185 unsigned kernel_index;
186 unsigned pc;
187 struct r600_pipe_compute *shader;
188 };
189
190 struct r600_framebuffer {
191 struct r600_atom atom;
192 struct pipe_framebuffer_state state;
193 unsigned compressed_cb_mask;
194 unsigned nr_samples;
195 bool export_16bpc;
196 bool cb0_is_integer;
197 bool is_msaa_resolve;
198 bool dual_src_blend;
199 bool do_update_surf_dirtiness;
200 };
201
202 struct r600_sample_mask {
203 struct r600_atom atom;
204 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
205 };
206
207 struct r600_config_state {
208 struct r600_atom atom;
209 unsigned sq_gpr_resource_mgmt_1;
210 unsigned sq_gpr_resource_mgmt_2;
211 unsigned sq_gpr_resource_mgmt_3;
212 bool dyn_gpr_enabled;
213 };
214
215 struct r600_stencil_ref
216 {
217 uint8_t ref_value[2];
218 uint8_t valuemask[2];
219 uint8_t writemask[2];
220 };
221
222 struct r600_stencil_ref_state {
223 struct r600_atom atom;
224 struct r600_stencil_ref state;
225 struct pipe_stencil_ref pipe_state;
226 };
227
228 struct r600_shader_stages_state {
229 struct r600_atom atom;
230 unsigned geom_enable;
231 };
232
233 struct r600_gs_rings_state {
234 struct r600_atom atom;
235 unsigned enable;
236 struct pipe_constant_buffer esgs_ring;
237 struct pipe_constant_buffer gsvs_ring;
238 };
239
240 /* This must start from 16. */
241 /* features */
242 #define DBG_NO_CP_DMA (1 << 30)
243
244 struct r600_screen {
245 struct r600_common_screen b;
246 bool has_msaa;
247 bool has_compressed_msaa_texturing;
248 bool has_atomics;
249
250 /*for compute global memory binding, we allocate stuff here, instead of
251 * buffers.
252 * XXX: Not sure if this is the best place for global_pool. Also,
253 * it's not thread safe, so it won't work with multiple contexts. */
254 struct compute_memory_pool *global_pool;
255 };
256
257 struct r600_pipe_sampler_view {
258 struct pipe_sampler_view base;
259 struct list_head list;
260 struct r600_resource *tex_resource;
261 uint32_t tex_resource_words[8];
262 bool skip_mip_address_reloc;
263 bool is_stencil_sampler;
264 };
265
266 struct r600_rasterizer_state {
267 struct r600_command_buffer buffer;
268 bool flatshade;
269 bool two_side;
270 unsigned sprite_coord_enable;
271 unsigned clip_plane_enable;
272 unsigned pa_sc_line_stipple;
273 unsigned pa_cl_clip_cntl;
274 unsigned pa_su_sc_mode_cntl;
275 float offset_units;
276 float offset_scale;
277 bool offset_enable;
278 bool offset_units_unscaled;
279 bool scissor_enable;
280 bool multisample_enable;
281 bool clip_halfz;
282 bool rasterizer_discard;
283 };
284
285 struct r600_poly_offset_state {
286 struct r600_atom atom;
287 enum pipe_format zs_format;
288 float offset_units;
289 float offset_scale;
290 bool offset_units_unscaled;
291 };
292
293 struct r600_blend_state {
294 struct r600_command_buffer buffer;
295 struct r600_command_buffer buffer_no_blend;
296 unsigned cb_target_mask;
297 unsigned cb_color_control;
298 unsigned cb_color_control_no_blend;
299 bool dual_src_blend;
300 bool alpha_to_one;
301 };
302
303 struct r600_dsa_state {
304 struct r600_command_buffer buffer;
305 unsigned alpha_ref;
306 uint8_t valuemask[2];
307 uint8_t writemask[2];
308 unsigned zwritemask;
309 unsigned sx_alpha_test_control;
310 };
311
312 struct r600_pipe_shader;
313
314 struct r600_pipe_shader_selector {
315 struct r600_pipe_shader *current;
316
317 struct tgsi_token *tokens;
318 struct nir_shader *nir;
319
320 size_t nir_blob_size;
321 void *nir_blob;
322
323 struct pipe_stream_output_info so;
324 struct tgsi_shader_info info;
325
326 unsigned num_shaders;
327
328 enum pipe_shader_type type;
329 enum pipe_shader_ir ir_type;
330
331 /* geometry shader properties */
332 enum mesa_prim gs_output_prim;
333 unsigned gs_max_out_vertices;
334 unsigned gs_num_invocations;
335
336 /* TCS/VS */
337 uint64_t lds_patch_outputs_written_mask;
338 uint64_t lds_outputs_written_mask;
339 };
340
341 struct r600_pipe_sampler_state {
342 uint32_t tex_sampler_words[3];
343 union pipe_color_union border_color;
344 bool border_color_use;
345 bool seamless_cube_map;
346 };
347
348 /* needed for blitter save */
349 #define NUM_TEX_UNITS 16
350
351 struct r600_seamless_cube_map {
352 struct r600_atom atom;
353 bool enabled;
354 };
355
356 struct r600_samplerview_state {
357 struct r600_atom atom;
358 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
359 uint32_t enabled_mask;
360 uint32_t dirty_mask;
361 uint32_t compressed_depthtex_mask; /* which textures are depth */
362 uint32_t compressed_colortex_mask;
363 bool dirty_buffer_constants;
364 };
365
366 struct r600_sampler_states {
367 struct r600_atom atom;
368 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
369 uint32_t enabled_mask;
370 uint32_t dirty_mask;
371 uint32_t has_bordercolor_mask; /* which states contain the border color */
372 };
373
374 struct r600_textures_info {
375 struct r600_samplerview_state views;
376 struct r600_sampler_states states;
377 bool is_array_sampler[NUM_TEX_UNITS];
378 };
379
380 struct r600_shader_driver_constants_info {
381 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
382 uint32_t *constants;
383 uint32_t alloc_size;
384 bool texture_const_dirty;
385 bool vs_ucp_dirty;
386 bool ps_sample_pos_dirty;
387 bool cs_block_grid_size_dirty;
388 bool tcs_default_levels_dirty;
389 };
390
391 struct r600_constbuf_state
392 {
393 struct r600_atom atom;
394 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
395 uint32_t enabled_mask;
396 uint32_t dirty_mask;
397 };
398
399 struct r600_vertexbuf_state
400 {
401 struct r600_atom atom;
402 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
403 uint32_t enabled_mask; /* non-NULL buffers */
404 uint32_t dirty_mask;
405 };
406
407 /* CSO (constant state object, in other words, immutable state). */
408 struct r600_cso_state
409 {
410 struct r600_atom atom;
411 void *cso; /* e.g. r600_blend_state */
412 struct r600_command_buffer *cb;
413 };
414
415 struct r600_fetch_shader {
416 struct r600_resource *buffer;
417 unsigned offset;
418 uint32_t buffer_mask;
419 unsigned strides[PIPE_MAX_ATTRIBS];
420 };
421
422 struct r600_shader_state {
423 struct r600_atom atom;
424 struct r600_pipe_shader *shader;
425 };
426
427 struct r600_atomic_buffer_state {
428 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
429 };
430
431 struct r600_image_view {
432 struct pipe_image_view base;
433 uint32_t cb_color_base;
434 uint32_t cb_color_pitch;
435 uint32_t cb_color_slice;
436 uint32_t cb_color_view;
437 uint32_t cb_color_info;
438 uint32_t cb_color_attrib;
439 uint32_t cb_color_dim;
440 uint32_t cb_color_fmask;
441 uint32_t cb_color_fmask_slice;
442 uint32_t immed_resource_words[8];
443 uint32_t resource_words[8];
444 bool skip_mip_address_reloc;
445 uint32_t buf_size;
446 };
447
448 struct r600_image_state {
449 struct r600_atom atom;
450 uint32_t enabled_mask;
451 uint32_t dirty_mask;
452 uint32_t compressed_depthtex_mask;
453 uint32_t compressed_colortex_mask;
454 bool dirty_buffer_constants;
455 struct r600_image_view views[R600_MAX_IMAGES];
456 };
457
458 /* Used to spill shader temps */
459 struct r600_scratch_buffer {
460 struct r600_resource *buffer;
461 bool dirty;
462 unsigned size;
463 unsigned item_size;
464 };
465
466 struct r600_context {
467 struct r600_common_context b;
468 struct r600_screen *screen;
469 struct blitter_context *blitter;
470 struct u_suballocator allocator_fetch_shader;
471
472 /* Hardware info. */
473 bool has_vertex_cache;
474 unsigned default_gprs[EG_NUM_HW_STAGES];
475 unsigned current_gprs[EG_NUM_HW_STAGES];
476 unsigned r6xx_num_clause_temp_gprs;
477
478 /* Miscellaneous state objects. */
479 void *custom_dsa_flush;
480 void *custom_blend_resolve;
481 void *custom_blend_decompress;
482 void *custom_blend_fastclear;
483 /* With rasterizer discard, there doesn't have to be a pixel shader.
484 * In that case, we bind this one: */
485 void *dummy_pixel_shader;
486 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
487 * bug where valid CMASK and FMASK are required to be present to avoid
488 * a hardlock in certain operations but aren't actually used
489 * for anything useful. */
490 struct r600_resource *dummy_fmask;
491 struct r600_resource *dummy_cmask;
492
493 /* State binding slots are here. */
494 struct r600_atom *atoms[R600_NUM_ATOMS];
495 /* Dirty atom bitmask for fast tests */
496 uint64_t dirty_atoms;
497 /* States for CS initialization. */
498 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
499 /** Compute specific registers initializations. The start_cs_cmd atom
500 * must be emitted before start_compute_cs_cmd. */
501 struct r600_command_buffer start_compute_cs_cmd;
502 /* Register states. */
503 struct r600_alphatest_state alphatest_state;
504 struct r600_cso_state blend_state;
505 struct r600_blend_color blend_color;
506 struct r600_cb_misc_state cb_misc_state;
507 struct r600_clip_misc_state clip_misc_state;
508 struct r600_clip_state clip_state;
509 struct r600_db_misc_state db_misc_state;
510 struct r600_db_state db_state;
511 struct r600_cso_state dsa_state;
512 struct r600_framebuffer framebuffer;
513 struct r600_poly_offset_state poly_offset_state;
514 struct r600_cso_state rasterizer_state;
515 struct r600_sample_mask sample_mask;
516 struct r600_seamless_cube_map seamless_cube_map;
517 struct r600_config_state config_state;
518 struct r600_stencil_ref_state stencil_ref;
519 struct r600_vgt_state vgt_state;
520 struct r600_atomic_buffer_state atomic_buffer_state;
521 /* only have images on fragment shader */
522 struct r600_image_state fragment_images;
523 struct r600_image_state compute_images;
524 struct r600_image_state fragment_buffers;
525 struct r600_image_state compute_buffers;
526 /* Shaders and shader resources. */
527 struct r600_cso_state vertex_fetch_shader;
528 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
529 struct r600_cs_shader_state cs_shader_state;
530 struct r600_shader_stages_state shader_stages;
531 struct r600_gs_rings_state gs_rings;
532 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
533 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
534
535 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
536
537 /** Vertex buffers for fetch shaders */
538 struct r600_vertexbuf_state vertex_buffer_state;
539 /** Vertex buffers for compute shaders */
540 struct r600_vertexbuf_state cs_vertex_buffer_state;
541
542 /* Additional context states. */
543 unsigned compute_cb_target_mask;
544 struct r600_pipe_shader_selector *ps_shader;
545 struct r600_pipe_shader_selector *vs_shader;
546 struct r600_pipe_shader_selector *gs_shader;
547
548 struct r600_pipe_shader_selector *tcs_shader;
549 struct r600_pipe_shader_selector *tes_shader;
550
551 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
552
553 struct r600_rasterizer_state *rasterizer;
554 bool alpha_to_one;
555 bool force_blend_disable;
556 bool gs_tri_strip_adj_fix;
557 bool dual_src_blend;
558 unsigned zwritemask;
559 unsigned ps_iter_samples;
560
561 /* The list of all texture buffer objects in this context.
562 * This list is walked when a buffer is invalidated/reallocated and
563 * the GPU addresses are updated. */
564 struct list_head texture_buffers;
565
566 /* Last draw state (-1 = unset). */
567 enum mesa_prim last_primitive_type; /* Last primitive type used in draw_vbo. */
568 enum mesa_prim current_rast_prim; /* primitive type after TES, GS */
569 enum mesa_prim last_rast_prim;
570 unsigned last_start_instance;
571
572 struct r600_isa *isa;
573 float sample_positions[4 * 16];
574 float tess_state[8];
575 uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/
576 struct r600_pipe_shader_selector *last_ls;
577 struct r600_pipe_shader_selector *last_tcs;
578 unsigned last_num_tcs_input_cp;
579 unsigned lds_alloc;
580
581 struct r600_scratch_buffer scratch_buffers[MAX2(R600_NUM_HW_STAGES, EG_NUM_HW_STAGES)];
582
583 /* Debug state. */
584 bool is_debug;
585 struct radeon_saved_cs last_gfx;
586 struct r600_resource *last_trace_buf;
587 struct r600_resource *trace_buf;
588 unsigned trace_id;
589
590 uint8_t patch_vertices;
591 bool cmd_buf_is_compute;
592 struct pipe_resource *append_fence;
593 uint32_t append_fence_id;
594 };
595
r600_emit_command_buffer(struct radeon_cmdbuf * cs,struct r600_command_buffer * cb)596 static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs,
597 struct r600_command_buffer *cb)
598 {
599 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
600 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
601 cs->current.cdw += cb->num_dw;
602 }
603
r600_set_atom_dirty(struct r600_context * rctx,struct r600_atom * atom,bool dirty)604 static inline void r600_set_atom_dirty(struct r600_context *rctx,
605 struct r600_atom *atom,
606 bool dirty)
607 {
608 uint64_t mask;
609
610 assert(atom->id != 0);
611 assert(atom->id < sizeof(mask) * 8);
612 mask = 1ull << atom->id;
613 if (dirty)
614 rctx->dirty_atoms |= mask;
615 else
616 rctx->dirty_atoms &= ~mask;
617 }
618
r600_mark_atom_dirty(struct r600_context * rctx,struct r600_atom * atom)619 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
620 struct r600_atom *atom)
621 {
622 r600_set_atom_dirty(rctx, atom, true);
623 }
624
r600_emit_atom(struct r600_context * rctx,struct r600_atom * atom)625 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
626 {
627 atom->emit(&rctx->b, atom);
628 r600_set_atom_dirty(rctx, atom, false);
629 }
630
r600_set_cso_state(struct r600_context * rctx,struct r600_cso_state * state,void * cso)631 static inline void r600_set_cso_state(struct r600_context *rctx,
632 struct r600_cso_state *state, void *cso)
633 {
634 state->cso = cso;
635 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
636 }
637
r600_set_cso_state_with_cb(struct r600_context * rctx,struct r600_cso_state * state,void * cso,struct r600_command_buffer * cb)638 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
639 struct r600_cso_state *state, void *cso,
640 struct r600_command_buffer *cb)
641 {
642 state->cb = cb;
643 state->atom.num_dw = cb ? cb->num_dw : 0;
644 r600_set_cso_state(rctx, state, cso);
645 }
646
647 /* compute_memory_pool.c */
648 struct compute_memory_pool;
649 void compute_memory_pool_delete(struct compute_memory_pool* pool);
650 struct compute_memory_pool* compute_memory_pool_new(
651 struct r600_screen *rscreen);
652
653 /* evergreen_state.c */
654 struct pipe_sampler_view *
655 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
656 struct pipe_resource *texture,
657 const struct pipe_sampler_view *state,
658 unsigned width0, unsigned height0,
659 unsigned force_level);
660 void evergreen_init_common_regs(struct r600_context *ctx,
661 struct r600_command_buffer *cb,
662 enum amd_gfx_level ctx_chip_class,
663 enum radeon_family ctx_family,
664 int ctx_drm_minor);
665 void cayman_init_common_regs(struct r600_command_buffer *cb,
666 enum amd_gfx_level ctx_chip_class,
667 enum radeon_family ctx_family,
668 int ctx_drm_minor);
669
670 void evergreen_init_state_functions(struct r600_context *rctx);
671 void evergreen_init_atom_start_cs(struct r600_context *rctx);
672 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
673 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
674 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
675 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
676 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
677 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
678 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
679 void *evergreen_create_resolve_blend(struct r600_context *rctx);
680 void *evergreen_create_decompress_blend(struct r600_context *rctx);
681 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
682 bool evergreen_is_format_supported(struct pipe_screen *screen,
683 enum pipe_format format,
684 enum pipe_texture_target target,
685 unsigned sample_count,
686 unsigned storage_sample_count,
687 unsigned usage);
688 void evergreen_init_color_surface(struct r600_context *rctx,
689 struct r600_surface *surf);
690 void evergreen_init_color_surface_rat(struct r600_context *rctx,
691 struct r600_surface *surf);
692 void evergreen_update_db_shader_control(struct r600_context * rctx);
693 bool evergreen_adjust_gprs(struct r600_context *rctx);
694 void evergreen_setup_scratch_buffers(struct r600_context *rctx);
695 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
696 unsigned nr_cbufs);
697 /* r600_blit.c */
698 void r600_init_blit_functions(struct r600_context *rctx);
699 void r600_decompress_depth_textures(struct r600_context *rctx,
700 struct r600_samplerview_state *textures);
701 void r600_decompress_depth_images(struct r600_context *rctx,
702 struct r600_image_state *images);
703 void r600_decompress_color_textures(struct r600_context *rctx,
704 struct r600_samplerview_state *textures);
705 void r600_decompress_color_images(struct r600_context *rctx,
706 struct r600_image_state *images);
707 void r600_resource_copy_region(struct pipe_context *ctx,
708 struct pipe_resource *dst,
709 unsigned dst_level,
710 unsigned dstx, unsigned dsty, unsigned dstz,
711 struct pipe_resource *src,
712 unsigned src_level,
713 const struct pipe_box *src_box);
714
715 /* r600_shader.c */
716 int r600_pipe_shader_create(struct pipe_context *ctx,
717 struct r600_pipe_shader *shader,
718 union r600_shader_key key);
719
720 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
721
722 /* r600_state.c */
723 struct pipe_sampler_view *
724 r600_create_sampler_view_custom(struct pipe_context *ctx,
725 struct pipe_resource *texture,
726 const struct pipe_sampler_view *state,
727 unsigned width_first_level, unsigned height_first_level);
728 void r600_init_state_functions(struct r600_context *rctx);
729 void r600_init_atom_start_cs(struct r600_context *rctx);
730 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
731 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
732 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
733 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
734 void *r600_create_db_flush_dsa(struct r600_context *rctx);
735 void *r600_create_resolve_blend(struct r600_context *rctx);
736 void *r700_create_resolve_blend(struct r600_context *rctx);
737 void *r600_create_decompress_blend(struct r600_context *rctx);
738 bool r600_adjust_gprs(struct r600_context *rctx);
739 bool r600_is_format_supported(struct pipe_screen *screen,
740 enum pipe_format format,
741 enum pipe_texture_target target,
742 unsigned sample_count,
743 unsigned storage_sample_count,
744 unsigned usage);
745 void r600_update_db_shader_control(struct r600_context * rctx);
746 void r600_setup_scratch_buffers(struct r600_context *rctx);
747
748 /* r600_hw_context.c */
749 void r600_context_gfx_flush(void *context, unsigned flags,
750 struct pipe_fence_handle **fence);
751 void r600_begin_new_cs(struct r600_context *ctx);
752 void r600_flush_emit(struct r600_context *ctx);
753 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, bool count_draw_in, unsigned num_atomics);
754 void r600_emit_pfp_sync_me(struct r600_context *rctx);
755 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
756 struct pipe_resource *dst, uint64_t dst_offset,
757 struct pipe_resource *src, uint64_t src_offset,
758 unsigned size);
759 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
760 struct pipe_resource *dst, uint64_t offset,
761 unsigned size, uint32_t clear_value,
762 enum r600_coherency coher);
763 void r600_dma_copy_buffer(struct r600_context *rctx,
764 struct pipe_resource *dst,
765 struct pipe_resource *src,
766 uint64_t dst_offset,
767 uint64_t src_offset,
768 uint64_t size);
769
770 /*
771 * evergreen_hw_context.c
772 */
773 void evergreen_dma_copy_buffer(struct r600_context *rctx,
774 struct pipe_resource *dst,
775 struct pipe_resource *src,
776 uint64_t dst_offset,
777 uint64_t src_offset,
778 uint64_t size);
779 void evergreen_setup_tess_constants(struct r600_context *rctx,
780 const struct pipe_draw_info *info,
781 unsigned *num_patches);
782 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
783 const struct pipe_draw_info *info,
784 unsigned num_patches);
785 void evergreen_set_ls_hs_config(struct r600_context *rctx,
786 struct radeon_cmdbuf *cs,
787 uint32_t ls_hs_config);
788 void evergreen_set_lds_alloc(struct r600_context *rctx,
789 struct radeon_cmdbuf *cs,
790 uint32_t lds_alloc);
791
792 /* r600_state_common.c */
793 void r600_init_common_state_functions(struct r600_context *rctx);
794 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
795 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
796 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
797 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
798 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
799 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
800 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
801 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
802 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
803 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
804 unsigned num_dw);
805 void r600_vertex_buffers_dirty(struct r600_context *rctx);
806 void r600_sampler_views_dirty(struct r600_context *rctx,
807 struct r600_samplerview_state *state);
808 void r600_sampler_states_dirty(struct r600_context *rctx,
809 struct r600_sampler_states *state);
810 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
811 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
812 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
813 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
814 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg);
815 uint32_t r600_translate_stencil_op(int s_op);
816 uint32_t r600_translate_fill(uint32_t func);
817 unsigned r600_tex_wrap(unsigned wrap);
818 unsigned r600_tex_mipfilter(unsigned filter);
819 unsigned r600_tex_compare(unsigned compare);
820 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
821 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
822 const unsigned char *swizzle_view,
823 bool vtx);
824 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
825 const unsigned char *swizzle_view,
826 uint32_t *word4_p, uint32_t *yuv_format_p,
827 bool do_endian_swap);
828 uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format,
829 bool do_endian_swap);
830 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
831
832 /* r600_uvd.c */
833 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
834 const struct pipe_video_codec *decoder);
835
836 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
837 const struct pipe_video_buffer *tmpl);
838
839 /*
840 * Helpers for building command buffers
841 */
842
843 #define PKT3_SET_CONFIG_REG 0x68
844 #define PKT3_SET_CONTEXT_REG 0x69
845 #define PKT3_SET_CTL_CONST 0x6F
846 #define PKT3_SET_LOOP_CONST 0x6C
847
848 #define R600_CONFIG_REG_OFFSET 0x08000
849 #define R600_CONTEXT_REG_OFFSET 0x28000
850 #define R600_CTL_CONST_OFFSET 0x3CFF0
851 #define R600_LOOP_CONST_OFFSET 0X0003E200
852 #define EG_LOOP_CONST_OFFSET 0x0003A200
853
854 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
855 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
856 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
857 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
858 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
859
860 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
861
862 /*Evergreen Compute packet3*/
863 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
864
r600_store_value(struct r600_command_buffer * cb,unsigned value)865 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
866 {
867 cb->buf[cb->num_dw++] = value;
868 }
869
r600_store_array(struct r600_command_buffer * cb,unsigned num,unsigned * ptr)870 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
871 {
872 assert(cb->num_dw+num <= cb->max_num_dw);
873 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
874 cb->num_dw += num;
875 }
876
r600_store_config_reg_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)877 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
878 {
879 assert(reg < R600_CONTEXT_REG_OFFSET);
880 assert(cb->num_dw+2+num <= cb->max_num_dw);
881 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
882 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
883 }
884
885 /**
886 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
887 * shaders.
888 */
r600_store_context_reg_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)889 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
890 {
891 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
892 assert(cb->num_dw+2+num <= cb->max_num_dw);
893 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
894 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
895 }
896
897 /**
898 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
899 * shaders.
900 */
r600_store_ctl_const_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)901 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
902 {
903 assert(reg >= R600_CTL_CONST_OFFSET);
904 assert(cb->num_dw+2+num <= cb->max_num_dw);
905 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
906 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
907 }
908
r600_store_loop_const_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)909 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
910 {
911 assert(reg >= R600_LOOP_CONST_OFFSET);
912 assert(cb->num_dw+2+num <= cb->max_num_dw);
913 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
914 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
915 }
916
917 /**
918 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
919 * shaders.
920 */
eg_store_loop_const_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)921 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
922 {
923 assert(reg >= EG_LOOP_CONST_OFFSET);
924 assert(cb->num_dw+2+num <= cb->max_num_dw);
925 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
926 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
927 }
928
r600_store_config_reg(struct r600_command_buffer * cb,unsigned reg,unsigned value)929 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
930 {
931 r600_store_config_reg_seq(cb, reg, 1);
932 r600_store_value(cb, value);
933 }
934
r600_store_context_reg(struct r600_command_buffer * cb,unsigned reg,unsigned value)935 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
936 {
937 r600_store_context_reg_seq(cb, reg, 1);
938 r600_store_value(cb, value);
939 }
940
r600_store_ctl_const(struct r600_command_buffer * cb,unsigned reg,unsigned value)941 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
942 {
943 r600_store_ctl_const_seq(cb, reg, 1);
944 r600_store_value(cb, value);
945 }
946
r600_store_loop_const(struct r600_command_buffer * cb,unsigned reg,unsigned value)947 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
948 {
949 r600_store_loop_const_seq(cb, reg, 1);
950 r600_store_value(cb, value);
951 }
952
eg_store_loop_const(struct r600_command_buffer * cb,unsigned reg,unsigned value)953 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
954 {
955 eg_store_loop_const_seq(cb, reg, 1);
956 r600_store_value(cb, value);
957 }
958
959 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
960 void r600_release_command_buffer(struct r600_command_buffer *cb);
961
radeon_compute_set_context_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)962 static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
963 {
964 radeon_set_context_reg_seq(cs, reg, num);
965 /* Set the compute bit on the packet header */
966 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
967 }
968
radeon_set_ctl_const_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)969 static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
970 {
971 assert(reg >= R600_CTL_CONST_OFFSET);
972 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
973 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
974 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
975 }
976
radeon_compute_set_context_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)977 static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
978 {
979 radeon_compute_set_context_reg_seq(cs, reg, 1);
980 radeon_emit(cs, value);
981 }
982
radeon_set_context_reg_flag(struct radeon_cmdbuf * cs,unsigned reg,unsigned value,unsigned flag)983 static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag)
984 {
985 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
986 radeon_compute_set_context_reg(cs, reg, value);
987 } else {
988 radeon_set_context_reg(cs, reg, value);
989 }
990 }
991
radeon_set_ctl_const(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)992 static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
993 {
994 radeon_set_ctl_const_seq(cs, reg, 1);
995 radeon_emit(cs, value);
996 }
997
998 /*
999 * common helpers
1000 */
1001
1002 /* 12.4 fixed-point */
r600_pack_float_12p4(float x)1003 static inline unsigned r600_pack_float_12p4(float x)
1004 {
1005 return x <= 0 ? 0 :
1006 x >= 4096 ? 0xffff : x * 16;
1007 }
1008
r600_get_flush_flags(enum r600_coherency coher)1009 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
1010 {
1011 switch (coher) {
1012 default:
1013 case R600_COHERENCY_NONE:
1014 return 0;
1015 case R600_COHERENCY_SHADER:
1016 return R600_CONTEXT_INV_CONST_CACHE |
1017 R600_CONTEXT_INV_VERTEX_CACHE |
1018 R600_CONTEXT_INV_TEX_CACHE |
1019 R600_CONTEXT_STREAMOUT_FLUSH;
1020 case R600_COHERENCY_CB_META:
1021 return R600_CONTEXT_FLUSH_AND_INV_CB |
1022 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1023 }
1024 }
1025
1026 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1027 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1028 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1029
1030 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1031
1032 void eg_trace_emit(struct r600_context *rctx);
1033 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1034 unsigned flags);
1035
1036 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
1037 const void *tokens,
1038 enum pipe_shader_ir,
1039 unsigned pipe_shader_type);
1040 int r600_shader_select(struct pipe_context *ctx,
1041 struct r600_pipe_shader_selector* sel,
1042 bool *dirty, bool precompile);
1043
1044 void r600_delete_shader_selector(struct pipe_context *ctx,
1045 struct r600_pipe_shader_selector *sel);
1046
1047 struct r600_shader_atomic;
1048 void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
1049 struct r600_pipe_shader *cs_shader,
1050 struct r600_shader_atomic *combined_atomics,
1051 uint8_t *atomic_used_mask_p);
1052 void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1053 bool is_compute,
1054 struct r600_shader_atomic *combined_atomics,
1055 uint8_t atomic_used_mask);
1056 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1057 bool is_compute,
1058 struct r600_shader_atomic *combined_atomics,
1059 uint8_t *atomic_used_mask_p);
1060 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
1061
1062 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
1063 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
1064 #endif
1065