1 /*
2 * Copyright 2010 Jerome Glisse <[email protected]>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r600_formats.h"
7 #include "r600_shader.h"
8 #include "r600d.h"
9 #include "r600d_common.h"
10
11 #include "pipe/p_shader_tokens.h"
12 #include "util/u_endian.h"
13 #include "util/u_pack_color.h"
14 #include "util/u_memory.h"
15 #include "util/u_framebuffer.h"
16 #include "util/u_dual_blend.h"
17
18 #include <assert.h>
19
r600_translate_blend_function(int blend_func)20 static uint32_t r600_translate_blend_function(int blend_func)
21 {
22 switch (blend_func) {
23 case PIPE_BLEND_ADD:
24 return V_028804_COMB_DST_PLUS_SRC;
25 case PIPE_BLEND_SUBTRACT:
26 return V_028804_COMB_SRC_MINUS_DST;
27 case PIPE_BLEND_REVERSE_SUBTRACT:
28 return V_028804_COMB_DST_MINUS_SRC;
29 case PIPE_BLEND_MIN:
30 return V_028804_COMB_MIN_DST_SRC;
31 case PIPE_BLEND_MAX:
32 return V_028804_COMB_MAX_DST_SRC;
33 default:
34 R600_ERR("Unknown blend function %d\n", blend_func);
35 assert(0);
36 break;
37 }
38 return 0;
39 }
40
r600_translate_blend_factor(int blend_fact)41 static uint32_t r600_translate_blend_factor(int blend_fact)
42 {
43 switch (blend_fact) {
44 case PIPE_BLENDFACTOR_ONE:
45 return V_028804_BLEND_ONE;
46 case PIPE_BLENDFACTOR_SRC_COLOR:
47 return V_028804_BLEND_SRC_COLOR;
48 case PIPE_BLENDFACTOR_SRC_ALPHA:
49 return V_028804_BLEND_SRC_ALPHA;
50 case PIPE_BLENDFACTOR_DST_ALPHA:
51 return V_028804_BLEND_DST_ALPHA;
52 case PIPE_BLENDFACTOR_DST_COLOR:
53 return V_028804_BLEND_DST_COLOR;
54 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
55 return V_028804_BLEND_SRC_ALPHA_SATURATE;
56 case PIPE_BLENDFACTOR_CONST_COLOR:
57 return V_028804_BLEND_CONST_COLOR;
58 case PIPE_BLENDFACTOR_CONST_ALPHA:
59 return V_028804_BLEND_CONST_ALPHA;
60 case PIPE_BLENDFACTOR_ZERO:
61 return V_028804_BLEND_ZERO;
62 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
63 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
64 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
65 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
66 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
67 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
68 case PIPE_BLENDFACTOR_INV_DST_COLOR:
69 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
70 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
71 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
72 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
73 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
74 case PIPE_BLENDFACTOR_SRC1_COLOR:
75 return V_028804_BLEND_SRC1_COLOR;
76 case PIPE_BLENDFACTOR_SRC1_ALPHA:
77 return V_028804_BLEND_SRC1_ALPHA;
78 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
79 return V_028804_BLEND_INV_SRC1_COLOR;
80 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
81 return V_028804_BLEND_INV_SRC1_ALPHA;
82 default:
83 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
84 assert(0);
85 break;
86 }
87 return 0;
88 }
89
r600_tex_dim(unsigned dim,unsigned nr_samples)90 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
91 {
92 switch (dim) {
93 default:
94 case PIPE_TEXTURE_1D:
95 return V_038000_SQ_TEX_DIM_1D;
96 case PIPE_TEXTURE_1D_ARRAY:
97 return V_038000_SQ_TEX_DIM_1D_ARRAY;
98 case PIPE_TEXTURE_2D:
99 case PIPE_TEXTURE_RECT:
100 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
101 V_038000_SQ_TEX_DIM_2D;
102 case PIPE_TEXTURE_2D_ARRAY:
103 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
104 V_038000_SQ_TEX_DIM_2D_ARRAY;
105 case PIPE_TEXTURE_3D:
106 return V_038000_SQ_TEX_DIM_3D;
107 case PIPE_TEXTURE_CUBE:
108 case PIPE_TEXTURE_CUBE_ARRAY:
109 return V_038000_SQ_TEX_DIM_CUBEMAP;
110 }
111 }
112
r600_translate_dbformat(enum pipe_format format)113 static uint32_t r600_translate_dbformat(enum pipe_format format)
114 {
115 switch (format) {
116 case PIPE_FORMAT_Z16_UNORM:
117 return V_028010_DEPTH_16;
118 case PIPE_FORMAT_Z24X8_UNORM:
119 return V_028010_DEPTH_X8_24;
120 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
121 return V_028010_DEPTH_8_24;
122 case PIPE_FORMAT_Z32_FLOAT:
123 return V_028010_DEPTH_32_FLOAT;
124 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
125 return V_028010_DEPTH_X24_8_32_FLOAT;
126 default:
127 return ~0U;
128 }
129 }
130
r600_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)131 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
132 {
133 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
134 false) != ~0U;
135 }
136
r600_is_colorbuffer_format_supported(enum amd_gfx_level chip,enum pipe_format format)137 static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format)
138 {
139 return r600_translate_colorformat(chip, format, false) != ~0U &&
140 r600_translate_colorswap(format, false) != ~0U;
141 }
142
r600_is_zs_format_supported(enum pipe_format format)143 static bool r600_is_zs_format_supported(enum pipe_format format)
144 {
145 return r600_translate_dbformat(format) != ~0U;
146 }
147
r600_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)148 bool r600_is_format_supported(struct pipe_screen *screen,
149 enum pipe_format format,
150 enum pipe_texture_target target,
151 unsigned sample_count,
152 unsigned storage_sample_count,
153 unsigned usage)
154 {
155 struct r600_screen *rscreen = (struct r600_screen*)screen;
156 unsigned retval = 0;
157
158 if (target >= PIPE_MAX_TEXTURE_TYPES) {
159 R600_ERR("r600: unsupported texture type %d\n", target);
160 return false;
161 }
162
163 if (util_format_get_num_planes(format) > 1)
164 return false;
165
166 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
167 return false;
168
169 if (sample_count > 1) {
170 if (!rscreen->has_msaa)
171 return false;
172
173 /* R11G11B10 is broken on R6xx. */
174 if (rscreen->b.gfx_level == R600 &&
175 format == PIPE_FORMAT_R11G11B10_FLOAT)
176 return false;
177
178 /* MSAA integer colorbuffers hang. */
179 if (util_format_is_pure_integer(format) &&
180 !util_format_is_depth_or_stencil(format))
181 return false;
182
183 switch (sample_count) {
184 case 2:
185 case 4:
186 case 8:
187 break;
188 default:
189 return false;
190 }
191 }
192
193 if (usage & PIPE_BIND_SAMPLER_VIEW) {
194 if (target == PIPE_BUFFER) {
195 if (r600_is_buffer_format_supported(format, false))
196 retval |= PIPE_BIND_SAMPLER_VIEW;
197 } else {
198 if (r600_is_sampler_format_supported(screen, format))
199 retval |= PIPE_BIND_SAMPLER_VIEW;
200 }
201 }
202
203 if ((usage & (PIPE_BIND_RENDER_TARGET |
204 PIPE_BIND_DISPLAY_TARGET |
205 PIPE_BIND_SCANOUT |
206 PIPE_BIND_SHARED |
207 PIPE_BIND_BLENDABLE)) &&
208 r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) {
209 retval |= usage &
210 (PIPE_BIND_RENDER_TARGET |
211 PIPE_BIND_DISPLAY_TARGET |
212 PIPE_BIND_SCANOUT |
213 PIPE_BIND_SHARED);
214 if (!util_format_is_pure_integer(format) &&
215 !util_format_is_depth_or_stencil(format))
216 retval |= usage & PIPE_BIND_BLENDABLE;
217 }
218
219 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
220 r600_is_zs_format_supported(format)) {
221 retval |= PIPE_BIND_DEPTH_STENCIL;
222 }
223
224 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
225 r600_is_buffer_format_supported(format, true)) {
226 retval |= PIPE_BIND_VERTEX_BUFFER;
227 }
228
229 if (usage & PIPE_BIND_INDEX_BUFFER &&
230 r600_is_index_format_supported(format)) {
231 retval |= PIPE_BIND_INDEX_BUFFER;
232 }
233
234 if ((usage & PIPE_BIND_LINEAR) &&
235 !util_format_is_compressed(format) &&
236 !(usage & PIPE_BIND_DEPTH_STENCIL))
237 retval |= PIPE_BIND_LINEAR;
238
239 return retval == usage;
240 }
241
r600_emit_polygon_offset(struct r600_context * rctx,struct r600_atom * a)242 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
243 {
244 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
245 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
246 float offset_units = state->offset_units;
247 float offset_scale = state->offset_scale;
248 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
249
250 if (!state->offset_units_unscaled) {
251 switch (state->zs_format) {
252 case PIPE_FORMAT_Z24X8_UNORM:
253 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
254 offset_units *= 2.0f;
255 pa_su_poly_offset_db_fmt_cntl =
256 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
257 break;
258 case PIPE_FORMAT_Z16_UNORM:
259 offset_units *= 4.0f;
260 pa_su_poly_offset_db_fmt_cntl =
261 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
262 break;
263 default:
264 pa_su_poly_offset_db_fmt_cntl =
265 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
266 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
267 }
268 }
269
270 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
271 radeon_emit(cs, fui(offset_scale));
272 radeon_emit(cs, fui(offset_units));
273 radeon_emit(cs, fui(offset_scale));
274 radeon_emit(cs, fui(offset_units));
275
276 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
277 pa_su_poly_offset_db_fmt_cntl);
278 }
279
r600_get_blend_control(const struct pipe_blend_state * state,unsigned i)280 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
281 {
282 int j = state->independent_blend_enable ? i : 0;
283
284 unsigned eqRGB = state->rt[j].rgb_func;
285 unsigned srcRGB = state->rt[j].rgb_src_factor;
286 unsigned dstRGB = state->rt[j].rgb_dst_factor;
287
288 unsigned eqA = state->rt[j].alpha_func;
289 unsigned srcA = state->rt[j].alpha_src_factor;
290 unsigned dstA = state->rt[j].alpha_dst_factor;
291 uint32_t bc = 0;
292
293 if (!state->rt[j].blend_enable)
294 return 0;
295
296 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
297 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
298 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
299
300 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
301 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
302 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
303 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
304 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
305 }
306 return bc;
307 }
308
r600_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,int mode)309 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
310 const struct pipe_blend_state *state,
311 int mode)
312 {
313 struct r600_context *rctx = (struct r600_context *)ctx;
314 uint32_t color_control = 0, target_mask = 0;
315 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
316
317 if (!blend) {
318 return NULL;
319 }
320
321 r600_init_command_buffer(&blend->buffer, 20);
322 r600_init_command_buffer(&blend->buffer_no_blend, 20);
323
324 /* R600 does not support per-MRT blends */
325 if (rctx->b.family > CHIP_R600)
326 color_control |= S_028808_PER_MRT_BLEND(1);
327
328 if (state->logicop_enable) {
329 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
330 } else {
331 color_control |= (0xcc << 16);
332 }
333 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
334 if (state->independent_blend_enable) {
335 for (int i = 0; i < 8; i++) {
336 if (state->rt[i].blend_enable) {
337 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
338 }
339 target_mask |= (state->rt[i].colormask << (4 * i));
340 }
341 } else {
342 for (int i = 0; i < 8; i++) {
343 if (state->rt[0].blend_enable) {
344 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
345 }
346 target_mask |= (state->rt[0].colormask << (4 * i));
347 }
348 }
349
350 if (target_mask)
351 color_control |= S_028808_SPECIAL_OP(mode);
352 else
353 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
354
355 /* only MRT0 has dual src blend */
356 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
357 blend->cb_target_mask = target_mask;
358 blend->cb_color_control = color_control;
359 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
360 blend->alpha_to_one = state->alpha_to_one;
361
362 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
363 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
364 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
365 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
366 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
367 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
368
369 /* Copy over the registers set so far into buffer_no_blend. */
370 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
371 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
372
373 /* Only add blend registers if blending is enabled. */
374 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
375 return blend;
376 }
377
378 /* The first R600 does not support per-MRT blends */
379 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
380 r600_get_blend_control(state, 0));
381
382 if (rctx->b.family > CHIP_R600) {
383 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
384 for (int i = 0; i < 8; i++) {
385 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
386 }
387 }
388 return blend;
389 }
390
r600_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)391 static void *r600_create_blend_state(struct pipe_context *ctx,
392 const struct pipe_blend_state *state)
393 {
394 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
395 }
396
r600_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)397 static void *r600_create_dsa_state(struct pipe_context *ctx,
398 const struct pipe_depth_stencil_alpha_state *state)
399 {
400 unsigned db_depth_control, alpha_test_control, alpha_ref;
401 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
402
403 if (!dsa) {
404 return NULL;
405 }
406
407 r600_init_command_buffer(&dsa->buffer, 3);
408
409 dsa->valuemask[0] = state->stencil[0].valuemask;
410 dsa->valuemask[1] = state->stencil[1].valuemask;
411 dsa->writemask[0] = state->stencil[0].writemask;
412 dsa->writemask[1] = state->stencil[1].writemask;
413 dsa->zwritemask = state->depth_writemask;
414
415 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
416 S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
417 S_028800_ZFUNC(state->depth_func);
418
419 /* stencil */
420 if (state->stencil[0].enabled) {
421 db_depth_control |= S_028800_STENCIL_ENABLE(1);
422 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
423 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
424 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
425 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
426
427 if (state->stencil[1].enabled) {
428 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
429 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
430 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
431 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
432 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
433 }
434 }
435
436 /* alpha */
437 alpha_test_control = 0;
438 alpha_ref = 0;
439 if (state->alpha_enabled) {
440 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha_func);
441 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
442 alpha_ref = fui(state->alpha_ref_value);
443 }
444 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
445 dsa->alpha_ref = alpha_ref;
446
447 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
448 return dsa;
449 }
450
r600_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)451 static void *r600_create_rs_state(struct pipe_context *ctx,
452 const struct pipe_rasterizer_state *state)
453 {
454 struct r600_context *rctx = (struct r600_context *)ctx;
455 unsigned tmp, sc_mode_cntl, spi_interp;
456 float psize_min, psize_max;
457 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
458
459 if (!rs) {
460 return NULL;
461 }
462
463 r600_init_command_buffer(&rs->buffer, 30);
464
465 rs->scissor_enable = state->scissor;
466 rs->clip_halfz = state->clip_halfz;
467 rs->flatshade = state->flatshade;
468 rs->sprite_coord_enable = state->sprite_coord_enable;
469 rs->rasterizer_discard = state->rasterizer_discard;
470 rs->two_side = state->light_twoside;
471 rs->clip_plane_enable = state->clip_plane_enable;
472 rs->pa_sc_line_stipple = state->line_stipple_enable ?
473 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
474 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
475 rs->pa_cl_clip_cntl =
476 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
477 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
478 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
479 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
480 if (rctx->b.gfx_level == R700) {
481 rs->pa_cl_clip_cntl |=
482 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
483 }
484 rs->multisample_enable = state->multisample;
485
486 /* offset */
487 rs->offset_units = state->offset_units;
488 rs->offset_scale = state->offset_scale * 16.0f;
489 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
490 rs->offset_units_unscaled = state->offset_units_unscaled;
491
492 if (state->point_size_per_vertex) {
493 psize_min = util_get_min_point_size(state);
494 psize_max = 8192;
495 } else {
496 /* Force the point size to be as if the vertex output was disabled. */
497 psize_min = state->point_size;
498 psize_max = state->point_size;
499 }
500
501 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
502 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
503 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
504 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
505 if (rctx->b.family == CHIP_RV770) {
506 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
507 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
508 }
509 if (rctx->b.gfx_level >= R700) {
510 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
511 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
512 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
513 } else {
514 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
515 }
516
517 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
518 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
519 S_0286D4_PNT_SPRITE_OVRD_X(2) |
520 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
521 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
522 S_0286D4_PNT_SPRITE_OVRD_W(1);
523 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
524 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
525 }
526
527 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
528 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
529 tmp = r600_pack_float_12p4(state->point_size/2);
530 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
531 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
532 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
533 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
534 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
535 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
536 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
537
538 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
539 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
540 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
541 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
542 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
543 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
544
545 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
546 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
547 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
548 S_028814_FACE(!state->front_ccw) |
549 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
550 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
551 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
552 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
553 state->fill_back != PIPE_POLYGON_MODE_FILL) |
554 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
555 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
556 if (rctx->b.gfx_level == R700) {
557 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
558 }
559 if (rctx->b.gfx_level == R600) {
560 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
561 S_028350_MULTIPASS(state->rasterizer_discard));
562 }
563 return rs;
564 }
565
r600_tex_filter(unsigned filter,unsigned max_aniso)566 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
567 {
568 if (filter == PIPE_TEX_FILTER_LINEAR)
569 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
570 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
571 else
572 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
573 : V_03C000_SQ_TEX_XY_FILTER_POINT;
574 }
575
r600_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)576 static void *r600_create_sampler_state(struct pipe_context *ctx,
577 const struct pipe_sampler_state *state)
578 {
579 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
580 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
581 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
582 : state->max_anisotropy;
583 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
584
585 if (!ss) {
586 return NULL;
587 }
588
589 ss->seamless_cube_map = state->seamless_cube_map;
590 ss->border_color_use = sampler_state_needs_border_color(state);
591
592 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
593 ss->tex_sampler_words[0] =
594 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
595 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
596 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
597 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
598 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
599 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
600 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
601 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
602 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
603 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
604 ss->tex_sampler_words[1] =
605 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
606 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
607 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
608 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
609 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
610
611 if (ss->border_color_use) {
612 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
613 }
614 return ss;
615 }
616
617 static struct pipe_sampler_view *
texture_buffer_sampler_view(struct r600_pipe_sampler_view * view,unsigned width0,unsigned height0)618 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
619 unsigned width0, unsigned height0)
620
621 {
622 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
623 int stride = util_format_get_blocksize(view->base.format);
624 unsigned format, num_format, format_comp, endian;
625 uint64_t offset = view->base.u.buf.offset;
626 unsigned size = view->base.u.buf.size;
627
628 r600_vertex_data_type(view->base.format,
629 &format, &num_format, &format_comp,
630 &endian);
631
632 view->tex_resource = &tmp->resource;
633 view->skip_mip_address_reloc = true;
634
635 view->tex_resource_words[0] = offset;
636 view->tex_resource_words[1] = size - 1;
637 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
638 S_038008_STRIDE(stride) |
639 S_038008_DATA_FORMAT(format) |
640 S_038008_NUM_FORMAT_ALL(num_format) |
641 S_038008_FORMAT_COMP_ALL(format_comp) |
642 S_038008_ENDIAN_SWAP(endian);
643 view->tex_resource_words[3] = 0;
644 /*
645 * in theory dword 4 is for number of elements, for use with resinfo,
646 * but it seems to utterly fail to work, the amd gpu shader analyser
647 * uses a const buffer to store the element sizes for buffer txq
648 */
649 view->tex_resource_words[4] = 0;
650 view->tex_resource_words[5] = 0;
651 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
652 return &view->base;
653 }
654
655 struct pipe_sampler_view *
r600_create_sampler_view_custom(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state,unsigned width_first_level,unsigned height_first_level)656 r600_create_sampler_view_custom(struct pipe_context *ctx,
657 struct pipe_resource *texture,
658 const struct pipe_sampler_view *state,
659 unsigned width_first_level, unsigned height_first_level)
660 {
661 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
662 struct r600_texture *tmp = (struct r600_texture*)texture;
663 unsigned format, endian;
664 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
665 unsigned char swizzle[4], array_mode = 0;
666 unsigned width, height, depth, offset_level, last_level;
667 bool do_endian_swap = false;
668
669 if (!view)
670 return NULL;
671
672 /* initialize base object */
673 view->base = *state;
674 view->base.texture = NULL;
675 pipe_reference(NULL, &texture->reference);
676 view->base.texture = texture;
677 view->base.reference.count = 1;
678 view->base.context = ctx;
679
680 if (texture->target == PIPE_BUFFER)
681 return texture_buffer_sampler_view(view, texture->width0, 1);
682
683 swizzle[0] = state->swizzle_r;
684 swizzle[1] = state->swizzle_g;
685 swizzle[2] = state->swizzle_b;
686 swizzle[3] = state->swizzle_a;
687
688 if (UTIL_ARCH_BIG_ENDIAN)
689 do_endian_swap = !tmp->db_compatible;
690
691 format = r600_translate_texformat(ctx->screen, state->format,
692 swizzle,
693 &word4, &yuv_format, do_endian_swap);
694 assert(format != ~0);
695 if (format == ~0) {
696 FREE(view);
697 return NULL;
698 }
699
700 if (state->format == PIPE_FORMAT_X24S8_UINT ||
701 state->format == PIPE_FORMAT_S8X24_UINT ||
702 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
703 state->format == PIPE_FORMAT_S8_UINT)
704 view->is_stencil_sampler = true;
705
706 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
707 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
708 FREE(view);
709 return NULL;
710 }
711 tmp = tmp->flushed_depth_texture;
712 }
713
714 endian = r600_colorformat_endian_swap(format, do_endian_swap);
715
716 offset_level = state->u.tex.first_level;
717 last_level = state->u.tex.last_level - offset_level;
718 width = width_first_level;
719 height = height_first_level;
720 depth = u_minify(texture->depth0, offset_level);
721 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
722
723 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
724 height = 1;
725 depth = texture->array_size;
726 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
727 depth = texture->array_size;
728 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
729 depth = texture->array_size / 6;
730
731 switch (tmp->surface.u.legacy.level[offset_level].mode) {
732 default:
733 case RADEON_SURF_MODE_LINEAR_ALIGNED:
734 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
735 break;
736 case RADEON_SURF_MODE_1D:
737 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
738 break;
739 case RADEON_SURF_MODE_2D:
740 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
741 break;
742 }
743
744 view->tex_resource = &tmp->resource;
745 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
746 S_038000_TILE_MODE(array_mode) |
747 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
748 S_038000_PITCH((pitch / 8) - 1) |
749 S_038000_TEX_WIDTH(width - 1));
750 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
751 S_038004_TEX_DEPTH(depth - 1) |
752 S_038004_DATA_FORMAT(format));
753 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B;
754 if (offset_level >= tmp->resource.b.b.last_level) {
755 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B;
756 } else {
757 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B;
758 }
759 view->tex_resource_words[4] = (word4 |
760 S_038010_REQUEST_SIZE(1) |
761 S_038010_ENDIAN_SWAP(endian) |
762 S_038010_BASE_LEVEL(0));
763 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
764 S_038014_LAST_ARRAY(state->u.tex.last_layer));
765 if (texture->nr_samples > 1) {
766 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
767 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
768 } else {
769 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
770 }
771 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
772 S_038018_MAX_ANISO(4 /* max 16 samples */));
773 return &view->base;
774 }
775
776 static struct pipe_sampler_view *
r600_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * tex,const struct pipe_sampler_view * state)777 r600_create_sampler_view(struct pipe_context *ctx,
778 struct pipe_resource *tex,
779 const struct pipe_sampler_view *state)
780 {
781 return r600_create_sampler_view_custom(ctx, tex, state,
782 u_minify(tex->width0, state->u.tex.first_level),
783 u_minify(tex->height0, state->u.tex.first_level));
784 }
785
r600_emit_clip_state(struct r600_context * rctx,struct r600_atom * atom)786 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
787 {
788 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
789 struct pipe_clip_state *state = &rctx->clip_state.state;
790
791 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
792 radeon_emit_array(cs, (unsigned*)state, 6*4);
793 }
794
r600_set_polygon_stipple(struct pipe_context * ctx,const struct pipe_poly_stipple * state)795 static void r600_set_polygon_stipple(struct pipe_context *ctx,
796 const struct pipe_poly_stipple *state)
797 {
798 }
799
r600_init_color_surface(struct r600_context * rctx,struct r600_surface * surf,bool force_cmask_fmask)800 static void r600_init_color_surface(struct r600_context *rctx,
801 struct r600_surface *surf,
802 bool force_cmask_fmask)
803 {
804 struct r600_screen *rscreen = rctx->screen;
805 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
806 unsigned level = surf->base.u.tex.level;
807 unsigned pitch, slice;
808 unsigned color_info;
809 unsigned color_view;
810 unsigned format, swap, ntype, endian;
811 unsigned offset;
812 const struct util_format_description *desc;
813 int i;
814 bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = false;
815
816 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
817 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
818 rtex = rtex->flushed_depth_texture;
819 assert(rtex);
820 }
821
822 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
823 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
824 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
825
826 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
827 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
828 if (slice) {
829 slice = slice - 1;
830 }
831 color_info = 0;
832 switch (rtex->surface.u.legacy.level[level].mode) {
833 default:
834 case RADEON_SURF_MODE_LINEAR_ALIGNED:
835 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
836 break;
837 case RADEON_SURF_MODE_1D:
838 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
839 break;
840 case RADEON_SURF_MODE_2D:
841 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
842 break;
843 }
844
845 desc = util_format_description(surf->base.format);
846
847 i = util_format_get_first_non_void_channel(surf->base.format);
848
849 ntype = V_0280A0_NUMBER_UNORM;
850 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
851 ntype = V_0280A0_NUMBER_SRGB;
852 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
853 if (desc->channel[i].normalized)
854 ntype = V_0280A0_NUMBER_SNORM;
855 else if (desc->channel[i].pure_integer)
856 ntype = V_0280A0_NUMBER_SINT;
857 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
858 if (desc->channel[i].normalized)
859 ntype = V_0280A0_NUMBER_UNORM;
860 else if (desc->channel[i].pure_integer)
861 ntype = V_0280A0_NUMBER_UINT;
862 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
863 ntype = V_0280A0_NUMBER_FLOAT;
864 }
865
866 if (UTIL_ARCH_BIG_ENDIAN)
867 do_endian_swap = !rtex->db_compatible;
868
869 format = r600_translate_colorformat(rctx->b.gfx_level, surf->base.format,
870 do_endian_swap);
871 assert(format != ~0);
872
873 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
874 assert(swap != ~0);
875
876 endian = r600_colorformat_endian_swap(format, do_endian_swap);
877
878 /* blend clamp should be set for all NORM/SRGB types */
879 if (ntype == V_0280A0_NUMBER_UNORM || ntype == V_0280A0_NUMBER_SNORM ||
880 ntype == V_0280A0_NUMBER_SRGB)
881 blend_clamp = 1;
882
883 /* set blend bypass according to docs if SINT/UINT or
884 8/24 COLOR variants */
885 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
886 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
887 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
888 blend_clamp = 0;
889 blend_bypass = 1;
890 }
891
892 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
893
894 color_info |= S_0280A0_FORMAT(format) |
895 S_0280A0_COMP_SWAP(swap) |
896 S_0280A0_BLEND_BYPASS(blend_bypass) |
897 S_0280A0_BLEND_CLAMP(blend_clamp) |
898 S_0280A0_SIMPLE_FLOAT(1) |
899 S_0280A0_NUMBER_TYPE(ntype) |
900 S_0280A0_ENDIAN(endian);
901
902 /* EXPORT_NORM is an optimization that can be enabled for better
903 * performance in certain cases
904 */
905 if (rctx->b.gfx_level == R600) {
906 /* EXPORT_NORM can be enabled if:
907 * - 11-bit or smaller UNORM/SNORM/SRGB
908 * - BLEND_CLAMP is enabled
909 * - BLEND_FLOAT32 is disabled
910 */
911 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
912 (desc->channel[i].size < 12 &&
913 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
914 ntype != V_0280A0_NUMBER_UINT &&
915 ntype != V_0280A0_NUMBER_SINT) &&
916 G_0280A0_BLEND_CLAMP(color_info) &&
917 /* XXX this condition is always true since BLEND_FLOAT32 is never set (bug?). */
918 !G_0280A0_BLEND_FLOAT32(color_info)) {
919 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
920 surf->export_16bpc = true;
921 }
922 } else {
923 /* EXPORT_NORM can be enabled if:
924 * - 11-bit or smaller UNORM/SNORM/SRGB
925 * - 16-bit or smaller FLOAT
926 */
927 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
928 ((desc->channel[i].size < 12 &&
929 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
930 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
931 (desc->channel[i].size < 17 &&
932 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
933 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
934 surf->export_16bpc = true;
935 }
936 }
937
938 /* These might not always be initialized to zero. */
939 surf->cb_color_base = offset >> 8;
940 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
941 S_028060_SLICE_TILE_MAX(slice);
942 surf->cb_color_fmask = surf->cb_color_base;
943 surf->cb_color_cmask = surf->cb_color_base;
944 surf->cb_color_mask = 0;
945
946 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
947 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
948
949 if (rtex->cmask.size) {
950 surf->cb_color_cmask = rtex->cmask.offset >> 8;
951 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
952
953 if (rtex->fmask.size) {
954 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
955 surf->cb_color_fmask = rtex->fmask.offset >> 8;
956 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
957 } else { /* cmask only */
958 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
959 }
960 } else if (force_cmask_fmask) {
961 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
962 *
963 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
964 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
965 * because it's not an MSAA buffer.
966 */
967 struct r600_cmask_info cmask;
968 struct r600_fmask_info fmask;
969
970 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
971 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
972
973 /* CMASK. */
974 if (!rctx->dummy_cmask ||
975 rctx->dummy_cmask->b.b.width0 < cmask.size ||
976 (1 << rctx->dummy_cmask->buf->alignment_log2) % cmask.alignment != 0) {
977 struct pipe_transfer *transfer;
978 void *ptr;
979
980 r600_resource_reference(&rctx->dummy_cmask, NULL);
981 rctx->dummy_cmask = (struct r600_resource*)
982 r600_aligned_buffer_create(&rscreen->b.b, 0,
983 PIPE_USAGE_DEFAULT,
984 cmask.size, cmask.alignment);
985
986 if (unlikely(!rctx->dummy_cmask)) {
987 surf->color_initialized = false;
988 return;
989 }
990
991 /* Set the contents to 0xCC. */
992 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_MAP_WRITE, &transfer);
993 memset(ptr, 0xCC, cmask.size);
994 pipe_buffer_unmap(&rctx->b.b, transfer);
995 }
996 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
997
998 /* FMASK. */
999 if (!rctx->dummy_fmask ||
1000 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1001 (1 << rctx->dummy_fmask->buf->alignment_log2) % fmask.alignment != 0) {
1002 r600_resource_reference(&rctx->dummy_fmask, NULL);
1003 rctx->dummy_fmask = (struct r600_resource*)
1004 r600_aligned_buffer_create(&rscreen->b.b, 0,
1005 PIPE_USAGE_DEFAULT,
1006 fmask.size, fmask.alignment);
1007
1008 if (unlikely(!rctx->dummy_fmask)) {
1009 surf->color_initialized = false;
1010 return;
1011 }
1012 }
1013 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1014
1015 /* Init the registers. */
1016 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1017 surf->cb_color_cmask = 0;
1018 surf->cb_color_fmask = 0;
1019 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1020 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1021 }
1022
1023 surf->cb_color_info = color_info;
1024 surf->cb_color_view = color_view;
1025 surf->color_initialized = true;
1026 }
1027
r600_init_depth_surface(struct r600_context * rctx,struct r600_surface * surf)1028 static void r600_init_depth_surface(struct r600_context *rctx,
1029 struct r600_surface *surf)
1030 {
1031 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1032 unsigned level, pitch, slice, format, offset, array_mode;
1033
1034 level = surf->base.u.tex.level;
1035 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1036 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
1037 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1038 if (slice) {
1039 slice = slice - 1;
1040 }
1041 switch (rtex->surface.u.legacy.level[level].mode) {
1042 case RADEON_SURF_MODE_2D:
1043 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1044 break;
1045 case RADEON_SURF_MODE_1D:
1046 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1047 default:
1048 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1049 break;
1050 }
1051
1052 format = r600_translate_dbformat(surf->base.format);
1053 assert(format != ~0);
1054
1055 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1056 surf->db_depth_base = offset >> 8;
1057 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1058 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1059 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1060 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
1061
1062 if (r600_htile_enabled(rtex, level)) {
1063 surf->db_htile_data_base = rtex->htile_offset >> 8;
1064 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1065 S_028D24_HTILE_HEIGHT(1) |
1066 S_028D24_FULL_CACHE(1);
1067 /* preload is not working properly on r6xx/r7xx */
1068 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1069 }
1070
1071 surf->depth_initialized = true;
1072 }
1073
r600_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)1074 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1075 const struct pipe_framebuffer_state *state)
1076 {
1077 struct r600_context *rctx = (struct r600_context *)ctx;
1078 struct r600_surface *surf;
1079 struct r600_texture *rtex;
1080 unsigned i;
1081 uint32_t target_mask = 0;
1082
1083 /* Flush TC when changing the framebuffer state, because the only
1084 * client not using TC that can change textures is the framebuffer.
1085 * Other places don't typically have to flush TC.
1086 */
1087 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1088 R600_CONTEXT_FLUSH_AND_INV |
1089 R600_CONTEXT_FLUSH_AND_INV_CB |
1090 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1091 R600_CONTEXT_FLUSH_AND_INV_DB |
1092 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1093 R600_CONTEXT_INV_TEX_CACHE;
1094
1095 /* Set the new state. */
1096 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1097
1098 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1099 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1100 util_format_is_pure_integer(state->cbufs[0]->format);
1101 rctx->framebuffer.compressed_cb_mask = 0;
1102 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1103 state->cbufs[0] && state->cbufs[1] &&
1104 state->cbufs[0]->texture->nr_samples > 1 &&
1105 state->cbufs[1]->texture->nr_samples <= 1;
1106 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1107
1108 /* Colorbuffers. */
1109 for (i = 0; i < state->nr_cbufs; i++) {
1110 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1111 bool force_cmask_fmask = rctx->b.gfx_level == R600 &&
1112 rctx->framebuffer.is_msaa_resolve &&
1113 i == 1;
1114
1115 surf = (struct r600_surface*)state->cbufs[i];
1116 if (!surf)
1117 continue;
1118
1119 rtex = (struct r600_texture*)surf->base.texture;
1120 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1121
1122 target_mask |= (0xf << (i * 4));
1123
1124 if (!surf->color_initialized || force_cmask_fmask) {
1125 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1126 if (force_cmask_fmask) {
1127 /* re-initialize later without compression */
1128 surf->color_initialized = false;
1129 }
1130 }
1131
1132 if (!surf->export_16bpc) {
1133 rctx->framebuffer.export_16bpc = false;
1134 }
1135
1136 if (rtex->fmask.size) {
1137 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1138 }
1139 }
1140
1141 /* Update alpha-test state dependencies.
1142 * Alpha-test is done on the first colorbuffer only. */
1143 if (state->nr_cbufs) {
1144 bool alphatest_bypass = false;
1145
1146 surf = (struct r600_surface*)state->cbufs[0];
1147 if (surf) {
1148 alphatest_bypass = surf->alphatest_bypass;
1149 }
1150
1151 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1152 rctx->alphatest_state.bypass = alphatest_bypass;
1153 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1154 }
1155 }
1156
1157 /* ZS buffer. */
1158 if (state->zsbuf) {
1159 surf = (struct r600_surface*)state->zsbuf;
1160
1161 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1162
1163 if (!surf->depth_initialized) {
1164 r600_init_depth_surface(rctx, surf);
1165 }
1166
1167 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1168 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1169 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1170 }
1171
1172 if (rctx->db_state.rsurf != surf) {
1173 rctx->db_state.rsurf = surf;
1174 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1175 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1176 }
1177 } else if (rctx->db_state.rsurf) {
1178 rctx->db_state.rsurf = NULL;
1179 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1180 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1181 }
1182
1183 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1184 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1185 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1186 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1187 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1188 }
1189
1190 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1191 rctx->alphatest_state.bypass = false;
1192 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1193 }
1194
1195 /* Calculate the CS size. */
1196 rctx->framebuffer.atom.num_dw =
1197 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1198
1199 if (rctx->framebuffer.state.nr_cbufs) {
1200 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1201 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1202 }
1203 if (rctx->framebuffer.state.zsbuf) {
1204 rctx->framebuffer.atom.num_dw += 16;
1205 } else {
1206 rctx->framebuffer.atom.num_dw += 3;
1207 }
1208 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1209 rctx->framebuffer.atom.num_dw += 2;
1210 }
1211
1212 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1213
1214 r600_set_sample_locations_constant_buffer(rctx);
1215 rctx->framebuffer.do_update_surf_dirtiness = true;
1216 }
1217
1218 static const uint32_t sample_locs_2x[] = {
1219 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1220 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1221 };
1222 static const unsigned max_dist_2x = 4;
1223
1224 static const uint32_t sample_locs_4x[] = {
1225 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1226 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1227 };
1228 static const unsigned max_dist_4x = 6;
1229 static const uint32_t sample_locs_8x[] = {
1230 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1231 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1232 };
1233 static const unsigned max_dist_8x = 7;
1234
r600_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)1235 static void r600_get_sample_position(struct pipe_context *ctx,
1236 unsigned sample_count,
1237 unsigned sample_index,
1238 float *out_value)
1239 {
1240 int offset, index;
1241 struct {
1242 int idx:4;
1243 } val;
1244 switch (sample_count) {
1245 case 1:
1246 default:
1247 out_value[0] = out_value[1] = 0.5;
1248 break;
1249 case 2:
1250 offset = 4 * (sample_index * 2);
1251 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1252 out_value[0] = (float)(val.idx + 8) / 16.0f;
1253 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1254 out_value[1] = (float)(val.idx + 8) / 16.0f;
1255 break;
1256 case 4:
1257 offset = 4 * (sample_index * 2);
1258 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1259 out_value[0] = (float)(val.idx + 8) / 16.0f;
1260 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1261 out_value[1] = (float)(val.idx + 8) / 16.0f;
1262 break;
1263 case 8:
1264 offset = 4 * (sample_index % 4 * 2);
1265 index = (sample_index / 4);
1266 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1267 out_value[0] = (float)(val.idx + 8) / 16.0f;
1268 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1269 out_value[1] = (float)(val.idx + 8) / 16.0f;
1270 break;
1271 }
1272 }
1273
r600_emit_msaa_state(struct r600_context * rctx,int nr_samples)1274 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1275 {
1276 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1277 unsigned max_dist = 0;
1278
1279 if (rctx->b.family == CHIP_R600) {
1280 switch (nr_samples) {
1281 default:
1282 nr_samples = 0;
1283 break;
1284 case 2:
1285 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1286 max_dist = max_dist_2x;
1287 break;
1288 case 4:
1289 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1290 max_dist = max_dist_4x;
1291 break;
1292 case 8:
1293 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1294 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1295 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1296 max_dist = max_dist_8x;
1297 break;
1298 }
1299 } else {
1300 switch (nr_samples) {
1301 default:
1302 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1303 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1304 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1305 nr_samples = 0;
1306 break;
1307 case 2:
1308 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1309 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1310 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1311 max_dist = max_dist_2x;
1312 break;
1313 case 4:
1314 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1315 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1316 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1317 max_dist = max_dist_4x;
1318 break;
1319 case 8:
1320 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1321 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1322 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1323 max_dist = max_dist_8x;
1324 break;
1325 }
1326 }
1327
1328 if (nr_samples > 1) {
1329 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1330 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1331 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1332 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1333 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1334 } else {
1335 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1336 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1337 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1338 }
1339 }
1340
r600_emit_framebuffer_state(struct r600_context * rctx,struct r600_atom * atom)1341 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1342 {
1343 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1344 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1345 unsigned nr_cbufs = state->nr_cbufs;
1346 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1347 unsigned i, sbu = 0;
1348
1349 /* Colorbuffers. */
1350 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1351 for (i = 0; i < nr_cbufs; i++) {
1352 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1353 }
1354 /* set CB_COLOR1_INFO for possible dual-src blending */
1355 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) {
1356 radeon_emit(cs, cb[0]->cb_color_info);
1357 i++;
1358 }
1359 for (; i < 8; i++) {
1360 radeon_emit(cs, 0);
1361 }
1362
1363 if (nr_cbufs) {
1364 for (i = 0; i < nr_cbufs; i++) {
1365 unsigned reloc;
1366
1367 if (!cb[i])
1368 continue;
1369
1370 /* COLOR_BASE */
1371 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1372
1373 reloc = radeon_add_to_buffer_list(&rctx->b,
1374 &rctx->b.gfx,
1375 (struct r600_resource*)cb[i]->base.texture,
1376 RADEON_USAGE_READWRITE |
1377 (cb[i]->base.texture->nr_samples > 1 ?
1378 RADEON_PRIO_COLOR_BUFFER_MSAA :
1379 RADEON_PRIO_COLOR_BUFFER));
1380 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1381 radeon_emit(cs, reloc);
1382
1383 /* FMASK */
1384 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1385
1386 reloc = radeon_add_to_buffer_list(&rctx->b,
1387 &rctx->b.gfx,
1388 cb[i]->cb_buffer_fmask,
1389 RADEON_USAGE_READWRITE |
1390 (cb[i]->base.texture->nr_samples > 1 ?
1391 RADEON_PRIO_COLOR_BUFFER_MSAA :
1392 RADEON_PRIO_COLOR_BUFFER));
1393 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1394 radeon_emit(cs, reloc);
1395
1396 /* CMASK */
1397 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1398
1399 reloc = radeon_add_to_buffer_list(&rctx->b,
1400 &rctx->b.gfx,
1401 cb[i]->cb_buffer_cmask,
1402 RADEON_USAGE_READWRITE |
1403 (cb[i]->base.texture->nr_samples > 1 ?
1404 RADEON_PRIO_COLOR_BUFFER_MSAA :
1405 RADEON_PRIO_COLOR_BUFFER));
1406 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1407 radeon_emit(cs, reloc);
1408 }
1409
1410 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1411 for (i = 0; i < nr_cbufs; i++) {
1412 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1413 }
1414
1415 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1416 for (i = 0; i < nr_cbufs; i++) {
1417 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1418 }
1419
1420 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1421 for (i = 0; i < nr_cbufs; i++) {
1422 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1423 }
1424
1425 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1426 }
1427
1428 /* SURFACE_BASE_UPDATE */
1429 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1430 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1431 radeon_emit(cs, sbu);
1432 sbu = 0;
1433 }
1434
1435 /* Zbuffer. */
1436 if (state->zsbuf) {
1437 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1438 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1439 &rctx->b.gfx,
1440 (struct r600_resource*)state->zsbuf->texture,
1441 RADEON_USAGE_READWRITE |
1442 (surf->base.texture->nr_samples > 1 ?
1443 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1444 RADEON_PRIO_DEPTH_BUFFER));
1445
1446 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1447 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1448 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1449 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1450 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1451 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1452
1453 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1454 radeon_emit(cs, reloc);
1455
1456 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1457
1458 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1459 } else {
1460 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1461 }
1462
1463 /* SURFACE_BASE_UPDATE */
1464 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1465 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1466 radeon_emit(cs, sbu);
1467 sbu = 0;
1468 }
1469
1470 /* Framebuffer dimensions. */
1471 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1472 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1473 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1474 radeon_emit(cs, S_028244_BR_X(state->width) |
1475 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1476
1477 if (rctx->framebuffer.is_msaa_resolve) {
1478 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1479 } else {
1480 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1481 * will assure that the alpha-test will work even if there is
1482 * no colorbuffer bound. */
1483 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1484 (1ull << MAX2(nr_cbufs, 1)) - 1);
1485 }
1486
1487 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1488 }
1489
r600_set_min_samples(struct pipe_context * ctx,unsigned min_samples)1490 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1491 {
1492 struct r600_context *rctx = (struct r600_context *)ctx;
1493
1494 if (rctx->ps_iter_samples == min_samples)
1495 return;
1496
1497 rctx->ps_iter_samples = min_samples;
1498 if (rctx->framebuffer.nr_samples > 1) {
1499 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1500 if (rctx->b.gfx_level == R600)
1501 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1502 }
1503 }
1504
r600_emit_cb_misc_state(struct r600_context * rctx,struct r600_atom * atom)1505 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1506 {
1507 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1508 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1509
1510 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1511 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1512 if (rctx->b.gfx_level == R600) {
1513 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1514 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1515 } else {
1516 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1517 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1518 }
1519 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1520 } else {
1521 unsigned fb_colormask = a->bound_cbufs_target_mask;
1522 unsigned ps_colormask = a->ps_color_export_mask;
1523 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1524
1525 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1526 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1527 /* Always enable the first color output to make sure alpha-test works even without one. */
1528 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1529 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1530 a->cb_color_control |
1531 S_028808_MULTIWRITE_ENABLE(multiwrite));
1532 }
1533 }
1534
r600_emit_db_state(struct r600_context * rctx,struct r600_atom * atom)1535 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1536 {
1537 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1538 struct r600_db_state *a = (struct r600_db_state*)atom;
1539
1540 if (a->rsurf && a->rsurf->db_htile_surface) {
1541 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1542 unsigned reloc_idx;
1543
1544 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1545 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1546 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1547 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
1548 RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
1549 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1550 radeon_emit(cs, reloc_idx);
1551 } else {
1552 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1553 }
1554 }
1555
r600_emit_db_misc_state(struct r600_context * rctx,struct r600_atom * atom)1556 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1557 {
1558 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1559 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1560 unsigned db_render_control = 0;
1561 unsigned db_render_override =
1562 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1563 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1564
1565 if (rctx->b.gfx_level >= R700) {
1566 switch (a->ps_conservative_z) {
1567 default: /* fall through */
1568 case FRAG_DEPTH_LAYOUT_ANY:
1569 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1570 break;
1571 case FRAG_DEPTH_LAYOUT_GREATER:
1572 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1573 break;
1574 case FRAG_DEPTH_LAYOUT_LESS:
1575 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1576 break;
1577 }
1578 }
1579
1580 if (rctx->b.num_occlusion_queries > 0 &&
1581 !a->occlusion_queries_disabled) {
1582 if (rctx->b.gfx_level >= R700) {
1583 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1584 }
1585 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1586 } else {
1587 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1588 }
1589
1590 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1591 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1592 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1593 /* This is to fix a lockup when hyperz and alpha test are enabled at
1594 * the same time somehow GPU get confuse on which order to pick for
1595 * z test
1596 */
1597 if (rctx->alphatest_state.sx_alpha_test_control) {
1598 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1599 }
1600 } else {
1601 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1602 }
1603 if (rctx->b.gfx_level == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1604 /* sample shading and hyperz causes lockups on R6xx chips */
1605 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1606 }
1607 if (a->flush_depthstencil_through_cb) {
1608 assert(a->copy_depth || a->copy_stencil);
1609
1610 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1611 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1612 S_028D0C_COPY_CENTROID(1) |
1613 S_028D0C_COPY_SAMPLE(a->copy_sample);
1614
1615 if (rctx->b.gfx_level == R600)
1616 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1617
1618 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1619 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1620 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1621 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1622 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1623 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1624 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1625 }
1626 if (a->htile_clear) {
1627 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1628 }
1629
1630 /* RV770 workaround for a hang with 8x MSAA. */
1631 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1632 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1633 }
1634
1635 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1636 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1637 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1638 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1639 }
1640
r600_emit_config_state(struct r600_context * rctx,struct r600_atom * atom)1641 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1642 {
1643 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1644 struct r600_config_state *a = (struct r600_config_state*)atom;
1645
1646 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1647 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1648 }
1649
r600_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)1650 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1651 {
1652 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1653 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
1654 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask & shader->buffer_mask;
1655
1656 while (dirty_mask) {
1657 struct pipe_vertex_buffer *vb;
1658 struct r600_resource *rbuffer;
1659 unsigned offset;
1660 unsigned buffer_index = u_bit_scan(&dirty_mask);
1661 unsigned stride = shader->strides[buffer_index];
1662
1663 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1664 rbuffer = (struct r600_resource*)vb->buffer.resource;
1665 assert(rbuffer);
1666
1667 offset = vb->buffer_offset;
1668
1669 /* fetch resources start at index 320 (OFFSET_FS) */
1670 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1671 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1672 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1673 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1674 radeon_emit(cs, /* RESOURCEi_WORD2 */
1675 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1676 S_038008_STRIDE(stride));
1677 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1678 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1679 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1680 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1681
1682 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1683 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1684 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER));
1685 }
1686 }
1687
r600_emit_constant_buffers(struct r600_context * rctx,struct r600_constbuf_state * state,unsigned buffer_id_base,unsigned reg_alu_constbuf_size,unsigned reg_alu_const_cache)1688 static void r600_emit_constant_buffers(struct r600_context *rctx,
1689 struct r600_constbuf_state *state,
1690 unsigned buffer_id_base,
1691 unsigned reg_alu_constbuf_size,
1692 unsigned reg_alu_const_cache)
1693 {
1694 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1695 uint32_t dirty_mask = state->dirty_mask;
1696
1697 while (dirty_mask) {
1698 struct pipe_constant_buffer *cb;
1699 struct r600_resource *rbuffer;
1700 unsigned offset;
1701 unsigned buffer_index = ffs(dirty_mask) - 1;
1702 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1703 cb = &state->cb[buffer_index];
1704 rbuffer = (struct r600_resource*)cb->buffer;
1705 assert(rbuffer);
1706
1707 offset = cb->buffer_offset;
1708
1709 if (!gs_ring_buffer) {
1710 assert(buffer_index < R600_MAX_ALU_CONST_BUFFERS);
1711 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1712 DIV_ROUND_UP(cb->buffer_size, 256));
1713 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1714 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1715 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1716 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
1717 }
1718
1719 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1720 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1721 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1722 radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */
1723 radeon_emit(cs, /* RESOURCEi_WORD2 */
1724 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1725 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1726 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1727 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1728 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1729 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1730
1731 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1732 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1733 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
1734
1735 dirty_mask &= ~(1 << buffer_index);
1736 }
1737 state->dirty_mask = 0;
1738 }
1739
r600_emit_vs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1740 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1741 {
1742 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1743 R600_FETCH_CONSTANTS_OFFSET_VS,
1744 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1745 R_028980_ALU_CONST_CACHE_VS_0);
1746 }
1747
r600_emit_gs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1748 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1749 {
1750 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1751 R600_FETCH_CONSTANTS_OFFSET_GS,
1752 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1753 R_0289C0_ALU_CONST_CACHE_GS_0);
1754 }
1755
r600_emit_ps_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1756 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1757 {
1758 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1759 R600_FETCH_CONSTANTS_OFFSET_PS,
1760 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1761 R_028940_ALU_CONST_CACHE_PS_0);
1762 }
1763
r600_emit_sampler_views(struct r600_context * rctx,struct r600_samplerview_state * state,unsigned resource_id_base)1764 static void r600_emit_sampler_views(struct r600_context *rctx,
1765 struct r600_samplerview_state *state,
1766 unsigned resource_id_base)
1767 {
1768 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1769 uint32_t dirty_mask = state->dirty_mask;
1770
1771 while (dirty_mask) {
1772 struct r600_pipe_sampler_view *rview;
1773 unsigned resource_index = u_bit_scan(&dirty_mask);
1774 unsigned reloc;
1775
1776 rview = state->views[resource_index];
1777 assert(rview);
1778
1779 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1780 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1781 radeon_emit_array(cs, rview->tex_resource_words, 7);
1782
1783 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1784 RADEON_USAGE_READ |
1785 r600_get_sampler_view_priority(rview->tex_resource));
1786 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1787 radeon_emit(cs, reloc);
1788 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1789 radeon_emit(cs, reloc);
1790 }
1791 state->dirty_mask = 0;
1792 }
1793
1794
r600_emit_vs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1795 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1796 {
1797 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1798 }
1799
r600_emit_gs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1800 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1801 {
1802 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1803 }
1804
r600_emit_ps_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1805 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1806 {
1807 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1808 }
1809
r600_emit_sampler_states(struct r600_context * rctx,struct r600_textures_info * texinfo,unsigned resource_id_base,unsigned border_color_reg)1810 static void r600_emit_sampler_states(struct r600_context *rctx,
1811 struct r600_textures_info *texinfo,
1812 unsigned resource_id_base,
1813 unsigned border_color_reg)
1814 {
1815 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1816 uint32_t dirty_mask = texinfo->states.dirty_mask;
1817
1818 while (dirty_mask) {
1819 struct r600_pipe_sampler_state *rstate;
1820 struct r600_pipe_sampler_view *rview;
1821 unsigned i = u_bit_scan(&dirty_mask);
1822
1823 rstate = texinfo->states.states[i];
1824 assert(rstate);
1825 rview = texinfo->views.views[i];
1826
1827 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1828 * filtering between layers.
1829 */
1830 enum pipe_texture_target target = PIPE_BUFFER;
1831 if (rview)
1832 target = rview->base.texture->target;
1833
1834 /* If seamless cube map is set, set the CAMP_(X|Y|Z) to
1835 * SQ_TEX_WRAP which seems to trigger properly ignoring the
1836 * texture wrap mode */
1837 if (target == PIPE_TEXTURE_CUBE ||
1838 target == PIPE_TEXTURE_CUBE_ARRAY) {
1839 if (rstate->seamless_cube_map){
1840 uint32_t mask = ~(S_03C000_CLAMP_X(7) |
1841 S_03C000_CLAMP_Y(7) |
1842 S_03C000_CLAMP_Z(7));
1843 rstate->tex_sampler_words[0] &= mask;
1844 }
1845 }
1846
1847 if (target == PIPE_TEXTURE_1D_ARRAY ||
1848 target == PIPE_TEXTURE_2D_ARRAY) {
1849 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1850 texinfo->is_array_sampler[i] = true;
1851 } else {
1852 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1853 texinfo->is_array_sampler[i] = false;
1854 }
1855
1856 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1857 radeon_emit(cs, (resource_id_base + i) * 3);
1858 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1859
1860 if (rstate->border_color_use) {
1861 unsigned offset;
1862
1863 offset = border_color_reg;
1864 offset += i * 16;
1865 radeon_set_config_reg_seq(cs, offset, 4);
1866 radeon_emit_array(cs, rstate->border_color.ui, 4);
1867 }
1868 }
1869 texinfo->states.dirty_mask = 0;
1870 }
1871
r600_emit_vs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1872 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1873 {
1874 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1875 }
1876
r600_emit_gs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1877 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1878 {
1879 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1880 }
1881
r600_emit_ps_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1882 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1883 {
1884 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1885 }
1886
r600_emit_seamless_cube_map(struct r600_context * rctx,struct r600_atom * atom)1887 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1888 {
1889 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1890 unsigned tmp;
1891
1892 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1893 S_009508_SYNC_GRADIENT(1) |
1894 S_009508_SYNC_WALKER(1) |
1895 S_009508_SYNC_ALIGNER(1);
1896 if (!rctx->seamless_cube_map.enabled) {
1897 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1898 }
1899 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1900 }
1901
r600_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)1902 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1903 {
1904 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1905 uint8_t mask = s->sample_mask;
1906
1907 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1908 mask | (mask << 8) | (mask << 16) | (mask << 24));
1909 }
1910
r600_emit_vertex_fetch_shader(struct r600_context * rctx,struct r600_atom * a)1911 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1912 {
1913 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1914 struct r600_cso_state *state = (struct r600_cso_state*)a;
1915 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1916
1917 if (!shader)
1918 return;
1919
1920 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1921 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1922 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1923 RADEON_USAGE_READ |
1924 RADEON_PRIO_SHADER_BINARY));
1925 }
1926
r600_emit_shader_stages(struct r600_context * rctx,struct r600_atom * a)1927 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1928 {
1929 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1930 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1931
1932 uint32_t v2 = 0, primid = 0;
1933
1934 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1935 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1936 primid = 1;
1937 }
1938
1939 if (state->geom_enable) {
1940 uint32_t cut_val;
1941
1942 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1943 cut_val = V_028A40_GS_CUT_128;
1944 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1945 cut_val = V_028A40_GS_CUT_256;
1946 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1947 cut_val = V_028A40_GS_CUT_512;
1948 else
1949 cut_val = V_028A40_GS_CUT_1024;
1950
1951 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1952 S_028A40_CUT_MODE(cut_val);
1953
1954 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1955 primid = 1;
1956 }
1957
1958 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1959 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1960 }
1961
r600_emit_gs_rings(struct r600_context * rctx,struct r600_atom * a)1962 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1963 {
1964 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1965 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1966 struct r600_resource *rbuffer;
1967
1968 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1969 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1970 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1971
1972 if (state->enable) {
1973 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1974 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1975 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1976 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1977 RADEON_USAGE_READWRITE |
1978 RADEON_PRIO_SHADER_RINGS));
1979 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1980 state->esgs_ring.buffer_size >> 8);
1981
1982 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1983 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1984 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1985 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1986 RADEON_USAGE_READWRITE |
1987 RADEON_PRIO_SHADER_RINGS));
1988 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1989 state->gsvs_ring.buffer_size >> 8);
1990 } else {
1991 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1992 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1993 }
1994
1995 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1996 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1997 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1998 }
1999
2000 /* Adjust GPR allocation on R6xx/R7xx */
r600_adjust_gprs(struct r600_context * rctx)2001 bool r600_adjust_gprs(struct r600_context *rctx)
2002 {
2003 unsigned num_gprs[R600_NUM_HW_STAGES];
2004 unsigned new_gprs[R600_NUM_HW_STAGES];
2005 unsigned cur_gprs[R600_NUM_HW_STAGES];
2006 unsigned def_gprs[R600_NUM_HW_STAGES];
2007 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2008 unsigned max_gprs;
2009 unsigned tmp, tmp2;
2010 unsigned i;
2011 bool need_recalc = false, use_default = true;
2012
2013 /* hardware will reserve twice num_clause_temp_gprs */
2014 max_gprs = def_num_clause_temp_gprs * 2;
2015 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2016 def_gprs[i] = rctx->default_gprs[i];
2017 max_gprs += def_gprs[i];
2018 }
2019
2020 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2021 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2022 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2023 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2024
2025 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2026 if (rctx->gs_shader) {
2027 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2028 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2029 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2030 } else {
2031 num_gprs[R600_HW_STAGE_ES] = 0;
2032 num_gprs[R600_HW_STAGE_GS] = 0;
2033 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2034 }
2035
2036 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2037 new_gprs[i] = num_gprs[i];
2038 if (new_gprs[i] > cur_gprs[i])
2039 need_recalc = true;
2040 if (new_gprs[i] > def_gprs[i])
2041 use_default = false;
2042 }
2043
2044 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2045 if (!need_recalc)
2046 return true;
2047
2048 /* try to use switch back to default */
2049 if (!use_default) {
2050 /* always privilege vs stage so that at worst we have the
2051 * pixel stage producing wrong output (not the vertex
2052 * stage) */
2053 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2054 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2055 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2056 } else {
2057 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2058 new_gprs[i] = def_gprs[i];
2059 }
2060
2061 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2062 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2063 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2064 * it will lockup. So in this case just discard the draw command
2065 * and don't change the current gprs repartitions.
2066 */
2067 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2068 if (num_gprs[i] > new_gprs[i]) {
2069 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2070 "for a combined maximum of %d\n",
2071 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2072 return false;
2073 }
2074 }
2075
2076 /* in some case we endup recomputing the current value */
2077 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2078 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2079 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2080
2081 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2082 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2083 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2084 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2085 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2086 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2087 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2088 }
2089 return true;
2090 }
2091
r600_init_atom_start_cs(struct r600_context * rctx)2092 void r600_init_atom_start_cs(struct r600_context *rctx)
2093 {
2094 int ps_prio;
2095 int vs_prio;
2096 int gs_prio;
2097 int es_prio;
2098 int num_ps_gprs;
2099 int num_vs_gprs;
2100 int num_gs_gprs;
2101 int num_es_gprs;
2102 int num_temp_gprs;
2103 int num_ps_threads;
2104 int num_vs_threads;
2105 int num_gs_threads;
2106 int num_es_threads;
2107 int num_ps_stack_entries;
2108 int num_vs_stack_entries;
2109 int num_gs_stack_entries;
2110 int num_es_stack_entries;
2111 enum radeon_family family;
2112 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2113 uint32_t tmp, i;
2114
2115 r600_init_command_buffer(cb, 256);
2116
2117 /* R6xx requires this packet at the start of each command buffer */
2118 if (rctx->b.gfx_level == R600) {
2119 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2120 r600_store_value(cb, 0);
2121 }
2122 /* All asics require this one */
2123 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2124 r600_store_value(cb, 0x80000000);
2125 r600_store_value(cb, 0x80000000);
2126
2127 /* We're setting config registers here. */
2128 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2129 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2130
2131 /* This enables pipeline stat & streamout queries.
2132 * They are only disabled by blits.
2133 */
2134 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2135 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2136
2137 family = rctx->b.family;
2138 ps_prio = 0;
2139 vs_prio = 1;
2140 gs_prio = 2;
2141 es_prio = 3;
2142 switch (family) {
2143 case CHIP_R600:
2144 num_ps_gprs = 192;
2145 num_vs_gprs = 56;
2146 num_temp_gprs = 4;
2147 num_gs_gprs = 0;
2148 num_es_gprs = 0;
2149 num_ps_threads = 136;
2150 num_vs_threads = 48;
2151 num_gs_threads = 4;
2152 num_es_threads = 4;
2153 num_ps_stack_entries = 128;
2154 num_vs_stack_entries = 128;
2155 num_gs_stack_entries = 0;
2156 num_es_stack_entries = 0;
2157 break;
2158 case CHIP_RV630:
2159 case CHIP_RV635:
2160 num_ps_gprs = 84;
2161 num_vs_gprs = 36;
2162 num_temp_gprs = 4;
2163 num_gs_gprs = 0;
2164 num_es_gprs = 0;
2165 num_ps_threads = 144;
2166 num_vs_threads = 40;
2167 num_gs_threads = 4;
2168 num_es_threads = 4;
2169 num_ps_stack_entries = 40;
2170 num_vs_stack_entries = 40;
2171 num_gs_stack_entries = 32;
2172 num_es_stack_entries = 16;
2173 break;
2174 case CHIP_RV610:
2175 case CHIP_RV620:
2176 case CHIP_RS780:
2177 case CHIP_RS880:
2178 default:
2179 num_ps_gprs = 84;
2180 num_vs_gprs = 36;
2181 num_temp_gprs = 4;
2182 num_gs_gprs = 0;
2183 num_es_gprs = 0;
2184 /* use limits 40 VS and at least 16 ES/GS */
2185 num_ps_threads = 120;
2186 num_vs_threads = 40;
2187 num_gs_threads = 16;
2188 num_es_threads = 16;
2189 num_ps_stack_entries = 40;
2190 num_vs_stack_entries = 40;
2191 num_gs_stack_entries = 32;
2192 num_es_stack_entries = 16;
2193 break;
2194 case CHIP_RV670:
2195 num_ps_gprs = 144;
2196 num_vs_gprs = 40;
2197 num_temp_gprs = 4;
2198 num_gs_gprs = 0;
2199 num_es_gprs = 0;
2200 num_ps_threads = 136;
2201 num_vs_threads = 48;
2202 num_gs_threads = 4;
2203 num_es_threads = 4;
2204 num_ps_stack_entries = 40;
2205 num_vs_stack_entries = 40;
2206 num_gs_stack_entries = 32;
2207 num_es_stack_entries = 16;
2208 break;
2209 case CHIP_RV770:
2210 num_ps_gprs = 130;
2211 num_vs_gprs = 56;
2212 num_temp_gprs = 4;
2213 num_gs_gprs = 31;
2214 num_es_gprs = 31;
2215 num_ps_threads = 180;
2216 num_vs_threads = 60;
2217 num_gs_threads = 4;
2218 num_es_threads = 4;
2219 num_ps_stack_entries = 128;
2220 num_vs_stack_entries = 128;
2221 num_gs_stack_entries = 128;
2222 num_es_stack_entries = 128;
2223 break;
2224 case CHIP_RV730:
2225 case CHIP_RV740:
2226 num_ps_gprs = 84;
2227 num_vs_gprs = 36;
2228 num_temp_gprs = 4;
2229 num_gs_gprs = 0;
2230 num_es_gprs = 0;
2231 num_ps_threads = 180;
2232 num_vs_threads = 60;
2233 num_gs_threads = 4;
2234 num_es_threads = 4;
2235 num_ps_stack_entries = 128;
2236 num_vs_stack_entries = 128;
2237 num_gs_stack_entries = 0;
2238 num_es_stack_entries = 0;
2239 break;
2240 case CHIP_RV710:
2241 num_ps_gprs = 192;
2242 num_vs_gprs = 56;
2243 num_temp_gprs = 4;
2244 num_gs_gprs = 0;
2245 num_es_gprs = 0;
2246 num_ps_threads = 136;
2247 num_vs_threads = 48;
2248 num_gs_threads = 4;
2249 num_es_threads = 4;
2250 num_ps_stack_entries = 128;
2251 num_vs_stack_entries = 128;
2252 num_gs_stack_entries = 0;
2253 num_es_stack_entries = 0;
2254 break;
2255 }
2256
2257 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2258 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2259 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2260 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2261
2262 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2263
2264 /* SQ_CONFIG */
2265 tmp = 0;
2266 switch (family) {
2267 case CHIP_RV610:
2268 case CHIP_RV620:
2269 case CHIP_RS780:
2270 case CHIP_RS880:
2271 case CHIP_RV710:
2272 break;
2273 default:
2274 tmp |= S_008C00_VC_ENABLE(1);
2275 break;
2276 }
2277 tmp |= S_008C00_DX9_CONSTS(0);
2278 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2279 tmp |= S_008C00_PS_PRIO(ps_prio);
2280 tmp |= S_008C00_VS_PRIO(vs_prio);
2281 tmp |= S_008C00_GS_PRIO(gs_prio);
2282 tmp |= S_008C00_ES_PRIO(es_prio);
2283 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2284
2285 /* SQ_GPR_RESOURCE_MGMT_2 */
2286 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2287 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2288 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2289 r600_store_value(cb, tmp);
2290
2291 /* SQ_THREAD_RESOURCE_MGMT */
2292 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2293 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2294 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2295 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2296 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2297
2298 /* SQ_STACK_RESOURCE_MGMT_1 */
2299 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2300 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2301 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2302
2303 /* SQ_STACK_RESOURCE_MGMT_2 */
2304 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2305 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2306 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2307
2308 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2309
2310 if (rctx->b.gfx_level >= R700) {
2311 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2312 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2313 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2314 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2315 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2316 } else {
2317 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2318 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2319 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2320 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2321 }
2322 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2323 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2324 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2325 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2326 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2327 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2328 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2329 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2330 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2331 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2332
2333 /* to avoid GPU doing any preloading of constant from random address */
2334 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2335 for (i = 0; i < 16; i++)
2336 r600_store_value(cb, 0);
2337
2338 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2339 for (i = 0; i < 16; i++)
2340 r600_store_value(cb, 0);
2341
2342 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2343 for (i = 0; i < 16; i++)
2344 r600_store_value(cb, 0);
2345
2346 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2347 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2348 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2349 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2350 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2351 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2352 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2353 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2354 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2355 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2356 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2357 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2358 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2359 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2360
2361 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2362 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2363 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2364
2365 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2366 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2367 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2368
2369 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2370
2371 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2372
2373 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2374
2375 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2376 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2377 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2378 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2379
2380 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2381 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2382 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2383 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2384
2385 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2386 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2387
2388 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2389 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2390
2391 if (rctx->b.gfx_level >= R700) {
2392 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2393 }
2394
2395 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2396 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2397 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2398 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2399 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2400
2401 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2402 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2403 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2404
2405 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2406 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2407 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2408
2409 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2410 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2411 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2412 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2413 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2414 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2415
2416 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2417
2418 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2419 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2420 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2421
2422 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2423
2424 if (rctx->b.gfx_level == R700)
2425 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2426 if (rctx->b.gfx_level == R700 && rctx->screen->b.has_streamout)
2427 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2428
2429 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2430 if (rctx->screen->b.has_streamout) {
2431 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2432 }
2433
2434 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2435 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2436 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2437 }
2438
r600_update_ps_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2439 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2440 {
2441 struct r600_context *rctx = (struct r600_context *)ctx;
2442 struct r600_command_buffer *cb = &shader->command_buffer;
2443 struct r600_shader *rshader = &shader->shader;
2444 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2445 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2446 unsigned tmp, sid, ufi = 0;
2447 int need_linear = 0;
2448 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2449
2450 /* Pull any state we use out of rctx. Make sure that any additional
2451 * state added to this list is also checked in the caller in
2452 * r600_update_derived_state().
2453 */
2454 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2455 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0;
2456 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
2457
2458 if (!cb->buf) {
2459 r600_init_command_buffer(cb, 64);
2460 } else {
2461 cb->num_dw = 0;
2462 }
2463
2464 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2465 for (i = 0; i < rshader->ninput; i++) {
2466 const gl_varying_slot varying_slot = rshader->input[i].varying_slot;
2467
2468 if (varying_slot == VARYING_SLOT_POS)
2469 pos_index = i;
2470 else if (varying_slot == VARYING_SLOT_FACE) {
2471 if (face_index == -1)
2472 face_index = i;
2473 }
2474 else if (rshader->input[i].system_value == SYSTEM_VALUE_SAMPLE_ID)
2475 fixed_pt_position_index = i;
2476
2477 sid = rshader->input[i].spi_sid;
2478
2479 tmp = S_028644_SEMANTIC(sid);
2480
2481 /* D3D 9 behaviour. GL is undefined */
2482 if (varying_slot == VARYING_SLOT_COL0)
2483 tmp |= S_028644_DEFAULT_VAL(3);
2484
2485 if (varying_slot == VARYING_SLOT_POS ||
2486 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2487 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && flatshade))
2488 tmp |= S_028644_FLAT_SHADE(1);
2489
2490 if (varying_slot == VARYING_SLOT_PNTC ||
2491 (varying_slot >= VARYING_SLOT_TEX0 && varying_slot <= VARYING_SLOT_TEX7 &&
2492 (sprite_coord_enable & (1 << ((int)varying_slot - (int)VARYING_SLOT_TEX0))))) {
2493 tmp |= S_028644_PT_SPRITE_TEX(1);
2494 }
2495
2496 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2497 tmp |= S_028644_SEL_CENTROID(1);
2498
2499 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2500 tmp |= S_028644_SEL_SAMPLE(1);
2501
2502 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2503 need_linear = 1;
2504 tmp |= S_028644_SEL_LINEAR(1);
2505 }
2506
2507 r600_store_value(cb, tmp);
2508 }
2509
2510 db_shader_control = 0;
2511 exports_ps = 0;
2512 for (i = 0; i < rshader->noutput; i++) {
2513 switch (rshader->output[i].frag_result) {
2514 case FRAG_RESULT_DEPTH:
2515 z_export = 1;
2516 exports_ps |= 1;
2517 break;
2518 case FRAG_RESULT_STENCIL:
2519 stencil_export = 1;
2520 exports_ps |= 1;
2521 break;
2522 case FRAG_RESULT_SAMPLE_MASK:
2523 if (msaa)
2524 mask_export = 1;
2525 exports_ps |= 1;
2526 break;
2527 default:
2528 break;
2529 }
2530 }
2531 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2532 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2533 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2534 if (rshader->uses_kill)
2535 db_shader_control |= S_02880C_KILL_ENABLE(1);
2536
2537 num_cout = rshader->nr_ps_color_exports;
2538 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2539 if (!exports_ps) {
2540 /* always at least export 1 component per pixel */
2541 exports_ps = 2;
2542 }
2543
2544 shader->nr_ps_color_outputs = num_cout;
2545 shader->ps_color_export_mask = rshader->ps_color_export_mask;
2546
2547 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2548 S_0286CC_PERSP_GRADIENT_ENA(1)|
2549 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2550 spi_input_z = 0;
2551 if (pos_index != -1) {
2552 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2553 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2554 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2555 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2556 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2557 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2558 }
2559
2560 spi_ps_in_control_1 = 0;
2561 if (face_index != -1) {
2562 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2563 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2564 }
2565 if (fixed_pt_position_index != -1) {
2566 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2567 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2568 }
2569
2570 /* HW bug in original R600 */
2571 if (rctx->b.family == CHIP_R600)
2572 ufi = 1;
2573
2574 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2575 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2576 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2577
2578 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2579
2580 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2581 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2582 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2583 /*
2584 * docs are misleading about the dx10_clamp bit. This only affects
2585 * instructions using CLAMP dst modifier, in which case they will
2586 * return 0 with this set for a NaN (otherwise NaN).
2587 */
2588 S_028850_DX10_CLAMP(1) |
2589 S_028850_STACK_SIZE(rshader->bc.nstack) |
2590 S_028850_UNCACHED_FIRST_INST(ufi));
2591 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2592
2593 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2594 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2595
2596 /* only set some bits here, the other bits are set in the dsa state */
2597 shader->db_shader_control = db_shader_control;
2598 shader->ps_depth_export = z_export | stencil_export | mask_export;
2599
2600 shader->sprite_coord_enable = sprite_coord_enable;
2601 shader->flatshade = flatshade;
2602 shader->msaa = msaa;
2603 }
2604
r600_update_vs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2605 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2606 {
2607 struct r600_command_buffer *cb = &shader->command_buffer;
2608 struct r600_shader *rshader = &shader->shader;
2609 unsigned spi_vs_out_id[10] = {};
2610 unsigned i;
2611
2612 for (i = 0; i < rshader->noutput; i++) {
2613 const int param = rshader->output[i].export_param;
2614 if (param < 0)
2615 continue;
2616 unsigned *const param_spi_vs_out_id = &spi_vs_out_id[param / 4];
2617 const unsigned param_shift = (param & 3) * 8;
2618 assert(!(*param_spi_vs_out_id & (0xFFu << param_shift)));
2619 *param_spi_vs_out_id |= (unsigned)rshader->output[i].spi_sid << param_shift;
2620 }
2621
2622 r600_init_command_buffer(cb, 32);
2623
2624 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2625 for (i = 0; i < 10; i++) {
2626 r600_store_value(cb, spi_vs_out_id[i]);
2627 }
2628
2629 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2630 S_0286C4_VS_EXPORT_COUNT(rshader->highest_export_param));
2631 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2632 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2633 S_028868_DX10_CLAMP(1) |
2634 S_028868_STACK_SIZE(rshader->bc.nstack));
2635 if (rshader->vs_position_window_space) {
2636 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2637 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2638 } else {
2639 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2640 S_028818_VTX_W0_FMT(1) |
2641 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2642 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2643 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2644
2645 }
2646 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2647 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2648
2649 shader->pa_cl_vs_out_cntl =
2650 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2651 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2652 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2653 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2654 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2655 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2656 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2657 }
2658
2659 #define RV610_GSVS_ALIGN 32
2660 #define R600_GSVS_ALIGN 16
2661
r600_update_gs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2662 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2663 {
2664 struct r600_context *rctx = (struct r600_context *)ctx;
2665 struct r600_command_buffer *cb = &shader->command_buffer;
2666 struct r600_shader *rshader = &shader->shader;
2667 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2668 unsigned gsvs_itemsize =
2669 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2670
2671 /* some r600s needs gsvs itemsize aligned to cacheline size
2672 this was fixed in rs780 and above. */
2673 switch (rctx->b.family) {
2674 case CHIP_RV610:
2675 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2676 break;
2677 case CHIP_R600:
2678 case CHIP_RV630:
2679 case CHIP_RV670:
2680 case CHIP_RV620:
2681 case CHIP_RV635:
2682 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2683 break;
2684 default:
2685 break;
2686 }
2687
2688 r600_init_command_buffer(cb, 64);
2689
2690 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2691 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2692
2693 if (rctx->b.gfx_level >= R700) {
2694 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2695 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2696 }
2697 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2698 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2699
2700 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2701 cp_shader->ring_item_sizes[0] >> 2);
2702
2703 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2704 (rshader->ring_item_sizes[0]) >> 2);
2705
2706 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2707 gsvs_itemsize);
2708
2709 /* FIXME calculate these values somehow ??? */
2710 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2711 r600_store_value(cb, 0x80); /* GS_PER_ES */
2712 r600_store_value(cb, 0x100); /* ES_PER_GS */
2713 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2714 r600_store_value(cb, 0x2); /* GS_PER_VS */
2715
2716 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2717 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2718 S_02887C_DX10_CLAMP(1) |
2719 S_02887C_STACK_SIZE(rshader->bc.nstack));
2720 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2721 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2722 }
2723
r600_update_es_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2724 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2725 {
2726 struct r600_command_buffer *cb = &shader->command_buffer;
2727 struct r600_shader *rshader = &shader->shader;
2728
2729 r600_init_command_buffer(cb, 32);
2730
2731 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2732 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2733 S_028890_DX10_CLAMP(1) |
2734 S_028890_STACK_SIZE(rshader->bc.nstack));
2735 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2736 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2737 }
2738
2739
r600_create_resolve_blend(struct r600_context * rctx)2740 void *r600_create_resolve_blend(struct r600_context *rctx)
2741 {
2742 struct pipe_blend_state blend;
2743 unsigned i;
2744
2745 memset(&blend, 0, sizeof(blend));
2746 blend.independent_blend_enable = true;
2747 for (i = 0; i < 2; i++) {
2748 blend.rt[i].colormask = 0xf;
2749 blend.rt[i].blend_enable = 1;
2750 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2751 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2752 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2753 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2754 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2755 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2756 }
2757 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2758 }
2759
r700_create_resolve_blend(struct r600_context * rctx)2760 void *r700_create_resolve_blend(struct r600_context *rctx)
2761 {
2762 struct pipe_blend_state blend;
2763
2764 memset(&blend, 0, sizeof(blend));
2765 blend.independent_blend_enable = true;
2766 blend.rt[0].colormask = 0xf;
2767 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2768 }
2769
r600_create_decompress_blend(struct r600_context * rctx)2770 void *r600_create_decompress_blend(struct r600_context *rctx)
2771 {
2772 struct pipe_blend_state blend;
2773
2774 memset(&blend, 0, sizeof(blend));
2775 blend.independent_blend_enable = true;
2776 blend.rt[0].colormask = 0xf;
2777 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2778 }
2779
r600_create_db_flush_dsa(struct r600_context * rctx)2780 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2781 {
2782 struct pipe_depth_stencil_alpha_state dsa;
2783 bool quirk = false;
2784
2785 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2786 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2787 quirk = true;
2788
2789 memset(&dsa, 0, sizeof(dsa));
2790
2791 if (quirk) {
2792 dsa.depth_enabled = 1;
2793 dsa.depth_func = PIPE_FUNC_LEQUAL;
2794 dsa.stencil[0].enabled = 1;
2795 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2796 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2797 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2798 dsa.stencil[0].writemask = 0xff;
2799 }
2800
2801 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2802 }
2803
r600_update_db_shader_control(struct r600_context * rctx)2804 void r600_update_db_shader_control(struct r600_context * rctx)
2805 {
2806 bool dual_export;
2807 unsigned db_shader_control;
2808 uint8_t ps_conservative_z;
2809
2810 if (!rctx->ps_shader) {
2811 return;
2812 }
2813
2814 dual_export = rctx->framebuffer.export_16bpc &&
2815 !rctx->ps_shader->current->ps_depth_export;
2816
2817 db_shader_control = rctx->ps_shader->current->db_shader_control |
2818 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2819
2820 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2821
2822 /* When alpha test is enabled we can't trust the hw to make the proper
2823 * decision on the order in which ztest should be run related to fragment
2824 * shader execution.
2825 *
2826 * If alpha test is enabled perform z test after fragment. RE_Z (early
2827 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2828 */
2829 if (rctx->alphatest_state.sx_alpha_test_control) {
2830 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2831 } else {
2832 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2833 }
2834
2835 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2836 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2837 rctx->db_misc_state.db_shader_control = db_shader_control;
2838 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2839 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2840 }
2841 }
2842
r600_array_mode(unsigned mode)2843 static inline unsigned r600_array_mode(unsigned mode)
2844 {
2845 switch (mode) {
2846 default:
2847 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2848 break;
2849 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2850 break;
2851 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2852 }
2853 }
2854
r600_dma_copy_tile(struct r600_context * rctx,struct pipe_resource * dst,unsigned dst_level,unsigned dst_x,unsigned dst_y,unsigned dst_z,struct pipe_resource * src,unsigned src_level,unsigned src_x,unsigned src_y,unsigned src_z,unsigned copy_height,unsigned pitch,unsigned bpp)2855 static bool r600_dma_copy_tile(struct r600_context *rctx,
2856 struct pipe_resource *dst,
2857 unsigned dst_level,
2858 unsigned dst_x,
2859 unsigned dst_y,
2860 unsigned dst_z,
2861 struct pipe_resource *src,
2862 unsigned src_level,
2863 unsigned src_x,
2864 unsigned src_y,
2865 unsigned src_z,
2866 unsigned copy_height,
2867 unsigned pitch,
2868 unsigned bpp)
2869 {
2870 struct radeon_cmdbuf *cs = &rctx->b.dma.cs;
2871 struct r600_texture *rsrc = (struct r600_texture*)src;
2872 struct r600_texture *rdst = (struct r600_texture*)dst;
2873 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2874 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2875 uint64_t base, addr;
2876
2877 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2878 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2879 assert(dst_mode != src_mode);
2880
2881 y = 0;
2882 lbpp = util_logbase2(bpp);
2883 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2884
2885 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2886 /* T2L */
2887 array_mode = r600_array_mode(src_mode);
2888 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
2889 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2890 /* linear height must be the same as the slice tile max height, it's ok even
2891 * if the linear destination/source have smaller height as the size of the
2892 * dma packet will be using the copy_height which is always smaller or equal
2893 * to the linear height
2894 */
2895 height = u_minify(rsrc->resource.b.b.height0, src_level);
2896 detile = 1;
2897 x = src_x;
2898 y = src_y;
2899 z = src_z;
2900 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2901 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2902 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2903 addr += dst_y * pitch + dst_x * bpp;
2904 } else {
2905 /* L2T */
2906 array_mode = r600_array_mode(dst_mode);
2907 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2908 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2909 /* linear height must be the same as the slice tile max height, it's ok even
2910 * if the linear destination/source have smaller height as the size of the
2911 * dma packet will be using the copy_height which is always smaller or equal
2912 * to the linear height
2913 */
2914 height = u_minify(rdst->resource.b.b.height0, dst_level);
2915 detile = 0;
2916 x = dst_x;
2917 y = dst_y;
2918 z = dst_z;
2919 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2920 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2921 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
2922 addr += src_y * pitch + src_x * bpp;
2923 }
2924 /* check that we are in dw/base alignment constraint */
2925 if (addr % 4 || base % 256) {
2926 return false;
2927 }
2928
2929 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2930 * line in the blit. Compute max 8 line we can copy in the size limit
2931 */
2932 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2933 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2934 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2935
2936 for (i = 0; i < ncopy; i++) {
2937 cheight = cheight > copy_height ? copy_height : cheight;
2938 size = (cheight * pitch) / 4;
2939 /* emit reloc before writing cs so that cs is always in consistent state */
2940 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ);
2941 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE);
2942 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2943 radeon_emit(cs, base >> 8);
2944 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2945 (lbpp << 24) | ((height - 1) << 10) |
2946 pitch_tile_max);
2947 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2948 radeon_emit(cs, (x << 3) | (y << 17));
2949 radeon_emit(cs, addr & 0xfffffffc);
2950 radeon_emit(cs, (addr >> 32UL) & 0xff);
2951 copy_height -= cheight;
2952 addr += cheight * pitch;
2953 y += cheight;
2954 }
2955 return true;
2956 }
2957
r600_dma_copy(struct pipe_context * ctx,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)2958 static void r600_dma_copy(struct pipe_context *ctx,
2959 struct pipe_resource *dst,
2960 unsigned dst_level,
2961 unsigned dstx, unsigned dsty, unsigned dstz,
2962 struct pipe_resource *src,
2963 unsigned src_level,
2964 const struct pipe_box *src_box)
2965 {
2966 struct r600_context *rctx = (struct r600_context *)ctx;
2967 struct r600_texture *rsrc = (struct r600_texture*)src;
2968 struct r600_texture *rdst = (struct r600_texture*)dst;
2969 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2970 unsigned src_w, dst_w;
2971 unsigned src_x, src_y;
2972 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2973
2974 if (rctx->b.dma.cs.priv == NULL) {
2975 goto fallback;
2976 }
2977
2978 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2979 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2980 goto fallback;
2981
2982 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2983 return;
2984 }
2985
2986 if (src_box->depth > 1 ||
2987 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2988 dstz, rsrc, src_level, src_box))
2989 goto fallback;
2990
2991 src_x = util_format_get_nblocksx(src->format, src_box->x);
2992 dst_x = util_format_get_nblocksx(src->format, dst_x);
2993 src_y = util_format_get_nblocksy(src->format, src_box->y);
2994 dst_y = util_format_get_nblocksy(src->format, dst_y);
2995
2996 bpp = rdst->surface.bpe;
2997 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
2998 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
2999 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3000 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3001 copy_height = src_box->height / rsrc->surface.blk_h;
3002
3003 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3004 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3005
3006 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3007 /* strict requirement on r6xx/r7xx */
3008 goto fallback;
3009 }
3010 /* lot of constraint on alignment this should capture them all */
3011 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3012 goto fallback;
3013 }
3014
3015 if (src_mode == dst_mode) {
3016 uint64_t dst_offset, src_offset, size;
3017
3018 /* simple dma blit would do NOTE code here assume :
3019 * src_box.x/y == 0
3020 * dst_x/y == 0
3021 * dst_pitch == src_pitch
3022 */
3023 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3024 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3025 src_offset += src_y * src_pitch + src_x * bpp;
3026 dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3027 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3028 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3029 size = src_box->height * src_pitch;
3030 /* must be dw aligned */
3031 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3032 goto fallback;
3033 }
3034 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3035 } else {
3036 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3037 src, src_level, src_x, src_y, src_box->z,
3038 copy_height, dst_pitch, bpp)) {
3039 goto fallback;
3040 }
3041 }
3042 return;
3043
3044 fallback:
3045 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3046 src, src_level, src_box);
3047 }
3048
r600_init_state_functions(struct r600_context * rctx)3049 void r600_init_state_functions(struct r600_context *rctx)
3050 {
3051 unsigned id = 1;
3052 unsigned i;
3053 /* !!!
3054 * To avoid GPU lockup registers must be emitted in a specific order
3055 * (no kidding ...). The order below is important and have been
3056 * partially inferred from analyzing fglrx command stream.
3057 *
3058 * Don't reorder atom without carefully checking the effect (GPU lockup
3059 * or piglit regression).
3060 * !!!
3061 */
3062
3063 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3064
3065 /* shader const */
3066 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3067 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3068 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3069
3070 /* sampler must be emitted before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3071 * does not take effect (TA_CNTL_AUX emitted by r600_emit_seamless_cube_map)
3072 */
3073 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3074 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3075 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3076 /* resource */
3077 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3078 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3079 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3080 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3081
3082 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3083
3084 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3085 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3086 rctx->sample_mask.sample_mask = ~0;
3087
3088 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3089 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3090 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3091 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3092 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3093 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3094 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3095 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3096 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3097 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3098 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3099 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3100 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3101 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3102 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3103 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3104 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3105 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3106 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3107 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3108 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3109 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3110 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3111
3112 rctx->b.b.create_blend_state = r600_create_blend_state;
3113 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3114 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3115 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3116 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3117 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3118 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3119 rctx->b.b.set_min_samples = r600_set_min_samples;
3120 rctx->b.b.get_sample_position = r600_get_sample_position;
3121 rctx->b.dma_copy = r600_dma_copy;
3122 }
3123 /* this function must be last */
3124