1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 * Authors: Dave Airlie <[email protected]>
5 * Jerome Glisse <[email protected]>
6 * SPDX-License-Identifier: MIT
7 */
8
9 #include "r600_formats.h"
10 #include "r600_shader.h"
11 #include "r600d.h"
12
13 #include "util/format/u_format_s3tc.h"
14 #include "util/u_draw.h"
15 #include "util/u_endian.h"
16 #include "util/u_index_modify.h"
17 #include "util/u_memory.h"
18 #include "util/u_upload_mgr.h"
19 #include "util/u_math.h"
20 #include "tgsi/tgsi_parse.h"
21 #include "tgsi/tgsi_scan.h"
22 #include "tgsi/tgsi_ureg.h"
23
24 #include "nir.h"
25 #include "nir/nir_to_tgsi_info.h"
26
r600_init_command_buffer(struct r600_command_buffer * cb,unsigned num_dw)27 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
28 {
29 assert(!cb->buf);
30 cb->buf = CALLOC(1, 4 * num_dw);
31 cb->max_num_dw = num_dw;
32 }
33
r600_release_command_buffer(struct r600_command_buffer * cb)34 void r600_release_command_buffer(struct r600_command_buffer *cb)
35 {
36 FREE(cb->buf);
37 }
38
r600_add_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id)39 void r600_add_atom(struct r600_context *rctx,
40 struct r600_atom *atom,
41 unsigned id)
42 {
43 assert(id < R600_NUM_ATOMS);
44 assert(rctx->atoms[id] == NULL);
45 rctx->atoms[id] = atom;
46 atom->id = id;
47 }
48
r600_init_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id,void (* emit)(struct r600_context * ctx,struct r600_atom * state),unsigned num_dw)49 void r600_init_atom(struct r600_context *rctx,
50 struct r600_atom *atom,
51 unsigned id,
52 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
53 unsigned num_dw)
54 {
55 atom->emit = (void*)emit;
56 atom->num_dw = num_dw;
57 r600_add_atom(rctx, atom, id);
58 }
59
r600_emit_cso_state(struct r600_context * rctx,struct r600_atom * atom)60 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
61 {
62 r600_emit_command_buffer(&rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
63 }
64
r600_emit_alphatest_state(struct r600_context * rctx,struct r600_atom * atom)65 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
66 {
67 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
68 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
69 unsigned alpha_ref = a->sx_alpha_ref;
70
71 if (rctx->b.gfx_level >= EVERGREEN && a->cb0_export_16bpc) {
72 alpha_ref &= ~0x1FFF;
73 }
74
75 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
76 a->sx_alpha_test_control |
77 S_028410_ALPHA_TEST_BYPASS(a->bypass));
78 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
79 }
80
r600_memory_barrier(struct pipe_context * ctx,unsigned flags)81 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
82 {
83 struct r600_context *rctx = (struct r600_context *)ctx;
84
85 if (!(flags & ~PIPE_BARRIER_UPDATE))
86 return;
87
88 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
89 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
90
91 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
92 PIPE_BARRIER_SHADER_BUFFER |
93 PIPE_BARRIER_TEXTURE |
94 PIPE_BARRIER_IMAGE |
95 PIPE_BARRIER_STREAMOUT_BUFFER |
96 PIPE_BARRIER_GLOBAL_BUFFER)) {
97 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
98 R600_CONTEXT_INV_TEX_CACHE;
99 }
100
101 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
102 PIPE_BARRIER_IMAGE))
103 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
104
105 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
106 }
107
r600_texture_barrier(struct pipe_context * ctx,unsigned flags)108 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
109 {
110 struct r600_context *rctx = (struct r600_context *)ctx;
111
112 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
113 R600_CONTEXT_FLUSH_AND_INV_CB |
114 R600_CONTEXT_FLUSH_AND_INV |
115 R600_CONTEXT_WAIT_3D_IDLE;
116 rctx->framebuffer.do_update_surf_dirtiness = true;
117 }
118
r600_conv_pipe_prim(unsigned prim)119 static unsigned r600_conv_pipe_prim(unsigned prim)
120 {
121 static const unsigned prim_conv[] = {
122 [MESA_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
123 [MESA_PRIM_LINES] = V_008958_DI_PT_LINELIST,
124 [MESA_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
125 [MESA_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
126 [MESA_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
127 [MESA_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
128 [MESA_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
129 [MESA_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
130 [MESA_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
131 [MESA_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
132 [MESA_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
133 [MESA_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
134 [MESA_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
135 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
136 [MESA_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
137 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
138 };
139 assert(prim < ARRAY_SIZE(prim_conv));
140 return prim_conv[prim];
141 }
142
r600_conv_prim_to_gs_out(unsigned mode)143 unsigned r600_conv_prim_to_gs_out(unsigned mode)
144 {
145 static const int prim_conv[] = {
146 [MESA_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
147 [MESA_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
148 [MESA_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
149 [MESA_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
150 [MESA_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
151 [MESA_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
152 [MESA_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
153 [MESA_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
154 [MESA_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
155 [MESA_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
156 [MESA_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
157 [MESA_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
158 [MESA_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
159 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
160 [MESA_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
161 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
162 };
163 assert(mode < ARRAY_SIZE(prim_conv));
164
165 return prim_conv[mode];
166 }
167
168 /* common state between evergreen and r600 */
169
r600_bind_blend_state_internal(struct r600_context * rctx,struct r600_blend_state * blend,bool blend_disable)170 static void r600_bind_blend_state_internal(struct r600_context *rctx,
171 struct r600_blend_state *blend, bool blend_disable)
172 {
173 unsigned color_control;
174 bool update_cb = false;
175
176 rctx->alpha_to_one = blend->alpha_to_one;
177 rctx->dual_src_blend = blend->dual_src_blend;
178
179 if (!blend_disable) {
180 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
181 color_control = blend->cb_color_control;
182 } else {
183 /* Blending is disabled. */
184 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
185 color_control = blend->cb_color_control_no_blend;
186 }
187
188 /* Update derived states. */
189 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
190 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
191 update_cb = true;
192 }
193 if (rctx->b.gfx_level <= R700 &&
194 rctx->cb_misc_state.cb_color_control != color_control) {
195 rctx->cb_misc_state.cb_color_control = color_control;
196 update_cb = true;
197 }
198 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
199 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
200 update_cb = true;
201 }
202 if (update_cb) {
203 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
204 }
205 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
206 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
207 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
208 }
209 }
210
r600_bind_blend_state(struct pipe_context * ctx,void * state)211 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
212 {
213 struct r600_context *rctx = (struct r600_context *)ctx;
214 struct r600_blend_state *blend = (struct r600_blend_state *)state;
215
216 if (!blend) {
217 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
218 return;
219 }
220
221 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
222 }
223
r600_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)224 static void r600_set_blend_color(struct pipe_context *ctx,
225 const struct pipe_blend_color *state)
226 {
227 struct r600_context *rctx = (struct r600_context *)ctx;
228
229 rctx->blend_color.state = *state;
230 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
231 }
232
r600_emit_blend_color(struct r600_context * rctx,struct r600_atom * atom)233 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
234 {
235 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
236 struct pipe_blend_color *state = &rctx->blend_color.state;
237
238 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
239 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
240 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
241 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
242 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
243 }
244
r600_emit_vgt_state(struct r600_context * rctx,struct r600_atom * atom)245 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
246 {
247 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
248 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
249
250 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
251 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
252 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
253 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
254 if (a->last_draw_was_indirect) {
255 a->last_draw_was_indirect = false;
256 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
257 }
258 }
259
r600_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)260 static void r600_set_clip_state(struct pipe_context *ctx,
261 const struct pipe_clip_state *state)
262 {
263 struct r600_context *rctx = (struct r600_context *)ctx;
264
265 rctx->clip_state.state = *state;
266 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
267 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
268 rctx->driver_consts[PIPE_SHADER_GEOMETRY].vs_ucp_dirty = true;
269 if (rctx->b.family >= CHIP_CEDAR)
270 rctx->driver_consts[PIPE_SHADER_TESS_EVAL].vs_ucp_dirty = true;
271 }
272
r600_set_stencil_ref(struct pipe_context * ctx,const struct r600_stencil_ref state)273 static void r600_set_stencil_ref(struct pipe_context *ctx,
274 const struct r600_stencil_ref state)
275 {
276 struct r600_context *rctx = (struct r600_context *)ctx;
277
278 rctx->stencil_ref.state = state;
279 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
280 }
281
r600_emit_stencil_ref(struct r600_context * rctx,struct r600_atom * atom)282 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
283 {
284 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
285 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
286
287 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
288 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
289 S_028430_STENCILREF(a->state.ref_value[0]) |
290 S_028430_STENCILMASK(a->state.valuemask[0]) |
291 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
292 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
293 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
294 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
295 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
296 }
297
r600_set_pipe_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref state)298 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
299 const struct pipe_stencil_ref state)
300 {
301 struct r600_context *rctx = (struct r600_context *)ctx;
302 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
303 struct r600_stencil_ref ref;
304
305 rctx->stencil_ref.pipe_state = state;
306
307 if (!dsa)
308 return;
309
310 ref.ref_value[0] = state.ref_value[0];
311 ref.ref_value[1] = state.ref_value[1];
312 ref.valuemask[0] = dsa->valuemask[0];
313 ref.valuemask[1] = dsa->valuemask[1];
314 ref.writemask[0] = dsa->writemask[0];
315 ref.writemask[1] = dsa->writemask[1];
316
317 r600_set_stencil_ref(ctx, ref);
318 }
319
r600_bind_dsa_state(struct pipe_context * ctx,void * state)320 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
321 {
322 struct r600_context *rctx = (struct r600_context *)ctx;
323 struct r600_dsa_state *dsa = state;
324 struct r600_stencil_ref ref;
325
326 if (!state) {
327 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
328 return;
329 }
330
331 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
332
333 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
334 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
335 ref.valuemask[0] = dsa->valuemask[0];
336 ref.valuemask[1] = dsa->valuemask[1];
337 ref.writemask[0] = dsa->writemask[0];
338 ref.writemask[1] = dsa->writemask[1];
339 if (rctx->zwritemask != dsa->zwritemask) {
340 rctx->zwritemask = dsa->zwritemask;
341 if (rctx->b.gfx_level >= EVERGREEN) {
342 /* work around some issue when not writing to zbuffer
343 * we are having lockup on evergreen so do not enable
344 * hyperz when not writing zbuffer
345 */
346 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
347 }
348 }
349
350 r600_set_stencil_ref(ctx, ref);
351
352 /* Update alphatest state. */
353 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
354 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
355 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
356 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
357 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
358 }
359 }
360
r600_bind_rs_state(struct pipe_context * ctx,void * state)361 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
362 {
363 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
364 struct r600_context *rctx = (struct r600_context *)ctx;
365
366 if (!state)
367 return;
368
369 rctx->rasterizer = rs;
370
371 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
372
373 if (rs->offset_enable &&
374 (rs->offset_units != rctx->poly_offset_state.offset_units ||
375 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
376 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
377 rctx->poly_offset_state.offset_units = rs->offset_units;
378 rctx->poly_offset_state.offset_scale = rs->offset_scale;
379 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
380 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
381 }
382
383 /* Update clip_misc_state. */
384 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
385 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
386 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
387 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
388 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
389 }
390
391 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
392
393 /* Re-emit PA_SC_LINE_STIPPLE. */
394 rctx->last_primitive_type = -1;
395 }
396
r600_delete_rs_state(struct pipe_context * ctx,void * state)397 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
398 {
399 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
400
401 r600_release_command_buffer(&rs->buffer);
402 FREE(rs);
403 }
404
r600_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)405 static void r600_sampler_view_destroy(struct pipe_context *ctx,
406 struct pipe_sampler_view *state)
407 {
408 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
409
410 if (view->tex_resource->gpu_address &&
411 view->tex_resource->b.b.target == PIPE_BUFFER)
412 list_delinit(&view->list);
413
414 pipe_resource_reference(&state->texture, NULL);
415 FREE(view);
416 }
417
r600_sampler_states_dirty(struct r600_context * rctx,struct r600_sampler_states * state)418 void r600_sampler_states_dirty(struct r600_context *rctx,
419 struct r600_sampler_states *state)
420 {
421 if (state->dirty_mask) {
422 if (state->dirty_mask & state->has_bordercolor_mask) {
423 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
424 }
425 state->atom.num_dw =
426 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
427 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
428 r600_mark_atom_dirty(rctx, &state->atom);
429 }
430 }
431
r600_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,void ** states)432 static void r600_bind_sampler_states(struct pipe_context *pipe,
433 enum pipe_shader_type shader,
434 unsigned start,
435 unsigned count, void **states)
436 {
437 struct r600_context *rctx = (struct r600_context *)pipe;
438 struct r600_textures_info *dst = &rctx->samplers[shader];
439 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
440 int seamless_cube_map = -1;
441 unsigned i;
442 /* This sets 1-bit for states with index >= count. */
443 uint32_t disable_mask = ~((1ull << count) - 1);
444 /* These are the new states set by this function. */
445 uint32_t new_mask = 0;
446
447 assert(start == 0); /* XXX fix below */
448
449 if (!states) {
450 disable_mask = ~0u;
451 count = 0;
452 }
453
454 for (i = 0; i < count; i++) {
455 struct r600_pipe_sampler_state *rstate = rstates[i];
456
457 if (rstate == dst->states.states[i]) {
458 continue;
459 }
460
461 if (rstate) {
462 if (rstate->border_color_use) {
463 dst->states.has_bordercolor_mask |= 1 << i;
464 } else {
465 dst->states.has_bordercolor_mask &= ~(1 << i);
466 }
467 seamless_cube_map = rstate->seamless_cube_map;
468
469 new_mask |= 1 << i;
470 } else {
471 disable_mask |= 1 << i;
472 }
473 }
474
475 memcpy(dst->states.states, rstates, sizeof(void*) * count);
476 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
477
478 dst->states.enabled_mask &= ~disable_mask;
479 dst->states.dirty_mask &= dst->states.enabled_mask;
480 dst->states.enabled_mask |= new_mask;
481 dst->states.dirty_mask |= new_mask;
482 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
483
484 r600_sampler_states_dirty(rctx, &dst->states);
485
486 /* Seamless cubemap state. */
487 if (rctx->b.gfx_level <= R700 &&
488 seamless_cube_map != -1 &&
489 seamless_cube_map != rctx->seamless_cube_map.enabled) {
490 /* change in TA_CNTL_AUX need a pipeline flush */
491 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
492 rctx->seamless_cube_map.enabled = seamless_cube_map;
493 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
494 }
495 }
496
r600_delete_sampler_state(struct pipe_context * ctx,void * state)497 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
498 {
499 free(state);
500 }
501
r600_delete_blend_state(struct pipe_context * ctx,void * state)502 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
503 {
504 struct r600_context *rctx = (struct r600_context *)ctx;
505 struct r600_blend_state *blend = (struct r600_blend_state*)state;
506
507 if (rctx->blend_state.cso == state) {
508 ctx->bind_blend_state(ctx, NULL);
509 }
510
511 r600_release_command_buffer(&blend->buffer);
512 r600_release_command_buffer(&blend->buffer_no_blend);
513 FREE(blend);
514 }
515
r600_delete_dsa_state(struct pipe_context * ctx,void * state)516 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
520
521 if (rctx->dsa_state.cso == state) {
522 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
523 }
524
525 r600_release_command_buffer(&dsa->buffer);
526 free(dsa);
527 }
528
r600_delete_vertex_elements(struct pipe_context * ctx,void * state)529 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
530 {
531 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
532 if (shader)
533 r600_resource_reference(&shader->buffer, NULL);
534 FREE(shader);
535 }
536
r600_vertex_buffers_dirty(struct r600_context * rctx)537 void r600_vertex_buffers_dirty(struct r600_context *rctx)
538 {
539 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
540 if (shader && (rctx->vertex_buffer_state.dirty_mask & shader->buffer_mask)) {
541 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 12 : 11) *
542 util_bitcount(rctx->vertex_buffer_state.dirty_mask & shader->buffer_mask);
543 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
544 }
545 }
546
r600_bind_vertex_elements(struct pipe_context * ctx,void * state)547 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
548 {
549 struct r600_context *rctx = (struct r600_context *)ctx;
550 struct r600_fetch_shader *prev = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
551 struct r600_fetch_shader *cso = state;
552
553 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
554 if (!prev || (cso && cso->buffer_mask &&
555 (prev->buffer_mask != cso->buffer_mask || memcmp(cso->strides, prev->strides, util_last_bit(cso->buffer_mask))))) {
556 rctx->vertex_buffer_state.dirty_mask |= cso ? cso->buffer_mask : 0;
557 r600_vertex_buffers_dirty(rctx);
558 }
559 }
560
r600_set_vertex_buffers(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_buffer * input)561 static void r600_set_vertex_buffers(struct pipe_context *ctx,
562 unsigned count,
563 const struct pipe_vertex_buffer *input)
564 {
565 struct r600_context *rctx = (struct r600_context *)ctx;
566 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
567 struct pipe_vertex_buffer *vb = state->vb;
568 unsigned i;
569 uint32_t disable_mask = 0;
570 /* These are the new buffers set by this function. */
571 uint32_t new_buffer_mask = 0;
572
573 /* Set vertex buffers. */
574 for (i = 0; i < count; i++) {
575 if (likely((input[i].buffer.resource != vb[i].buffer.resource) ||
576 (vb[i].buffer_offset != input[i].buffer_offset) ||
577 (vb[i].is_user_buffer != input[i].is_user_buffer))) {
578 if (input[i].buffer.resource) {
579 vb[i].buffer_offset = input[i].buffer_offset;
580 pipe_resource_reference(&vb[i].buffer.resource, NULL);
581 vb[i].buffer.resource = input[i].buffer.resource;
582 new_buffer_mask |= 1 << i;
583 r600_context_add_resource_size(ctx, input[i].buffer.resource);
584 } else {
585 pipe_resource_reference(&vb[i].buffer.resource, NULL);
586 disable_mask |= 1 << i;
587 }
588 } else if (input[i].buffer.resource) {
589 pipe_resource_reference(&vb[i].buffer.resource, NULL);
590 vb[i].buffer.resource = input[i].buffer.resource;
591 }
592 }
593
594 unsigned last_count = util_last_bit(rctx->vertex_buffer_state.enabled_mask);
595 for (; i < last_count; i++)
596 pipe_resource_reference(&vb[i].buffer.resource, NULL);
597
598 if (last_count > count)
599 disable_mask |= BITFIELD_RANGE(count, last_count - count);
600
601 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
602 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
603 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
604 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
605
606 r600_vertex_buffers_dirty(rctx);
607 }
608
r600_sampler_views_dirty(struct r600_context * rctx,struct r600_samplerview_state * state)609 void r600_sampler_views_dirty(struct r600_context *rctx,
610 struct r600_samplerview_state *state)
611 {
612 if (state->dirty_mask) {
613 state->atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 14 : 13) *
614 util_bitcount(state->dirty_mask);
615 r600_mark_atom_dirty(rctx, &state->atom);
616 }
617 }
618
r600_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)619 static void r600_set_sampler_views(struct pipe_context *pipe,
620 enum pipe_shader_type shader,
621 unsigned start, unsigned count,
622 unsigned unbind_num_trailing_slots,
623 bool take_ownership,
624 struct pipe_sampler_view **views)
625 {
626 struct r600_context *rctx = (struct r600_context *) pipe;
627 struct r600_textures_info *dst = &rctx->samplers[shader];
628 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
629 uint32_t dirty_sampler_states_mask = 0;
630 unsigned i;
631 /* This sets 1-bit for textures with index >= count. */
632 uint32_t disable_mask = ~((1ull << count) - 1);
633 /* These are the new textures set by this function. */
634 uint32_t new_mask = 0;
635
636 /* Set textures with index >= count to NULL. */
637 uint32_t remaining_mask;
638
639 assert(start == 0); /* XXX fix below */
640
641 if (!views) {
642 disable_mask = ~0u;
643 count = 0;
644 }
645
646 remaining_mask = dst->views.enabled_mask & disable_mask;
647
648 while (remaining_mask) {
649 i = u_bit_scan(&remaining_mask);
650 assert(dst->views.views[i]);
651
652 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
653 }
654
655 for (i = 0; i < count; i++) {
656 if (rviews[i] == dst->views.views[i]) {
657 if (take_ownership) {
658 struct pipe_sampler_view *view = views[i];
659 pipe_sampler_view_reference(&view, NULL);
660 }
661 continue;
662 }
663
664 if (rviews[i]) {
665 struct r600_texture *rtex =
666 (struct r600_texture*)rviews[i]->base.texture;
667 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
668
669 if (!is_buffer && rtex->db_compatible) {
670 dst->views.compressed_depthtex_mask |= 1 << i;
671 } else {
672 dst->views.compressed_depthtex_mask &= ~(1 << i);
673 }
674
675 /* Track compressed colorbuffers. */
676 if (!is_buffer && rtex->cmask.size) {
677 dst->views.compressed_colortex_mask |= 1 << i;
678 } else {
679 dst->views.compressed_colortex_mask &= ~(1 << i);
680 }
681
682 /* Changing from array to non-arrays textures and vice versa requires
683 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
684 if (rctx->b.gfx_level <= R700 &&
685 (dst->states.enabled_mask & (1 << i)) &&
686 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
687 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
688 dirty_sampler_states_mask |= 1 << i;
689 }
690
691 if (take_ownership) {
692 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
693 dst->views.views[i] = (struct r600_pipe_sampler_view*)views[i];
694 } else {
695 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
696 }
697 new_mask |= 1 << i;
698 r600_context_add_resource_size(pipe, views[i]->texture);
699 } else {
700 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
701 disable_mask |= 1 << i;
702 }
703 }
704
705 dst->views.enabled_mask &= ~disable_mask;
706 dst->views.dirty_mask &= dst->views.enabled_mask;
707 dst->views.enabled_mask |= new_mask;
708 dst->views.dirty_mask |= new_mask;
709 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
710 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
711 dst->views.dirty_buffer_constants = true;
712 r600_sampler_views_dirty(rctx, &dst->views);
713
714 if (dirty_sampler_states_mask) {
715 dst->states.dirty_mask |= dirty_sampler_states_mask;
716 r600_sampler_states_dirty(rctx, &dst->states);
717 }
718 }
719
r600_update_compressed_colortex_mask(struct r600_samplerview_state * views)720 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
721 {
722 uint32_t mask = views->enabled_mask;
723
724 while (mask) {
725 unsigned i = u_bit_scan(&mask);
726 struct pipe_resource *res = views->views[i]->base.texture;
727
728 if (res && res->target != PIPE_BUFFER) {
729 struct r600_texture *rtex = (struct r600_texture *)res;
730
731 if (rtex->cmask.size) {
732 views->compressed_colortex_mask |= 1 << i;
733 } else {
734 views->compressed_colortex_mask &= ~(1 << i);
735 }
736 }
737 }
738 }
739
r600_get_hw_atomic_count(const struct pipe_context * ctx,enum pipe_shader_type shader)740 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
741 enum pipe_shader_type shader)
742 {
743 const struct r600_context *rctx = (struct r600_context *)ctx;
744 int value = 0;
745 switch (shader) {
746 case PIPE_SHADER_FRAGMENT:
747 case PIPE_SHADER_COMPUTE:
748 default:
749 break;
750 case PIPE_SHADER_VERTEX:
751 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
752 break;
753 case PIPE_SHADER_GEOMETRY:
754 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
755 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
756 break;
757 case PIPE_SHADER_TESS_EVAL:
758 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
759 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
760 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
761 break;
762 case PIPE_SHADER_TESS_CTRL:
763 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
764 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
765 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
766 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
767 break;
768 }
769 return value;
770 }
771
r600_update_compressed_colortex_mask_images(struct r600_image_state * images)772 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
773 {
774 uint32_t mask = images->enabled_mask;
775
776 while (mask) {
777 unsigned i = u_bit_scan(&mask);
778 struct pipe_resource *res = images->views[i].base.resource;
779
780 if (res && res->target != PIPE_BUFFER) {
781 struct r600_texture *rtex = (struct r600_texture *)res;
782
783 if (rtex->cmask.size) {
784 images->compressed_colortex_mask |= 1 << i;
785 } else {
786 images->compressed_colortex_mask &= ~(1 << i);
787 }
788 }
789 }
790 }
791
792 /* Compute the key for the hw shader variant */
r600_shader_selector_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)793 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
794 const struct r600_pipe_shader_selector *sel,
795 union r600_shader_key *key)
796 {
797 const struct r600_context *rctx = (struct r600_context *)ctx;
798 memset(key, 0, sizeof(*key));
799
800 switch (sel->type) {
801 case PIPE_SHADER_VERTEX: {
802 key->vs.as_ls = (rctx->tes_shader != NULL);
803 if (!key->vs.as_ls)
804 key->vs.as_es = (rctx->gs_shader != NULL);
805
806 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
807 key->vs.as_gs_a = true;
808 }
809 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
810 break;
811 }
812 case PIPE_SHADER_GEOMETRY:
813 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
814 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
815 break;
816 case PIPE_SHADER_FRAGMENT: {
817 if (rctx->ps_shader->info.images_declared)
818 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
819 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
820 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
821 key->ps.alpha_to_one = rctx->alpha_to_one &&
822 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
823 !rctx->framebuffer.cb0_is_integer;
824 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
825 key->ps.apply_sample_id_mask = (rctx->ps_iter_samples > 1) || !rctx->rasterizer->multisample_enable;
826 /* Dual-source blending only makes sense with nr_cbufs == 1. */
827 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend) {
828 key->ps.nr_cbufs = 2;
829 key->ps.dual_source_blend = 1;
830 }
831 break;
832 }
833 case PIPE_SHADER_TESS_EVAL:
834 key->tes.as_es = (rctx->gs_shader != NULL);
835 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
836 break;
837 case PIPE_SHADER_TESS_CTRL:
838 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
839 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
840 break;
841 case PIPE_SHADER_COMPUTE:
842 break;
843 default:
844 assert(0);
845 }
846 }
847
848 static void
r600_shader_precompile_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)849 r600_shader_precompile_key(const struct pipe_context *ctx,
850 const struct r600_pipe_shader_selector *sel,
851 union r600_shader_key *key)
852 {
853 memset(key, 0, sizeof(*key));
854
855 switch (sel->type) {
856 case PIPE_SHADER_VERTEX:
857 case PIPE_SHADER_TESS_EVAL:
858 /* Assume no tess or GS for setting .as_es. In order to
859 * precompile with es, we'd need the other shaders we're linked
860 * with (see the link_shader screen method)
861 */
862 break;
863
864 case PIPE_SHADER_GEOMETRY:
865 break;
866
867 case PIPE_SHADER_FRAGMENT:
868 key->ps.image_size_const_offset = sel->info.file_max[TGSI_FILE_IMAGE];
869
870 /* This is used for gl_FragColor output expansion to the number
871 * of color buffers bound, but also with sb it'll drop outputs
872 * to unused cbufs.
873 */
874 key->ps.nr_cbufs = sel->info.file_max[TGSI_FILE_OUTPUT] + 1;
875 break;
876
877 case PIPE_SHADER_TESS_CTRL:
878 /* Prim mode comes from the TES, but we need some valid value. */
879 key->tcs.prim_mode = MESA_PRIM_TRIANGLES;
880 break;
881
882 case PIPE_SHADER_COMPUTE:
883 break;
884
885 default:
886 unreachable("bad shader stage");
887 break;
888 }
889 }
890
891 /* Select the hw shader variant depending on the current state.
892 * (*dirty) is set to 1 if current variant was changed */
r600_shader_select(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel,bool * dirty,bool precompile)893 int r600_shader_select(struct pipe_context *ctx,
894 struct r600_pipe_shader_selector* sel,
895 bool *dirty, bool precompile)
896 {
897 union r600_shader_key key;
898 struct r600_pipe_shader * shader = NULL;
899 int r;
900
901 if (precompile)
902 r600_shader_precompile_key(ctx, sel, &key);
903 else
904 r600_shader_selector_key(ctx, sel, &key);
905
906 /* Check if we don't need to change anything.
907 * This path is also used for most shaders that don't need multiple
908 * variants, it will cost just a computation of the key and this
909 * test. */
910 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
911 return 0;
912 }
913
914 /* lookup if we have other variants in the list */
915 if (sel->num_shaders > 1) {
916 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
917
918 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
919 p = c;
920 c = c->next_variant;
921 }
922
923 if (c) {
924 p->next_variant = c->next_variant;
925 shader = c;
926 }
927 }
928
929 if (unlikely(!shader)) {
930 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
931 shader->selector = sel;
932
933 r = r600_pipe_shader_create(ctx, shader, key);
934 if (unlikely(r)) {
935 R600_ERR("Failed to build shader variant (type=%u) %d\n",
936 sel->type, r);
937 sel->current = NULL;
938 FREE(shader);
939 return r;
940 }
941
942 memcpy(&shader->key, &key, sizeof(key));
943 sel->num_shaders++;
944 }
945
946 if (dirty)
947 *dirty = true;
948
949 shader->next_variant = sel->current;
950 sel->current = shader;
951
952 return 0;
953 }
954
r600_create_shader_state_tokens(struct pipe_context * ctx,const void * prog,enum pipe_shader_ir ir,unsigned pipe_shader_type)955 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
956 const void *prog, enum pipe_shader_ir ir,
957 unsigned pipe_shader_type)
958 {
959 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
960
961 sel->type = pipe_shader_type;
962 if (ir == PIPE_SHADER_IR_TGSI) {
963 sel->tokens = tgsi_dup_tokens((const struct tgsi_token *)prog);
964 tgsi_scan_shader(sel->tokens, &sel->info);
965 } else if (ir == PIPE_SHADER_IR_NIR){
966 sel->nir = (nir_shader *)prog;
967 nir_tgsi_scan_shader(sel->nir, &sel->info, true);
968 }
969 sel->ir_type = ir;
970 return sel;
971 }
972
r600_create_shader_state(struct pipe_context * ctx,const struct pipe_shader_state * state,unsigned pipe_shader_type)973 static void *r600_create_shader_state(struct pipe_context *ctx,
974 const struct pipe_shader_state *state,
975 unsigned pipe_shader_type)
976 {
977 int i;
978 struct r600_pipe_shader_selector *sel;
979
980 if (state->type == PIPE_SHADER_IR_TGSI)
981 sel = r600_create_shader_state_tokens(ctx, state->tokens, state->type, pipe_shader_type);
982 else if (state->type == PIPE_SHADER_IR_NIR) {
983 sel = r600_create_shader_state_tokens(ctx, state->ir.nir, state->type, pipe_shader_type);
984 } else
985 unreachable("Unknown shader type");
986
987 sel->so = state->stream_output;
988
989 switch (pipe_shader_type) {
990 case PIPE_SHADER_GEOMETRY:
991 sel->gs_output_prim =
992 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
993 sel->gs_max_out_vertices =
994 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
995 sel->gs_num_invocations =
996 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
997 break;
998 case PIPE_SHADER_VERTEX:
999 case PIPE_SHADER_TESS_CTRL:
1000 sel->lds_patch_outputs_written_mask = 0;
1001 sel->lds_outputs_written_mask = 0;
1002
1003 for (i = 0; i < sel->info.num_outputs; i++) {
1004 unsigned name = sel->info.output_semantic_name[i];
1005 unsigned index = sel->info.output_semantic_index[i];
1006
1007 switch (name) {
1008 case TGSI_SEMANTIC_TESSINNER:
1009 case TGSI_SEMANTIC_TESSOUTER:
1010 case TGSI_SEMANTIC_PATCH:
1011 sel->lds_patch_outputs_written_mask |=
1012 1ull << r600_get_lds_unique_index(name, index);
1013 break;
1014 default:
1015 sel->lds_outputs_written_mask |=
1016 1ull << r600_get_lds_unique_index(name, index);
1017 }
1018 }
1019 break;
1020 default:
1021 break;
1022 }
1023
1024 /* Precompile the shader with the expected shader key, to reduce jank at
1025 * draw time. Also produces output for shader-db.
1026 */
1027 bool dirty;
1028 r600_shader_select(ctx, sel, &dirty, true);
1029
1030 return sel;
1031 }
1032
r600_create_ps_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1033 static void *r600_create_ps_state(struct pipe_context *ctx,
1034 const struct pipe_shader_state *state)
1035 {
1036 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1037 }
1038
r600_create_vs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1039 static void *r600_create_vs_state(struct pipe_context *ctx,
1040 const struct pipe_shader_state *state)
1041 {
1042 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1043 }
1044
r600_create_gs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1045 static void *r600_create_gs_state(struct pipe_context *ctx,
1046 const struct pipe_shader_state *state)
1047 {
1048 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
1049 }
1050
r600_create_tcs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1051 static void *r600_create_tcs_state(struct pipe_context *ctx,
1052 const struct pipe_shader_state *state)
1053 {
1054 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
1055 }
1056
r600_create_tes_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1057 static void *r600_create_tes_state(struct pipe_context *ctx,
1058 const struct pipe_shader_state *state)
1059 {
1060 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
1061 }
1062
r600_bind_ps_state(struct pipe_context * ctx,void * state)1063 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
1064 {
1065 struct r600_context *rctx = (struct r600_context *)ctx;
1066
1067 if (!state)
1068 state = rctx->dummy_pixel_shader;
1069
1070 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
1071 }
1072
r600_get_vs_info(struct r600_context * rctx)1073 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1074 {
1075 if (rctx->gs_shader)
1076 return &rctx->gs_shader->info;
1077 else if (rctx->tes_shader)
1078 return &rctx->tes_shader->info;
1079 else if (rctx->vs_shader)
1080 return &rctx->vs_shader->info;
1081 else
1082 return NULL;
1083 }
1084
r600_bind_vs_state(struct pipe_context * ctx,void * state)1085 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1086 {
1087 struct r600_context *rctx = (struct r600_context *)ctx;
1088
1089 if (!state || rctx->vs_shader == state)
1090 return;
1091
1092 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1093 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1094
1095 if (rctx->vs_shader->so.num_outputs)
1096 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1097 }
1098
r600_bind_gs_state(struct pipe_context * ctx,void * state)1099 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1100 {
1101 struct r600_context *rctx = (struct r600_context *)ctx;
1102
1103 if (state == rctx->gs_shader)
1104 return;
1105
1106 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1107 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1108
1109 if (!state)
1110 return;
1111
1112 if (rctx->gs_shader->so.num_outputs)
1113 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1114 }
1115
r600_bind_tcs_state(struct pipe_context * ctx,void * state)1116 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1117 {
1118 struct r600_context *rctx = (struct r600_context *)ctx;
1119
1120 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1121 }
1122
r600_bind_tes_state(struct pipe_context * ctx,void * state)1123 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1124 {
1125 struct r600_context *rctx = (struct r600_context *)ctx;
1126
1127 if (state == rctx->tes_shader)
1128 return;
1129
1130 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1131 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1132
1133 if (!state)
1134 return;
1135
1136 if (rctx->tes_shader->so.num_outputs)
1137 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1138 }
1139
r600_delete_shader_selector(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel)1140 void r600_delete_shader_selector(struct pipe_context *ctx,
1141 struct r600_pipe_shader_selector *sel)
1142 {
1143 struct r600_pipe_shader *p = sel->current, *c;
1144 while (p) {
1145 c = p->next_variant;
1146 if (p->gs_copy_shader) {
1147 r600_pipe_shader_destroy(ctx, p->gs_copy_shader);
1148 free(p->gs_copy_shader);
1149 }
1150 r600_pipe_shader_destroy(ctx, p);
1151 free(p);
1152 p = c;
1153 }
1154
1155 if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
1156 free(sel->tokens);
1157 /* We might have converted the TGSI shader to a NIR shader */
1158 if (sel->nir)
1159 ralloc_free(sel->nir);
1160 }
1161 else if (sel->ir_type == PIPE_SHADER_IR_NIR)
1162 ralloc_free(sel->nir);
1163 if (sel->nir_blob)
1164 free(sel->nir_blob);
1165 free(sel);
1166 }
1167
1168
r600_delete_ps_state(struct pipe_context * ctx,void * state)1169 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1170 {
1171 struct r600_context *rctx = (struct r600_context *)ctx;
1172 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1173
1174 if (rctx->ps_shader == sel) {
1175 rctx->ps_shader = NULL;
1176 }
1177
1178 r600_delete_shader_selector(ctx, sel);
1179 }
1180
r600_delete_vs_state(struct pipe_context * ctx,void * state)1181 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1182 {
1183 struct r600_context *rctx = (struct r600_context *)ctx;
1184 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1185
1186 if (rctx->vs_shader == sel) {
1187 rctx->vs_shader = NULL;
1188 }
1189
1190 r600_delete_shader_selector(ctx, sel);
1191 }
1192
1193
r600_delete_gs_state(struct pipe_context * ctx,void * state)1194 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1195 {
1196 struct r600_context *rctx = (struct r600_context *)ctx;
1197 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1198
1199 if (rctx->gs_shader == sel) {
1200 rctx->gs_shader = NULL;
1201 }
1202
1203 r600_delete_shader_selector(ctx, sel);
1204 }
1205
r600_delete_tcs_state(struct pipe_context * ctx,void * state)1206 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1207 {
1208 struct r600_context *rctx = (struct r600_context *)ctx;
1209 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1210
1211 if (rctx->tcs_shader == sel) {
1212 rctx->tcs_shader = NULL;
1213 }
1214
1215 r600_delete_shader_selector(ctx, sel);
1216 }
1217
r600_delete_tes_state(struct pipe_context * ctx,void * state)1218 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1219 {
1220 struct r600_context *rctx = (struct r600_context *)ctx;
1221 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1222
1223 if (rctx->tes_shader == sel) {
1224 rctx->tes_shader = NULL;
1225 }
1226
1227 r600_delete_shader_selector(ctx, sel);
1228 }
1229
r600_constant_buffers_dirty(struct r600_context * rctx,struct r600_constbuf_state * state)1230 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1231 {
1232 if (state->dirty_mask) {
1233 state->atom.num_dw = rctx->b.gfx_level >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1234 : util_bitcount(state->dirty_mask)*19;
1235 r600_mark_atom_dirty(rctx, &state->atom);
1236 }
1237 }
1238
r600_set_constant_buffer(struct pipe_context * ctx,enum pipe_shader_type shader,uint index,bool take_ownership,const struct pipe_constant_buffer * input)1239 static void r600_set_constant_buffer(struct pipe_context *ctx,
1240 enum pipe_shader_type shader, uint index,
1241 bool take_ownership,
1242 const struct pipe_constant_buffer *input)
1243 {
1244 struct r600_context *rctx = (struct r600_context *)ctx;
1245 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1246 struct pipe_constant_buffer *cb;
1247 const uint8_t *ptr;
1248
1249 /* Note that the gallium frontend can unbind constant buffers by
1250 * passing NULL here.
1251 */
1252 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1253 state->enabled_mask &= ~(1 << index);
1254 state->dirty_mask &= ~(1 << index);
1255 pipe_resource_reference(&state->cb[index].buffer, NULL);
1256 return;
1257 }
1258
1259 cb = &state->cb[index];
1260 cb->buffer_size = input->buffer_size;
1261
1262 ptr = input->user_buffer;
1263
1264 if (ptr) {
1265 /* Upload the user buffer. */
1266 if (UTIL_ARCH_BIG_ENDIAN) {
1267 uint32_t *tmpPtr;
1268 unsigned i, size = input->buffer_size;
1269
1270 if (!(tmpPtr = malloc(size))) {
1271 R600_ERR("Failed to allocate BE swap buffer.\n");
1272 return;
1273 }
1274
1275 for (i = 0; i < size / 4; ++i) {
1276 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1277 }
1278
1279 u_upload_data(ctx->stream_uploader, 0, size, 256,
1280 tmpPtr, &cb->buffer_offset, &cb->buffer);
1281 free(tmpPtr);
1282 } else {
1283 u_upload_data(ctx->stream_uploader, 0,
1284 input->buffer_size, 256, ptr,
1285 &cb->buffer_offset, &cb->buffer);
1286 }
1287 /* account it in gtt */
1288 rctx->b.gtt += input->buffer_size;
1289 } else {
1290 /* Setup the hw buffer. */
1291 cb->buffer_offset = input->buffer_offset;
1292 if (take_ownership) {
1293 pipe_resource_reference(&cb->buffer, NULL);
1294 cb->buffer = input->buffer;
1295 } else {
1296 pipe_resource_reference(&cb->buffer, input->buffer);
1297 }
1298 r600_context_add_resource_size(ctx, input->buffer);
1299 }
1300
1301 state->enabled_mask |= 1 << index;
1302 state->dirty_mask |= 1 << index;
1303 r600_constant_buffers_dirty(rctx, state);
1304 }
1305
r600_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)1306 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1307 {
1308 struct r600_context *rctx = (struct r600_context*)pipe;
1309
1310 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1311 return;
1312
1313 rctx->sample_mask.sample_mask = sample_mask;
1314 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1315 }
1316
r600_update_driver_const_buffers(struct r600_context * rctx,bool compute_only)1317 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only)
1318 {
1319 int sh, size;
1320 void *ptr;
1321 struct pipe_constant_buffer cb;
1322 int start, end;
1323
1324 start = compute_only ? PIPE_SHADER_COMPUTE : 0;
1325 end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
1326
1327 int last_vertex_stage = PIPE_SHADER_VERTEX;
1328 if (rctx->tes_shader)
1329 last_vertex_stage = PIPE_SHADER_TESS_EVAL;
1330 if (rctx->gs_shader)
1331 last_vertex_stage = PIPE_SHADER_GEOMETRY;
1332
1333 for (sh = start; sh < end; sh++) {
1334 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1335 if (!info->vs_ucp_dirty &&
1336 !info->texture_const_dirty &&
1337 !info->ps_sample_pos_dirty &&
1338 !info->tcs_default_levels_dirty &&
1339 !info->cs_block_grid_size_dirty)
1340 continue;
1341
1342 ptr = info->constants;
1343 size = info->alloc_size;
1344 if (info->vs_ucp_dirty) {
1345 assert(sh == PIPE_SHADER_VERTEX ||
1346 sh == PIPE_SHADER_GEOMETRY ||
1347 sh == PIPE_SHADER_TESS_EVAL);
1348 if (!size) {
1349 ptr = rctx->clip_state.state.ucp;
1350 size = R600_UCP_SIZE;
1351 } else {
1352 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1353 }
1354 info->vs_ucp_dirty = false;
1355 }
1356
1357 else if (info->ps_sample_pos_dirty) {
1358 assert(sh == PIPE_SHADER_FRAGMENT);
1359 if (!size) {
1360 ptr = rctx->sample_positions;
1361 size = R600_UCP_SIZE;
1362 } else {
1363 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1364 }
1365 info->ps_sample_pos_dirty = false;
1366 }
1367
1368 else if (info->cs_block_grid_size_dirty) {
1369 assert(sh == PIPE_SHADER_COMPUTE);
1370 if (!size) {
1371 ptr = rctx->cs_block_grid_sizes;
1372 size = R600_CS_BLOCK_GRID_SIZE;
1373 } else {
1374 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1375 }
1376 info->cs_block_grid_size_dirty = false;
1377 }
1378
1379 else if (info->tcs_default_levels_dirty) {
1380 /*
1381 * We'd only really need this for default tcs shader.
1382 */
1383 assert(sh == PIPE_SHADER_TESS_CTRL);
1384 if (!size) {
1385 ptr = rctx->tess_state;
1386 size = R600_TCS_DEFAULT_LEVELS_SIZE;
1387 } else {
1388 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1389 }
1390 info->tcs_default_levels_dirty = false;
1391 }
1392
1393 if (info->texture_const_dirty) {
1394 assert (ptr);
1395 assert (size);
1396 if (sh == last_vertex_stage)
1397 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1398 if (sh == PIPE_SHADER_FRAGMENT)
1399 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1400 if (sh == PIPE_SHADER_COMPUTE)
1401 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1402 if (sh == PIPE_SHADER_TESS_CTRL)
1403 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1404 }
1405 info->texture_const_dirty = false;
1406
1407 cb.buffer = NULL;
1408 cb.user_buffer = ptr;
1409 cb.buffer_offset = 0;
1410 cb.buffer_size = size;
1411 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, false, &cb);
1412 pipe_resource_reference(&cb.buffer, NULL);
1413 }
1414 }
1415
r600_alloc_buf_consts(struct r600_context * rctx,int shader_type,unsigned array_size,uint32_t * base_offset)1416 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1417 unsigned array_size, uint32_t *base_offset)
1418 {
1419 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1420 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1421 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1422 info->alloc_size = array_size + R600_UCP_SIZE;
1423 }
1424 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1425 info->texture_const_dirty = true;
1426 *base_offset = R600_UCP_SIZE;
1427 return info->constants;
1428 }
1429 /*
1430 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1431 * doesn't require full swizzles it does need masking and setting alpha
1432 * to one, so we setup a set of 5 constants with the masks + alpha value
1433 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1434 * then OR the alpha with the value given here.
1435 * We use a 6th constant to store the txq buffer size in
1436 * we use 7th slot for number of cube layers in a cube map array.
1437 */
r600_setup_buffer_constants(struct r600_context * rctx,int shader_type)1438 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1439 {
1440 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1441 int bits;
1442 uint32_t array_size;
1443 int i, j;
1444 uint32_t *constants;
1445 uint32_t base_offset;
1446 if (!samplers->views.dirty_buffer_constants)
1447 return;
1448
1449 samplers->views.dirty_buffer_constants = false;
1450
1451 bits = util_last_bit(samplers->views.enabled_mask);
1452 array_size = bits * 8 * sizeof(uint32_t);
1453
1454 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1455
1456 for (i = 0; i < bits; i++) {
1457 if (samplers->views.enabled_mask & (1 << i)) {
1458 int offset = (base_offset / 4) + i * 8;
1459 const struct util_format_description *desc;
1460 desc = util_format_description(samplers->views.views[i]->base.format);
1461
1462 for (j = 0; j < 4; j++)
1463 if (j < desc->nr_channels)
1464 constants[offset+j] = 0xffffffff;
1465 else
1466 constants[offset+j] = 0x0;
1467 if (desc->nr_channels < 4) {
1468 if (desc->channel[0].pure_integer)
1469 constants[offset+4] = 1;
1470 else
1471 constants[offset+4] = fui(1.0);
1472 } else
1473 constants[offset + 4] = 0;
1474
1475 constants[offset + 5] = samplers->views.views[i]->base.u.buf.size /
1476 util_format_get_blocksize(samplers->views.views[i]->base.format);
1477 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1478 }
1479 }
1480
1481 }
1482
1483 /* On evergreen we store one value
1484 * 1. number of cube layers in a cube map array.
1485 */
eg_setup_buffer_constants(struct r600_context * rctx,int shader_type)1486 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1487 {
1488 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1489 struct r600_image_state *images = NULL;
1490 int bits, sview_bits, img_bits;
1491 uint32_t array_size;
1492 int i;
1493 uint32_t *constants;
1494 uint32_t base_offset;
1495
1496 if (shader_type == PIPE_SHADER_FRAGMENT) {
1497 images = &rctx->fragment_images;
1498 } else if (shader_type == PIPE_SHADER_COMPUTE) {
1499 images = &rctx->compute_images;
1500 }
1501
1502 if (!samplers->views.dirty_buffer_constants &&
1503 !(images && images->dirty_buffer_constants))
1504 return;
1505
1506 if (images)
1507 images->dirty_buffer_constants = false;
1508 samplers->views.dirty_buffer_constants = false;
1509
1510 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1511 if (images)
1512 bits += util_last_bit(images->enabled_mask);
1513 img_bits = bits;
1514
1515 array_size = bits * sizeof(uint32_t);
1516
1517 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1518 &base_offset);
1519
1520 for (i = 0; i < sview_bits; i++) {
1521 if (samplers->views.enabled_mask & (1 << i)) {
1522 uint32_t offset = (base_offset / 4) + i;
1523 constants[offset] = samplers->views.views[i]->base.texture->array_size / 6;
1524 }
1525 }
1526 if (images) {
1527 for (i = sview_bits; i < img_bits; i++) {
1528 int idx = i - sview_bits;
1529 if (images->enabled_mask & (1 << idx)) {
1530 uint32_t offset = (base_offset / 4) + i;
1531 constants[offset] = images->views[idx].base.resource->array_size / 6;
1532 }
1533 }
1534 }
1535 }
1536
1537 /* set sample xy locations as array of fragment shader constants */
r600_set_sample_locations_constant_buffer(struct r600_context * rctx)1538 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1539 {
1540 struct pipe_context *ctx = &rctx->b.b;
1541
1542 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1543 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1544
1545 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1546 for (unsigned i = 0; i < rctx->framebuffer.nr_samples; i++) {
1547 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1548 /* Also fill in center-zeroed positions used for interpolateAtSample */
1549 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1550 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1551 }
1552
1553 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1554 }
1555
update_shader_atom(struct pipe_context * ctx,struct r600_shader_state * state,struct r600_pipe_shader * shader)1556 static void update_shader_atom(struct pipe_context *ctx,
1557 struct r600_shader_state *state,
1558 struct r600_pipe_shader *shader)
1559 {
1560 struct r600_context *rctx = (struct r600_context *)ctx;
1561
1562 state->shader = shader;
1563 if (shader) {
1564 state->atom.num_dw = shader->command_buffer.num_dw;
1565 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1566 } else {
1567 state->atom.num_dw = 0;
1568 }
1569 r600_mark_atom_dirty(rctx, &state->atom);
1570 }
1571
update_gs_block_state(struct r600_context * rctx,unsigned enable)1572 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1573 {
1574 if (rctx->shader_stages.geom_enable != enable) {
1575 rctx->shader_stages.geom_enable = enable;
1576 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1577 }
1578
1579 if (rctx->gs_rings.enable != enable) {
1580 rctx->gs_rings.enable = enable;
1581 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1582
1583 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1584 unsigned size = 0x1C000;
1585 rctx->gs_rings.esgs_ring.buffer =
1586 pipe_buffer_create(rctx->b.b.screen, 0,
1587 PIPE_USAGE_DEFAULT, size);
1588 rctx->gs_rings.esgs_ring.buffer_size = size;
1589
1590 size = 0x4000000;
1591
1592 rctx->gs_rings.gsvs_ring.buffer =
1593 pipe_buffer_create(rctx->b.b.screen, 0,
1594 PIPE_USAGE_DEFAULT, size);
1595 rctx->gs_rings.gsvs_ring.buffer_size = size;
1596 }
1597
1598 if (enable) {
1599 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1600 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.esgs_ring);
1601 if (rctx->tes_shader) {
1602 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1603 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.gsvs_ring);
1604 } else {
1605 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1606 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.gsvs_ring);
1607 }
1608 } else {
1609 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1610 R600_GS_RING_CONST_BUFFER, false, NULL);
1611 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1612 R600_GS_RING_CONST_BUFFER, false, NULL);
1613 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1614 R600_GS_RING_CONST_BUFFER, false, NULL);
1615 }
1616 }
1617 }
1618
r600_update_clip_state(struct r600_context * rctx,struct r600_pipe_shader * current)1619 static void r600_update_clip_state(struct r600_context *rctx,
1620 struct r600_pipe_shader *current)
1621 {
1622 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1623 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1624 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1625 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1626 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1627 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1628 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1629 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1630 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1631 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1632 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1633 }
1634 }
1635
r600_generate_fixed_func_tcs(struct r600_context * rctx)1636 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1637 {
1638 struct ureg_src const0, const1;
1639 struct ureg_dst tessouter, tessinner;
1640 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1641
1642 if (!ureg)
1643 return; /* if we get here, we're screwed */
1644
1645 assert(!rctx->fixed_func_tcs_shader);
1646
1647 ureg_DECL_constant2D(ureg, 0, 1, R600_BUFFER_INFO_CONST_BUFFER);
1648 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1649 R600_BUFFER_INFO_CONST_BUFFER);
1650 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1651 R600_BUFFER_INFO_CONST_BUFFER);
1652
1653 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1654 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1655
1656 ureg_MOV(ureg, tessouter, const0);
1657 ureg_MOV(ureg, tessinner, const1);
1658 ureg_END(ureg);
1659
1660 rctx->fixed_func_tcs_shader =
1661 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1662 }
1663
r600_update_compressed_resource_state(struct r600_context * rctx,bool compute_only)1664 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1665 {
1666 unsigned i;
1667 unsigned counter;
1668
1669 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1670 if (counter != rctx->b.last_compressed_colortex_counter) {
1671 rctx->b.last_compressed_colortex_counter = counter;
1672
1673 if (compute_only) {
1674 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1675 } else {
1676 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1677 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1678 }
1679 }
1680 if (!compute_only)
1681 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1682 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1683 }
1684
1685 /* Decompress textures if needed. */
1686 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1687 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1688
1689 if (compute_only)
1690 if (i != PIPE_SHADER_COMPUTE)
1691 continue;
1692 if (views->compressed_depthtex_mask) {
1693 r600_decompress_depth_textures(rctx, views);
1694 }
1695 if (views->compressed_colortex_mask) {
1696 r600_decompress_color_textures(rctx, views);
1697 }
1698 }
1699
1700 {
1701 struct r600_image_state *istate;
1702
1703 if (!compute_only) {
1704 istate = &rctx->fragment_images;
1705 if (istate->compressed_depthtex_mask)
1706 r600_decompress_depth_images(rctx, istate);
1707 if (istate->compressed_colortex_mask)
1708 r600_decompress_color_images(rctx, istate);
1709 }
1710
1711 istate = &rctx->compute_images;
1712 if (istate->compressed_depthtex_mask)
1713 r600_decompress_depth_images(rctx, istate);
1714 if (istate->compressed_colortex_mask)
1715 r600_decompress_color_images(rctx, istate);
1716 }
1717 }
1718
1719 /* update MEM_SCRATCH buffers if needed */
r600_setup_scratch_area_for_shader(struct r600_context * rctx,struct r600_pipe_shader * shader,struct r600_scratch_buffer * scratch,unsigned ring_base_reg,unsigned item_size_reg,unsigned ring_size_reg)1720 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
1721 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
1722 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg)
1723 {
1724 unsigned num_ses = rctx->screen->b.info.max_se;
1725 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
1726 unsigned nthreads = 128;
1727
1728 unsigned itemsize = shader->scratch_space_needed * 4;
1729 unsigned size = align(itemsize * nthreads * num_pipes * num_ses * 4, 256);
1730
1731 if (scratch->dirty ||
1732 unlikely(shader->scratch_space_needed != scratch->item_size ||
1733 size > scratch->size)) {
1734 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1735
1736 scratch->dirty = false;
1737
1738 if (size > scratch->size) {
1739 // Release prior one if any
1740 if (scratch->buffer) {
1741 pipe_resource_reference((struct pipe_resource**)&scratch->buffer, NULL);
1742 }
1743
1744 scratch->buffer = (struct r600_resource *)pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1745 PIPE_USAGE_DEFAULT, size);
1746 if (scratch->buffer) {
1747 scratch->size = size;
1748 }
1749 }
1750
1751 scratch->item_size = shader->scratch_space_needed;
1752
1753 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1755 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1756
1757 // multi-SE chips need programming per SE
1758 for (unsigned se = 0; se < num_ses; se++) {
1759 struct r600_resource *rbuffer = scratch->buffer;
1760 unsigned size_per_se = size / num_ses;
1761
1762 // Direct to particular SE
1763 if (num_ses > 1) {
1764 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1765 S_0802C_INSTANCE_INDEX(0) |
1766 S_0802C_SE_INDEX(se) |
1767 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1768 S_0802C_SE_BROADCAST_WRITES(0));
1769 }
1770
1771 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1772 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1773 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1774 RADEON_USAGE_READWRITE |
1775 RADEON_PRIO_SCRATCH_BUFFER));
1776 radeon_set_context_reg(cs, item_size_reg, itemsize);
1777 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1778 }
1779
1780 // Restore broadcast mode
1781 if (num_ses > 1) {
1782 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1783 S_0802C_INSTANCE_INDEX(0) |
1784 S_0802C_SE_INDEX(0) |
1785 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1786 S_0802C_SE_BROADCAST_WRITES(1));
1787 }
1788
1789 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1790 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1791 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1792 }
1793 }
1794
r600_setup_scratch_buffers(struct r600_context * rctx)1795 void r600_setup_scratch_buffers(struct r600_context *rctx) {
1796 static const struct {
1797 unsigned ring_base;
1798 unsigned item_size;
1799 unsigned ring_size;
1800 } regs[R600_NUM_HW_STAGES] = {
1801 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
1802 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
1803 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
1804 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE }
1805 };
1806
1807 for (unsigned i = 0; i < R600_NUM_HW_STAGES; i++) {
1808 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
1809
1810 if (stage && unlikely(stage->scratch_space_needed)) {
1811 r600_setup_scratch_area_for_shader(rctx, stage,
1812 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
1813 }
1814 }
1815 }
1816
1817 #define SELECT_SHADER_OR_FAIL(x) do { \
1818 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty, false); \
1819 if (unlikely(!rctx->x##_shader->current)) \
1820 return false; \
1821 } while(0)
1822
1823 #define UPDATE_SHADER(hw, sw) do { \
1824 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1825 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1826 } while(0)
1827
1828 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1829 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1830 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1831 clip_so_current = rctx->sw##_shader->current; \
1832 } \
1833 } while(0)
1834
1835 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1836 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1837 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1838 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1839 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1840 } \
1841 } while(0)
1842
1843 #define SET_NULL_SHADER(hw) do { \
1844 if (rctx->hw_shader_stages[(hw)].shader) \
1845 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1846 } while (0)
1847
r600_update_derived_state(struct r600_context * rctx)1848 static bool r600_update_derived_state(struct r600_context *rctx)
1849 {
1850 struct pipe_context * ctx = (struct pipe_context*)rctx;
1851 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1852 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1853 bool blend_disable;
1854 bool need_buf_const;
1855 struct r600_pipe_shader *clip_so_current = NULL;
1856
1857 if (!rctx->blitter->running)
1858 r600_update_compressed_resource_state(rctx, false);
1859
1860 SELECT_SHADER_OR_FAIL(ps);
1861
1862 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1863
1864 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1865
1866 if (rctx->gs_shader)
1867 SELECT_SHADER_OR_FAIL(gs);
1868
1869 /* Hull Shader */
1870 if (rctx->tcs_shader) {
1871 SELECT_SHADER_OR_FAIL(tcs);
1872
1873 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1874 } else if (rctx->tes_shader) {
1875 if (!rctx->fixed_func_tcs_shader) {
1876 r600_generate_fixed_func_tcs(rctx);
1877 if (!rctx->fixed_func_tcs_shader)
1878 return false;
1879
1880 }
1881 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1882
1883 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1884 } else
1885 SET_NULL_SHADER(EG_HW_STAGE_HS);
1886
1887 if (rctx->tes_shader) {
1888 SELECT_SHADER_OR_FAIL(tes);
1889 }
1890
1891 SELECT_SHADER_OR_FAIL(vs);
1892
1893 if (rctx->gs_shader) {
1894 if (!rctx->shader_stages.geom_enable) {
1895 rctx->shader_stages.geom_enable = true;
1896 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1897 }
1898
1899 /* gs_shader provides GS and VS (copy shader) */
1900 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1901
1902 /* vs_shader is used as ES */
1903
1904 if (rctx->tes_shader) {
1905 /* VS goes to LS, TES goes to ES */
1906 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1907 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1908 } else {
1909 /* vs_shader is used as ES */
1910 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1911 SET_NULL_SHADER(EG_HW_STAGE_LS);
1912 }
1913 } else {
1914 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1915 SET_NULL_SHADER(R600_HW_STAGE_GS);
1916 SET_NULL_SHADER(R600_HW_STAGE_ES);
1917 rctx->shader_stages.geom_enable = false;
1918 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1919 }
1920
1921 if (rctx->tes_shader) {
1922 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1923 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1924 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1925 } else {
1926 SET_NULL_SHADER(EG_HW_STAGE_LS);
1927 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1928 }
1929 }
1930
1931 /*
1932 * XXX: I believe there's some fatal flaw in the dirty state logic when
1933 * enabling/disabling tes.
1934 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1935 * it will therefore overwrite the VS slots. If it now gets disabled,
1936 * the VS needs to rebind all buffer/resource/sampler slots - not only
1937 * has TES overwritten the corresponding slots, but when the VS was
1938 * operating as LS the things with corresponding dirty bits got bound
1939 * to LS slots and won't reflect what is dirty as VS stage even if the
1940 * TES didn't overwrite it. The story for re-enabled TES is similar.
1941 * In any case, we're not allowed to submit any TES state when
1942 * TES is disabled (the gallium frontend may not do this but this looks
1943 * like an optimization to me, not something which can be relied on).
1944 */
1945
1946 /* Update clip misc state. */
1947 if (clip_so_current) {
1948 r600_update_clip_state(rctx, clip_so_current);
1949 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1950 }
1951
1952 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1953 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1954 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1955
1956 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
1957 if (unlikely(rctx->ps_shader &&
1958 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1959 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade) ||
1960 (msaa != rctx->ps_shader->current->msaa)))) {
1961
1962 if (rctx->b.gfx_level >= EVERGREEN)
1963 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1964 else
1965 r600_update_ps_state(ctx, rctx->ps_shader->current);
1966 }
1967
1968 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs ||
1969 rctx->cb_misc_state.ps_color_export_mask != rctx->ps_shader->current->ps_color_export_mask) {
1970 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1971 rctx->cb_misc_state.ps_color_export_mask = rctx->ps_shader->current->ps_color_export_mask;
1972 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1973 }
1974
1975 if (rctx->b.gfx_level <= R700) {
1976 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1977
1978 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1979 rctx->cb_misc_state.multiwrite = multiwrite;
1980 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1981 }
1982 }
1983
1984 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1985 }
1986 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1987
1988 if (rctx->b.gfx_level >= EVERGREEN) {
1989 evergreen_update_db_shader_control(rctx);
1990 } else {
1991 r600_update_db_shader_control(rctx);
1992 }
1993
1994 /* on R600 we stuff masks + txq info into one constant buffer */
1995 /* on evergreen we only need a txq info one */
1996 if (rctx->ps_shader) {
1997 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1998 if (need_buf_const) {
1999 if (rctx->b.gfx_level < EVERGREEN)
2000 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
2001 else
2002 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
2003 }
2004 }
2005
2006 if (rctx->vs_shader) {
2007 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
2008 if (need_buf_const) {
2009 if (rctx->b.gfx_level < EVERGREEN)
2010 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
2011 else
2012 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
2013 }
2014 }
2015
2016 if (rctx->gs_shader) {
2017 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
2018 if (need_buf_const) {
2019 if (rctx->b.gfx_level < EVERGREEN)
2020 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
2021 else
2022 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
2023 }
2024 }
2025
2026 if (rctx->tes_shader) {
2027 assert(rctx->b.gfx_level >= EVERGREEN);
2028 need_buf_const = rctx->tes_shader->current->shader.uses_tex_buffers ||
2029 rctx->tes_shader->current->shader.has_txq_cube_array_z_comp;
2030 if (need_buf_const) {
2031 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_EVAL);
2032 }
2033 if (rctx->tcs_shader) {
2034 need_buf_const = rctx->tcs_shader->current->shader.uses_tex_buffers ||
2035 rctx->tcs_shader->current->shader.has_txq_cube_array_z_comp;
2036 if (need_buf_const) {
2037 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_CTRL);
2038 }
2039 }
2040 }
2041
2042 r600_update_driver_const_buffers(rctx, false);
2043
2044 if (rctx->b.gfx_level < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
2045 if (!r600_adjust_gprs(rctx)) {
2046 /* discard rendering */
2047 return false;
2048 }
2049 }
2050
2051 if (rctx->b.gfx_level == EVERGREEN) {
2052 if (!evergreen_adjust_gprs(rctx)) {
2053 /* discard rendering */
2054 return false;
2055 }
2056 }
2057
2058 blend_disable = (rctx->dual_src_blend &&
2059 rctx->ps_shader->current->nr_ps_color_outputs < 2);
2060
2061 if (blend_disable != rctx->force_blend_disable) {
2062 rctx->force_blend_disable = blend_disable;
2063 r600_bind_blend_state_internal(rctx,
2064 rctx->blend_state.cso,
2065 blend_disable);
2066 }
2067
2068 return true;
2069 }
2070
r600_emit_clip_misc_state(struct r600_context * rctx,struct r600_atom * atom)2071 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2072 {
2073 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2074 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
2075
2076 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2077 state->pa_cl_clip_cntl |
2078 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
2079 S_028810_CLIP_DISABLE(state->clip_disable));
2080 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2081 state->pa_cl_vs_out_cntl |
2082 (state->clip_plane_enable & state->clip_dist_write) |
2083 (state->cull_dist_write << 8));
2084 /* reuse needs to be set off if we write oViewport */
2085 if (rctx->b.gfx_level >= EVERGREEN)
2086 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2087 S_028AB4_REUSE_OFF(state->vs_out_viewport));
2088 }
2089
2090 /* rast_prim is the primitive type after GS. */
r600_emit_rasterizer_prim_state(struct r600_context * rctx)2091 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
2092 {
2093 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2094 enum mesa_prim rast_prim = rctx->current_rast_prim;
2095
2096 /* Skip this if not rendering lines. */
2097 if (rast_prim != MESA_PRIM_LINES &&
2098 rast_prim != MESA_PRIM_LINE_LOOP &&
2099 rast_prim != MESA_PRIM_LINE_STRIP &&
2100 rast_prim != MESA_PRIM_LINES_ADJACENCY &&
2101 rast_prim != MESA_PRIM_LINE_STRIP_ADJACENCY)
2102 return;
2103
2104 if (rast_prim == rctx->last_rast_prim)
2105 return;
2106
2107 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2108 * reset the stipple pattern at each packet (line strips, line loops).
2109 */
2110 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
2111 S_028A0C_AUTO_RESET_CNTL(rast_prim == MESA_PRIM_LINES ? 1 : 2) |
2112 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
2113 rctx->last_rast_prim = rast_prim;
2114 }
2115
r600_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2116 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
2117 unsigned drawid_offset,
2118 const struct pipe_draw_indirect_info *indirect,
2119 const struct pipe_draw_start_count_bias *draws,
2120 unsigned num_draws)
2121 {
2122 if (num_draws > 1) {
2123 util_draw_multi(ctx, info, drawid_offset, indirect, draws, num_draws);
2124 return;
2125 }
2126
2127 struct r600_context *rctx = (struct r600_context *)ctx;
2128 struct pipe_resource *indexbuf = !info->index_size || info->has_user_indices ? NULL : info->index.resource;
2129 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2130 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
2131 bool has_user_indices = info->index_size && info->has_user_indices;
2132 uint64_t mask;
2133 unsigned num_patches, dirty_tex_counter, index_offset = 0;
2134 unsigned index_size = info->index_size;
2135 int index_bias;
2136 struct r600_shader_atomic combined_atomics[8];
2137 uint8_t atomic_used_mask = 0;
2138 struct pipe_stream_output_target *count_from_so = NULL;
2139
2140 if (indirect && indirect->count_from_stream_output) {
2141 count_from_so = indirect->count_from_stream_output;
2142 indirect = NULL;
2143 }
2144
2145 if (!indirect && !draws[0].count && (index_size || !count_from_so)) {
2146 return;
2147 }
2148
2149 if (unlikely(!rctx->vs_shader)) {
2150 assert(0);
2151 return;
2152 }
2153 if (unlikely(!rctx->ps_shader &&
2154 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
2155 assert(0);
2156 return;
2157 }
2158
2159 /* make sure that the gfx ring is only one active */
2160 if (radeon_emitted(&rctx->b.dma.cs, 0)) {
2161 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2162 }
2163
2164 if (rctx->cmd_buf_is_compute) {
2165 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2166 rctx->cmd_buf_is_compute = false;
2167 }
2168
2169 /* Re-emit the framebuffer state if needed. */
2170 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
2171 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
2172 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
2173 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
2174 rctx->framebuffer.do_update_surf_dirtiness = true;
2175 }
2176
2177 if (rctx->gs_shader) {
2178 /* Determine whether the GS triangle strip adjacency fix should
2179 * be applied. Rotate every other triangle if
2180 * - triangle strips with adjacency are fed to the GS and
2181 * - primitive restart is disabled (the rotation doesn't help
2182 * when the restart occurs after an odd number of triangles).
2183 */
2184 bool gs_tri_strip_adj_fix =
2185 !rctx->tes_shader &&
2186 info->mode == MESA_PRIM_TRIANGLE_STRIP_ADJACENCY &&
2187 !info->primitive_restart;
2188 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
2189 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2190 }
2191 if (!r600_update_derived_state(rctx)) {
2192 /* useless to render because current rendering command
2193 * can't be achieved
2194 */
2195 return;
2196 }
2197
2198 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
2199 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
2200 : info->mode;
2201
2202 if (rctx->b.gfx_level >= EVERGREEN) {
2203 evergreen_emit_atomic_buffer_setup_count(rctx, NULL, combined_atomics, &atomic_used_mask);
2204 }
2205
2206 if (index_size) {
2207 index_offset += draws[0].start * index_size;
2208
2209 /* Translate 8-bit indices to 16-bit. */
2210 if (unlikely(index_size == 1)) {
2211 struct pipe_resource *out_buffer = NULL;
2212 unsigned out_offset;
2213 void *ptr;
2214 unsigned start, count;
2215
2216 if (likely(!indirect)) {
2217 start = 0;
2218 count = draws[0].count;
2219 }
2220 else {
2221 /* Have to get start/count from indirect buffer, slow path ahead... */
2222 struct r600_resource *indirect_resource = (struct r600_resource *)indirect->buffer;
2223 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
2224 PIPE_MAP_READ);
2225 if (data) {
2226 data += indirect->offset / sizeof(unsigned);
2227 start = data[2] * index_size;
2228 count = data[0];
2229 }
2230 else {
2231 start = 0;
2232 count = 0;
2233 }
2234 }
2235
2236 u_upload_alloc(ctx->stream_uploader, start, count * 2,
2237 256, &out_offset, &out_buffer, &ptr);
2238 if (unlikely(!ptr))
2239 return;
2240
2241 util_shorten_ubyte_elts_to_userptr(
2242 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
2243
2244 indexbuf = out_buffer;
2245 index_offset = out_offset;
2246 index_size = 2;
2247 has_user_indices = false;
2248 }
2249
2250 /* Upload the index buffer.
2251 * The upload is skipped for small index counts on little-endian machines
2252 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2253 * Indirect draws never use immediate indices.
2254 * Note: Instanced rendering in combination with immediate indices hangs. */
2255 if (has_user_indices && (UTIL_ARCH_BIG_ENDIAN || indirect ||
2256 info->instance_count > 1 ||
2257 draws[0].count*index_size > 20)) {
2258 unsigned start_offset = draws[0].start * index_size;
2259 indexbuf = NULL;
2260 u_upload_data(ctx->stream_uploader, start_offset,
2261 draws[0].count * index_size, 256,
2262 (char*)info->index.user + start_offset,
2263 &index_offset, &indexbuf);
2264 index_offset -= start_offset;
2265 has_user_indices = false;
2266 }
2267 index_bias = draws->index_bias;
2268 } else {
2269 index_bias = indirect ? 0 : draws[0].start;
2270 }
2271
2272 /* Set the index offset and primitive restart. */
2273 bool restart_index_changed = info->primitive_restart &&
2274 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index;
2275
2276 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
2277 restart_index_changed ||
2278 rctx->vgt_state.vgt_indx_offset != index_bias ||
2279 (rctx->vgt_state.last_draw_was_indirect && !indirect)) {
2280 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
2281 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
2282 rctx->vgt_state.vgt_indx_offset = index_bias;
2283 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
2284 }
2285
2286 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2287 if (rctx->b.gfx_level == R600) {
2288 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2289 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2290 }
2291
2292 if (rctx->b.gfx_level >= EVERGREEN)
2293 evergreen_setup_tess_constants(rctx, info, &num_patches);
2294
2295 /* Emit states. */
2296 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, true, util_bitcount(atomic_used_mask));
2297 r600_flush_emit(rctx);
2298
2299 mask = rctx->dirty_atoms;
2300 while (mask != 0) {
2301 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2302 }
2303
2304 if (rctx->b.gfx_level >= EVERGREEN) {
2305 evergreen_emit_atomic_buffer_setup(rctx, false, combined_atomics, atomic_used_mask);
2306 }
2307
2308 if (rctx->b.gfx_level == CAYMAN) {
2309 /* Copied from radeonsi. */
2310 unsigned primgroup_size = 128; /* recommended without a GS */
2311 bool ia_switch_on_eop = false;
2312 bool partial_vs_wave = false;
2313
2314 if (rctx->gs_shader)
2315 primgroup_size = 64; /* recommended with a GS */
2316
2317 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2318 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2319 ia_switch_on_eop = true;
2320 }
2321
2322 if (r600_get_strmout_en(&rctx->b))
2323 partial_vs_wave = true;
2324
2325 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2326 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2327 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2328 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2329 }
2330
2331 if (rctx->b.gfx_level >= EVERGREEN) {
2332 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2333 num_patches);
2334
2335 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2336 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2337 }
2338
2339 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2340 * even though it should have no effect on those. */
2341 if (rctx->b.gfx_level == R600 && rctx->rasterizer) {
2342 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2343 unsigned prim = info->mode;
2344
2345 if (rctx->gs_shader) {
2346 prim = rctx->gs_shader->gs_output_prim;
2347 }
2348 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2349
2350 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2351 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2352 info->mode == R600_PRIM_RECTANGLE_LIST) {
2353 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2354 }
2355 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2356 }
2357
2358 /* Update start instance. */
2359 if (!indirect && rctx->last_start_instance != info->start_instance) {
2360 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2361 rctx->last_start_instance = info->start_instance;
2362 }
2363
2364 /* Update the primitive type. */
2365 if (rctx->last_primitive_type != info->mode) {
2366 r600_emit_rasterizer_prim_state(rctx);
2367 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2368 r600_conv_pipe_prim(info->mode));
2369
2370 rctx->last_primitive_type = info->mode;
2371 }
2372
2373 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
2374 if (rctx->b.gfx_level >= EVERGREEN) {
2375 evergreen_setup_scratch_buffers(rctx);
2376 } else {
2377 r600_setup_scratch_buffers(rctx);
2378 }
2379
2380 /* Draw packets. */
2381 if (likely(!indirect)) {
2382 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2383 radeon_emit(cs, info->instance_count);
2384 } else {
2385 uint64_t va = r600_resource(indirect->buffer)->gpu_address;
2386 assert(rctx->b.gfx_level >= EVERGREEN);
2387
2388 // Invalidate so non-indirect draw calls reset this state
2389 rctx->vgt_state.last_draw_was_indirect = true;
2390 rctx->last_start_instance = -1;
2391
2392 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2393 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2394 radeon_emit(cs, va);
2395 radeon_emit(cs, (va >> 32UL) & 0xFF);
2396
2397 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2398 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2399 (struct r600_resource*)indirect->buffer,
2400 RADEON_USAGE_READ |
2401 RADEON_PRIO_DRAW_INDIRECT));
2402 }
2403
2404 if (index_size) {
2405 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2406 radeon_emit(cs, index_size == 4 ?
2407 (VGT_INDEX_32 | (UTIL_ARCH_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2408 (VGT_INDEX_16 | (UTIL_ARCH_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2409
2410 if (has_user_indices) {
2411 unsigned size_bytes = draws[0].count*index_size;
2412 unsigned size_dw = align(size_bytes, 4) / 4;
2413 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2414 radeon_emit(cs, draws[0].count);
2415 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2416 memcpy(cs->current.buf + cs->current.cdw,
2417 info->index.user + draws[0].start * index_size, size_bytes);
2418 cs->current.cdw += size_dw;
2419 } else {
2420 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2421
2422 if (likely(!indirect)) {
2423 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2424 radeon_emit(cs, va);
2425 radeon_emit(cs, (va >> 32UL) & 0xFF);
2426 radeon_emit(cs, draws[0].count);
2427 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2428 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2429 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2430 (struct r600_resource*)indexbuf,
2431 RADEON_USAGE_READ |
2432 RADEON_PRIO_INDEX_BUFFER));
2433 }
2434 else {
2435 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2436
2437 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2438 radeon_emit(cs, va);
2439 radeon_emit(cs, (va >> 32UL) & 0xFF);
2440
2441 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2442 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2443 (struct r600_resource*)indexbuf,
2444 RADEON_USAGE_READ |
2445 RADEON_PRIO_INDEX_BUFFER));
2446
2447 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2448 radeon_emit(cs, max_size);
2449
2450 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2451 radeon_emit(cs, indirect->offset);
2452 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2453 }
2454 }
2455 } else {
2456 if (unlikely(count_from_so)) {
2457 struct r600_so_target *t = (struct r600_so_target*)count_from_so;
2458 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2459
2460 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2461
2462 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2463 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2464 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2465 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2466 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2467 radeon_emit(cs, 0); /* unused */
2468
2469 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2470 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2471 t->buf_filled_size, RADEON_USAGE_READ |
2472 RADEON_PRIO_SO_FILLED_SIZE));
2473 }
2474
2475 if (likely(!indirect)) {
2476 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2477 radeon_emit(cs, draws[0].count);
2478 }
2479 else {
2480 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2481 radeon_emit(cs, indirect->offset);
2482 }
2483 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2484 (count_from_so ? S_0287F0_USE_OPAQUE(1) : 0));
2485 }
2486
2487 /* SMX returns CONTEXT_DONE too early workaround */
2488 if (rctx->b.family == CHIP_R600 ||
2489 rctx->b.family == CHIP_RV610 ||
2490 rctx->b.family == CHIP_RV630 ||
2491 rctx->b.family == CHIP_RV635) {
2492 /* if we have gs shader or streamout
2493 we need to do a wait idle after every draw */
2494 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2495 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2496 }
2497 }
2498
2499 /* ES ring rolling over at EOP - workaround */
2500 if (rctx->b.gfx_level == R600) {
2501 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2502 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2503 }
2504
2505
2506 if (rctx->b.gfx_level >= EVERGREEN)
2507 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2508
2509 if (rctx->trace_buf)
2510 eg_trace_emit(rctx);
2511
2512 if (rctx->framebuffer.do_update_surf_dirtiness) {
2513 /* Set the depth buffer as dirty. */
2514 if (rctx->framebuffer.state.zsbuf) {
2515 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2516 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2517
2518 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2519
2520 if (rtex->surface.has_stencil)
2521 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2522 }
2523 if (rctx->framebuffer.compressed_cb_mask) {
2524 struct pipe_surface *surf;
2525 struct r600_texture *rtex;
2526 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2527
2528 do {
2529 unsigned i = u_bit_scan(&mask);
2530 surf = rctx->framebuffer.state.cbufs[i];
2531 rtex = (struct r600_texture*)surf->texture;
2532
2533 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2534
2535 } while (mask);
2536 }
2537 rctx->framebuffer.do_update_surf_dirtiness = false;
2538 }
2539
2540 if (index_size && indexbuf != info->index.resource)
2541 pipe_resource_reference(&indexbuf, NULL);
2542 rctx->b.num_draw_calls++;
2543 }
2544
r600_translate_stencil_op(int s_op)2545 uint32_t r600_translate_stencil_op(int s_op)
2546 {
2547 switch (s_op) {
2548 case PIPE_STENCIL_OP_KEEP:
2549 return V_028800_STENCIL_KEEP;
2550 case PIPE_STENCIL_OP_ZERO:
2551 return V_028800_STENCIL_ZERO;
2552 case PIPE_STENCIL_OP_REPLACE:
2553 return V_028800_STENCIL_REPLACE;
2554 case PIPE_STENCIL_OP_INCR:
2555 return V_028800_STENCIL_INCR;
2556 case PIPE_STENCIL_OP_DECR:
2557 return V_028800_STENCIL_DECR;
2558 case PIPE_STENCIL_OP_INCR_WRAP:
2559 return V_028800_STENCIL_INCR_WRAP;
2560 case PIPE_STENCIL_OP_DECR_WRAP:
2561 return V_028800_STENCIL_DECR_WRAP;
2562 case PIPE_STENCIL_OP_INVERT:
2563 return V_028800_STENCIL_INVERT;
2564 default:
2565 R600_ERR("Unknown stencil op %d", s_op);
2566 assert(0);
2567 break;
2568 }
2569 return 0;
2570 }
2571
r600_translate_fill(uint32_t func)2572 uint32_t r600_translate_fill(uint32_t func)
2573 {
2574 switch(func) {
2575 case PIPE_POLYGON_MODE_FILL:
2576 return 2;
2577 case PIPE_POLYGON_MODE_LINE:
2578 return 1;
2579 case PIPE_POLYGON_MODE_POINT:
2580 return 0;
2581 default:
2582 assert(0);
2583 return 0;
2584 }
2585 }
2586
r600_tex_wrap(unsigned wrap)2587 unsigned r600_tex_wrap(unsigned wrap)
2588 {
2589 switch (wrap) {
2590 default:
2591 case PIPE_TEX_WRAP_REPEAT:
2592 return V_03C000_SQ_TEX_WRAP;
2593 case PIPE_TEX_WRAP_CLAMP:
2594 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2595 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2596 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2597 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2598 return V_03C000_SQ_TEX_CLAMP_BORDER;
2599 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2600 return V_03C000_SQ_TEX_MIRROR;
2601 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2602 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2603 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2604 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2605 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2606 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2607 }
2608 }
2609
r600_tex_mipfilter(unsigned filter)2610 unsigned r600_tex_mipfilter(unsigned filter)
2611 {
2612 switch (filter) {
2613 case PIPE_TEX_MIPFILTER_NEAREST:
2614 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2615 case PIPE_TEX_MIPFILTER_LINEAR:
2616 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2617 default:
2618 case PIPE_TEX_MIPFILTER_NONE:
2619 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2620 }
2621 }
2622
r600_tex_compare(unsigned compare)2623 unsigned r600_tex_compare(unsigned compare)
2624 {
2625 switch (compare) {
2626 default:
2627 case PIPE_FUNC_NEVER:
2628 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2629 case PIPE_FUNC_LESS:
2630 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2631 case PIPE_FUNC_EQUAL:
2632 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2633 case PIPE_FUNC_LEQUAL:
2634 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2635 case PIPE_FUNC_GREATER:
2636 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2637 case PIPE_FUNC_NOTEQUAL:
2638 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2639 case PIPE_FUNC_GEQUAL:
2640 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2641 case PIPE_FUNC_ALWAYS:
2642 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2643 }
2644 }
2645
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)2646 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2647 {
2648 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2649 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2650 (linear_filter &&
2651 (wrap == PIPE_TEX_WRAP_CLAMP ||
2652 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2653 }
2654
sampler_state_needs_border_color(const struct pipe_sampler_state * state)2655 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2656 {
2657 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2658 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2659
2660 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2661 state->border_color.ui[2] || state->border_color.ui[3]) &&
2662 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2663 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2664 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2665 }
2666
r600_emit_shader(struct r600_context * rctx,struct r600_atom * a)2667 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2668 {
2669
2670 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2671 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2672
2673 if (!shader)
2674 return;
2675
2676 r600_emit_command_buffer(cs, &shader->command_buffer);
2677 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2678 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2679 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY));
2680 }
2681
r600_get_swizzle_combined(const unsigned char * swizzle_format,const unsigned char * swizzle_view,bool vtx)2682 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2683 const unsigned char *swizzle_view,
2684 bool vtx)
2685 {
2686 unsigned i;
2687 unsigned char swizzle[4];
2688 unsigned result = 0;
2689 const uint32_t tex_swizzle_shift[4] = {
2690 16, 19, 22, 25,
2691 };
2692 const uint32_t vtx_swizzle_shift[4] = {
2693 3, 6, 9, 12,
2694 };
2695 const uint32_t swizzle_bit[4] = {
2696 0, 1, 2, 3,
2697 };
2698 const uint32_t *swizzle_shift = tex_swizzle_shift;
2699
2700 if (vtx)
2701 swizzle_shift = vtx_swizzle_shift;
2702
2703 if (swizzle_view) {
2704 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2705 } else {
2706 memcpy(swizzle, swizzle_format, 4);
2707 }
2708
2709 /* Get swizzle. */
2710 for (i = 0; i < 4; i++) {
2711 switch (swizzle[i]) {
2712 case PIPE_SWIZZLE_Y:
2713 result |= swizzle_bit[1] << swizzle_shift[i];
2714 break;
2715 case PIPE_SWIZZLE_Z:
2716 result |= swizzle_bit[2] << swizzle_shift[i];
2717 break;
2718 case PIPE_SWIZZLE_W:
2719 result |= swizzle_bit[3] << swizzle_shift[i];
2720 break;
2721 case PIPE_SWIZZLE_0:
2722 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2723 break;
2724 case PIPE_SWIZZLE_1:
2725 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2726 break;
2727 default: /* PIPE_SWIZZLE_X */
2728 result |= swizzle_bit[0] << swizzle_shift[i];
2729 }
2730 }
2731 return result;
2732 }
2733
2734 /* texture format translate */
r600_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const unsigned char * swizzle_view,uint32_t * word4_p,uint32_t * yuv_format_p,bool do_endian_swap)2735 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2736 enum pipe_format format,
2737 const unsigned char *swizzle_view,
2738 uint32_t *word4_p, uint32_t *yuv_format_p,
2739 bool do_endian_swap)
2740 {
2741 struct r600_screen *rscreen = (struct r600_screen *)screen;
2742 uint32_t result = 0, word4 = 0, yuv_format = 0;
2743 const struct util_format_description *desc;
2744 bool uniform = true;
2745 bool is_srgb_valid = false;
2746 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2747 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2748 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2749 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2750 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2751
2752 int i;
2753 const uint32_t sign_bit[4] = {
2754 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2755 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2756 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2757 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2758 };
2759
2760 /* Need to replace the specified texture formats in case of big-endian.
2761 * These formats are formats that have channels with number of bits
2762 * not divisible by 8.
2763 * Mesa conversion functions don't swap bits for those formats, and because
2764 * we transmit this over a serial bus to the GPU (PCIe), the
2765 * bit-endianness is important!!!
2766 * In case we have an "opposite" format, just use that for the swizzling
2767 * information. If we don't have such an "opposite" format, we need
2768 * to use a fixed swizzle info instead (see below)
2769 */
2770 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2771 format = PIPE_FORMAT_A4R4_UNORM;
2772
2773 desc = util_format_description(format);
2774
2775 /* Depth and stencil swizzling is handled separately. */
2776 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2777 /* Need to check for specific texture formats that don't have
2778 * an "opposite" format we can use. For those formats, we directly
2779 * specify the swizzling, which is the LE swizzling as defined in
2780 * u_format.csv
2781 */
2782 if (do_endian_swap) {
2783 if (format == PIPE_FORMAT_L4A4_UNORM)
2784 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, false);
2785 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2786 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, false);
2787 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2788 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, false);
2789 else
2790 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, false);
2791 } else {
2792 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, false);
2793 }
2794 }
2795
2796 /* Colorspace (return non-RGB formats directly). */
2797 switch (desc->colorspace) {
2798 /* Depth stencil formats */
2799 case UTIL_FORMAT_COLORSPACE_ZS:
2800 switch (format) {
2801 /* Depth sampler formats. */
2802 case PIPE_FORMAT_Z16_UNORM:
2803 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2804 result = FMT_16;
2805 goto out_word4;
2806 case PIPE_FORMAT_Z24X8_UNORM:
2807 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2808 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2809 result = FMT_8_24;
2810 goto out_word4;
2811 case PIPE_FORMAT_X8Z24_UNORM:
2812 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2813 if (rscreen->b.gfx_level < EVERGREEN)
2814 goto out_unknown;
2815 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, false);
2816 result = FMT_24_8;
2817 goto out_word4;
2818 case PIPE_FORMAT_Z32_FLOAT:
2819 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2820 result = FMT_32_FLOAT;
2821 goto out_word4;
2822 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2823 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2824 result = FMT_X24_8_32_FLOAT;
2825 goto out_word4;
2826 /* Stencil sampler formats. */
2827 case PIPE_FORMAT_S8_UINT:
2828 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2829 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2830 result = FMT_8;
2831 goto out_word4;
2832 case PIPE_FORMAT_X24S8_UINT:
2833 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2834 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, false);
2835 result = FMT_8_24;
2836 goto out_word4;
2837 case PIPE_FORMAT_S8X24_UINT:
2838 if (rscreen->b.gfx_level < EVERGREEN)
2839 goto out_unknown;
2840 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2841 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2842 result = FMT_24_8;
2843 goto out_word4;
2844 case PIPE_FORMAT_X32_S8X24_UINT:
2845 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2846 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, false);
2847 result = FMT_X24_8_32_FLOAT;
2848 goto out_word4;
2849 default:
2850 goto out_unknown;
2851 }
2852
2853 case UTIL_FORMAT_COLORSPACE_YUV:
2854 yuv_format |= (1 << 30);
2855 switch (format) {
2856 case PIPE_FORMAT_UYVY:
2857 case PIPE_FORMAT_YUYV:
2858 default:
2859 break;
2860 }
2861 goto out_unknown; /* XXX */
2862
2863 case UTIL_FORMAT_COLORSPACE_SRGB:
2864 word4 |= S_038010_FORCE_DEGAMMA(1);
2865 break;
2866
2867 default:
2868 break;
2869 }
2870
2871 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2872 switch (format) {
2873 case PIPE_FORMAT_RGTC1_SNORM:
2874 case PIPE_FORMAT_LATC1_SNORM:
2875 word4 |= sign_bit[0];
2876 FALLTHROUGH;
2877 case PIPE_FORMAT_RGTC1_UNORM:
2878 case PIPE_FORMAT_LATC1_UNORM:
2879 result = FMT_BC4;
2880 goto out_word4;
2881 case PIPE_FORMAT_RGTC2_SNORM:
2882 case PIPE_FORMAT_LATC2_SNORM:
2883 word4 |= sign_bit[0] | sign_bit[1];
2884 FALLTHROUGH;
2885 case PIPE_FORMAT_RGTC2_UNORM:
2886 case PIPE_FORMAT_LATC2_UNORM:
2887 result = FMT_BC5;
2888 goto out_word4;
2889 default:
2890 goto out_unknown;
2891 }
2892 }
2893
2894 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2895 switch (format) {
2896 case PIPE_FORMAT_DXT1_RGB:
2897 case PIPE_FORMAT_DXT1_RGBA:
2898 case PIPE_FORMAT_DXT1_SRGB:
2899 case PIPE_FORMAT_DXT1_SRGBA:
2900 result = FMT_BC1;
2901 is_srgb_valid = true;
2902 goto out_word4;
2903 case PIPE_FORMAT_DXT3_RGBA:
2904 case PIPE_FORMAT_DXT3_SRGBA:
2905 result = FMT_BC2;
2906 is_srgb_valid = true;
2907 goto out_word4;
2908 case PIPE_FORMAT_DXT5_RGBA:
2909 case PIPE_FORMAT_DXT5_SRGBA:
2910 result = FMT_BC3;
2911 is_srgb_valid = true;
2912 goto out_word4;
2913 default:
2914 goto out_unknown;
2915 }
2916 }
2917
2918 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2919 if (rscreen->b.gfx_level < EVERGREEN)
2920 goto out_unknown;
2921
2922 switch (format) {
2923 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2924 case PIPE_FORMAT_BPTC_SRGBA:
2925 result = FMT_BC7;
2926 is_srgb_valid = true;
2927 goto out_word4;
2928 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2929 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2930 FALLTHROUGH;
2931 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2932 result = FMT_BC6;
2933 goto out_word4;
2934 default:
2935 goto out_unknown;
2936 }
2937 }
2938
2939 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2940 switch (format) {
2941 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2942 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2943 result = FMT_GB_GR;
2944 goto out_word4;
2945 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2946 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2947 result = FMT_BG_RG;
2948 goto out_word4;
2949 default:
2950 goto out_unknown;
2951 }
2952 }
2953
2954 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2955 result = FMT_5_9_9_9_SHAREDEXP;
2956 goto out_word4;
2957 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2958 result = FMT_10_11_11_FLOAT;
2959 goto out_word4;
2960 }
2961
2962
2963 for (i = 0; i < desc->nr_channels; i++) {
2964 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2965 word4 |= sign_bit[i];
2966 }
2967 }
2968
2969 /* R8G8Bx_SNORM - XXX CxV8U8 */
2970
2971 /* See whether the components are of the same size. */
2972 for (i = 1; i < desc->nr_channels; i++) {
2973 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2974 }
2975
2976 /* Non-uniform formats. */
2977 if (!uniform) {
2978 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2979 desc->channel[0].pure_integer)
2980 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2981 switch(desc->nr_channels) {
2982 case 3:
2983 if (desc->channel[0].size == 5 &&
2984 desc->channel[1].size == 6 &&
2985 desc->channel[2].size == 5) {
2986 result = FMT_5_6_5;
2987 goto out_word4;
2988 }
2989 goto out_unknown;
2990 case 4:
2991 if (desc->channel[0].size == 5 &&
2992 desc->channel[1].size == 5 &&
2993 desc->channel[2].size == 5 &&
2994 desc->channel[3].size == 1) {
2995 result = FMT_1_5_5_5;
2996 goto out_word4;
2997 }
2998 if (desc->channel[0].size == 10 &&
2999 desc->channel[1].size == 10 &&
3000 desc->channel[2].size == 10 &&
3001 desc->channel[3].size == 2) {
3002 result = FMT_2_10_10_10;
3003 goto out_word4;
3004 }
3005 goto out_unknown;
3006 }
3007 goto out_unknown;
3008 }
3009
3010 i = util_format_get_first_non_void_channel(format);
3011 if (i == -1)
3012 goto out_unknown;
3013
3014 /* uniform formats */
3015 switch (desc->channel[i].type) {
3016 case UTIL_FORMAT_TYPE_UNSIGNED:
3017 case UTIL_FORMAT_TYPE_SIGNED:
3018 #if 0
3019 if (!desc->channel[i].normalized &&
3020 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
3021 goto out_unknown;
3022 }
3023 #endif
3024 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
3025 desc->channel[i].pure_integer)
3026 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
3027
3028 switch (desc->channel[i].size) {
3029 case 4:
3030 switch (desc->nr_channels) {
3031 case 2:
3032 result = FMT_4_4;
3033 goto out_word4;
3034 case 4:
3035 result = FMT_4_4_4_4;
3036 goto out_word4;
3037 }
3038 goto out_unknown;
3039 case 8:
3040 switch (desc->nr_channels) {
3041 case 1:
3042 result = FMT_8;
3043 is_srgb_valid = true;
3044 goto out_word4;
3045 case 2:
3046 result = FMT_8_8;
3047 goto out_word4;
3048 case 4:
3049 result = FMT_8_8_8_8;
3050 is_srgb_valid = true;
3051 goto out_word4;
3052 }
3053 goto out_unknown;
3054 case 16:
3055 switch (desc->nr_channels) {
3056 case 1:
3057 result = FMT_16;
3058 goto out_word4;
3059 case 2:
3060 result = FMT_16_16;
3061 goto out_word4;
3062 case 4:
3063 result = FMT_16_16_16_16;
3064 goto out_word4;
3065 }
3066 goto out_unknown;
3067 case 32:
3068 switch (desc->nr_channels) {
3069 case 1:
3070 result = FMT_32;
3071 goto out_word4;
3072 case 2:
3073 result = FMT_32_32;
3074 goto out_word4;
3075 case 4:
3076 result = FMT_32_32_32_32;
3077 goto out_word4;
3078 }
3079 }
3080 goto out_unknown;
3081
3082 case UTIL_FORMAT_TYPE_FLOAT:
3083 switch (desc->channel[i].size) {
3084 case 16:
3085 switch (desc->nr_channels) {
3086 case 1:
3087 result = FMT_16_FLOAT;
3088 goto out_word4;
3089 case 2:
3090 result = FMT_16_16_FLOAT;
3091 goto out_word4;
3092 case 4:
3093 result = FMT_16_16_16_16_FLOAT;
3094 goto out_word4;
3095 }
3096 goto out_unknown;
3097 case 32:
3098 switch (desc->nr_channels) {
3099 case 1:
3100 result = FMT_32_FLOAT;
3101 goto out_word4;
3102 case 2:
3103 result = FMT_32_32_FLOAT;
3104 goto out_word4;
3105 case 4:
3106 result = FMT_32_32_32_32_FLOAT;
3107 goto out_word4;
3108 }
3109 }
3110 goto out_unknown;
3111 }
3112
3113 out_word4:
3114
3115 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
3116 return ~0;
3117 if (word4_p)
3118 *word4_p = word4;
3119 if (yuv_format_p)
3120 *yuv_format_p = yuv_format;
3121 return result;
3122 out_unknown:
3123 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3124 return ~0;
3125 }
3126
r600_translate_colorformat(enum amd_gfx_level chip,enum pipe_format format,bool do_endian_swap)3127 uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format,
3128 bool do_endian_swap)
3129 {
3130 const struct util_format_description *desc = util_format_description(format);
3131 int channel = util_format_get_first_non_void_channel(format);
3132 bool is_float;
3133
3134 #define HAS_SIZE(x,y,z,w) \
3135 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3136 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3137
3138 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
3139 return V_0280A0_COLOR_10_11_11_FLOAT;
3140
3141 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
3142 channel == -1)
3143 return ~0U;
3144
3145 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
3146
3147 switch (desc->nr_channels) {
3148 case 1:
3149 switch (desc->channel[0].size) {
3150 case 8:
3151 return V_0280A0_COLOR_8;
3152 case 16:
3153 if (is_float)
3154 return V_0280A0_COLOR_16_FLOAT;
3155 else
3156 return V_0280A0_COLOR_16;
3157 case 32:
3158 if (is_float)
3159 return V_0280A0_COLOR_32_FLOAT;
3160 else
3161 return V_0280A0_COLOR_32;
3162 }
3163 break;
3164 case 2:
3165 if (desc->channel[0].size == desc->channel[1].size) {
3166 switch (desc->channel[0].size) {
3167 case 4:
3168 if (chip <= R700)
3169 return V_0280A0_COLOR_4_4;
3170 else
3171 return ~0U; /* removed on Evergreen */
3172 case 8:
3173 return V_0280A0_COLOR_8_8;
3174 case 16:
3175 if (is_float)
3176 return V_0280A0_COLOR_16_16_FLOAT;
3177 else
3178 return V_0280A0_COLOR_16_16;
3179 case 32:
3180 if (is_float)
3181 return V_0280A0_COLOR_32_32_FLOAT;
3182 else
3183 return V_0280A0_COLOR_32_32;
3184 }
3185 } else if (HAS_SIZE(8,24,0,0)) {
3186 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
3187 } else if (HAS_SIZE(24,8,0,0)) {
3188 return V_0280A0_COLOR_8_24;
3189 }
3190 break;
3191 case 3:
3192 if (HAS_SIZE(5,6,5,0)) {
3193 return V_0280A0_COLOR_5_6_5;
3194 } else if (HAS_SIZE(32,8,24,0)) {
3195 return V_0280A0_COLOR_X24_8_32_FLOAT;
3196 }
3197 break;
3198 case 4:
3199 if (desc->channel[0].size == desc->channel[1].size &&
3200 desc->channel[0].size == desc->channel[2].size &&
3201 desc->channel[0].size == desc->channel[3].size) {
3202 switch (desc->channel[0].size) {
3203 case 4:
3204 return V_0280A0_COLOR_4_4_4_4;
3205 case 8:
3206 return V_0280A0_COLOR_8_8_8_8;
3207 case 16:
3208 if (is_float)
3209 return V_0280A0_COLOR_16_16_16_16_FLOAT;
3210 else
3211 return V_0280A0_COLOR_16_16_16_16;
3212 case 32:
3213 if (is_float)
3214 return V_0280A0_COLOR_32_32_32_32_FLOAT;
3215 else
3216 return V_0280A0_COLOR_32_32_32_32;
3217 }
3218 } else if (HAS_SIZE(5,5,5,1)) {
3219 return V_0280A0_COLOR_1_5_5_5;
3220 } else if (HAS_SIZE(10,10,10,2)) {
3221 return V_0280A0_COLOR_2_10_10_10;
3222 }
3223 break;
3224 }
3225 return ~0U;
3226 }
3227
r600_colorformat_endian_swap(uint32_t colorformat,bool do_endian_swap)3228 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
3229 {
3230 if (UTIL_ARCH_BIG_ENDIAN) {
3231 switch(colorformat) {
3232 /* 8-bit buffers. */
3233 case V_0280A0_COLOR_4_4:
3234 case V_0280A0_COLOR_8:
3235 return ENDIAN_NONE;
3236
3237 /* 16-bit buffers. */
3238 case V_0280A0_COLOR_8_8:
3239 /*
3240 * No need to do endian swaps on array formats,
3241 * as mesa<-->pipe formats conversion take into account
3242 * the endianness
3243 */
3244 return ENDIAN_NONE;
3245
3246 case V_0280A0_COLOR_5_6_5:
3247 case V_0280A0_COLOR_1_5_5_5:
3248 case V_0280A0_COLOR_4_4_4_4:
3249 case V_0280A0_COLOR_16:
3250 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
3251
3252 /* 32-bit buffers. */
3253 case V_0280A0_COLOR_8_8_8_8:
3254 /*
3255 * No need to do endian swaps on array formats,
3256 * as mesa<-->pipe formats conversion take into account
3257 * the endianness
3258 */
3259 return ENDIAN_NONE;
3260
3261 case V_0280A0_COLOR_2_10_10_10:
3262 case V_0280A0_COLOR_8_24:
3263 case V_0280A0_COLOR_24_8:
3264 case V_0280A0_COLOR_32_FLOAT:
3265 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
3266
3267 case V_0280A0_COLOR_16_16_FLOAT:
3268 case V_0280A0_COLOR_16_16:
3269 return ENDIAN_8IN16;
3270
3271 /* 64-bit buffers. */
3272 case V_0280A0_COLOR_16_16_16_16:
3273 case V_0280A0_COLOR_16_16_16_16_FLOAT:
3274 return ENDIAN_8IN16;
3275
3276 case V_0280A0_COLOR_32_32_FLOAT:
3277 case V_0280A0_COLOR_32_32:
3278 case V_0280A0_COLOR_X24_8_32_FLOAT:
3279 return ENDIAN_8IN32;
3280
3281 /* 128-bit buffers. */
3282 case V_0280A0_COLOR_32_32_32_32_FLOAT:
3283 case V_0280A0_COLOR_32_32_32_32:
3284 return ENDIAN_8IN32;
3285 default:
3286 return ENDIAN_NONE; /* Unsupported. */
3287 }
3288 } else {
3289 return ENDIAN_NONE;
3290 }
3291 }
3292
r600_invalidate_buffer(struct pipe_context * ctx,struct pipe_resource * buf)3293 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3294 {
3295 struct r600_context *rctx = (struct r600_context*)ctx;
3296 struct r600_resource *rbuffer = r600_resource(buf);
3297 unsigned i, shader, mask;
3298 struct r600_pipe_sampler_view *view;
3299
3300 /* Reallocate the buffer in the same pipe_resource. */
3301 r600_alloc_resource(&rctx->screen->b, rbuffer);
3302
3303 /* We changed the buffer, now we need to bind it where the old one was bound. */
3304 /* Vertex buffers. */
3305 mask = rctx->vertex_buffer_state.enabled_mask;
3306 while (mask) {
3307 i = u_bit_scan(&mask);
3308 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3309 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3310 r600_vertex_buffers_dirty(rctx);
3311 }
3312 }
3313 /* Streamout buffers. */
3314 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3315 if (rctx->b.streamout.targets[i] &&
3316 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3317 if (rctx->b.streamout.begin_emitted) {
3318 r600_emit_streamout_end(&rctx->b);
3319 }
3320 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3321 r600_streamout_buffers_dirty(&rctx->b);
3322 }
3323 }
3324
3325 /* Constant buffers. */
3326 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3327 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3328 bool found = false;
3329 uint32_t mask = state->enabled_mask;
3330
3331 while (mask) {
3332 unsigned i = u_bit_scan(&mask);
3333 if (state->cb[i].buffer == &rbuffer->b.b) {
3334 found = true;
3335 state->dirty_mask |= 1 << i;
3336 }
3337 }
3338 if (found) {
3339 r600_constant_buffers_dirty(rctx, state);
3340 }
3341 }
3342
3343 /* Texture buffer objects - update the virtual addresses in descriptors. */
3344 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3345 if (view->base.texture == &rbuffer->b.b) {
3346 uint64_t offset = view->base.u.buf.offset;
3347 uint64_t va = rbuffer->gpu_address + offset;
3348
3349 view->tex_resource_words[0] = va;
3350 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3351 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3352 }
3353 }
3354 /* Texture buffer objects - make bindings dirty if needed. */
3355 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3356 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3357 bool found = false;
3358 uint32_t mask = state->enabled_mask;
3359
3360 while (mask) {
3361 unsigned i = u_bit_scan(&mask);
3362 if (state->views[i]->base.texture == &rbuffer->b.b) {
3363 found = true;
3364 state->dirty_mask |= 1 << i;
3365 }
3366 }
3367 if (found) {
3368 r600_sampler_views_dirty(rctx, state);
3369 }
3370 }
3371
3372 /* SSBOs */
3373 struct r600_image_state *istate = &rctx->fragment_buffers;
3374 {
3375 uint32_t mask = istate->enabled_mask;
3376 bool found = false;
3377 while (mask) {
3378 unsigned i = u_bit_scan(&mask);
3379 if (istate->views[i].base.resource == &rbuffer->b.b) {
3380 found = true;
3381 istate->dirty_mask |= 1 << i;
3382 }
3383 }
3384 if (found) {
3385 r600_mark_atom_dirty(rctx, &istate->atom);
3386 }
3387 }
3388
3389 }
3390
r600_set_active_query_state(struct pipe_context * ctx,bool enable)3391 static void r600_set_active_query_state(struct pipe_context *ctx, bool enable)
3392 {
3393 struct r600_context *rctx = (struct r600_context*)ctx;
3394
3395 /* Pipeline stat & streamout queries. */
3396 if (enable) {
3397 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3398 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3399 } else {
3400 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3401 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3402 }
3403
3404 /* Occlusion queries. */
3405 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3406 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3407 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3408 }
3409 }
3410
r600_need_gfx_cs_space(struct pipe_context * ctx,unsigned num_dw,bool include_draw_vbo)3411 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3412 bool include_draw_vbo)
3413 {
3414 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo, 0);
3415 }
3416
3417 /* keep this at the end of this file, please */
r600_init_common_state_functions(struct r600_context * rctx)3418 void r600_init_common_state_functions(struct r600_context *rctx)
3419 {
3420 rctx->b.b.create_fs_state = r600_create_ps_state;
3421 rctx->b.b.create_vs_state = r600_create_vs_state;
3422 rctx->b.b.create_gs_state = r600_create_gs_state;
3423 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3424 rctx->b.b.create_tes_state = r600_create_tes_state;
3425 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3426 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3427 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3428 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3429 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3430 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3431 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3432 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3433 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3434 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3435 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3436 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3437 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3438 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3439 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3440 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3441 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3442 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3443 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3444 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3445 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3446 rctx->b.b.set_blend_color = r600_set_blend_color;
3447 rctx->b.b.set_clip_state = r600_set_clip_state;
3448 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3449 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3450 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3451 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3452 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3453 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3454 rctx->b.b.memory_barrier = r600_memory_barrier;
3455 rctx->b.b.texture_barrier = r600_texture_barrier;
3456 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3457 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3458
3459 rctx->b.b.draw_vbo = r600_draw_vbo;
3460 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3461 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3462 }
3463