xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/r600/r600_streamout.c (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  * Authors: Marek Olšák <[email protected]>
4  * SPDX-License-Identifier: MIT
5  */
6 
7 #include "r600_pipe_common.h"
8 #include "r600_cs.h"
9 
10 #include "util/u_memory.h"
11 #include "evergreend.h"
12 
13 #define R_008490_CP_STRMOUT_CNTL		     0x008490
14 #define R_028AB0_VGT_STRMOUT_EN                      0x028AB0
15 #define R_028B20_VGT_STRMOUT_BUFFER_EN               0x028B20
16 
17 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
18 
19 static struct pipe_stream_output_target *
r600_create_so_target(struct pipe_context * ctx,struct pipe_resource * buffer,unsigned buffer_offset,unsigned buffer_size)20 r600_create_so_target(struct pipe_context *ctx,
21 		      struct pipe_resource *buffer,
22 		      unsigned buffer_offset,
23 		      unsigned buffer_size)
24 {
25 	struct r600_common_context *rctx = (struct r600_common_context *)ctx;
26 	struct r600_so_target *t;
27 	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
28 
29 	t = CALLOC_STRUCT(r600_so_target);
30 	if (!t) {
31 		return NULL;
32 	}
33 
34 	u_suballocator_alloc(&rctx->allocator_zeroed_memory, 4, 4,
35 			     &t->buf_filled_size_offset,
36 			     (struct pipe_resource**)&t->buf_filled_size);
37 	if (!t->buf_filled_size) {
38 		FREE(t);
39 		return NULL;
40 	}
41 
42 	t->b.reference.count = 1;
43 	t->b.context = ctx;
44 	pipe_resource_reference(&t->b.buffer, buffer);
45 	t->b.buffer_offset = buffer_offset;
46 	t->b.buffer_size = buffer_size;
47 
48 	util_range_add(buffer, &rbuffer->valid_buffer_range, buffer_offset,
49 		       buffer_offset + buffer_size);
50 	return &t->b;
51 }
52 
r600_so_target_destroy(struct pipe_context * ctx,struct pipe_stream_output_target * target)53 static void r600_so_target_destroy(struct pipe_context *ctx,
54 				   struct pipe_stream_output_target *target)
55 {
56 	struct r600_so_target *t = (struct r600_so_target*)target;
57 	pipe_resource_reference(&t->b.buffer, NULL);
58 	r600_resource_reference(&t->buf_filled_size, NULL);
59 	FREE(t);
60 }
61 
r600_streamout_buffers_dirty(struct r600_common_context * rctx)62 void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
63 {
64 	struct r600_atom *begin = &rctx->streamout.begin_atom;
65 	unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
66 	unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
67 						   rctx->streamout.append_bitmask);
68 
69 	if (!num_bufs)
70 		return;
71 
72 	rctx->streamout.num_dw_for_end =
73 		12 + /* flush_vgt_streamout */
74 		num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
75 
76 	begin->num_dw = 12; /* flush_vgt_streamout */
77 
78 	begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
79 
80 	if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
81 		begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
82 
83 	begin->num_dw +=
84 		num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
85 		(num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
86 		(rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
87 
88 	rctx->set_atom_dirty(rctx, begin, true);
89 
90 	r600_set_streamout_enable(rctx, true);
91 }
92 
r600_set_streamout_targets(struct pipe_context * ctx,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)93 void r600_set_streamout_targets(struct pipe_context *ctx,
94 				unsigned num_targets,
95 				struct pipe_stream_output_target **targets,
96 				const unsigned *offsets)
97 {
98 	struct r600_common_context *rctx = (struct r600_common_context *)ctx;
99 	unsigned i;
100         unsigned enabled_mask = 0, append_bitmask = 0;
101 
102 	/* Stop streamout. */
103 	if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
104 		r600_emit_streamout_end(rctx);
105 	}
106 
107 	/* Set the new targets. */
108 	for (i = 0; i < num_targets; i++) {
109 		pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
110 		if (!targets[i])
111 			continue;
112 
113 		r600_context_add_resource_size(ctx, targets[i]->buffer);
114 		enabled_mask |= 1 << i;
115 		if (offsets[i] == ((unsigned)-1))
116 			append_bitmask |= 1 << i;
117 	}
118 	for (; i < rctx->streamout.num_targets; i++) {
119 		pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
120 	}
121 
122 	rctx->streamout.enabled_mask = enabled_mask;
123 
124 	rctx->streamout.num_targets = num_targets;
125 	rctx->streamout.append_bitmask = append_bitmask;
126 
127 	if (num_targets) {
128 		r600_streamout_buffers_dirty(rctx);
129 	} else {
130 		rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
131 		r600_set_streamout_enable(rctx, false);
132 	}
133 }
134 
r600_flush_vgt_streamout(struct r600_common_context * rctx)135 static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
136 {
137 	struct radeon_cmdbuf *cs = &rctx->gfx.cs;
138 	unsigned reg_strmout_cntl;
139 
140 	/* The register is at different places on different ASICs. */
141 	if (rctx->gfx_level >= EVERGREEN) {
142 		reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
143 	} else {
144 		reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
145 	}
146 
147 	radeon_set_config_reg(cs, reg_strmout_cntl, 0);
148 
149 	radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
150 	radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
151 
152 	radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
153 	radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
154 	radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
155 	radeon_emit(cs, 0);
156 	radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
157 	radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
158 	radeon_emit(cs, 4); /* poll interval */
159 }
160 
r600_emit_streamout_begin(struct r600_common_context * rctx,struct r600_atom * atom)161 static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
162 {
163 	struct radeon_cmdbuf *cs = &rctx->gfx.cs;
164 	struct r600_so_target **t = rctx->streamout.targets;
165 	uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
166 	unsigned i, update_flags = 0;
167 
168 	r600_flush_vgt_streamout(rctx);
169 
170 	for (i = 0; i < rctx->streamout.num_targets; i++) {
171 		if (!t[i])
172 			continue;
173 
174 		t[i]->stride_in_dw = stride_in_dw[i];
175 
176 		uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
177 
178 		update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
179 
180 		radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
181 		radeon_emit(cs, (t[i]->b.buffer_offset +
182 				 t[i]->b.buffer_size) >> 2);	/* BUFFER_SIZE (in DW) */
183 		radeon_emit(cs, stride_in_dw[i]);		/* VTX_STRIDE (in DW) */
184 		radeon_emit(cs, va >> 8);			/* BUFFER_BASE */
185 
186 		r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
187 				RADEON_USAGE_WRITE | RADEON_PRIO_SHADER_RW_BUFFER);
188 
189 		/* R7xx requires this packet after updating BUFFER_BASE.
190 		 * Without this, R7xx locks up. */
191 		if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
192 			radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0));
193 			radeon_emit(cs, i);
194 			radeon_emit(cs, va >> 8);
195 
196 			r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
197 					RADEON_USAGE_WRITE | RADEON_PRIO_SHADER_RW_BUFFER);
198 		}
199 
200 		if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
201 			uint64_t va = t[i]->buf_filled_size->gpu_address +
202 				      t[i]->buf_filled_size_offset;
203 
204 			/* Append. */
205 			radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
206 			radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
207 				    STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
208 			radeon_emit(cs, 0); /* unused */
209 			radeon_emit(cs, 0); /* unused */
210 			radeon_emit(cs, va); /* src address lo */
211 			radeon_emit(cs, va >> 32); /* src address hi */
212 
213 			r600_emit_reloc(rctx,  &rctx->gfx, t[i]->buf_filled_size,
214 					RADEON_USAGE_READ | RADEON_PRIO_SO_FILLED_SIZE);
215 		} else {
216 			/* Start from the beginning. */
217 			radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
218 			radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
219 				    STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
220 			radeon_emit(cs, 0); /* unused */
221 			radeon_emit(cs, 0); /* unused */
222 			radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
223 			radeon_emit(cs, 0); /* unused */
224 		}
225 	}
226 
227 	if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
228 		radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
229 		radeon_emit(cs, update_flags);
230 	}
231 	rctx->streamout.begin_emitted = true;
232 }
233 
r600_emit_streamout_end(struct r600_common_context * rctx)234 void r600_emit_streamout_end(struct r600_common_context *rctx)
235 {
236 	struct radeon_cmdbuf *cs = &rctx->gfx.cs;
237 	struct r600_so_target **t = rctx->streamout.targets;
238 	unsigned i;
239 	uint64_t va;
240 
241 	r600_flush_vgt_streamout(rctx);
242 
243 	for (i = 0; i < rctx->streamout.num_targets; i++) {
244 		if (!t[i])
245 			continue;
246 
247 		va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
248 		radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
249 		radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
250 			    STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
251 			    STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
252 		radeon_emit(cs, va);     /* dst address lo */
253 		radeon_emit(cs, va >> 32); /* dst address hi */
254 		radeon_emit(cs, 0); /* unused */
255 		radeon_emit(cs, 0); /* unused */
256 
257 		r600_emit_reloc(rctx,  &rctx->gfx, t[i]->buf_filled_size,
258 				RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);
259 
260 		/* Zero the buffer size. The counters (primitives generated,
261 		 * primitives emitted) may be enabled even if there is not
262 		 * buffer bound. This ensures that the primitives-emitted query
263 		 * won't increment. */
264 		radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
265 
266 		t[i]->buf_filled_size_valid = true;
267 	}
268 
269 	rctx->streamout.begin_emitted = false;
270 	rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
271 }
272 
273 /* STREAMOUT CONFIG DERIVED STATE
274  *
275  * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
276  * The buffer mask is an independent state, so no writes occur if there
277  * are no buffers bound.
278  */
279 
r600_emit_streamout_enable(struct r600_common_context * rctx,struct r600_atom * atom)280 static void r600_emit_streamout_enable(struct r600_common_context *rctx,
281 				       struct r600_atom *atom)
282 {
283 	unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
284 	unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
285 	unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
286 	unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
287 				      rctx->streamout.enabled_stream_buffers_mask;
288 
289 	if (rctx->gfx_level >= EVERGREEN) {
290 		strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
291 
292 		strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
293 		strmout_config_val |=
294 			S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
295 			S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
296 			S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
297 	}
298 	radeon_set_context_reg(&rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
299 	radeon_set_context_reg(&rctx->gfx.cs, strmout_config_reg, strmout_config_val);
300 }
301 
r600_set_streamout_enable(struct r600_common_context * rctx,bool enable)302 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
303 {
304 	bool old_strmout_en = r600_get_strmout_en(rctx);
305 	unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
306 
307 	rctx->streamout.streamout_enabled = enable;
308 
309 	rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
310 					  (rctx->streamout.enabled_mask << 4) |
311 					  (rctx->streamout.enabled_mask << 8) |
312 					  (rctx->streamout.enabled_mask << 12);
313 
314 	if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
315             (old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
316 		rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
317 	}
318 }
319 
r600_update_prims_generated_query_state(struct r600_common_context * rctx,unsigned type,int diff)320 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
321 					     unsigned type, int diff)
322 {
323 	if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
324 		bool old_strmout_en = r600_get_strmout_en(rctx);
325 
326 		rctx->streamout.num_prims_gen_queries += diff;
327 		assert(rctx->streamout.num_prims_gen_queries >= 0);
328 
329 		rctx->streamout.prims_gen_query_enabled =
330 			rctx->streamout.num_prims_gen_queries != 0;
331 
332 		if (old_strmout_en != r600_get_strmout_en(rctx)) {
333 			rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
334 		}
335 	}
336 }
337 
r600_streamout_init(struct r600_common_context * rctx)338 void r600_streamout_init(struct r600_common_context *rctx)
339 {
340 	rctx->b.create_stream_output_target = r600_create_so_target;
341 	rctx->b.stream_output_target_destroy = r600_so_target_destroy;
342 	rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
343 	rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
344 	rctx->streamout.enable_atom.num_dw = 6;
345 }
346