1 /*
2 * Copyright 2010 Jerome Glisse <[email protected]>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r600_asm.h"
7 #include "r700_sq.h"
8
r700_bytecode_cf_vtx_build(uint32_t * bytecode,const struct r600_bytecode_cf * cf)9 void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
10 {
11 unsigned count = (cf->ndw / 4) - 1;
12 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
13 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R700, cf->op)) |
14 S_SQ_CF_WORD1_BARRIER(1) |
15 S_SQ_CF_WORD1_COUNT(count) |
16 S_SQ_CF_WORD1_COUNT_3(count >> 3)|
17 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
18 }
19
r700_bytecode_alu_build(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,unsigned id)20 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
21 {
22 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
23 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
24 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
25 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
26 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
27 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
28 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
29 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
30 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
31 S_SQ_ALU_WORD0_LAST(alu->last);
32
33 /* don't replace gpr by pv or ps for destination register */
34 if (alu->is_op3) {
35 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
36 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
37 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
38 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
39 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
40 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
41 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
42 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
43 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
44 S_SQ_ALU_WORD1_OP3_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
45 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
46 } else {
47 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
48 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
49 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
50 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
51 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
52 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
53 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
54 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
55 S_SQ_ALU_WORD1_OP2_ALU_INST(r600_isa_alu_opcode(bc->isa->hw_class, alu->op)) |
56 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
57 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
58 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
59 }
60 return 0;
61 }
62
r700_bytecode_alu_read(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,uint32_t word0,uint32_t word1)63 void r700_bytecode_alu_read(struct r600_bytecode *bc,
64 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
65 {
66 /* WORD0 */
67 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
68 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
69 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
70 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
71 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
72 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
73 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
74 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
75 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
76 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
77 alu->last = G_SQ_ALU_WORD0_LAST(word0);
78
79 /* WORD1 */
80 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
81 if (alu->bank_swizzle)
82 alu->bank_swizzle_force = alu->bank_swizzle;
83 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
84 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
85 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
86 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
87 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
88 {
89 alu->is_op3 = 1;
90 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
91 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
92 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
93 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
94 alu->op = r600_isa_alu_by_opcode(bc->isa,
95 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), 1);
96 }
97 else /*ALU_DWORD1_OP2*/
98 {
99 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
100 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
101 alu->op = r600_isa_alu_by_opcode(bc->isa,
102 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), 0);
103 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
104 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
105 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
106 alu->execute_mask =
107 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
108 }
109 }
110
r700_bytecode_fetch_mem_build(struct r600_bytecode * bc,struct r600_bytecode_vtx * mem,unsigned id)111 int r700_bytecode_fetch_mem_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *mem, unsigned id)
112 {
113 unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, mem->op) >> 8;
114
115 bc->bytecode[id++] = S_SQ_MEM_RD_WORD0_MEM_INST(2) |
116 S_SQ_MEM_RD_WORD0_ELEM_SIZE(mem->elem_size) |
117 S_SQ_MEM_RD_WORD0_FETCH_WHOLE_QUAD(0) |
118 S_SQ_MEM_RD_WORD0_MEM_OP(opcode) |
119 S_SQ_MEM_RD_WORD0_UNCACHED(mem->uncached) |
120 S_SQ_MEM_RD_WORD0_INDEXED(mem->indexed) |
121 S_SQ_MEM_RD_WORD0_SRC_SEL_Y(mem->src_sel_y) |
122 S_SQ_MEM_RD_WORD0_SRC_GPR(mem->src_gpr) |
123 S_SQ_MEM_RD_WORD0_SRC_REL(mem->src_rel) |
124 S_SQ_MEM_RD_WORD0_SRC_SEL_X(mem->src_sel_x) |
125 S_SQ_MEM_RD_WORD0_BURST_COUNT(mem->burst_count) |
126 S_SQ_MEM_RD_WORD0_LDS_REQ(0) |
127 S_SQ_MEM_RD_WORD0_COALESCED_READ(0);
128
129 bc->bytecode[id++] = S_SQ_MEM_RD_WORD1_DST_GPR(mem->dst_gpr) |
130 S_SQ_MEM_RD_WORD1_DST_REL(mem->dst_rel) |
131 S_SQ_MEM_RD_WORD1_DST_SEL_X(mem->dst_sel_x) |
132 S_SQ_MEM_RD_WORD1_DST_SEL_Y(mem->dst_sel_y) |
133 S_SQ_MEM_RD_WORD1_DST_SEL_W(mem->dst_sel_w) |
134 S_SQ_MEM_RD_WORD1_DST_SEL_Z(mem->dst_sel_z) |
135 S_SQ_MEM_RD_WORD1_DATA_FORMAT(mem->data_format) |
136 S_SQ_MEM_RD_WORD1_NUM_FORMAT_ALL(mem->num_format_all) |
137 S_SQ_MEM_RD_WORD1_FORMAT_COMP_ALL(mem->format_comp_all) |
138 S_SQ_MEM_RD_WORD1_SRF_MODE_ALL(mem->srf_mode_all);
139
140 bc->bytecode[id++] = S_SQ_MEM_RD_WORD2_ARRAY_BASE(mem->array_base) |
141 S_SQ_MEM_RD_WORD2_ENDIAN_SWAP(0) |
142 S_SQ_MEM_RD_WORD2_ARRAY_SIZE(mem->array_size);
143
144
145 bc->bytecode[id++] = 0; /* MEM ops are 4 word aligned */
146
147 return 0;
148 }
149