1 /************************************************************************** 2 * 3 * Copyright 2018 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef _RADEON_UVD_ENC_H 10 #define _RADEON_UVD_ENC_H 11 12 #include "radeon_video.h" 13 14 #define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1 15 #define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1 16 17 #define RENC_UVD_IB_PARAM_SESSION_INFO 0x00000001 18 #define RENC_UVD_IB_PARAM_TASK_INFO 0x00000002 19 #define RENC_UVD_IB_PARAM_SESSION_INIT 0x00000003 20 #define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x00000004 21 #define RENC_UVD_IB_PARAM_LAYER_SELECT 0x00000005 22 #define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x00000006 23 #define RENC_UVD_IB_PARAM_SPEC_MISC 0x00000007 24 #define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000008 25 #define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000009 26 #define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x0000000a 27 #define RENC_UVD_IB_PARAM_SLICE_HEADER 0x0000000b 28 #define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x0000000c 29 #define RENC_UVD_IB_PARAM_QUALITY_PARAMS 0x0000000d 30 #define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x0000000e 31 #define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x0000000f 32 #define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000010 33 #define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000011 34 #define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER 0x00000012 35 #define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER 0x00000013 36 #define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL 0x00000014 37 38 #define RENC_UVD_IB_OP_INITIALIZE 0x08000001 39 #define RENC_UVD_IB_OP_CLOSE_SESSION 0x08000002 40 #define RENC_UVD_IB_OP_ENCODE 0x08000003 41 #define RENC_UVD_IB_OP_INIT_RC 0x08000004 42 #define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x08000005 43 #define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE 0x08000006 44 #define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE 0x08000007 45 #define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE 0x08000008 46 47 #define RENC_UVD_IF_MAJOR_VERSION_MASK 0xFFFF0000 48 #define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16 49 #define RENC_UVD_IF_MINOR_VERSION_MASK 0x0000FFFF 50 #define RENC_UVD_IF_MINOR_VERSION_SHIFT 0 51 52 #define RENC_UVD_PREENCODE_MODE_NONE 0x00000000 53 #define RENC_UVD_PREENCODE_MODE_1X 0x00000001 54 #define RENC_UVD_PREENCODE_MODE_2X 0x00000002 55 #define RENC_UVD_PREENCODE_MODE_4X 0x00000004 56 57 #define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000 58 #define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 59 60 #define RENC_UVD_RATE_CONTROL_METHOD_NONE 0x00000000 61 #define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001 62 #define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002 63 #define RENC_UVD_RATE_CONTROL_METHOD_CBR 0x00000003 64 65 #define RENC_UVD_NALU_TYPE_AUD 0x00000001 66 #define RENC_UVD_NALU_TYPE_VPS 0x00000002 67 #define RENC_UVD_NALU_TYPE_SPS 0x00000003 68 #define RENC_UVD_NALU_TYPE_PPS 0x00000004 69 #define RENC_UVD_NALU_TYPE_END_OF_SEQUENCE 0x00000005 70 71 #define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16 72 #define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16 73 74 #define RENC_UVD_HEADER_INSTRUCTION_END 0 75 #define RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 1 76 #define RENC_UVD_HEADER_INSTRUCTION_COPY 2 77 #define RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE 3 78 #define RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT 4 79 #define RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA 5 80 81 #define RENC_UVD_PICTURE_TYPE_B 0 82 #define RENC_UVD_PICTURE_TYPE_P 1 83 #define RENC_UVD_PICTURE_TYPE_I 2 84 #define RENC_UVD_PICTURE_TYPE_P_SKIP 3 85 86 #define RENC_UVD_SWIZZLE_MODE_LINEAR 0 87 #define RENC_UVD_SWIZZLE_MODE_256B_D 2 88 #define RENC_UVD_SWIZZLE_MODE_4kB_D 6 89 #define RENC_UVD_SWIZZLE_MODE_64kB_D 10 90 #define RENC_UVD_INTRA_REFRESH_MODE_NONE 0 91 #define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_ROWS 1 92 #define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2 93 94 #define RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES 34 95 #define RENC_UVD_ADDR_MODE_LINEAR 0 96 #define RENC_UVD_ADDR_MODE_PELE_8X8_1D 1 97 #define RENC_UVD_ADDR_MODE_32AS8_88 2 98 99 #define RENC_UVD_ARRAY_MODE_LINEAR 0 100 #define RENC_UVD_ARRAY_MODE_PELE_8X8_1D 2 101 #define RENC_UVD_ARRAY_MODE_2D_TILED_THIN1 4 102 103 #define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0 104 #define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1 105 106 #define RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR 0 107 #define RENC_UVD_FEEDBACK_BUFFER_MODE_CIRCULAR 1 108 109 #define RENC_UVD_FEEDBACK_STATUS_OK 0x00000000 110 #define RENC_UVD_FEEDBACK_STATUS_NOT_ENCODED 0x10000001 111 112 typedef struct radeon_uvd_enc_feedback_s { 113 uint32_t task_id; 114 uint32_t first_in_task; 115 uint32_t last_in_task; 116 uint32_t status; 117 uint32_t has_bitstream; 118 uint32_t bitstream_offset; 119 uint32_t bitstream_size; 120 uint32_t enabled_filler_data; 121 uint32_t filler_data_size; 122 uint32_t extra_bytes; 123 } radeon_uvd_enc_feedback_t; 124 125 typedef struct ruvd_enc_session_info_s { 126 uint32_t reserved; 127 uint32_t interface_version; 128 uint32_t sw_context_address_hi; 129 uint32_t sw_context_address_lo; 130 } ruvd_enc_session_info_t; 131 132 typedef struct ruvd_enc_task_info_s { 133 uint32_t total_size_of_all_packages; 134 uint32_t task_id; 135 uint32_t allowed_max_num_feedbacks; 136 } ruvd_enc_task_info_t; 137 138 typedef struct ruvd_enc_session_init_s { 139 uint32_t aligned_picture_width; 140 uint32_t aligned_picture_height; 141 uint32_t padding_width; 142 uint32_t padding_height; 143 uint32_t pre_encode_mode; 144 uint32_t pre_encode_chroma_enabled; 145 } ruvd_enc_session_init_t; 146 147 typedef struct ruvd_enc_layer_control_s { 148 uint32_t max_num_temporal_layers; 149 uint32_t num_temporal_layers; 150 } ruvd_enc_layer_control_t; 151 152 typedef struct ruvd_enc_layer_select_s { 153 uint32_t temporal_layer_index; 154 } ruvd_enc_layer_select_t; 155 156 typedef struct ruvd_enc_hevc_slice_control_s { 157 uint32_t slice_control_mode; 158 union { 159 struct { 160 uint32_t num_ctbs_per_slice; 161 uint32_t num_ctbs_per_slice_segment; 162 } fixed_ctbs_per_slice; 163 164 struct { 165 uint32_t num_bits_per_slice; 166 uint32_t num_bits_per_slice_segment; 167 } fixed_bits_per_slice; 168 }; 169 } ruvd_enc_hevc_slice_control_t; 170 171 typedef struct ruvd_enc_hevc_spec_misc_s { 172 uint32_t log2_min_luma_coding_block_size_minus3; 173 uint32_t amp_disabled; 174 uint32_t strong_intra_smoothing_enabled; 175 uint32_t constrained_intra_pred_flag; 176 uint32_t cabac_init_flag; 177 uint32_t half_pel_enabled; 178 uint32_t quarter_pel_enabled; 179 } ruvd_enc_hevc_spec_misc_t; 180 181 typedef struct ruvd_enc_rate_ctl_session_init_s { 182 uint32_t rate_control_method; 183 uint32_t vbv_buffer_level; 184 } ruvd_enc_rate_ctl_session_init_t; 185 186 typedef struct ruvd_enc_rate_ctl_layer_init_s { 187 uint32_t target_bit_rate; 188 uint32_t peak_bit_rate; 189 uint32_t frame_rate_num; 190 uint32_t frame_rate_den; 191 uint32_t vbv_buffer_size; 192 uint32_t avg_target_bits_per_picture; 193 uint32_t peak_bits_per_picture_integer; 194 uint32_t peak_bits_per_picture_fractional; 195 } ruvd_enc_rate_ctl_layer_init_t; 196 197 typedef struct ruvd_enc_rate_ctl_per_picture_s { 198 uint32_t qp; 199 uint32_t min_qp_app; 200 uint32_t max_qp_app; 201 uint32_t max_au_size; 202 uint32_t enabled_filler_data; 203 uint32_t skip_frame_enable; 204 uint32_t enforce_hrd; 205 } ruvd_enc_rate_ctl_per_picture_t; 206 207 typedef struct ruvd_enc_quality_params_s { 208 uint32_t vbaq_mode; 209 uint32_t scene_change_sensitivity; 210 uint32_t scene_change_min_idr_interval; 211 } ruvd_enc_quality_params_t; 212 213 typedef struct ruvd_enc_direct_output_nalu_s { 214 uint32_t type; 215 uint32_t size; 216 uint32_t data[1]; 217 } ruvd_enc_direct_output_nalu_t; 218 219 typedef struct ruvd_enc_slice_header_s { 220 uint32_t bitstream_template[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS]; 221 struct { 222 uint32_t instruction; 223 uint32_t num_bits; 224 } instructions[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS]; 225 } ruvd_enc_slice_header_t; 226 227 typedef struct ruvd_enc_encode_params_s { 228 uint32_t pic_type; 229 uint32_t allowed_max_bitstream_size; 230 uint32_t input_picture_luma_address_hi; 231 uint32_t input_picture_luma_address_lo; 232 uint32_t input_picture_chroma_address_hi; 233 uint32_t input_picture_chroma_address_lo; 234 uint32_t input_pic_luma_pitch; 235 uint32_t input_pic_chroma_pitch; 236 union { 237 uint32_t input_pic_addr_mode; 238 uint32_t reserved; 239 }; 240 union { 241 uint32_t input_pic_array_mode; 242 uint32_t input_pic_swizzle_mode; 243 }; 244 uint32_t reference_picture_index; 245 uint32_t reconstructed_picture_index; 246 } ruvd_enc_encode_params_t; 247 248 typedef struct ruvd_enc_hevc_deblocking_filter_s { 249 uint32_t loop_filter_across_slices_enabled; 250 int32_t deblocking_filter_disabled; 251 int32_t beta_offset_div2; 252 int32_t tc_offset_div2; 253 int32_t cb_qp_offset; 254 int32_t cr_qp_offset; 255 } ruvd_enc_hevc_deblocking_filter_t; 256 257 typedef struct ruvd_enc_intra_refresh_s { 258 uint32_t intra_refresh_mode; 259 uint32_t offset; 260 uint32_t region_size; 261 } ruvd_enc_intra_refresh_t; 262 263 typedef struct ruvd_enc_reconstructed_picture_s { 264 uint32_t luma_offset; 265 uint32_t chroma_offset; 266 } ruvd_enc_reconstructed_picture_t; 267 268 typedef struct ruvd_enc_encode_context_buffer_s { 269 uint32_t encode_context_address_hi; 270 uint32_t encode_context_address_lo; 271 union { 272 uint32_t addr_mode; 273 uint32_t reserved; 274 }; 275 union { 276 uint32_t array_mode; 277 uint32_t swizzle_mode; 278 }; 279 uint32_t rec_luma_pitch; 280 uint32_t rec_chroma_pitch; 281 uint32_t num_reconstructed_pictures; 282 ruvd_enc_reconstructed_picture_t reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES]; 283 uint32_t pre_encode_picture_luma_pitch; 284 uint32_t pre_encode_picture_chroma_pitch; 285 ruvd_enc_reconstructed_picture_t 286 pre_encode_reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES]; 287 ruvd_enc_reconstructed_picture_t pre_encode_input_picture; 288 } ruvd_enc_encode_context_buffer_t; 289 290 typedef struct ruvd_enc_video_bitstream_buffer_s { 291 uint32_t mode; 292 uint32_t video_bitstream_buffer_address_hi; 293 uint32_t video_bitstream_buffer_address_lo; 294 uint32_t video_bitstream_buffer_size; 295 uint32_t video_bitstream_data_offset; 296 } ruvd_enc_video_bitstream_buffer_t; 297 298 typedef struct ruvd_enc_feedback_buffer_s { 299 uint32_t mode; 300 uint32_t feedback_buffer_address_hi; 301 uint32_t feedback_buffer_address_lo; 302 uint32_t feedback_buffer_size; 303 uint32_t feedback_data_size; 304 } ruvd_enc_feedback_buffer_t; 305 306 typedef struct ruvd_enc_vui_info_s 307 { 308 uint32_t vui_parameters_present_flag; 309 struct { 310 uint32_t aspect_ratio_info_present_flag : 1; 311 uint32_t timing_info_present_flag : 1; 312 uint32_t video_signal_type_present_flag : 1; 313 uint32_t colour_description_present_flag : 1; 314 uint32_t chroma_loc_info_present_flag : 1; 315 } flags; 316 uint32_t aspect_ratio_idc; 317 uint32_t sar_width; 318 uint32_t sar_height; 319 uint32_t num_units_in_tick; 320 uint32_t time_scale; 321 uint32_t video_format; 322 uint32_t video_full_range_flag; 323 uint32_t colour_primaries; 324 uint32_t transfer_characteristics; 325 uint32_t matrix_coefficients; 326 uint32_t chroma_sample_loc_type_top_field; 327 uint32_t chroma_sample_loc_type_bottom_field; 328 uint32_t max_num_reorder_frames; 329 } ruvd_enc_vui_info; 330 331 typedef void (*radeon_uvd_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer_lean **handle, 332 struct radeon_surf **surface); 333 334 struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context, 335 const struct pipe_video_codec *templat, 336 struct radeon_winsys *ws, 337 radeon_uvd_enc_get_buffer get_buffer); 338 339 struct radeon_uvd_enc_pic { 340 enum pipe_h2645_enc_picture_type picture_type; 341 342 unsigned frame_num; 343 unsigned pic_order_cnt; 344 unsigned pic_order_cnt_type; 345 unsigned crop_left; 346 unsigned crop_right; 347 unsigned crop_top; 348 unsigned crop_bottom; 349 unsigned general_tier_flag; 350 unsigned general_profile_idc; 351 unsigned general_level_idc; 352 unsigned max_poc; 353 unsigned log2_max_poc; 354 unsigned chroma_format_idc; 355 unsigned pic_width_in_luma_samples; 356 unsigned pic_height_in_luma_samples; 357 unsigned log2_diff_max_min_luma_coding_block_size; 358 unsigned log2_min_transform_block_size_minus2; 359 unsigned log2_diff_max_min_transform_block_size; 360 unsigned max_transform_hierarchy_depth_inter; 361 unsigned max_transform_hierarchy_depth_intra; 362 unsigned log2_parallel_merge_level_minus2; 363 unsigned bit_depth_luma_minus8; 364 unsigned bit_depth_chroma_minus8; 365 unsigned nal_unit_type; 366 unsigned max_num_merge_cand; 367 ruvd_enc_vui_info vui_info; 368 369 bool not_referenced; 370 bool is_iframe; 371 bool is_even_frame; 372 bool sample_adaptive_offset_enabled_flag; 373 bool pcm_enabled_flag; 374 bool sps_temporal_mvp_enabled_flag; 375 376 ruvd_enc_task_info_t task_info; 377 ruvd_enc_session_init_t session_init; 378 ruvd_enc_layer_control_t layer_ctrl; 379 ruvd_enc_layer_select_t layer_sel; 380 ruvd_enc_hevc_slice_control_t hevc_slice_ctrl; 381 ruvd_enc_hevc_spec_misc_t hevc_spec_misc; 382 ruvd_enc_rate_ctl_session_init_t rc_session_init; 383 ruvd_enc_rate_ctl_layer_init_t rc_layer_init; 384 ruvd_enc_hevc_deblocking_filter_t hevc_deblock; 385 ruvd_enc_rate_ctl_per_picture_t rc_per_pic; 386 ruvd_enc_quality_params_t quality_params; 387 ruvd_enc_encode_context_buffer_t ctx_buf; 388 ruvd_enc_video_bitstream_buffer_t bit_buf; 389 ruvd_enc_feedback_buffer_t fb_buf; 390 ruvd_enc_intra_refresh_t intra_ref; 391 ruvd_enc_encode_params_t enc_params; 392 }; 393 394 struct radeon_uvd_encoder { 395 struct pipe_video_codec base; 396 397 void (*begin)(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic); 398 void (*encode)(struct radeon_uvd_encoder *enc); 399 void (*destroy)(struct radeon_uvd_encoder *enc); 400 401 unsigned stream_handle; 402 403 struct pipe_screen *screen; 404 struct radeon_winsys *ws; 405 struct radeon_cmdbuf cs; 406 407 radeon_uvd_enc_get_buffer get_buffer; 408 409 struct pb_buffer_lean *handle; 410 struct radeon_surf *luma; 411 struct radeon_surf *chroma; 412 413 struct pb_buffer_lean *bs_handle; 414 unsigned bs_size; 415 416 unsigned cpb_num; 417 418 struct rvid_buffer *si; 419 struct rvid_buffer *fb; 420 struct rvid_buffer cpb; 421 struct radeon_uvd_enc_pic enc_pic; 422 423 unsigned shifter; 424 unsigned bits_in_shifter; 425 unsigned num_zeros; 426 unsigned byte_index; 427 unsigned bits_output; 428 uint32_t total_task_size; 429 uint32_t *p_task_size; 430 431 bool emulation_prevention; 432 bool need_feedback; 433 }; 434 435 struct si_screen; 436 437 void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc); 438 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen); 439 440 #endif // _RADEON_UVD_ENC_H 441