1 /*
2 * Copyright © 2019 Valve Corporation.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #ifndef RADV_SHADER_ARGS_H
8 #define RADV_SHADER_ARGS_H
9
10 #include "compiler/shader_enums.h"
11 #include "util/list.h"
12 #include "util/macros.h"
13 #include "ac_shader_args.h"
14 #include "amd_family.h"
15 #include "radv_constants.h"
16
17 enum radv_ud_index {
18 AC_UD_SCRATCH_RING_OFFSETS = 0,
19 AC_UD_PUSH_CONSTANTS = 1,
20 AC_UD_INLINE_PUSH_CONSTANTS = 2,
21 AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
22 AC_UD_VIEW_INDEX = 4,
23 AC_UD_STREAMOUT_BUFFERS = 5,
24 AC_UD_STREAMOUT_STATE = 6,
25 AC_UD_SHADER_QUERY_STATE = 7,
26 AC_UD_NGG_PROVOKING_VTX = 8,
27 AC_UD_NGG_CULLING_SETTINGS = 9,
28 AC_UD_NGG_VIEWPORT = 10,
29 AC_UD_NGG_LDS_LAYOUT = 11,
30 AC_UD_VGT_ESGS_RING_ITEMSIZE = 12,
31 AC_UD_FORCE_VRS_RATES = 13,
32 AC_UD_TASK_RING_ENTRY = 14,
33 AC_UD_NUM_VERTS_PER_PRIM = 15,
34 AC_UD_NEXT_STAGE_PC = 16,
35 AC_UD_EPILOG_PC = 17,
36 AC_UD_SHADER_START = 18,
37 AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
38 AC_UD_VS_BASE_VERTEX_START_INSTANCE,
39 AC_UD_VS_PROLOG_INPUTS,
40 AC_UD_VS_MAX_UD,
41 AC_UD_PS_STATE,
42 AC_UD_PS_MAX_UD,
43 AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
44 AC_UD_CS_SBT_DESCRIPTORS,
45 AC_UD_CS_RAY_LAUNCH_SIZE_ADDR,
46 AC_UD_CS_RAY_DYNAMIC_CALLABLE_STACK_BASE,
47 AC_UD_CS_TRAVERSAL_SHADER_ADDR,
48 AC_UD_CS_TASK_RING_OFFSETS,
49 AC_UD_CS_TASK_DRAW_ID,
50 AC_UD_CS_TASK_IB,
51 AC_UD_CS_MAX_UD,
52 AC_UD_GS_MAX_UD,
53 AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
54 AC_UD_TCS_MAX_UD,
55 /* We might not know the previous stage when compiling a geometry shader, so we just
56 * declare both TES and VS user SGPRs.
57 */
58 AC_UD_TES_MAX_UD = AC_UD_TCS_MAX_UD,
59 AC_UD_MAX_UD = AC_UD_CS_MAX_UD,
60 };
61
62 struct radv_userdata_info {
63 int8_t sgpr_idx;
64 uint8_t num_sgprs;
65 };
66
67 struct radv_userdata_locations {
68 struct radv_userdata_info descriptor_sets[MAX_SETS];
69 struct radv_userdata_info shader_data[AC_UD_MAX_UD];
70 uint32_t descriptor_sets_enabled;
71 };
72
73 struct radv_shader_args {
74 struct ac_shader_args ac;
75
76 struct ac_arg descriptor_sets[MAX_SETS];
77 /* User data 2/3. same as ring_offsets but for task shaders. */
78 struct ac_arg task_ring_offsets;
79
80 /* Streamout */
81 struct ac_arg streamout_buffers;
82 struct ac_arg streamout_state; /* GFX12+ */
83
84 /* Emulated query */
85 struct ac_arg shader_query_state;
86
87 /* NGG */
88 struct ac_arg ngg_provoking_vtx;
89 struct ac_arg ngg_lds_layout;
90
91 /* NGG GS */
92 struct ac_arg ngg_culling_settings;
93 struct ac_arg ngg_viewport_scale[2];
94 struct ac_arg ngg_viewport_translate[2];
95
96 /* Fragment shaders */
97 struct ac_arg ps_state;
98
99 struct ac_arg prolog_inputs;
100 struct ac_arg vs_inputs[MAX_VERTEX_ATTRIBS];
101
102 /* PS epilogs */
103 struct ac_arg colors[MAX_RTS];
104 struct ac_arg depth;
105 struct ac_arg stencil;
106 struct ac_arg sample_mask;
107
108 /* TCS */
109 /* # [0:6] = the number of tessellation patches minus one, max = 127
110 * # [7:11] = the number of output patch control points minus one, max = 31
111 * # [12:16] = the number of input patch control points minus one, max = 31
112 * # [17:22] = the number of LS outputs, up to 32
113 * # [23:28] = the number of HS per-vertex outputs, up to 32
114 * # [29:30] = tess_primitive_mode
115 * # [31] = whether TES reads tess factors
116 */
117 struct ac_arg tcs_offchip_layout;
118
119 /* GS */
120 struct ac_arg vgt_esgs_ring_itemsize;
121
122 /* NGG VS streamout */
123 struct ac_arg num_verts_per_prim;
124
125 /* For non-monolithic VS or TES on GFX9+. */
126 struct ac_arg next_stage_pc;
127
128 /* PS/TCS epilogs PC. */
129 struct ac_arg epilog_pc;
130
131 struct radv_userdata_locations user_sgprs_locs;
132 unsigned num_user_sgprs;
133
134 bool explicit_scratch_args;
135 bool remap_spi_ps_input;
136 bool load_grid_size_from_user_sgpr;
137 };
138
139 static inline struct radv_shader_args *
radv_shader_args_from_ac(struct ac_shader_args * args)140 radv_shader_args_from_ac(struct ac_shader_args *args)
141 {
142 return container_of(args, struct radv_shader_args, ac);
143 }
144
145 struct radv_graphics_state_key;
146 struct radv_shader_info;
147 struct radv_ps_epilog_key;
148 struct radv_device;
149
150 void radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
151 const struct radv_shader_info *info, gl_shader_stage stage,
152 gl_shader_stage previous_stage, struct radv_shader_args *args);
153
154 void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
155 struct radv_shader_args *args);
156
157 void radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_args *args);
158
159 #endif /* RADV_SHADER_ARGS_H */
160