1 /* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * SPDX-License-Identifier: MIT 9 */ 10 11 #ifndef RADV_SQTT_H 12 #define RADV_SQTT_H 13 14 #include "radv_device.h" 15 16 struct radv_cmd_buffer; 17 struct radv_dispatch_info; 18 struct radv_graphics_pipeline; 19 20 struct radv_barrier_data { 21 union { 22 struct { 23 uint16_t depth_stencil_expand : 1; 24 uint16_t htile_hiz_range_expand : 1; 25 uint16_t depth_stencil_resummarize : 1; 26 uint16_t dcc_decompress : 1; 27 uint16_t fmask_decompress : 1; 28 uint16_t fast_clear_eliminate : 1; 29 uint16_t fmask_color_expand : 1; 30 uint16_t init_mask_ram : 1; 31 uint16_t reserved : 8; 32 }; 33 uint16_t all; 34 } layout_transitions; 35 }; 36 37 /** 38 * Value for the reason field of an RGP barrier start marker originating from 39 * the Vulkan client (does not include PAL-defined values). (Table 15) 40 */ 41 enum rgp_barrier_reason { 42 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF, 43 44 /* External app-generated barrier reasons, i.e. API synchronization 45 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF]. 46 */ 47 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001, 48 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002, 49 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003, 50 51 /* Internal barrier reasons, i.e. implicit synchronization inserted by 52 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE]. 53 */ 54 RGP_BARRIER_INTERNAL_BASE = 0xC0000000, 55 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0, 56 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1, 57 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2, 58 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3 59 }; 60 61 bool radv_is_instruction_timing_enabled(void); 62 63 bool radv_sqtt_queue_events_enabled(void); 64 65 void radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords); 66 67 void radv_emit_spi_config_cntl(const struct radv_device *device, struct radeon_cmdbuf *cs, bool enable); 68 69 void radv_emit_inhibit_clockgating(const struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit); 70 71 VkResult radv_sqtt_acquire_gpu_timestamp(struct radv_device *device, struct radeon_winsys_bo **gpu_timestamp_bo, 72 uint32_t *gpu_timestamp_offset, void **gpu_timestamp_ptr); 73 74 bool radv_sqtt_init(struct radv_device *device); 75 76 void radv_sqtt_finish(struct radv_device *device); 77 78 bool radv_begin_sqtt(struct radv_queue *queue); 79 80 bool radv_end_sqtt(struct radv_queue *queue); 81 82 bool radv_get_sqtt_trace(struct radv_queue *queue, struct ac_sqtt_trace *sqtt_trace); 83 84 void radv_reset_sqtt_trace(struct radv_device *device); 85 86 bool radv_sqtt_sample_clocks(struct radv_device *device); 87 88 VkResult radv_sqtt_get_timed_cmdbuf(struct radv_queue *queue, struct radeon_winsys_bo *timestamp_bo, 89 uint32_t timestamp_offset, VkPipelineStageFlags2 timestamp_stage, 90 VkCommandBuffer *pcmdbuf); 91 92 void radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics_pipeline *pipeline); 93 94 void radv_write_user_event_marker(struct radv_cmd_buffer *cmd_buffer, enum rgp_sqtt_marker_user_event_type type, 95 const char *str); 96 97 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer); 98 99 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer); 100 101 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer); 102 103 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info); 104 105 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer, VkImageAspectFlagBits aspects); 106 107 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer); 108 109 void radv_describe_begin_render_pass_resolve(struct radv_cmd_buffer *cmd_buffer); 110 111 void radv_describe_end_render_pass_resolve(struct radv_cmd_buffer *cmd_buffer); 112 113 void radv_describe_barrier_end_delayed(struct radv_cmd_buffer *cmd_buffer); 114 115 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer, enum rgp_barrier_reason reason); 116 117 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer); 118 119 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer, const struct radv_barrier_data *barrier); 120 121 void radv_describe_begin_accel_struct_build(struct radv_cmd_buffer *cmd_buffer, uint32_t count); 122 123 void radv_describe_end_accel_struct_build(struct radv_cmd_buffer *cmd_buffer); 124 125 #endif /* RADV_SQTT_H */ 126