xref: /aosp_15_r20/external/coreboot/src/arch/riscv/romstage.S (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <arch/encoding.h>
4#include <bits.h>
5#include <mcall.h>
6
7.section ".text._start", "ax", %progbits
8.globl _start
9_start:
10	# initialize stack point for each hart
11	# and the stack must be page-aligned.
12	# 0xDEADBEEF used to check stack overflow
13	csrr a0, mhartid
14	la   t0, _stack
15	slli t1, a0, RISCV_PGSHIFT
16	add  t0, t0, t1
17	li   t1, 0xDEADBEEF
18	STORE t1, 0(t0)
19	li   t1, RISCV_PGSIZE - HLS_SIZE
20	add  sp, t0, t1
21
22	# initialize hart-local storage
23	csrr a0, mhartid
24	call hls_init
25
26	li   a0, CONFIG_RISCV_WORKING_HARTID
27	call smp_pause
28
29	# initialize entry of interrupt/exception
30	la   t0, trap_entry
31	csrw mtvec, t0
32
33	# clear any pending interrupts
34	csrwi mip, 0
35
36	# set up the mstatus register
37	call mstatus_init
38	tail main
39